[AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instructions:

INT:
   SMLAL
   SMLSL
   UMLAL
   UMLSL
FP:
  BFMLAL
  BFMLSL
  FMLAL
  FMLSL

For multiple and indexed vector, Multiple and Single vector and
Multi vectors, for 1, 2 and 4 ZA registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds a new immediate:

uimm3s2range for off3
uimm2s2range for off2

to represent the vector select offset.
The new operands have the range between the first and the last vector position.

Depends on: D135563

[CarolineConcatto]

-rebase

[aemerson]

LGTM unless Sander/Paul have any comments.

[sdesmalen]

Looks fine to me as well.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 }
 def sme_elm_idx0_15 : Operand<i64>, ImmLeaf<i64, [{
   return ((uint64_t)Imm) <= 15;
 }]> {
   let ParserMatchClass = Imm0_15Operand;
   let PrintMethod = "printMatrixIndex";
 }
 
+class UImmScaledMemoryIndexedRange<int Width, int Scale, int OffsetVal> : AsmOperandClass {
+  let Name = "UImm" # Width # "s" # Scale # "Range";
+  let DiagnosticType = "InvalidMemoryIndexedRange" # Scale # "UImm" # Width;
+  let RenderMethod = "addImmScaledRangeOperands<" # Scale # ">";
+  let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ", " # OffsetVal # ", /*IsRange=*/true>";
+  let ParserMethod = "tryParseImmRange";
+}
+
+def UImm2s2RangeOperand : UImmScaledMemoryIndexedRange<2, 2, 1>;
+def UImm3s2RangeOperand : UImmScaledMemoryIndexedRange<3, 2, 1>;
+
+def uimm2s2range : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm <= 6 && ((Imm % 2) == 0); }], UImmS2XForm> {
+  let PrintMethod = "printImmRangeScale<2, 1>";
+  let ParserMatchClass = UImm2s2RangeOperand;
+}
+
+
+def uimm3s2range : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm <= 14 && ((Imm % 2) == 0); }], UImmS2XForm> {
+  let PrintMethod = "printImmRangeScale<2, 1>";
+  let ParserMatchClass = UImm3s2RangeOperand;
+}
+
+
 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
 // are encoded as the eight bit value 'abcdefgh'.
 def simdimmtype10 : Operand<i32>,
                     FPImmLeaf<f64, [{
       return AArch64_AM::isAdvSIMDModImmType10(
                  Imm.bitcastToAPInt().getZExtValue());
     }], SDNodeXForm<fpimm, [{

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
 defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
 
 defm ADD_VG2_2ZZ  : sme2_sqdmulh_add_vector_vg2_single<"add", 0b011000>;
 defm ADD_VG4_4ZZ  : sme2_sqdmulh_add_vector_vg4_single<"add", 0b011000>;
 
 defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
 defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
+
+defm FMLAL_MZZI      : sme2_mla_long_array_index<"fmlal",  0b10,   0b00>;
+defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal",   0b00>;
+defm FMLAL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlal",   0b00>;
+defm FMLAL_MZZ       : sme2_mla_long_array_single<"fmlal", 0b00,   0b00>;
+defm FMLAL_VG2_M2ZZ  : sme2_fp_mla_long_array_vg2_single<"fmlal",  0b00>;
+defm FMLAL_VG4_M4ZZ  : sme2_fp_mla_long_array_vg4_single<"fmlal",  0b00>;
+defm FMLAL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"fmlal",   0b00>;
+defm FMLAL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"fmlal",   0b00>;
+
+defm FMLSL_MZZI      : sme2_mla_long_array_index<"fmlsl",  0b10,   0b01>;
+defm FMLSL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlsl",   0b01>;
+defm FMLSL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlsl",   0b01>;
+defm FMLSL_MZZ       : sme2_mla_long_array_single<"fmlsl", 0b00,   0b01>;
+defm FMLSL_VG2_M2ZZ  : sme2_fp_mla_long_array_vg2_single<"fmlsl",  0b01>;
+defm FMLSL_VG4_M4ZZ  : sme2_fp_mla_long_array_vg4_single<"fmlsl",  0b01>;
+defm FMLSL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"fmlsl",   0b01>;
+defm FMLSL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"fmlsl",   0b01>;
+
+defm BFMLAL_MZZI      : sme2_mla_long_array_index<"bfmlal",  0b10,   0b10>;
+defm BFMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"bfmlal",   0b10>;
+defm BFMLAL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"bfmlal",   0b10>;
+defm BFMLAL_MZZ       : sme2_mla_long_array_single<"bfmlal", 0b00,   0b10>;
+defm BFMLAL_VG2_M2ZZ  : sme2_fp_mla_long_array_vg2_single<"bfmlal",  0b10>;
+defm BFMLAL_VG4_M4ZZ  : sme2_fp_mla_long_array_vg4_single<"bfmlal",  0b10>;
+defm BFMLAL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"bfmlal",   0b10>;
+defm BFMLAL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"bfmlal",   0b10>;
+
+defm BFMLSL_MZZI      : sme2_mla_long_array_index<"bfmlsl",  0b10,   0b11>;
+defm BFMLSL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"bfmlsl",   0b11>;
+defm BFMLSL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"bfmlsl",   0b11>;
+defm BFMLSL_MZZ       : sme2_mla_long_array_single<"bfmlsl", 0b00,   0b11>;
+defm BFMLSL_VG2_M2ZZ  : sme2_fp_mla_long_array_vg2_single<"bfmlsl",  0b11>;
+defm BFMLSL_VG4_M4ZZ  : sme2_fp_mla_long_array_vg4_single<"bfmlsl",  0b11>;
+defm BFMLSL_VG2_M2Z2Z : sme2_fp_mla_long_array_vg2_multi<"bfmlsl",   0b11>;
+defm BFMLSL_VG4_M4Z4Z : sme2_fp_mla_long_array_vg4_multi<"bfmlsl",   0b11>;
+
+defm SMLAL_MZZI      : sme2_mla_long_array_index<"smlal", 0b11,    0b00>;
+defm SMLAL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"smlal",  0b00>;
+defm SMLAL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"smlal",  0b00>;
+defm SMLAL_MZZ       : sme2_mla_long_array_single<"smlal",0b01,    0b00>;
+defm SMLAL_VG2_M2ZZ  : sme2_int_mla_long_array_vg2_single<"smlal", 0b00>;
+defm SMLAL_VG4_M4ZZ  : sme2_int_mla_long_array_vg4_single<"smlal", 0b00>;
+defm SMLAL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"smlal",  0b00>;
+defm SMLAL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"smlal",  0b00>;
+
+defm SMLSL_MZZI      : sme2_mla_long_array_index<"smlsl", 0b11,    0b01>;
+defm SMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"smlsl",  0b01>;
+defm SMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"smlsl",  0b01>;
+defm SMLSL_MZZ       : sme2_mla_long_array_single<"smlsl",0b01,    0b01>;
+defm SMLSL_VG2_M2ZZ  : sme2_int_mla_long_array_vg2_single<"smlsl", 0b01>;
+defm SMLSL_VG4_M4ZZ  : sme2_int_mla_long_array_vg4_single<"smlsl", 0b01>;
+defm SMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"smlsl",  0b01>;
+defm SMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"smlsl",  0b01>;
+
+defm UMLAL_MZZI      : sme2_mla_long_array_index<"umlal", 0b11,    0b10>;
+defm UMLAL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlal",  0b10>;
+defm UMLAL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlal",  0b10>;
+defm UMLAL_MZZ       : sme2_mla_long_array_single<"umlal",0b01,    0b10>;
+defm UMLAL_VG2_M2ZZ  : sme2_int_mla_long_array_vg2_single<"umlal", 0b10>;
+defm UMLAL_VG4_M4ZZ  : sme2_int_mla_long_array_vg4_single<"umlal", 0b10>;
+defm UMLAL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlal",  0b10>;
+defm UMLAL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlal",  0b10>;
+
+defm UMLSL_MZZI      : sme2_mla_long_array_index<"umlsl", 0b11,    0b11>;
+defm UMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlsl",  0b11>;
+defm UMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlsl",  0b11>;
+defm UMLSL_MZZ       : sme2_mla_long_array_single<"umlsl",0b01,    0b11>;
+defm UMLSL_VG2_M2ZZ  : sme2_int_mla_long_array_vg2_single<"umlsl", 0b11>;
+defm UMLSL_VG4_M4ZZ  : sme2_int_mla_long_array_vg4_single<"umlsl", 0b11>;
+defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl",  0b11>;
+defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl",  0b11>;
 }
 
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
 defm ADD_VG4_M4ZZ_D  : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
 defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
 defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

#include "AArch64GenAsmMatcher.inc"
   OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
   OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
   template <RegKind VectorKind>
   OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
                                           bool ExpectMatch = false);
   OperandMatchResultTy tryParseMatrixTileList(OperandVector &Operands);
   OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64x8(OperandVector &Operands);
+  OperandMatchResultTy tryParseImmRange(OperandVector &Operands);
 
 public:
   enum AArch64MatchResultTy {
     Match_InvalidSuffix = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "AArch64GenAsmMatcher.inc"
   };
   bool IsILP32;

 
 /// AArch64Operand - Instances of this class represent a parsed AArch64 machine
 /// instruction.
 class AArch64Operand : public MCParsedAsmOperand {
 private:
   enum KindTy {
     k_Immediate,
     k_ShiftedImm,
+    k_ImmRange,
     k_CondCode,
     k_Register,
     k_MatrixRegister,
     k_MatrixTileList,
     k_SVCR,
     k_VectorList,
     k_VectorIndex,
     k_Token,
struct ImmOp {
     const MCExpr *Val;
   };
 
   struct ShiftedImmOp {
     const MCExpr *Val;
     unsigned ShiftAmount;
   };
 
+  struct ImmRangeOp {
+    unsigned First;
+    unsigned Last;
+  };
+
   struct CondCodeOp {
     AArch64CC::CondCode Code;
   };
 
   struct FPImmOp {
     uint64_t Val; // APFloat value bitcasted to uint64_t.
     bool IsExact; // describes whether parsed value was exact.
   };
union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct MatrixRegOp MatrixReg;
     struct MatrixTileListOp MatrixTileList;
     struct VectorListOp VectorList;
     struct VectorIndexOp VectorIndex;
     struct ImmOp Imm;
     struct ShiftedImmOp ShiftedImm;
+    struct ImmRangeOp ImmRange;
     struct CondCodeOp CondCode;
     struct FPImmOp FPImm;
     struct BarrierOp Barrier;
     struct SysRegOp SysReg;
     struct SysCRImmOp SysCRImm;
     struct PrefetchOp Prefetch;
     struct PSBHintOp PSBHint;
     struct BTIHintOp BTIHint;
case k_Token:
       Tok = o.Tok;
       break;
     case k_Immediate:
       Imm = o.Imm;
       break;
     case k_ShiftedImm:
       ShiftedImm = o.ShiftedImm;
       break;
+    case k_ImmRange:
+      ImmRange = o.ImmRange;
+      break;
     case k_CondCode:
       CondCode = o.CondCode;
       break;
     case k_FPImm:
       FPImm = o.FPImm;
       break;
     case k_Barrier:
       Barrier = o.Barrier;
const MCExpr *getShiftedImmVal() const {
     return ShiftedImm.Val;
   }
 
   unsigned getShiftedImmShift() const {
     assert(Kind == k_ShiftedImm && "Invalid access!");
     return ShiftedImm.ShiftAmount;
   }
 
+  unsigned getFirstImmVal() const {
+    assert(Kind == k_ImmRange && "Invalid access!");
+    return ImmRange.First;
+  }
+
+  unsigned getLastImmVal() const {
+    assert(Kind == k_ImmRange && "Invalid access!");
+    return ImmRange.Last;
+  }
+
   AArch64CC::CondCode getCondCode() const {
     assert(Kind == k_CondCode && "Invalid access!");
     return CondCode.Code;
   }
 
   APFloat getFPImm() const {
     assert (Kind == k_FPImm && "Invalid access!");
     return APFloat(APFloat::IEEEdouble(), APInt(64, FPImm.Val, true));
public:
   }
 
   template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
 
   template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
     return isImmScaled<Bits, Scale>(true);
   }
 
-  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
-    return isImmScaled<Bits, Scale>(false);
+  template <int Bits, int Scale, int Offset = 0, bool IsRange = false>
+  DiagnosticPredicate isUImmScaled() const {
+    if (IsRange && isImmRange() &&
+        (getLastImmVal() != getFirstImmVal() + Offset))
+      return DiagnosticPredicateTy::NoMatch;
+
+    return isImmScaled<Bits, Scale, IsRange>(false);
   }
 
-  template <int Bits, int Scale>
+  template <int Bits, int Scale, bool IsRange = false>
   DiagnosticPredicate isImmScaled(bool Signed) const {
-    if (!isImm())
+    if ((!isImm() && !isImmRange()) || (isImm() && IsRange) ||
+        (isImmRange() && !IsRange))
       return DiagnosticPredicateTy::NoMatch;
 
+    int64_t Val;
+    if (isImmRange())
+      Val = getFirstImmVal();
+    else {
       const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
       if (!MCE)
         return DiagnosticPredicateTy::NoMatch;
+      Val = MCE->getValue();
+    }
 
     int64_t MinVal, MaxVal;
     if (Signed) {
       int64_t Shift = Bits - 1;
       MinVal = (int64_t(1) << Shift) * -Scale;
       MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
     } else {
       MinVal = 0;
       MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
     }
 
-    int64_t Val = MCE->getValue();
     if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0)
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;
   }
 
   DiagnosticPredicate isSVEPattern() const {
     if (!isImm())
bool isLogicalImm() const {
     if ((Val & Upper) && (Val & Upper) != Upper)
       return false;
 
     return AArch64_AM::isLogicalImmediate(Val & ~Upper, sizeof(T) * 8);
   }
 
   bool isShiftedImm() const { return Kind == k_ShiftedImm; }
 
+  bool isImmRange() const { return Kind == k_ImmRange; }
+
   /// Returns the immediate value as a pair of (imm, shift) if the immediate is
   /// a shifted immediate by value 'Shift' or '0', or if it is an unshifted
   /// immediate that can be shifted by 'Shift'.
   template <unsigned Width>
   Optional<std::pair<int64_t, unsigned> > getShiftedVal() const {
     if (isShiftedImm() && Width == getShiftedImmShift())
       if (auto *CE = dyn_cast<MCConstantExpr>(getShiftedImmVal()))
         return std::make_pair(CE->getValue(), Width);

 
   template <int Scale>
   void addImmScaledOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
     Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
   }
 
+  template <int Scale>
+  void addImmScaledRangeOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getFirstImmVal() / Scale));
+  }
+
   template <typename T>
   void addLogicalImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
     std::make_unsigned_t<T> Val = MCE->getValue();
     uint64_t encoding = AArch64_AM::encodeLogicalImmediate(Val, sizeof(T) * 8);
     Inst.addOperand(MCOperand::createImm(encoding));
   }
static std::unique_ptr<AArch64Operand> CreateShiftedImm(const MCExpr *Val,
     auto Op = std::make_unique<AArch64Operand>(k_ShiftedImm, Ctx);
     Op->ShiftedImm .Val = Val;
     Op->ShiftedImm.ShiftAmount = ShiftAmount;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static std::unique_ptr<AArch64Operand> CreateImmRange(unsigned First,
+                                                        unsigned Last, SMLoc S,
+                                                        SMLoc E,
+                                                        MCContext &Ctx) {
+    auto Op = std::make_unique<AArch64Operand>(k_ImmRange, Ctx);
+    Op->ImmRange.First = First;
+    Op->ImmRange.Last = Last;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static std::unique_ptr<AArch64Operand>
   CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) {
     auto Op = std::make_unique<AArch64Operand>(k_CondCode, Ctx);
     Op->CondCode.Code = Code;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
case k_Immediate:
     break;
   case k_ShiftedImm: {
     unsigned Shift = getShiftedImmShift();
     OS << "<shiftedimm ";
     OS << *getShiftedImmVal();
     OS << ", lsl #" << AArch64_AM::getShiftValue(Shift) << ">";
     break;
   }
+  case k_ImmRange: {
+    OS << "<immrange ";
+    OS << getFirstImmVal();
+    OS << ":" << getLastImmVal() << ">";
+    break;
+  }
   case k_CondCode:
     OS << "<condcode " << getCondCode() << ">";
     break;
   case k_VectorList: {
     OS << "<vectorlist ";
     unsigned Reg = getVectorListStart();
     for (unsigned i = 0, e = getVectorListCount(); i != e; ++i)
       OS << Reg + i << " ";
AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
   SMLoc S = getLoc();
 
   if (getTok().is(AsmToken::Hash))
     Lex(); // Eat '#'
   else if (getTok().isNot(AsmToken::Integer))
     // Operand should start from # or should be integer, emit error otherwise.
     return MatchOperand_NoMatch;
 
+  if (getTok().is(AsmToken::Integer) &&
+      getLexer().peekTok().is(AsmToken::Colon))
+    return tryParseImmRange(Operands);
+
   const MCExpr *Imm = nullptr;
   if (parseSymbolicImmVal(Imm))
     return MatchOperand_ParseFail;
   else if (getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(
         AArch64Operand::CreateImm(Imm, S, getLoc(), getContext()));
     return MatchOperand_Success;
   }
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidImm1_8:
     return Error(Loc, "immediate must be an integer in range [1, 8].");
   case Match_InvalidImm1_16:
     return Error(Loc, "immediate must be an integer in range [1, 16].");
   case Match_InvalidImm1_32:
     return Error(Loc, "immediate must be an integer in range [1, 32].");
   case Match_InvalidImm1_64:
     return Error(Loc, "immediate must be an integer in range [1, 64].");
+  case Match_InvalidMemoryIndexedRange2UImm2:
+  case Match_InvalidMemoryIndexedRange2UImm3:
+    return Error(
+        Loc,
+        "vector select offset must be an immediate range of the form "
+        "<immf>:<imml>, "
+        "where the first immediate is a multiple of 2 in the range [0, 6] or "
+        "[0, 14] "
+        "depending on the instruction, and the second immediate is immf + 1.");
   case Match_InvalidSVEAddSubImm8:
     return Error(Loc, "immediate must be an integer in range [0, 255]"
                       " with a shift amount of 0");
   case Match_InvalidSVEAddSubImm16:
   case Match_InvalidSVEAddSubImm32:
   case Match_InvalidSVEAddSubImm64:
     return Error(Loc, "immediate must be an integer in range [0, 255] or a "
                       "multiple of 256 in range [256, 65280]");
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidImm0_63:
   case Match_InvalidImm0_127:
   case Match_InvalidImm0_255:
   case Match_InvalidImm0_65535:
   case Match_InvalidImm1_8:
   case Match_InvalidImm1_16:
   case Match_InvalidImm1_32:
   case Match_InvalidImm1_64:
+  case Match_InvalidMemoryIndexedRange2UImm2:
+  case Match_InvalidMemoryIndexedRange2UImm3:
   case Match_InvalidSVEAddSubImm8:
   case Match_InvalidSVEAddSubImm16:
   case Match_InvalidSVEAddSubImm32:
   case Match_InvalidSVEAddSubImm64:
   case Match_InvalidSVECpyImm8:
   case Match_InvalidSVECpyImm16:
   case Match_InvalidSVECpyImm32:
   case Match_InvalidSVECpyImm64:
if (!X8Reg) {
     Error(SS, "expected an even-numbered x-register in the range [x0,x22]");
     return MatchOperand_ParseFail;
   }
 
   Operands.push_back(
       AArch64Operand::CreateReg(X8Reg, RegKind::Scalar, SS, getLoc(), ctx));
   return MatchOperand_Success;
 }
+
+OperandMatchResultTy
+AArch64AsmParser::tryParseImmRange(OperandVector &Operands) {
+  SMLoc S = getLoc();
+
+  if (getTok().isNot(AsmToken::Integer))
+    return MatchOperand_NoMatch;
+
+  if (getLexer().peekTok().isNot(AsmToken::Colon))
+    return MatchOperand_NoMatch;
+
+  const MCExpr *ImmF;
+  if (getParser().parseExpression(ImmF))
+    return MatchOperand_NoMatch;
+
+  if (getTok().isNot(AsmToken::Colon))
+    return MatchOperand_NoMatch;
+
+  Lex(); // Eat ':'
+  if (getTok().isNot(AsmToken::Integer))
+    return MatchOperand_NoMatch;
+
+  SMLoc E = getTok().getLoc();
+  const MCExpr *ImmL;
+  if (getParser().parseExpression(ImmL))
+    return MatchOperand_NoMatch;
+
+  unsigned ImmFVal = dyn_cast<MCConstantExpr>(ImmF)->getValue();
+  unsigned ImmLVal = dyn_cast<MCConstantExpr>(ImmL)->getValue();
+
+  Operands.push_back(
+      AArch64Operand::CreateImmRange(ImmFVal, ImmLVal, S, E, getContext()));
+  return MatchOperand_Success;
+}

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

protected:
 
   void printAMNoIndex(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
 
   template <int Scale>
   void printImmScale(const MCInst *MI, unsigned OpNum,
                      const MCSubtargetInfo &STI, raw_ostream &O);
 
+  template <int Scale, int Offset>
+  void printImmRangeScale(const MCInst *MI, unsigned OpNum,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+
   template <bool IsSVEPrefetch = false>
   void printPrefetchOp(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
 
   void printPSBHintOp(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
 
   void printBTIHintOp(const MCInst *MI, unsigned OpNum,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

 template<int Scale>
 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
   O << markup("<imm:") << '#'
     << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
 }
 
+template <int Scale, int Offset>
+void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
+                                            const MCSubtargetInfo &STI,
+                                            raw_ostream &O) {
+  unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
+  O << formatImm(FirstImm);
+  O << ":" << formatImm(FirstImm + Offset);
+}
+
 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
                                            unsigned Scale, raw_ostream &O) {
   const MCOperand MO = MI->getOperand(OpNum);
   if (MO.isImm()) {
     O << markup("<imm:") << '#' << formatImm(MO.getImm() * Scale)
       << markup(">");
   } else {
     assert(MO.isExpr() && "Unexpected operand type!");

llvm/lib/Target/AArch64/SMEInstrFormats.td

 
 multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
   def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
   def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
   def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
   def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
 }
 
+//===----------------------------------------------------------------------===//
+// SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources
+
+class sme2_mla_long_array_index_base<bits<2> op0, bits<2> op, Operand index_ty,
+                                RegisterOperand multi_vector_ty,
+                                string mnemonic, string vg_acronym="">
+    : I<(outs MatrixOp32:$ZAda),
+        (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm, multi_vector_ty:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3),
+        mnemonic, "\t$ZAda[$Rv, $imm" # !if(!eq(vg_acronym, ""), "", ", " # vg_acronym) # "], $Zn, $Zm$i3",
+        "", []>, Sched<[]> {
+  bits<4> Zm;
+  bits<2> Rv;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = op0;
+  let Inst{21}    = 0b0;
+  let Inst{20}    = !if(!eq(vg_acronym, ""), 0, 1);
+  let Inst{19-16} = Zm;
+  let Inst{14-13} = Rv;
+  let Inst{12}    = 0b1;
+  let Inst{4-3}   = op;
+
+  let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_mla_long_array_index<string mnemonic, bits<2> op0, bits<2> op> {
+  def _S : sme2_mla_long_array_index_base<op0, op, uimm3s2range, ZPR16,
+                                mnemonic> {
+    bits<3> i3;
+    bits<5> Zn;
+    bits<3> imm;
+    let Inst{15}    = i3{2};
+    let Inst{11-10} = i3{1-0};
+    let Inst{9-5}   = Zn;
+    let Inst{2-0}   = imm;
+  }
+}
+
+class sme2_mla_long_array_vg2_index<string mnemonic, bits<2> op0, bits<2> op>
+    : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZ_h_mul_r,
+                                mnemonic, "vgx2"> {
+  bits<3> i3;
+  bits<4> Zn;
+  bits<2> imm;
+  let Inst{15}    = 0b0;
+  let Inst{11-10} = i3{2-1};
+  let Inst{9-6}   = Zn;
+  let Inst{5}     = 0b0;
+  let Inst{2}     = i3{0};
+  let Inst{1-0}   = imm;
+}
+
+multiclass sme2_fp_mla_long_array_vg2_index<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg2_index<mnemonic, 0b10, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i3",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg2_index<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg2_index<mnemonic, 0b11, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i3",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3), 0>;
+}
+
+class sme2_mla_long_array_vg4_index<string mnemonic, bits<2> op0, bits<2> op>
+    : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZZZ_h_mul_r,
+                                mnemonic, "vgx4"> {
+  bits<3> i3;
+  bits<3> Zn;
+  bits<2> imm;
+  let Inst{15}    = 0b1;
+  let Inst{11-10} = i3{2-1};
+  let Inst{9-7}   = Zn;
+  let Inst{6-5}   = 0b00;
+  let Inst{2}     = i3{0};
+  let Inst{1-0}   = imm;
+}
+
+multiclass sme2_fp_mla_long_array_vg4_index<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg4_index<mnemonic, 0b10, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i3",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg4_index<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg4_index<mnemonic, 0b11, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i3",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i3), 0>;
+}
+
+class sme2_mla_long_array<bits<2>op0, bits<2> op, Operand index_ty,
+                                 RegisterOperand first_vector_ty,
+                                 RegisterOperand second_vector_ty,
+                                 string mnemonic, string vg_acronym="">
+   : I<(outs MatrixOp32:$ZAda),
+       (ins  MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv,
+       index_ty:$imm, first_vector_ty:$Zn, second_vector_ty:$Zm),
+       mnemonic,"\t$ZAda[$Rv, $imm" # !if(!eq(vg_acronym, ""), "", ", " # vg_acronym) # "], $Zn, $Zm",
+       "", []> , Sched<[]> {
+  bits<2> Rv;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = op0;
+  let Inst{21}    = 0b1;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = Rv;
+  let Inst{12-11} = 0b01;
+  let Inst{10}    = !if(!eq(vg_acronym, ""), 1, 0);
+  let Inst{4-3}   = op;
+
+  let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_mla_long_array_single<string mnemonic, bits<2> op0, bits<2> op> {
+  def _S : sme2_mla_long_array<op0, op, uimm3s2range, ZPR16, ZPR4b16,
+                                 mnemonic> {
+    bits<4> Zm;
+    bits<5> Zn;
+    bits<3> imm;
+    let Inst{20}    = 0b0;
+    let Inst{19-16} = Zm;
+    let Inst{9-5}   = Zn;
+    let Inst{2-0}   = imm;
+  }
+}
+
+class sme2_mla_long_array_vg24_single<bits<2> op0, bit vg4, bits<2> op,
+                                      RegisterOperand first_vector_ty,
+                                      string mnemonic, string vg_acronym>
+    : sme2_mla_long_array<op0, op, uimm2s2range, first_vector_ty, ZPR4b16,
+                                 mnemonic, vg_acronym> {
+  bits<4> Zm;
+  bits<5> Zn;
+  bits<2> imm;
+  let Inst{20}    = vg4;
+  let Inst{19-16} = Zm;
+  let Inst{9-5}   = Zn;
+  let Inst{2}     = 0b0;
+  let Inst{1-0}   = imm;
+}
+
+multiclass sme2_fp_mla_long_array_vg2_single<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg24_single<0b00, 0b0, op, ZZ_h, mnemonic,
+                                             "vgx2">;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZ_h:$Zn, ZPR4b16:$Zm), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg2_single<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg24_single<0b01, 0b0, op, ZZ_h, mnemonic,
+                                             "vgx2">;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZ_h:$Zn, ZPR4b16:$Zm), 0>;
+}
+
+multiclass sme2_fp_mla_long_array_vg4_single<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg24_single<0b00, 0b1, op, ZZZZ_h, mnemonic,
+                                             "vgx4">;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZZZ_h:$Zn, ZPR4b16:$Zm), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg4_single<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg24_single<0b01, 0b1, op, ZZZZ_h, mnemonic,
+                                             "vgx4">;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZZZ_h:$Zn, ZPR4b16:$Zm), 0>;
+}
+class sme2_mla_long_array_vg2_multi<string mnemonic, bits<2> op0, bits<2> op>
+   : sme2_mla_long_array<op0, op, uimm2s2range, ZZ_h_mul_r, ZZ_h_mul_r,  mnemonic,
+                                    "vgx2"> {
+  bits<4> Zm;
+  bits<4> Zn;
+  bits<2> imm;
+  let Inst{20-17} = Zm;
+  let Inst{16}    = 0b0;
+  let Inst{9-6}   = Zn;
+  let Inst{5}     = 0b0;
+  let Inst{2}     = 0b0;
+  let Inst{1-0}   = imm;
+}
+
+multiclass sme2_fp_mla_long_array_vg2_multi<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg2_multi<mnemonic, 0b10, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZ_h_mul_r:$Zn, ZZ_h_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg2_multi<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg2_multi<mnemonic, 0b11, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm2], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm2, ZZ_h_mul_r:$Zn, ZZ_h_mul_r:$Zm), 0>;
+}
+
+class sme2_mla_long_array_vg4_multi<string mnemonic, bits<2> op0, bits<2> op>
+   : sme2_mla_long_array<op0, op, uimm2s2range, ZZZZ_h_mul_r, ZZZZ_h_mul_r, mnemonic,
+                                    "vgx4"> {
+  bits<3> Zm;
+  bits<3> Zn;
+  bits<2> imm;
+  let Inst{20-18} = Zm;
+  let Inst{17}    = 0b0;
+  let Inst{16}    = 0b1;
+  let Inst{9-7}   = Zn;
+  let Inst{6-5}   = 0b00;
+  let Inst{2}     = 0b0;
+  let Inst{1-0}   = imm;
+}
+
+multiclass sme2_fp_mla_long_array_vg4_multi<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg4_multi<mnemonic, 0b10, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm, ZZZZ_h_mul_r:$Zn, ZZZZ_h_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_int_mla_long_array_vg4_multi<string mnemonic, bits<2> op> {
+  def _S : sme2_mla_long_array_vg4_multi<mnemonic, 0b11, op>;
+
+  def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm2], $Zn, $Zm",
+                 (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm2, ZZZZ_h_mul_r:$Zn, ZZZZ_h_mul_r:$Zm), 0>;
+}

llvm/test/MC/AArch64/SME2/bfmlal-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+bfmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: bfmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: bfmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+bfmlal za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: bfmlal za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w8, 0:1], z0.h, z30.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: bfmlal za.s[w8, 0:1], z0.h, z30.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+bfmlal za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfmlal za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfmlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+bfmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
+// CHECK-NEXT: bfmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+bfmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: bfmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/bfmlal.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+bfmlal  za.s[w8, 0:1], z0.h, z0.h  // 11000001-00100000-00001100-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x10,0x0c,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200c10 <unknown>
+
+bfmlal  za.s[w10, 10:11], z10.h, z5.h  // 11000001-00100101-01001101-01010101
+// CHECK-INST: bfmlal  za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x55,0x4d,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254d55 <unknown>
+
+bfmlal  za.s[w11, 14:15], z13.h, z8.h  // 11000001-00101000-01101101-10110111
+// CHECK-INST: bfmlal  za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x6d,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1286db7 <unknown>
+
+bfmlal  za.s[w11, 14:15], z31.h, z15.h  // 11000001-00101111-01101111-11110111
+// CHECK-INST: bfmlal  za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xf7,0x6f,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6ff7 <unknown>
+
+bfmlal  za.s[w8, 10:11], z17.h, z0.h  // 11000001-00100000-00001110-00110101
+// CHECK-INST: bfmlal  za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x35,0x0e,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200e35 <unknown>
+
+bfmlal  za.s[w8, 2:3], z1.h, z14.h  // 11000001-00101110-00001100-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x31,0x0c,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0c31 <unknown>
+
+bfmlal  za.s[w10, 0:1], z19.h, z4.h  // 11000001-00100100-01001110-01110000
+// CHECK-INST: bfmlal  za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x70,0x4e,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244e70 <unknown>
+
+bfmlal  za.s[w8, 0:1], z12.h, z2.h  // 11000001-00100010-00001101-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x90,0x0d,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220d90 <unknown>
+
+bfmlal  za.s[w10, 2:3], z1.h, z10.h  // 11000001-00101010-01001100-00110001
+// CHECK-INST: bfmlal  za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x31,0x4c,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4c31 <unknown>
+
+bfmlal  za.s[w8, 10:11], z22.h, z14.h  // 11000001-00101110-00001110-11010101
+// CHECK-INST: bfmlal  za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xd5,0x0e,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ed5 <unknown>
+
+bfmlal  za.s[w11, 4:5], z9.h, z1.h  // 11000001-00100001-01101101-00110010
+// CHECK-INST: bfmlal  za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x32,0x6d,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216d32 <unknown>
+
+bfmlal  za.s[w9, 14:15], z12.h, z11.h  // 11000001-00101011-00101101-10010111
+// CHECK-INST: bfmlal  za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x97,0x2d,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2d97 <unknown>
+
+
+bfmlal  za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-10000000-00010000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801010 <unknown>
+
+bfmlal  za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-10000101-01010101-01010101
+// CHECK-INST: bfmlal  za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x55,0x55,0x85,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1855555 <unknown>
+
+bfmlal  za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-10001000-11111101-10110111
+// CHECK-INST: bfmlal  za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xb7,0xfd,0x88,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c188fdb7 <unknown>
+
+bfmlal  za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-10001111-11111111-11110111
+// CHECK-INST: bfmlal  za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xf7,0xff,0x8f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18ffff7 <unknown>
+
+bfmlal  za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-10000000-00011110-00110101
+// CHECK-INST: bfmlal  za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x35,0x1e,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801e35 <unknown>
+
+bfmlal  za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-10001110-10010100-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x31,0x94,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e9431 <unknown>
+
+bfmlal  za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-10000100-01010110-01110000
+// CHECK-INST: bfmlal  za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x70,0x56,0x84,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1845670 <unknown>
+
+bfmlal  za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-10000010-00011001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x90,0x19,0x82,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1821990 <unknown>
+
+bfmlal  za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-10001010-11011000-00110001
+// CHECK-INST: bfmlal  za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x31,0xd8,0x8a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18ad831 <unknown>
+
+bfmlal  za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-10001110-00011010-11010101
+// CHECK-INST: bfmlal  za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xd5,0x1a,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e1ad5 <unknown>
+
+bfmlal  za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-10000001-11110101-00110010
+// CHECK-INST: bfmlal  za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x32,0xf5,0x81,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c181f532 <unknown>
+
+bfmlal  za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-10001011-10111001-10010111
+// CHECK-INST: bfmlal  za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x97,0xb9,0x8b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18bb997 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 00100000, 00001000, 00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200810 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-00100000-00001000-00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200810 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 00100101, 01001001, 01010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254951 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-00100101-01001001-01010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254951 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 00101000, 01101001, 10110011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869b3 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-00101000-01101001-10110011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869b3 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 00101111, 01101011, 11110011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6bf3 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-00101111-01101011-11110011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6bf3 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 00100000, 00001010, 00110001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a31 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-00100000-00001010-00110001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a31 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 00101110, 00001000, 00110001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0831 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-00101110-00001000-00110001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0831 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 00100100, 01001010, 01110000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a70 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-00100100-01001010-01110000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a70 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 00100010, 00001001, 10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-00100010-00001001-10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 00101010, 01001000, 00110001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4831 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-00101010-01001000-00110001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4831 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 00101110, 00001010, 11010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ad1 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-00101110-00001010-11010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ad1 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 00100001, 01101001, 00110010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216932 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-00100001-01101001-00110010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216932 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 00101011, 00101001, 10010011
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2993 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-00101011-00101001-10010011
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2993 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 10010000, 00010000, 00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901010 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-10010000-00010000-00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901010 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 10010101, 01010101, 01010101
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1955555 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-10010101-01010101-01010101
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1955555 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 10011000, 01111101, 10010111
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d97 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-10011000-01111101-10010111
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d97 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 10011111, 01111111, 11010111
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xd7,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fd7 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-10011111-01111111-11010111
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xd7,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fd7 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 10010000, 00011110, 00010101
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e15 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-10010000-00011110-00010101
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e15 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 10011110, 00010100, 00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1411 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-10011110-00010100-00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1411 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 10010100, 01010110, 01010000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x50,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945650 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-10010100-01010110-01010000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x50,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945650 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 10010010, 00011001, 10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-10010010-00011001-10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 10011010, 01011000, 00010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5811 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-10011010-01011000-00010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5811 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 10011110, 00011010, 11010101
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xd5,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1ad5 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-10011110-00011010-11010101
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xd5,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1ad5 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 10010001, 01110101, 00010010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1917512 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-10010001-01110101-00010010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1917512 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 10011011, 00111001, 10010111
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b3997 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-10011011-00111001-10010111
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b3997 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 10100000, 00001000, 00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x10,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00810 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-10100000-00001000-00010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x10,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00810 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001001, 01010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x51,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44951 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-10110100-01001001-01010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x51,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44951 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 10101000, 01101001, 10010011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x93,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a86993 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-10101000-01101001-10010011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x93,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a86993 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 10111110, 01101011, 11010011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd3,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bd3 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-10111110-01101011-11010011
+// CHECK, INST: bfmlal  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd3,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bd3 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 10110000, 00001010, 00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x11,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a11 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-10110000-00001010-00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x11,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a11 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001000, 00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0811 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-10111110-00001000-00010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0811 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001010, 01010000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x50,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a50 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-10110100-01001010-01010000
+// CHECK, INST: bfmlal  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x50,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a50 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 10100010, 00001001, 10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-10100010-00001001-10010000
+// CHECK, INST: bfmlal  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 10111010, 01001000, 00010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4811 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-10111010-01001000-00010001
+// CHECK, INST: bfmlal  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4811 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001010, 11010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd1,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ad1 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-10111110-00001010-11010001
+// CHECK, INST: bfmlal  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd1,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ad1 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 10100000, 01101001, 00010010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x12,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a06912 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-10100000-01101001-00010010
+// CHECK, INST: bfmlal  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x12,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a06912 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 10101010, 00101001, 10010011
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa2993 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-10101010-00101001-10010011
+// CHECK, INST: bfmlal  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa2993 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300810 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300810 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354951 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354951 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10110011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869b3 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10110011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869b3 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z31.h - z2.h}, z15.h  // 11000001-00111111-01101011-11110011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6bf3 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z31.h - z2.h}, z15.h  // 11000001-00111111-01101011-11110011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6bf3 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a31 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a31 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0831 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00110001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0831 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01110000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a70 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01110000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a70 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00110001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4831 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00110001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4831 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ad1 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ad1 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00110010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1316932 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00110010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1316932 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10010011
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b2993 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10010011
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b2993 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909010 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909010 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00010101
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x15,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d515 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00010101
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x15,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d515 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10010111
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd97 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10010111
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd97 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10010111
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x97,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff97 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10010111
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x97,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff97 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00010101
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e15 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00010101
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e15 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9411 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9411 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00010000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x10,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d610 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00010000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x10,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d610 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad811 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad811 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10010101
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x95,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a95 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10010101
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x95,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a95 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00010010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f512 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00010010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f512 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10010111
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb997 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10010111
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb997 <unknown>
+
+
+bfmlal  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x10,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10810 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x10,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10810 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x11,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54911 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x11,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54911 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10010011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a96993 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10010011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a96993 <unknown>
+
+bfmlal  za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10010011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x93,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b93 <unknown>
+
+bfmlal  za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10010011
+// CHECK-INST: bfmlal  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x93,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b93 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x11,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a11 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x11,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a11 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0811 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0811 <unknown>
+
+bfmlal  za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00010000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x10,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a10 <unknown>
+
+bfmlal  za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00010000
+// CHECK-INST: bfmlal  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x10,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a10 <unknown>
+
+bfmlal  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10990 <unknown>
+
+bfmlal  za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10010000
+// CHECK-INST: bfmlal  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10990 <unknown>
+
+bfmlal  za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94811 <unknown>
+
+bfmlal  za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00010001
+// CHECK-INST: bfmlal  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94811 <unknown>
+
+bfmlal  za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x91,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a91 <unknown>
+
+bfmlal  za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10010001
+// CHECK-INST: bfmlal  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x91,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a91 <unknown>
+
+bfmlal  za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00010010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x12,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a16912 <unknown>
+
+bfmlal  za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00010010
+// CHECK-INST: bfmlal  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x12,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a16912 <unknown>
+
+bfmlal  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10010011
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a92993 <unknown>
+
+bfmlal  za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10010011
+// CHECK-INST: bfmlal  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a92993 <unknown>
+

llvm/test/MC/AArch64/SME2/bfmlsl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+bfmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: bfmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+bfmlsl za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: bfmlsl za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w8, 0:1], z0.h, z30.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: bfmlsl za.s[w8, 0:1], z0.h, z30.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+bfmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+bfmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
+// CHECK-NEXT: bfmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+bfmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: bfmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/bfmlsl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+bfmlsl  za.s[w8, 0:1], z0.h, z0.h  // 11000001-00100000-00001100-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x18,0x0c,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200c18 <unknown>
+
+bfmlsl  za.s[w10, 10:11], z10.h, z5.h  // 11000001-00100101-01001101-01011101
+// CHECK-INST: bfmlsl  za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x5d,0x4d,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254d5d <unknown>
+
+bfmlsl  za.s[w11, 14:15], z13.h, z8.h  // 11000001-00101000-01101101-10111111
+// CHECK-INST: bfmlsl  za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xbf,0x6d,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1286dbf <unknown>
+
+bfmlsl  za.s[w11, 14:15], z31.h, z15.h  // 11000001-00101111-01101111-11111111
+// CHECK-INST: bfmlsl  za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xff,0x6f,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6fff <unknown>
+
+bfmlsl  za.s[w8, 10:11], z17.h, z0.h  // 11000001-00100000-00001110-00111101
+// CHECK-INST: bfmlsl  za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x3d,0x0e,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200e3d <unknown>
+
+bfmlsl  za.s[w8, 2:3], z1.h, z14.h  // 11000001-00101110-00001100-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x39,0x0c,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0c39 <unknown>
+
+bfmlsl  za.s[w10, 0:1], z19.h, z4.h  // 11000001-00100100-01001110-01111000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x78,0x4e,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244e78 <unknown>
+
+bfmlsl  za.s[w8, 0:1], z12.h, z2.h  // 11000001-00100010-00001101-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x98,0x0d,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220d98 <unknown>
+
+bfmlsl  za.s[w10, 2:3], z1.h, z10.h  // 11000001-00101010-01001100-00111001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x39,0x4c,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4c39 <unknown>
+
+bfmlsl  za.s[w8, 10:11], z22.h, z14.h  // 11000001-00101110-00001110-11011101
+// CHECK-INST: bfmlsl  za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xdd,0x0e,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0edd <unknown>
+
+bfmlsl  za.s[w11, 4:5], z9.h, z1.h  // 11000001-00100001-01101101-00111010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x3a,0x6d,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216d3a <unknown>
+
+bfmlsl  za.s[w9, 14:15], z12.h, z11.h  // 11000001-00101011-00101101-10011111
+// CHECK-INST: bfmlsl  za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x9f,0x2d,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2d9f <unknown>
+
+
+bfmlsl  za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-10000000-00010000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801018 <unknown>
+
+bfmlsl  za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-10000101-01010101-01011101
+// CHECK-INST: bfmlsl  za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x55,0x85,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c185555d <unknown>
+
+bfmlsl  za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-10001000-11111101-10111111
+// CHECK-INST: bfmlsl  za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xbf,0xfd,0x88,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c188fdbf <unknown>
+
+bfmlsl  za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-10001111-11111111-11111111
+// CHECK-INST: bfmlsl  za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xff,0xff,0x8f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18fffff <unknown>
+
+bfmlsl  za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-10000000-00011110-00111101
+// CHECK-INST: bfmlsl  za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x3d,0x1e,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801e3d <unknown>
+
+bfmlsl  za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-10001110-10010100-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x39,0x94,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e9439 <unknown>
+
+bfmlsl  za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-10000100-01010110-01111000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x78,0x56,0x84,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1845678 <unknown>
+
+bfmlsl  za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-10000010-00011001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x98,0x19,0x82,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1821998 <unknown>
+
+bfmlsl  za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-10001010-11011000-00111001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x39,0xd8,0x8a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18ad839 <unknown>
+
+bfmlsl  za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-10001110-00011010-11011101
+// CHECK-INST: bfmlsl  za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x1a,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e1add <unknown>
+
+bfmlsl  za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-10000001-11110101-00111010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x3a,0xf5,0x81,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c181f53a <unknown>
+
+bfmlsl  za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-10001011-10111001-10011111
+// CHECK-INST: bfmlsl  za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x9f,0xb9,0x8b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18bb99f <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 00100000, 00001000, 00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200818 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-00100000-00001000-00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200818 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 00100101, 01001001, 01011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254959 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-00100101-01001001-01011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254959 <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 00101000, 01101001, 10111011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869bb <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-00101000-01101001-10111011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869bb <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 00101111, 01101011, 11111011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6bfb <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-00101111-01101011-11111011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6bfb <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 00100000, 00001010, 00111001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a39 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-00100000-00001010-00111001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a39 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 00101110, 00001000, 00111001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0839 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-00101110-00001000-00111001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0839 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 00100100, 01001010, 01111000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a78 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-00100100-01001010-01111000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a78 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 00100010, 00001001, 10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-00100010-00001001-10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 00101010, 01001000, 00111001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4839 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-00101010-01001000-00111001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4839 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 00101110, 00001010, 11011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ad9 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-00101110-00001010-11011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ad9 <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 00100001, 01101001, 00111010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c121693a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-00100001-01101001-00111010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c121693a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 00101011, 00101001, 10011011
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b299b <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-00101011-00101001-10011011
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b299b <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 10010000, 00010000, 00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901018 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-10010000-00010000-00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901018 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 10010101, 01010101, 01011101
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x5d,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195555d <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-10010101-01010101-01011101
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x5d,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195555d <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 10011000, 01111101, 10011111
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d9f <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-10011000-01111101-10011111
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d9f <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 10011111, 01111111, 11011111
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xdf,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fdf <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-10011111-01111111-11011111
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xdf,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fdf <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 10010000, 00011110, 00011101
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e1d <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-10010000-00011110-00011101
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e1d <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 10011110, 00010100, 00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1419 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-10011110-00010100-00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1419 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 10010100, 01010110, 01011000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x58,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945658 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-10010100-01010110-01011000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x58,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945658 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 10010010, 00011001, 10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-10010010-00011001-10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 10011010, 01011000, 00011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5819 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-10011010-01011000-00011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5819 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 10011110, 00011010, 11011101
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xdd,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1add <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-10011110-00011010-11011101
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xdd,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1add <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 10010001, 01110101, 00011010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191751a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-10010001-01110101-00011010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191751a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 10011011, 00111001, 10011111
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b399f <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-10011011-00111001-10011111
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b399f <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 10100000, 00001000, 00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x18,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00818 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-10100000-00001000-00011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x18,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00818 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001001, 01011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x59,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44959 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-10110100-01001001-01011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x59,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44959 <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 10101000, 01101001, 10011011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x9b,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8699b <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-10101000-01101001-10011011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x9b,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8699b <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 10111110, 01101011, 11011011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdb,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bdb <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-10111110-01101011-11011011
+// CHECK, INST: bfmlsl  za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdb,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bdb <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 10110000, 00001010, 00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x19,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a19 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-10110000-00001010-00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x19,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a19 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001000, 00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0819 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-10111110-00001000-00011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0819 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001010, 01011000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x58,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a58 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-10110100-01001010-01011000
+// CHECK, INST: bfmlsl  za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x58,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a58 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 10100010, 00001001, 10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-10100010-00001001-10011000
+// CHECK, INST: bfmlsl  za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 10111010, 01001000, 00011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4819 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-10111010-01001000-00011001
+// CHECK, INST: bfmlsl  za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4819 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001010, 11011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd9,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ad9 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-10111110-00001010-11011001
+// CHECK, INST: bfmlsl  za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd9,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ad9 <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 10100000, 01101001, 00011010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x1a,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0691a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-10100000-01101001-00011010
+// CHECK, INST: bfmlsl  za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x1a,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0691a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 10101010, 00101001, 10011011
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa299b <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-10101010-00101001-10011011
+// CHECK, INST: bfmlsl  za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa299b <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300818 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300818 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354959 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354959 <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10111011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869bb <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10111011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869bb <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z31.h - z2.h}, z15.h  // 11000001-00111111-01101011-11111011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6bfb <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z31.h - z2.h}, z15.h  // 11000001-00111111-01101011-11111011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6bfb <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a39 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a39 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0839 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00111001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0839 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01111000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a78 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01111000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a78 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00111001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4839 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00111001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4839 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ad9 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ad9 <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00111010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c131693a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00111010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c131693a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10011011
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b299b <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10011011
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b299b <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909018 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909018 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00011101
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x1d,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d51d <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00011101
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x1d,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d51d <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10011111
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd9f <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10011111
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd9f <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10011111
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x9f,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff9f <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10011111
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x9f,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff9f <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00011101
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e1d <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00011101
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e1d <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9419 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9419 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00011000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x18,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d618 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00011000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x18,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d618 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad819 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad819 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10011101
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x9d,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a9d <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10011101
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x9d,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a9d <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00011010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f51a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00011010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f51a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10011111
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb99f <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10011111
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb99f <unknown>
+
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x18,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10818 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x18,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10818 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x19,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54919 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x19,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54919 <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10011011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9699b <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10011011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9699b <unknown>
+
+bfmlsl  za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10011011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9b,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b9b <unknown>
+
+bfmlsl  za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10011011
+// CHECK-INST: bfmlsl  za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9b,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b9b <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x19,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a19 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x19,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a19 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0819 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0819 <unknown>
+
+bfmlsl  za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00011000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x18,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a18 <unknown>
+
+bfmlsl  za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00011000
+// CHECK-INST: bfmlsl  za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x18,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a18 <unknown>
+
+bfmlsl  za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10998 <unknown>
+
+bfmlsl  za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10011000
+// CHECK-INST: bfmlsl  za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10998 <unknown>
+
+bfmlsl  za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94819 <unknown>
+
+bfmlsl  za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00011001
+// CHECK-INST: bfmlsl  za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94819 <unknown>
+
+bfmlsl  za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x99,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a99 <unknown>
+
+bfmlsl  za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10011001
+// CHECK-INST: bfmlsl  za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x99,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a99 <unknown>
+
+bfmlsl  za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00011010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x1a,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1691a <unknown>
+
+bfmlsl  za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00011010
+// CHECK-INST: bfmlsl  za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x1a,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1691a <unknown>
+
+bfmlsl  za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10011011
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9299b <unknown>
+
+bfmlsl  za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10011011
+// CHECK-INST: bfmlsl  za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9299b <unknown>
+

llvm/test/MC/AArch64/SME2/fmlal-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+fmlal za.s[w8, 0:1], z0.h, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmlal za.s[w8, 0:1], z0.h, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlal za.s[w8, 0:1], z0.h, z30.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmlal za.s[w8, 0:1], z0.h, z30.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+fmlal za.s[w3, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fmlal za.s[w3, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+fmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
+// CHECK-NEXT: fmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: fmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fmlal.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmlal   za.s[w8, 0:1], z0.h, z0.h  // 11000001-00100000-00001100-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x0c,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200c00 <unknown>
+
+fmlal   za.s[w10, 10:11], z10.h, z5.h  // 11000001-00100101-01001101-01000101
+// CHECK-INST: fmlal   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x45,0x4d,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254d45 <unknown>
+
+fmlal   za.s[w11, 14:15], z13.h, z8.h  // 11000001-00101000-01101101-10100111
+// CHECK-INST: fmlal   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xa7,0x6d,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1286da7 <unknown>
+
+fmlal   za.s[w11, 14:15], z31.h, z15.h  // 11000001-00101111-01101111-11100111
+// CHECK-INST: fmlal   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xe7,0x6f,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6fe7 <unknown>
+
+fmlal   za.s[w8, 10:11], z17.h, z0.h  // 11000001-00100000-00001110-00100101
+// CHECK-INST: fmlal   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x25,0x0e,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200e25 <unknown>
+
+fmlal   za.s[w8, 2:3], z1.h, z14.h  // 11000001-00101110-00001100-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x21,0x0c,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0c21 <unknown>
+
+fmlal   za.s[w10, 0:1], z19.h, z4.h  // 11000001-00100100-01001110-01100000
+// CHECK-INST: fmlal   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x60,0x4e,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244e60 <unknown>
+
+fmlal   za.s[w8, 0:1], z12.h, z2.h  // 11000001-00100010-00001101-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x80,0x0d,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220d80 <unknown>
+
+fmlal   za.s[w10, 2:3], z1.h, z10.h  // 11000001-00101010-01001100-00100001
+// CHECK-INST: fmlal   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x21,0x4c,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4c21 <unknown>
+
+fmlal   za.s[w8, 10:11], z22.h, z14.h  // 11000001-00101110-00001110-11000101
+// CHECK-INST: fmlal   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xc5,0x0e,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ec5 <unknown>
+
+fmlal   za.s[w11, 4:5], z9.h, z1.h  // 11000001-00100001-01101101-00100010
+// CHECK-INST: fmlal   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x22,0x6d,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216d22 <unknown>
+
+fmlal   za.s[w9, 14:15], z12.h, z11.h  // 11000001-00101011-00101101-10000111
+// CHECK-INST: fmlal   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x87,0x2d,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2d87 <unknown>
+
+
+fmlal   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-10000000-00010000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801000 <unknown>
+
+fmlal   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-10000101-01010101-01000101
+// CHECK-INST: fmlal   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x45,0x55,0x85,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1855545 <unknown>
+
+fmlal   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-10001000-11111101-10100111
+// CHECK-INST: fmlal   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xa7,0xfd,0x88,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c188fda7 <unknown>
+
+fmlal   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-10001111-11111111-11100111
+// CHECK-INST: fmlal   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xe7,0xff,0x8f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18fffe7 <unknown>
+
+fmlal   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-10000000-00011110-00100101
+// CHECK-INST: fmlal   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x25,0x1e,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801e25 <unknown>
+
+fmlal   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-10001110-10010100-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x21,0x94,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e9421 <unknown>
+
+fmlal   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-10000100-01010110-01100000
+// CHECK-INST: fmlal   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x60,0x56,0x84,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1845660 <unknown>
+
+fmlal   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-10000010-00011001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x80,0x19,0x82,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1821980 <unknown>
+
+fmlal   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-10001010-11011000-00100001
+// CHECK-INST: fmlal   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x21,0xd8,0x8a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18ad821 <unknown>
+
+fmlal   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-10001110-00011010-11000101
+// CHECK-INST: fmlal   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xc5,0x1a,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e1ac5 <unknown>
+
+fmlal   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-10000001-11110101-00100010
+// CHECK-INST: fmlal   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x22,0xf5,0x81,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c181f522 <unknown>
+
+fmlal   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-10001011-10111001-10000111
+// CHECK-INST: fmlal   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x87,0xb9,0x8b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18bb987 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 00100000, 00001000, 00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200800 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-00100000-00001000-00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200800 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 00100101, 01001001, 01000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254941 <unknown>
+
+fmlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-00100101-01001001-01000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254941 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 00101000, 01101001, 10100011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869a3 <unknown>
+
+fmlal   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-00101000-01101001-10100011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869a3 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 00101111, 01101011, 11100011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6be3 <unknown>
+
+fmlal   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-00101111-01101011-11100011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6be3 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 00100000, 00001010, 00100001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a21 <unknown>
+
+fmlal   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-00100000-00001010-00100001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a21 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 00101110, 00001000, 00100001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0821 <unknown>
+
+fmlal   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-00101110-00001000-00100001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0821 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 00100100, 01001010, 01100000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a60 <unknown>
+
+fmlal   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-00100100-01001010-01100000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a60 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 00100010, 00001001, 10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-00100010-00001001-10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 00101010, 01001000, 00100001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4821 <unknown>
+
+fmlal   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-00101010-01001000-00100001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4821 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 00101110, 00001010, 11000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ac1 <unknown>
+
+fmlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-00101110-00001010-11000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ac1 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 00100001, 01101001, 00100010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216922 <unknown>
+
+fmlal   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-00100001-01101001-00100010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216922 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 00101011, 00101001, 10000011
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2983 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-00101011-00101001-10000011
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2983 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 10010000, 00010000, 00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901000 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-10010000-00010000-00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901000 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 10010101, 01010101, 01000101
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x45,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1955545 <unknown>
+
+fmlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-10010101-01010101-01000101
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x45,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1955545 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 10011000, 01111101, 10000111
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d87 <unknown>
+
+fmlal   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-10011000-01111101-10000111
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d87 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 10011111, 01111111, 11000111
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xc7,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fc7 <unknown>
+
+fmlal   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-10011111-01111111-11000111
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xc7,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fc7 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 10010000, 00011110, 00000101
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e05 <unknown>
+
+fmlal   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-10010000-00011110-00000101
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e05 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 10011110, 00010100, 00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1401 <unknown>
+
+fmlal   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-10011110-00010100-00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1401 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 10010100, 01010110, 01000000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x40,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945640 <unknown>
+
+fmlal   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-10010100-01010110-01000000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x40,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945640 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 10010010, 00011001, 10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-10010010-00011001-10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 10011010, 01011000, 00000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5801 <unknown>
+
+fmlal   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-10011010-01011000-00000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5801 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 10011110, 00011010, 11000101
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xc5,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1ac5 <unknown>
+
+fmlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-10011110-00011010-11000101
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xc5,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1ac5 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 10010001, 01110101, 00000010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1917502 <unknown>
+
+fmlal   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-10010001-01110101-00000010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1917502 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 10011011, 00111001, 10000111
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b3987 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-10011011-00111001-10000111
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b3987 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 10100000, 00001000, 00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00800 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-10100000-00001000-00000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00800 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001001, 01000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x41,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44941 <unknown>
+
+fmlal   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-10110100-01001001-01000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x41,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44941 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 10101000, 01101001, 10000011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x83,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a86983 <unknown>
+
+fmlal   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-10101000-01101001-10000011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x83,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a86983 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 10111110, 01101011, 11000011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc3,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bc3 <unknown>
+
+fmlal   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-10111110-01101011-11000011
+// CHECK, INST: fmlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc3,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bc3 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 10110000, 00001010, 00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x01,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a01 <unknown>
+
+fmlal   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-10110000-00001010-00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x01,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a01 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001000, 00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0801 <unknown>
+
+fmlal   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-10111110-00001000-00000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0801 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001010, 01000000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x40,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a40 <unknown>
+
+fmlal   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-10110100-01001010-01000000
+// CHECK, INST: fmlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x40,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a40 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 10100010, 00001001, 10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-10100010-00001001-10000000
+// CHECK, INST: fmlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 10111010, 01001000, 00000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4801 <unknown>
+
+fmlal   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-10111010-01001000-00000001
+// CHECK, INST: fmlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4801 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001010, 11000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc1,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ac1 <unknown>
+
+fmlal   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-10111110-00001010-11000001
+// CHECK, INST: fmlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc1,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ac1 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 10100000, 01101001, 00000010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x02,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a06902 <unknown>
+
+fmlal   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-10100000-01101001-00000010
+// CHECK, INST: fmlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x02,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a06902 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 10101010, 00101001, 10000011
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa2983 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-10101010-00101001-10000011
+// CHECK, INST: fmlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa2983 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300800 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300800 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354941 <unknown>
+
+fmlal   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354941 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10100011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869a3 <unknown>
+
+fmlal   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10100011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869a3 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-00111111-01101011-11100011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6be3 <unknown>
+
+fmlal   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-00111111-01101011-11100011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6be3 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a21 <unknown>
+
+fmlal   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a21 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0821 <unknown>
+
+fmlal   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00100001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0821 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01100000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a60 <unknown>
+
+fmlal   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01100000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a60 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00100001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4821 <unknown>
+
+fmlal   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00100001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4821 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ac1 <unknown>
+
+fmlal   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ac1 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00100010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1316922 <unknown>
+
+fmlal   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00100010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1316922 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10000011
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b2983 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10000011
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b2983 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909000 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909000 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00000101
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x05,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d505 <unknown>
+
+fmlal   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00000101
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x05,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d505 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10000111
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd87 <unknown>
+
+fmlal   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10000111
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd87 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10000111
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x87,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff87 <unknown>
+
+fmlal   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10000111
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x87,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff87 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00000101
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e05 <unknown>
+
+fmlal   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00000101
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e05 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9401 <unknown>
+
+fmlal   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9401 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00000000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x00,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d600 <unknown>
+
+fmlal   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00000000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x00,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d600 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad801 <unknown>
+
+fmlal   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad801 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10000101
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x85,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a85 <unknown>
+
+fmlal   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10000101
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x85,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a85 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00000010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f502 <unknown>
+
+fmlal   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00000010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f502 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10000111
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb987 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10000111
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb987 <unknown>
+
+
+fmlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10800 <unknown>
+
+fmlal   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10800 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x01,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54901 <unknown>
+
+fmlal   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x01,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54901 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10000011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a96983 <unknown>
+
+fmlal   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10000011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a96983 <unknown>
+
+fmlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10000011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x83,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b83 <unknown>
+
+fmlal   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10000011
+// CHECK-INST: fmlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x83,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b83 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x01,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a01 <unknown>
+
+fmlal   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x01,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a01 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0801 <unknown>
+
+fmlal   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0801 <unknown>
+
+fmlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00000000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x00,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a00 <unknown>
+
+fmlal   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00000000
+// CHECK-INST: fmlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x00,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a00 <unknown>
+
+fmlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10980 <unknown>
+
+fmlal   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10000000
+// CHECK-INST: fmlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10980 <unknown>
+
+fmlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94801 <unknown>
+
+fmlal   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00000001
+// CHECK-INST: fmlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94801 <unknown>
+
+fmlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x81,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a81 <unknown>
+
+fmlal   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10000001
+// CHECK-INST: fmlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x81,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a81 <unknown>
+
+fmlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00000010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a16902 <unknown>
+
+fmlal   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00000010
+// CHECK-INST: fmlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a16902 <unknown>
+
+fmlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10000011
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a92983 <unknown>
+
+fmlal   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10000011
+// CHECK-INST: fmlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a92983 <unknown>
+

llvm/test/MC/AArch64/SME2/fmlsl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fmlsl za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+fmlsl za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmlsl za.s[w8, 0:1], z0.h, z17.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlsl za.s[w8, 0:1], z0.h, z30.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fmlsl za.s[w8, 0:1], z0.h, z30.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+fmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fmlsl za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fmlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+fmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmlsl za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
+// CHECK-NEXT: fmlsl za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+fmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: fmlsl za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+fmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: fmlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fmlsl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmlsl   za.s[w8, 0:1], z0.h, z0.h  // 11000001-00100000-00001100-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x08,0x0c,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200c08 <unknown>
+
+fmlsl   za.s[w10, 10:11], z10.h, z5.h  // 11000001-00100101-01001101-01001101
+// CHECK-INST: fmlsl   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x4d,0x4d,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254d4d <unknown>
+
+fmlsl   za.s[w11, 14:15], z13.h, z8.h  // 11000001-00101000-01101101-10101111
+// CHECK-INST: fmlsl   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xaf,0x6d,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1286daf <unknown>
+
+fmlsl   za.s[w11, 14:15], z31.h, z15.h  // 11000001-00101111-01101111-11101111
+// CHECK-INST: fmlsl   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xef,0x6f,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6fef <unknown>
+
+fmlsl   za.s[w8, 10:11], z17.h, z0.h  // 11000001-00100000-00001110-00101101
+// CHECK-INST: fmlsl   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x2d,0x0e,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200e2d <unknown>
+
+fmlsl   za.s[w8, 2:3], z1.h, z14.h  // 11000001-00101110-00001100-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x29,0x0c,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0c29 <unknown>
+
+fmlsl   za.s[w10, 0:1], z19.h, z4.h  // 11000001-00100100-01001110-01101000
+// CHECK-INST: fmlsl   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x68,0x4e,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244e68 <unknown>
+
+fmlsl   za.s[w8, 0:1], z12.h, z2.h  // 11000001-00100010-00001101-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x88,0x0d,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220d88 <unknown>
+
+fmlsl   za.s[w10, 2:3], z1.h, z10.h  // 11000001-00101010-01001100-00101001
+// CHECK-INST: fmlsl   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x29,0x4c,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4c29 <unknown>
+
+fmlsl   za.s[w8, 10:11], z22.h, z14.h  // 11000001-00101110-00001110-11001101
+// CHECK-INST: fmlsl   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xcd,0x0e,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ecd <unknown>
+
+fmlsl   za.s[w11, 4:5], z9.h, z1.h  // 11000001-00100001-01101101-00101010
+// CHECK-INST: fmlsl   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x2a,0x6d,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1216d2a <unknown>
+
+fmlsl   za.s[w9, 14:15], z12.h, z11.h  // 11000001-00101011-00101101-10001111
+// CHECK-INST: fmlsl   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x8f,0x2d,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b2d8f <unknown>
+
+
+fmlsl   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-10000000-00010000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801008 <unknown>
+
+fmlsl   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-10000101-01010101-01001101
+// CHECK-INST: fmlsl   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x55,0x85,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c185554d <unknown>
+
+fmlsl   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-10001000-11111101-10101111
+// CHECK-INST: fmlsl   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xaf,0xfd,0x88,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c188fdaf <unknown>
+
+fmlsl   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-10001111-11111111-11101111
+// CHECK-INST: fmlsl   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xef,0xff,0x8f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18fffef <unknown>
+
+fmlsl   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-10000000-00011110-00101101
+// CHECK-INST: fmlsl   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x2d,0x1e,0x80,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1801e2d <unknown>
+
+fmlsl   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-10001110-10010100-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x29,0x94,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e9429 <unknown>
+
+fmlsl   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-10000100-01010110-01101000
+// CHECK-INST: fmlsl   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x68,0x56,0x84,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1845668 <unknown>
+
+fmlsl   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-10000010-00011001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x88,0x19,0x82,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1821988 <unknown>
+
+fmlsl   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-10001010-11011000-00101001
+// CHECK-INST: fmlsl   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x29,0xd8,0x8a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18ad829 <unknown>
+
+fmlsl   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-10001110-00011010-11001101
+// CHECK-INST: fmlsl   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x1a,0x8e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18e1acd <unknown>
+
+fmlsl   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-10000001-11110101-00101010
+// CHECK-INST: fmlsl   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x2a,0xf5,0x81,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c181f52a <unknown>
+
+fmlsl   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-10001011-10111001-10001111
+// CHECK-INST: fmlsl   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x8f,0xb9,0x8b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c18bb98f <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 00100000, 00001000, 00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200808 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-00100000-00001000-00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200808 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 00100101, 01001001, 01001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254949 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-00100101-01001001-01001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1254949 <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 00101000, 01101001, 10101011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869ab <unknown>
+
+fmlsl   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-00101000-01101001-10101011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12869ab <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 00101111, 01101011, 11101011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6beb <unknown>
+
+fmlsl   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-00101111-01101011-11101011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12f6beb <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 00100000, 00001010, 00101001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a29 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-00100000-00001010-00101001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1200a29 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 00101110, 00001000, 00101001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0829 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-00101110-00001000-00101001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0829 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 00100100, 01001010, 01101000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a68 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-00100100-01001010-01101000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x24,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1244a68 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 00100010, 00001001, 10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-00100010-00001001-10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x22,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1220988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 00101010, 01001000, 00101001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4829 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-00101010-01001000-00101001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x2a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12a4829 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 00101110, 00001010, 11001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ac9 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-00101110-00001010-11001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x2e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12e0ac9 <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 00100001, 01101001, 00101010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c121692a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-00100001-01101001-00101010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c121692a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 00101011, 00101001, 10001011
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b298b <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-00101011-00101001-10001011
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x2b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12b298b <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 10010000, 00010000, 00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901008 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-10010000-00010000-00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901008 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 10010101, 01010101, 01001101
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x4d,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195554d <unknown>
+
+fmlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-10010101-01010101-01001101
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x4d,0x55,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195554d <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 10011000, 01111101, 10001111
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d8f <unknown>
+
+fmlsl   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-10011000-01111101-10001111
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0x7d,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1987d8f <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 10011111, 01111111, 11001111
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xcf,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fcf <unknown>
+
+fmlsl   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-10011111-01111111-11001111
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xcf,0x7f,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19f7fcf <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 10010000, 00011110, 00001101
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e0d <unknown>
+
+fmlsl   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-10010000-00011110-00001101
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x1e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1901e0d <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 10011110, 00010100, 00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1409 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-10011110-00010100-00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x14,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1409 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 10010100, 01010110, 01001000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x48,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945648 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-10010100-01010110-01001000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x48,0x56,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1945648 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 10010010, 00011001, 10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-10010010-00011001-10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x19,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1921988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 10011010, 01011000, 00001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5809 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-10011010-01011000-00001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0x58,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19a5809 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 10011110, 00011010, 11001101
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xcd,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1acd <unknown>
+
+fmlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-10011110-00011010-11001101
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xcd,0x1a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e1acd <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 10010001, 01110101, 00001010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191750a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-10010001-01110101-00001010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0x75,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191750a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 10011011, 00111001, 10001111
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b398f <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-10011011-00111001-10001111
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0x39,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19b398f <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 10100000, 00001000, 00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x08,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00808 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-10100000-00001000-00001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x08,0x08,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a00808 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001001, 01001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x49,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44949 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-10110100-01001001-01001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x49,0x49,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44949 <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 10101000, 01101001, 10001011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x8b,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8698b <unknown>
+
+fmlsl   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-10101000-01101001-10001011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x8b,0x69,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8698b <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 10111110, 01101011, 11001011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xcb,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bcb <unknown>
+
+fmlsl   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-10111110-01101011-11001011
+// CHECK, INST: fmlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xcb,0x6b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be6bcb <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 10110000, 00001010, 00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x09,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a09 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-10110000-00001010-00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x09,0x0a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b00a09 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001000, 00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0809 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-10111110-00001000-00001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0809 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 10110100, 01001010, 01001000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x48,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a48 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-10110100-01001010-01001000
+// CHECK, INST: fmlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x48,0x4a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b44a48 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 10100010, 00001001, 10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-10100010-00001001-10001000
+// CHECK, INST: fmlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a20988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 10111010, 01001000, 00001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4809 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-10111010-01001000-00001001
+// CHECK, INST: fmlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba4809 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 10111110, 00001010, 11001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc9,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ac9 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-10111110-00001010-11001001
+// CHECK, INST: fmlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc9,0x0a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be0ac9 <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 10100000, 01101001, 00001010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x0a,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0690a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-10100000-01101001-00001010
+// CHECK, INST: fmlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x0a,0x69,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0690a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 10101010, 00101001, 10001011
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa298b <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-10101010-00101001-10001011
+// CHECK, INST: fmlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa298b <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300808 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-00110000-00001000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300808 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354949 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-00110101-01001001-01001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1354949 <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10101011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869ab <unknown>
+
+fmlsl   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-00111000-01101001-10101011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x38,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13869ab <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-00111111-01101011-11101011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6beb <unknown>
+
+fmlsl   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-00111111-01101011-11101011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13f6beb <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a29 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-00110000-00001010-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x30,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1300a29 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0829 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-00111110-00001000-00101001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0829 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01101000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a68 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-00110100-01001010-01101000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1344a68 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-00110010-00001001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x32,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1320988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00101001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4829 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-00111010-01001000-00101001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x3a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13a4829 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ac9 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-00111110-00001010-11001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13e0ac9 <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00101010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c131692a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-00110001-01101001-00101010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x31,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c131692a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10001011
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b298b <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-00111011-00101001-10001011
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x3b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13b298b <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909008 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-10010000-10010000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909008 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00001101
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x0d,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d50d <unknown>
+
+fmlsl   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-10010101-11010101-00001101
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x0d,0xd5,0x95,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c195d50d <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10001111
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd8f <unknown>
+
+fmlsl   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-10011000-11111101-10001111
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0xfd,0x98,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c198fd8f <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10001111
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x8f,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff8f <unknown>
+
+fmlsl   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-10011111-11111111-10001111
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x8f,0xff,0x9f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19fff8f <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00001101
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e0d <unknown>
+
+fmlsl   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-10010000-10011110-00001101
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x9e,0x90,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1909e0d <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9409 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-10011110-10010100-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x94,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9409 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00001000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x08,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d608 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-10010100-11010110-00001000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x08,0xd6,0x94,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c194d608 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-10010010-10011001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x99,0x92,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1929988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad809 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-10011010-11011000-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0xd8,0x9a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19ad809 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10001101
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x8d,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a8d <unknown>
+
+fmlsl   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-10011110-10011010-10001101
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x8d,0x9a,0x9e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19e9a8d <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00001010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f50a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-10010001-11110101-00001010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0xf5,0x91,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c191f50a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10001111
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb98f <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-10011011-10111001-10001111
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0xb9,0x9b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c19bb98f <unknown>
+
+
+fmlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x08,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10808 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-10100001-00001000-00001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x08,0x08,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10808 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x09,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54909 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-10110101-01001001-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x09,0x49,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54909 <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10001011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9698b <unknown>
+
+fmlsl   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-01101001-10001011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x69,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9698b <unknown>
+
+fmlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10001011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x8b,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b8b <unknown>
+
+fmlsl   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-10111101-01101011-10001011
+// CHECK-INST: fmlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x8b,0x6b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd6b8b <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x09,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a09 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-10110001-00001010-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x09,0x0a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b10a09 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0809 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-10111101-00001000-00001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0809 <unknown>
+
+fmlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00001000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x08,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a08 <unknown>
+
+fmlsl   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-10110101-01001010-00001000
+// CHECK-INST: fmlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x08,0x4a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b54a08 <unknown>
+
+fmlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10988 <unknown>
+
+fmlsl   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-10100001-00001001-10001000
+// CHECK-INST: fmlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a10988 <unknown>
+
+fmlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94809 <unknown>
+
+fmlsl   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-10111001-01001000-00001001
+// CHECK-INST: fmlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b94809 <unknown>
+
+fmlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x89,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a89 <unknown>
+
+fmlsl   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-10111101-00001010-10001001
+// CHECK-INST: fmlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x89,0x0a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd0a89 <unknown>
+
+fmlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00001010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x0a,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1690a <unknown>
+
+fmlsl   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-10100001-01101001-00001010
+// CHECK-INST: fmlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x0a,0x69,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1690a <unknown>
+
+fmlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10001011
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9298b <unknown>
+
+fmlsl   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-10101001-00101001-10001011
+// CHECK-INST: fmlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9298b <unknown>
+

llvm/test/MC/AArch64/SME2/smlal-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+smlal za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: smlal za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: smlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+smlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: smlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: smlal za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+smlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlal za.s[w8, 10:12], z17.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlal za.s[w8, 10:12], z17.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: smlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/smlal.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smlal   za.s[w8, 0:1], z0.h, z0.h  // 11000001-01100000-00001100-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x0c,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600c00 <unknown>
+
+smlal   za.s[w10, 10:11], z10.h, z5.h  // 11000001-01100101-01001101-01000101
+// CHECK-INST: smlal   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x45,0x4d,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654d45 <unknown>
+
+smlal   za.s[w11, 14:15], z13.h, z8.h  // 11000001-01101000-01101101-10100111
+// CHECK-INST: smlal   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xa7,0x6d,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1686da7 <unknown>
+
+smlal   za.s[w11, 14:15], z31.h, z15.h  // 11000001-01101111-01101111-11100111
+// CHECK-INST: smlal   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xe7,0x6f,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6fe7 <unknown>
+
+smlal   za.s[w8, 10:11], z17.h, z0.h  // 11000001-01100000-00001110-00100101
+// CHECK-INST: smlal   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x25,0x0e,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600e25 <unknown>
+
+smlal   za.s[w8, 2:3], z1.h, z14.h  // 11000001-01101110-00001100-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x21,0x0c,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0c21 <unknown>
+
+smlal   za.s[w10, 0:1], z19.h, z4.h  // 11000001-01100100-01001110-01100000
+// CHECK-INST: smlal   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x60,0x4e,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644e60 <unknown>
+
+smlal   za.s[w8, 0:1], z12.h, z2.h  // 11000001-01100010-00001101-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x80,0x0d,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620d80 <unknown>
+
+smlal   za.s[w10, 2:3], z1.h, z10.h  // 11000001-01101010-01001100-00100001
+// CHECK-INST: smlal   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x21,0x4c,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4c21 <unknown>
+
+smlal   za.s[w8, 10:11], z22.h, z14.h  // 11000001-01101110-00001110-11000101
+// CHECK-INST: smlal   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xc5,0x0e,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ec5 <unknown>
+
+smlal   za.s[w11, 4:5], z9.h, z1.h  // 11000001-01100001-01101101-00100010
+// CHECK-INST: smlal   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x22,0x6d,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616d22 <unknown>
+
+smlal   za.s[w9, 14:15], z12.h, z11.h  // 11000001-01101011-00101101-10000111
+// CHECK-INST: smlal   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x87,0x2d,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2d87 <unknown>
+
+
+smlal   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-11000000-00010000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01000 <unknown>
+
+smlal   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-11000101-01010101-01000101
+// CHECK-INST: smlal   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x45,0x55,0xc5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c55545 <unknown>
+
+smlal   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-11001000-11111101-10100111
+// CHECK-INST: smlal   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xa7,0xfd,0xc8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c8fda7 <unknown>
+
+smlal   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-11001111-11111111-11100111
+// CHECK-INST: smlal   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xe7,0xff,0xcf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cfffe7 <unknown>
+
+smlal   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-11000000-00011110-00100101
+// CHECK-INST: smlal   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x25,0x1e,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01e25 <unknown>
+
+smlal   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-11001110-10010100-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x21,0x94,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce9421 <unknown>
+
+smlal   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-11000100-01010110-01100000
+// CHECK-INST: smlal   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x60,0x56,0xc4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c45660 <unknown>
+
+smlal   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-11000010-00011001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x80,0x19,0xc2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c21980 <unknown>
+
+smlal   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-11001010-11011000-00100001
+// CHECK-INST: smlal   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x21,0xd8,0xca,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cad821 <unknown>
+
+smlal   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-11001110-00011010-11000101
+// CHECK-INST: smlal   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xc5,0x1a,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce1ac5 <unknown>
+
+smlal   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-11000001-11110101-00100010
+// CHECK-INST: smlal   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x22,0xf5,0xc1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c1f522 <unknown>
+
+smlal   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-11001011-10111001-10000111
+// CHECK-INST: smlal   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x87,0xb9,0xcb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cbb987 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 01100000, 00001000, 00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600800 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-01100000-00001000-00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600800 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 01100101, 01001001, 01000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654941 <unknown>
+
+smlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-01100101-01001001-01000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654941 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 01101000, 01101001, 10100011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869a3 <unknown>
+
+smlal   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-01101000-01101001-10100011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869a3 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 01101111, 01101011, 11100011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6be3 <unknown>
+
+smlal   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-01101111-01101011-11100011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6be3 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 01100000, 00001010, 00100001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a21 <unknown>
+
+smlal   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-01100000-00001010-00100001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a21 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 01101110, 00001000, 00100001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0821 <unknown>
+
+smlal   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-01101110-00001000-00100001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0821 <unknown>
+
+smlal   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 01100100, 01001010, 01100000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a60 <unknown>
+
+smlal   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-01100100-01001010-01100000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a60 <unknown>
+
+smlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 01100010, 00001001, 10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-01100010-00001001-10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 01101010, 01001000, 00100001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4821 <unknown>
+
+smlal   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-01101010-01001000-00100001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4821 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 01101110, 00001010, 11000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ac1 <unknown>
+
+smlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-01101110-00001010-11000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ac1 <unknown>
+
+smlal   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 01100001, 01101001, 00100010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616922 <unknown>
+
+smlal   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-01100001-01101001-00100010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616922 <unknown>
+
+smlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 01101011, 00101001, 10000011
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2983 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-01101011-00101001-10000011
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2983 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 11010000, 00010000, 00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01000 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-11010000-00010000-00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01000 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 11010101, 01010101, 01000101
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d55545 <unknown>
+
+smlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-11010101-01010101-01000101
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d55545 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 11011000, 01111101, 10000111
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d87 <unknown>
+
+smlal   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-11011000-01111101-10000111
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d87 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 11011111, 01111111, 11000111
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xc7,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fc7 <unknown>
+
+smlal   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-11011111-01111111-11000111
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xc7,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fc7 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 11010000, 00011110, 00000101
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e05 <unknown>
+
+smlal   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-11010000-00011110-00000101
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e05 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 11011110, 00010100, 00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1401 <unknown>
+
+smlal   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-11011110-00010100-00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1401 <unknown>
+
+smlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 11010100, 01010110, 01000000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x40,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45640 <unknown>
+
+smlal   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-11010100-01010110-01000000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x40,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45640 <unknown>
+
+smlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 11010010, 00011001, 10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-11010010-00011001-10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 11011010, 01011000, 00000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5801 <unknown>
+
+smlal   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-11011010-01011000-00000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5801 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 11011110, 00011010, 11000101
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xc5,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1ac5 <unknown>
+
+smlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-11011110-00011010-11000101
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xc5,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1ac5 <unknown>
+
+smlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 11010001, 01110101, 00000010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d17502 <unknown>
+
+smlal   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-11010001-01110101-00000010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d17502 <unknown>
+
+smlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 11011011, 00111001, 10000111
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db3987 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-11011011-00111001-10000111
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db3987 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 11100000, 00001000, 00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00800 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-11100000-00001000-00000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00800 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001001, 01000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x41,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44941 <unknown>
+
+smlal   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-11110100-01001001-01000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x41,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44941 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 11101000, 01101001, 10000011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x83,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e86983 <unknown>
+
+smlal   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-11101000-01101001-10000011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x83,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e86983 <unknown>
+
+smlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 11111110, 01101011, 11000011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc3,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bc3 <unknown>
+
+smlal   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-11111110-01101011-11000011
+// CHECK, INST: smlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc3,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bc3 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 11110000, 00001010, 00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x01,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a01 <unknown>
+
+smlal   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-11110000-00001010-00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x01,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a01 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001000, 00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0801 <unknown>
+
+smlal   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-11111110-00001000-00000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0801 <unknown>
+
+smlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001010, 01000000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x40,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a40 <unknown>
+
+smlal   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-11110100-01001010-01000000
+// CHECK, INST: smlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x40,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a40 <unknown>
+
+smlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 11100010, 00001001, 10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-11100010-00001001-10000000
+// CHECK, INST: smlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 11111010, 01001000, 00000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4801 <unknown>
+
+smlal   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-11111010-01001000-00000001
+// CHECK, INST: smlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4801 <unknown>
+
+smlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001010, 11000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc1,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ac1 <unknown>
+
+smlal   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-11111110-00001010-11000001
+// CHECK, INST: smlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc1,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ac1 <unknown>
+
+smlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 11100000, 01101001, 00000010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x02,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e06902 <unknown>
+
+smlal   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-11100000-01101001-00000010
+// CHECK, INST: smlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x02,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e06902 <unknown>
+
+smlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 11101010, 00101001, 10000011
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea2983 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-11101010-00101001-10000011
+// CHECK, INST: smlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea2983 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700800 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700800 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754941 <unknown>
+
+smlal   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x41,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754941 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10100011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869a3 <unknown>
+
+smlal   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10100011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xa3,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869a3 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11100011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6be3 <unknown>
+
+smlal   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11100011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xe3,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6be3 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a21 <unknown>
+
+smlal   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x21,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a21 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0821 <unknown>
+
+smlal   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00100001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x21,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0821 <unknown>
+
+smlal   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01100000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a60 <unknown>
+
+smlal   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01100000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x60,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a60 <unknown>
+
+smlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x80,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00100001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4821 <unknown>
+
+smlal   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00100001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x21,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4821 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ac1 <unknown>
+
+smlal   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc1,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ac1 <unknown>
+
+smlal   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00100010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1716922 <unknown>
+
+smlal   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00100010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x22,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1716922 <unknown>
+
+smlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10000011
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b2983 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10000011
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x83,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b2983 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09000 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09000 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00000101
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x05,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d505 <unknown>
+
+smlal   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00000101
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x05,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d505 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10000111
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd87 <unknown>
+
+smlal   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10000111
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x87,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd87 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10000111
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x87,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff87 <unknown>
+
+smlal   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10000111
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x87,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff87 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00000101
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e05 <unknown>
+
+smlal   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00000101
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x05,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e05 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9401 <unknown>
+
+smlal   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x01,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9401 <unknown>
+
+smlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00000000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x00,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d600 <unknown>
+
+smlal   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00000000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x00,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d600 <unknown>
+
+smlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x80,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad801 <unknown>
+
+smlal   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x01,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad801 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10000101
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x85,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a85 <unknown>
+
+smlal   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10000101
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x85,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a85 <unknown>
+
+smlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00000010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f502 <unknown>
+
+smlal   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00000010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x02,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f502 <unknown>
+
+smlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10000111
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb987 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10000111
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x87,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb987 <unknown>
+
+
+smlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10800 <unknown>
+
+smlal   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10800 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x01,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54901 <unknown>
+
+smlal   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x01,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54901 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10000011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e96983 <unknown>
+
+smlal   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10000011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e96983 <unknown>
+
+smlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10000011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x83,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b83 <unknown>
+
+smlal   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10000011
+// CHECK-INST: smlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x83,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b83 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x01,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a01 <unknown>
+
+smlal   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x01,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a01 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0801 <unknown>
+
+smlal   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x01,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0801 <unknown>
+
+smlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00000000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x00,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a00 <unknown>
+
+smlal   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00000000
+// CHECK-INST: smlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x00,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a00 <unknown>
+
+smlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10980 <unknown>
+
+smlal   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10000000
+// CHECK-INST: smlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x80,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10980 <unknown>
+
+smlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94801 <unknown>
+
+smlal   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00000001
+// CHECK-INST: smlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x01,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94801 <unknown>
+
+smlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x81,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a81 <unknown>
+
+smlal   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10000001
+// CHECK-INST: smlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x81,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a81 <unknown>
+
+smlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00000010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e16902 <unknown>
+
+smlal   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00000010
+// CHECK-INST: smlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e16902 <unknown>
+
+smlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10000011
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e92983 <unknown>
+
+smlal   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10000011
+// CHECK-INST: smlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x83,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e92983 <unknown>
+

llvm/test/MC/AArch64/SME2/smlsl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+smlsl za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlsl za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlsl za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlsl za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+smlsl za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: smlsl za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlsl za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: smlsl za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+smlsl za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: smlsl za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: smlsl za.s[w12, 6:7, vgx4], {z12.h-z15.h}, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+smlsl za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlsl za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlsl za.s[w8, 10:12], z17.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlsl za.s[w8, 10:12], z17.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+smlsl za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: smlsl za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+smlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/smlsl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+smlsl   za.s[w8, 0:1], z0.h, z0.h  // 11000001-01100000-00001100-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x08,0x0c,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600c08 <unknown>
+
+smlsl   za.s[w10, 10:11], z10.h, z5.h  // 11000001-01100101-01001101-01001101
+// CHECK-INST: smlsl   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x4d,0x4d,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654d4d <unknown>
+
+smlsl   za.s[w11, 14:15], z13.h, z8.h  // 11000001-01101000-01101101-10101111
+// CHECK-INST: smlsl   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xaf,0x6d,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1686daf <unknown>
+
+smlsl   za.s[w11, 14:15], z31.h, z15.h  // 11000001-01101111-01101111-11101111
+// CHECK-INST: smlsl   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xef,0x6f,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6fef <unknown>
+
+smlsl   za.s[w8, 10:11], z17.h, z0.h  // 11000001-01100000-00001110-00101101
+// CHECK-INST: smlsl   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x2d,0x0e,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600e2d <unknown>
+
+smlsl   za.s[w8, 2:3], z1.h, z14.h  // 11000001-01101110-00001100-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x29,0x0c,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0c29 <unknown>
+
+smlsl   za.s[w10, 0:1], z19.h, z4.h  // 11000001-01100100-01001110-01101000
+// CHECK-INST: smlsl   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x68,0x4e,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644e68 <unknown>
+
+smlsl   za.s[w8, 0:1], z12.h, z2.h  // 11000001-01100010-00001101-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x88,0x0d,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620d88 <unknown>
+
+smlsl   za.s[w10, 2:3], z1.h, z10.h  // 11000001-01101010-01001100-00101001
+// CHECK-INST: smlsl   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x29,0x4c,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4c29 <unknown>
+
+smlsl   za.s[w8, 10:11], z22.h, z14.h  // 11000001-01101110-00001110-11001101
+// CHECK-INST: smlsl   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xcd,0x0e,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ecd <unknown>
+
+smlsl   za.s[w11, 4:5], z9.h, z1.h  // 11000001-01100001-01101101-00101010
+// CHECK-INST: smlsl   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x2a,0x6d,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616d2a <unknown>
+
+smlsl   za.s[w9, 14:15], z12.h, z11.h  // 11000001-01101011-00101101-10001111
+// CHECK-INST: smlsl   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x8f,0x2d,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2d8f <unknown>
+
+
+smlsl   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-11000000-00010000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01008 <unknown>
+
+smlsl   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-11000101-01010101-01001101
+// CHECK-INST: smlsl   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x55,0xc5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c5554d <unknown>
+
+smlsl   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-11001000-11111101-10101111
+// CHECK-INST: smlsl   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xaf,0xfd,0xc8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c8fdaf <unknown>
+
+smlsl   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-11001111-11111111-11101111
+// CHECK-INST: smlsl   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xef,0xff,0xcf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cfffef <unknown>
+
+smlsl   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-11000000-00011110-00101101
+// CHECK-INST: smlsl   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x2d,0x1e,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01e2d <unknown>
+
+smlsl   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-11001110-10010100-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x29,0x94,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce9429 <unknown>
+
+smlsl   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-11000100-01010110-01101000
+// CHECK-INST: smlsl   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x68,0x56,0xc4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c45668 <unknown>
+
+smlsl   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-11000010-00011001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x88,0x19,0xc2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c21988 <unknown>
+
+smlsl   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-11001010-11011000-00101001
+// CHECK-INST: smlsl   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x29,0xd8,0xca,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cad829 <unknown>
+
+smlsl   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-11001110-00011010-11001101
+// CHECK-INST: smlsl   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x1a,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce1acd <unknown>
+
+smlsl   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-11000001-11110101-00101010
+// CHECK-INST: smlsl   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x2a,0xf5,0xc1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c1f52a <unknown>
+
+smlsl   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-11001011-10111001-10001111
+// CHECK-INST: smlsl   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x8f,0xb9,0xcb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cbb98f <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 01100000, 00001000, 00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600808 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-01100000-00001000-00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600808 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 01100101, 01001001, 01001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654949 <unknown>
+
+smlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-01100101-01001001-01001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654949 <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 01101000, 01101001, 10101011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869ab <unknown>
+
+smlsl   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-01101000-01101001-10101011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869ab <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 01101111, 01101011, 11101011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6beb <unknown>
+
+smlsl   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-01101111-01101011-11101011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6beb <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 01100000, 00001010, 00101001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a29 <unknown>
+
+smlsl   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-01100000-00001010-00101001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a29 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 01101110, 00001000, 00101001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0829 <unknown>
+
+smlsl   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-01101110-00001000-00101001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0829 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 01100100, 01001010, 01101000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a68 <unknown>
+
+smlsl   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-01100100-01001010-01101000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a68 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 01100010, 00001001, 10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-01100010-00001001-10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 01101010, 01001000, 00101001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4829 <unknown>
+
+smlsl   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-01101010-01001000-00101001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4829 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 01101110, 00001010, 11001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ac9 <unknown>
+
+smlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-01101110-00001010-11001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ac9 <unknown>
+
+smlsl   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 01100001, 01101001, 00101010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c161692a <unknown>
+
+smlsl   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-01100001-01101001-00101010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c161692a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 01101011, 00101001, 10001011
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b298b <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-01101011-00101001-10001011
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b298b <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 11010000, 00010000, 00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01008 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-11010000-00010000-00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01008 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 11010101, 01010101, 01001101
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x4d,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5554d <unknown>
+
+smlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-11010101-01010101-01001101
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x4d,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5554d <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 11011000, 01111101, 10001111
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d8f <unknown>
+
+smlsl   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-11011000-01111101-10001111
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d8f <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 11011111, 01111111, 11001111
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xcf,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fcf <unknown>
+
+smlsl   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-11011111-01111111-11001111
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xcf,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fcf <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 11010000, 00011110, 00001101
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e0d <unknown>
+
+smlsl   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-11010000-00011110-00001101
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e0d <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 11011110, 00010100, 00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1409 <unknown>
+
+smlsl   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-11011110-00010100-00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1409 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 11010100, 01010110, 01001000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x48,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45648 <unknown>
+
+smlsl   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-11010100-01010110-01001000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x48,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45648 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 11010010, 00011001, 10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-11010010-00011001-10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 11011010, 01011000, 00001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5809 <unknown>
+
+smlsl   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-11011010-01011000-00001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5809 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 11011110, 00011010, 11001101
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xcd,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1acd <unknown>
+
+smlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-11011110-00011010-11001101
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xcd,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1acd <unknown>
+
+smlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 11010001, 01110101, 00001010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1750a <unknown>
+
+smlsl   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-11010001-01110101-00001010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1750a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 11011011, 00111001, 10001111
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db398f <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-11011011-00111001-10001111
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db398f <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 11100000, 00001000, 00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x08,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00808 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-11100000-00001000-00001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x08,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00808 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001001, 01001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x49,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44949 <unknown>
+
+smlsl   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-11110100-01001001-01001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x49,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44949 <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 11101000, 01101001, 10001011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x8b,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8698b <unknown>
+
+smlsl   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-11101000-01101001-10001011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x8b,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8698b <unknown>
+
+smlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 11111110, 01101011, 11001011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xcb,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bcb <unknown>
+
+smlsl   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-11111110-01101011-11001011
+// CHECK, INST: smlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xcb,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bcb <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 11110000, 00001010, 00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x09,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a09 <unknown>
+
+smlsl   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-11110000-00001010-00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x09,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a09 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001000, 00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0809 <unknown>
+
+smlsl   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-11111110-00001000-00001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0809 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001010, 01001000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x48,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a48 <unknown>
+
+smlsl   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-11110100-01001010-01001000
+// CHECK, INST: smlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x48,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a48 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 11100010, 00001001, 10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-11100010-00001001-10001000
+// CHECK, INST: smlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 11111010, 01001000, 00001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4809 <unknown>
+
+smlsl   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-11111010-01001000-00001001
+// CHECK, INST: smlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4809 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001010, 11001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc9,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ac9 <unknown>
+
+smlsl   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-11111110-00001010-11001001
+// CHECK, INST: smlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xc9,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ac9 <unknown>
+
+smlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 11100000, 01101001, 00001010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x0a,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0690a <unknown>
+
+smlsl   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-11100000-01101001-00001010
+// CHECK, INST: smlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x0a,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0690a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 11101010, 00101001, 10001011
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea298b <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-11101010-00101001-10001011
+// CHECK, INST: smlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea298b <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700808 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x08,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700808 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754949 <unknown>
+
+smlsl   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x49,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754949 <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10101011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869ab <unknown>
+
+smlsl   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10101011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xab,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869ab <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11101011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6beb <unknown>
+
+smlsl   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11101011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xeb,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6beb <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a29 <unknown>
+
+smlsl   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x29,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a29 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0829 <unknown>
+
+smlsl   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00101001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x29,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0829 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01101000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a68 <unknown>
+
+smlsl   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01101000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x68,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a68 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x88,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00101001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4829 <unknown>
+
+smlsl   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00101001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x29,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4829 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ac9 <unknown>
+
+smlsl   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xc9,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ac9 <unknown>
+
+smlsl   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00101010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c171692a <unknown>
+
+smlsl   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00101010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x2a,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c171692a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10001011
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b298b <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10001011
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x8b,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b298b <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09008 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09008 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00001101
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x0d,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d50d <unknown>
+
+smlsl   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00001101
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x0d,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d50d <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10001111
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd8f <unknown>
+
+smlsl   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10001111
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x8f,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd8f <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10001111
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x8f,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff8f <unknown>
+
+smlsl   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10001111
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x8f,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff8f <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00001101
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e0d <unknown>
+
+smlsl   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00001101
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x0d,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e0d <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9409 <unknown>
+
+smlsl   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x09,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9409 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00001000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x08,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d608 <unknown>
+
+smlsl   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00001000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x08,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d608 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x88,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad809 <unknown>
+
+smlsl   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x09,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad809 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10001101
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x8d,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a8d <unknown>
+
+smlsl   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10001101
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x8d,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a8d <unknown>
+
+smlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00001010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f50a <unknown>
+
+smlsl   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00001010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x0a,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f50a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10001111
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb98f <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10001111
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x8f,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb98f <unknown>
+
+
+smlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x08,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10808 <unknown>
+
+smlsl   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x08,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10808 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x09,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54909 <unknown>
+
+smlsl   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x09,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54909 <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10001011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9698b <unknown>
+
+smlsl   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10001011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9698b <unknown>
+
+smlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10001011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x8b,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b8b <unknown>
+
+smlsl   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10001011
+// CHECK-INST: smlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x8b,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b8b <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x09,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a09 <unknown>
+
+smlsl   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x09,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a09 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0809 <unknown>
+
+smlsl   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x09,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0809 <unknown>
+
+smlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00001000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x08,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a08 <unknown>
+
+smlsl   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00001000
+// CHECK-INST: smlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x08,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a08 <unknown>
+
+smlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10988 <unknown>
+
+smlsl   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10001000
+// CHECK-INST: smlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x88,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10988 <unknown>
+
+smlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94809 <unknown>
+
+smlsl   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00001001
+// CHECK-INST: smlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x09,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94809 <unknown>
+
+smlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x89,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a89 <unknown>
+
+smlsl   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10001001
+// CHECK-INST: smlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x89,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a89 <unknown>
+
+smlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00001010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x0a,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1690a <unknown>
+
+smlsl   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00001010
+// CHECK-INST: smlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x0a,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1690a <unknown>
+
+smlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10001011
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9298b <unknown>
+
+smlsl   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10001011
+// CHECK-INST: smlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x8b,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9298b <unknown>
+

llvm/test/MC/AArch64/SME2/umlal-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlal za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlal za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+umlal za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: umlal za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: umlal za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+umlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: umlal za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlal za.s[w12, 6:7], {z12.h-z15.h}, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: umlal za.s[w12, 6:7], {z12.h-z15.h}, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+umlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlal za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlal za.s[w8, 10:12], z17.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlal za.s[w8, 10:12], z17.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: umlal za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+umlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/umlal.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umlal   za.s[w8, 0:1], z0.h, z0.h  // 11000001-01100000-00001100-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x10,0x0c,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600c10 <unknown>
+
+umlal   za.s[w10, 10:11], z10.h, z5.h  // 11000001-01100101-01001101-01010101
+// CHECK-INST: umlal   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x55,0x4d,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654d55 <unknown>
+
+umlal   za.s[w11, 14:15], z13.h, z8.h  // 11000001-01101000-01101101-10110111
+// CHECK-INST: umlal   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x6d,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1686db7 <unknown>
+
+umlal   za.s[w11, 14:15], z31.h, z15.h  // 11000001-01101111-01101111-11110111
+// CHECK-INST: umlal   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xf7,0x6f,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6ff7 <unknown>
+
+umlal   za.s[w8, 10:11], z17.h, z0.h  // 11000001-01100000-00001110-00110101
+// CHECK-INST: umlal   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x35,0x0e,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600e35 <unknown>
+
+umlal   za.s[w8, 2:3], z1.h, z14.h  // 11000001-01101110-00001100-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x31,0x0c,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0c31 <unknown>
+
+umlal   za.s[w10, 0:1], z19.h, z4.h  // 11000001-01100100-01001110-01110000
+// CHECK-INST: umlal   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x70,0x4e,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644e70 <unknown>
+
+umlal   za.s[w8, 0:1], z12.h, z2.h  // 11000001-01100010-00001101-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x90,0x0d,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620d90 <unknown>
+
+umlal   za.s[w10, 2:3], z1.h, z10.h  // 11000001-01101010-01001100-00110001
+// CHECK-INST: umlal   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x31,0x4c,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4c31 <unknown>
+
+umlal   za.s[w8, 10:11], z22.h, z14.h  // 11000001-01101110-00001110-11010101
+// CHECK-INST: umlal   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xd5,0x0e,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ed5 <unknown>
+
+umlal   za.s[w11, 4:5], z9.h, z1.h  // 11000001-01100001-01101101-00110010
+// CHECK-INST: umlal   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x32,0x6d,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616d32 <unknown>
+
+umlal   za.s[w9, 14:15], z12.h, z11.h  // 11000001-01101011-00101101-10010111
+// CHECK-INST: umlal   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x97,0x2d,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2d97 <unknown>
+
+
+umlal   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-11000000-00010000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01010 <unknown>
+
+umlal   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-11000101-01010101-01010101
+// CHECK-INST: umlal   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x55,0x55,0xc5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c55555 <unknown>
+
+umlal   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-11001000-11111101-10110111
+// CHECK-INST: umlal   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xb7,0xfd,0xc8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c8fdb7 <unknown>
+
+umlal   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-11001111-11111111-11110111
+// CHECK-INST: umlal   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xf7,0xff,0xcf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cffff7 <unknown>
+
+umlal   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-11000000-00011110-00110101
+// CHECK-INST: umlal   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x35,0x1e,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01e35 <unknown>
+
+umlal   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-11001110-10010100-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x31,0x94,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce9431 <unknown>
+
+umlal   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-11000100-01010110-01110000
+// CHECK-INST: umlal   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x70,0x56,0xc4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c45670 <unknown>
+
+umlal   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-11000010-00011001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x90,0x19,0xc2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c21990 <unknown>
+
+umlal   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-11001010-11011000-00110001
+// CHECK-INST: umlal   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x31,0xd8,0xca,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cad831 <unknown>
+
+umlal   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-11001110-00011010-11010101
+// CHECK-INST: umlal   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xd5,0x1a,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce1ad5 <unknown>
+
+umlal   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-11000001-11110101-00110010
+// CHECK-INST: umlal   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x32,0xf5,0xc1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c1f532 <unknown>
+
+umlal   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-11001011-10111001-10010111
+// CHECK-INST: umlal   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x97,0xb9,0xcb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cbb997 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 01100000, 00001000, 00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600810 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-01100000-00001000-00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600810 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 01100101, 01001001, 01010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654951 <unknown>
+
+umlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-01100101-01001001-01010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654951 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 01101000, 01101001, 10110011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869b3 <unknown>
+
+umlal   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-01101000-01101001-10110011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869b3 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 01101111, 01101011, 11110011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6bf3 <unknown>
+
+umlal   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-01101111-01101011-11110011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6bf3 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 01100000, 00001010, 00110001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a31 <unknown>
+
+umlal   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-01100000-00001010-00110001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a31 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 01101110, 00001000, 00110001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0831 <unknown>
+
+umlal   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-01101110-00001000-00110001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0831 <unknown>
+
+umlal   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 01100100, 01001010, 01110000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a70 <unknown>
+
+umlal   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-01100100-01001010-01110000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a70 <unknown>
+
+umlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 01100010, 00001001, 10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-01100010-00001001-10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 01101010, 01001000, 00110001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4831 <unknown>
+
+umlal   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-01101010-01001000-00110001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4831 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 01101110, 00001010, 11010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ad1 <unknown>
+
+umlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-01101110-00001010-11010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ad1 <unknown>
+
+umlal   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 01100001, 01101001, 00110010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616932 <unknown>
+
+umlal   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-01100001-01101001-00110010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616932 <unknown>
+
+umlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 01101011, 00101001, 10010011
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2993 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-01101011-00101001-10010011
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2993 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 11010000, 00010000, 00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01010 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-11010000-00010000-00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01010 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 11010101, 01010101, 01010101
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d55555 <unknown>
+
+umlal   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-11010101-01010101-01010101
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d55555 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 11011000, 01111101, 10010111
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d97 <unknown>
+
+umlal   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-11011000-01111101-10010111
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d97 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 11011111, 01111111, 11010111
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xd7,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fd7 <unknown>
+
+umlal   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-11011111-01111111-11010111
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xd7,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fd7 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 11010000, 00011110, 00010101
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e15 <unknown>
+
+umlal   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-11010000-00011110-00010101
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e15 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 11011110, 00010100, 00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1411 <unknown>
+
+umlal   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-11011110-00010100-00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1411 <unknown>
+
+umlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 11010100, 01010110, 01010000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x50,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45650 <unknown>
+
+umlal   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-11010100-01010110-01010000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x50,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45650 <unknown>
+
+umlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 11010010, 00011001, 10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-11010010-00011001-10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 11011010, 01011000, 00010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5811 <unknown>
+
+umlal   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-11011010-01011000-00010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5811 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 11011110, 00011010, 11010101
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xd5,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1ad5 <unknown>
+
+umlal   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-11011110-00011010-11010101
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xd5,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1ad5 <unknown>
+
+umlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 11010001, 01110101, 00010010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d17512 <unknown>
+
+umlal   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-11010001-01110101-00010010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d17512 <unknown>
+
+umlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 11011011, 00111001, 10010111
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db3997 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-11011011-00111001-10010111
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db3997 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 11100000, 00001000, 00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x10,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00810 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-11100000-00001000-00010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x10,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00810 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001001, 01010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x51,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44951 <unknown>
+
+umlal   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-11110100-01001001-01010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x51,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44951 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 11101000, 01101001, 10010011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x93,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e86993 <unknown>
+
+umlal   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-11101000-01101001-10010011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x93,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e86993 <unknown>
+
+umlal   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 11111110, 01101011, 11010011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd3,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bd3 <unknown>
+
+umlal   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-11111110-01101011-11010011
+// CHECK, INST: umlal   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd3,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bd3 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 11110000, 00001010, 00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x11,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a11 <unknown>
+
+umlal   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-11110000-00001010-00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x11,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a11 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001000, 00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0811 <unknown>
+
+umlal   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-11111110-00001000-00010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0811 <unknown>
+
+umlal   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001010, 01010000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x50,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a50 <unknown>
+
+umlal   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-11110100-01001010-01010000
+// CHECK, INST: umlal   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x50,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a50 <unknown>
+
+umlal   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 11100010, 00001001, 10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-11100010-00001001-10010000
+// CHECK, INST: umlal   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 11111010, 01001000, 00010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4811 <unknown>
+
+umlal   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-11111010-01001000-00010001
+// CHECK, INST: umlal   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4811 <unknown>
+
+umlal   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001010, 11010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd1,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ad1 <unknown>
+
+umlal   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-11111110-00001010-11010001
+// CHECK, INST: umlal   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd1,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ad1 <unknown>
+
+umlal   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 11100000, 01101001, 00010010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x12,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e06912 <unknown>
+
+umlal   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-11100000-01101001-00010010
+// CHECK, INST: umlal   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x12,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e06912 <unknown>
+
+umlal   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 11101010, 00101001, 10010011
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea2993 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-11101010-00101001-10010011
+// CHECK, INST: umlal   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea2993 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700810 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x10,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700810 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754951 <unknown>
+
+umlal   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x51,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754951 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10110011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869b3 <unknown>
+
+umlal   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10110011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xb3,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869b3 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11110011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6bf3 <unknown>
+
+umlal   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11110011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xf3,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6bf3 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a31 <unknown>
+
+umlal   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x31,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a31 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0831 <unknown>
+
+umlal   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00110001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x31,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0831 <unknown>
+
+umlal   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01110000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a70 <unknown>
+
+umlal   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01110000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x70,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a70 <unknown>
+
+umlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x90,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00110001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4831 <unknown>
+
+umlal   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00110001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x31,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4831 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ad1 <unknown>
+
+umlal   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd1,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ad1 <unknown>
+
+umlal   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00110010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1716932 <unknown>
+
+umlal   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00110010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x32,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1716932 <unknown>
+
+umlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10010011
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b2993 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10010011
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x93,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b2993 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09010 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09010 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00010101
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x15,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d515 <unknown>
+
+umlal   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00010101
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x15,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d515 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10010111
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd97 <unknown>
+
+umlal   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10010111
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x97,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd97 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10010111
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x97,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff97 <unknown>
+
+umlal   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10010111
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x97,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff97 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00010101
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e15 <unknown>
+
+umlal   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00010101
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x15,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e15 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9411 <unknown>
+
+umlal   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x11,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9411 <unknown>
+
+umlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00010000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x10,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d610 <unknown>
+
+umlal   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00010000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x10,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d610 <unknown>
+
+umlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x90,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad811 <unknown>
+
+umlal   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x11,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad811 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10010101
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x95,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a95 <unknown>
+
+umlal   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10010101
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x95,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a95 <unknown>
+
+umlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00010010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f512 <unknown>
+
+umlal   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00010010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x12,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f512 <unknown>
+
+umlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10010111
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb997 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10010111
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x97,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb997 <unknown>
+
+
+umlal   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x10,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10810 <unknown>
+
+umlal   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x10,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10810 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x11,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54911 <unknown>
+
+umlal   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x11,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54911 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10010011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e96993 <unknown>
+
+umlal   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10010011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e96993 <unknown>
+
+umlal   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10010011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x93,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b93 <unknown>
+
+umlal   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10010011
+// CHECK-INST: umlal   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x93,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b93 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x11,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a11 <unknown>
+
+umlal   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x11,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a11 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0811 <unknown>
+
+umlal   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x11,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0811 <unknown>
+
+umlal   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00010000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x10,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a10 <unknown>
+
+umlal   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00010000
+// CHECK-INST: umlal   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x10,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a10 <unknown>
+
+umlal   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10990 <unknown>
+
+umlal   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10010000
+// CHECK-INST: umlal   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x90,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10990 <unknown>
+
+umlal   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94811 <unknown>
+
+umlal   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00010001
+// CHECK-INST: umlal   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x11,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94811 <unknown>
+
+umlal   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x91,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a91 <unknown>
+
+umlal   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10010001
+// CHECK-INST: umlal   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x91,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a91 <unknown>
+
+umlal   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00010010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x12,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e16912 <unknown>
+
+umlal   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00010010
+// CHECK-INST: umlal   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x12,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e16912 <unknown>
+
+umlal   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10010011
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e92993 <unknown>
+
+umlal   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10010011
+// CHECK-INST: umlal   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x93,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e92993 <unknown>
+

llvm/test/MC/AArch64/SME2/umlsl-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+umlsl za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlsl za.s[w8, 0:1, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlsl za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlsl za.s[w9, 6:7], {z13.h-z16.h}, {z9.h-z12.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid indexed-vector register
+
+umlsl za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: umlsl za.s[w11, 14:15], z31.h, z15.b[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlsl za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: umlsl za.s[w11, 6:7, vgx2], {z12.h-z13.h}, z31.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+umlsl za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: umlsl za.s[w7, 6:7], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlsl za.s[w12, 6:7], {z12.h-z13.h}, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: umlsl za.s[w12, 6:7], {z12.h-z13.h}, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+umlsl za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlsl za.s[w11, 4:8], {z30.h-z31.h}, z15.h[15]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlsl za.s[w8, 10:12], z17.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlsl za.s[w8, 10:12], z17.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+umlsl za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: umlsl za.b[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+umlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlsl za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/umlsl.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+umlsl   za.s[w8, 0:1], z0.h, z0.h  // 11000001-01100000-00001100-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1], z0.h, z0.h
+// CHECK-ENCODING: [0x18,0x0c,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600c18 <unknown>
+
+umlsl   za.s[w10, 10:11], z10.h, z5.h  // 11000001-01100101-01001101-01011101
+// CHECK-INST: umlsl   za.s[w10, 10:11], z10.h, z5.h
+// CHECK-ENCODING: [0x5d,0x4d,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654d5d <unknown>
+
+umlsl   za.s[w11, 14:15], z13.h, z8.h  // 11000001-01101000-01101101-10111111
+// CHECK-INST: umlsl   za.s[w11, 14:15], z13.h, z8.h
+// CHECK-ENCODING: [0xbf,0x6d,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1686dbf <unknown>
+
+umlsl   za.s[w11, 14:15], z31.h, z15.h  // 11000001-01101111-01101111-11111111
+// CHECK-INST: umlsl   za.s[w11, 14:15], z31.h, z15.h
+// CHECK-ENCODING: [0xff,0x6f,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6fff <unknown>
+
+umlsl   za.s[w8, 10:11], z17.h, z0.h  // 11000001-01100000-00001110-00111101
+// CHECK-INST: umlsl   za.s[w8, 10:11], z17.h, z0.h
+// CHECK-ENCODING: [0x3d,0x0e,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600e3d <unknown>
+
+umlsl   za.s[w8, 2:3], z1.h, z14.h  // 11000001-01101110-00001100-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3], z1.h, z14.h
+// CHECK-ENCODING: [0x39,0x0c,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0c39 <unknown>
+
+umlsl   za.s[w10, 0:1], z19.h, z4.h  // 11000001-01100100-01001110-01111000
+// CHECK-INST: umlsl   za.s[w10, 0:1], z19.h, z4.h
+// CHECK-ENCODING: [0x78,0x4e,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644e78 <unknown>
+
+umlsl   za.s[w8, 0:1], z12.h, z2.h  // 11000001-01100010-00001101-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1], z12.h, z2.h
+// CHECK-ENCODING: [0x98,0x0d,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620d98 <unknown>
+
+umlsl   za.s[w10, 2:3], z1.h, z10.h  // 11000001-01101010-01001100-00111001
+// CHECK-INST: umlsl   za.s[w10, 2:3], z1.h, z10.h
+// CHECK-ENCODING: [0x39,0x4c,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4c39 <unknown>
+
+umlsl   za.s[w8, 10:11], z22.h, z14.h  // 11000001-01101110-00001110-11011101
+// CHECK-INST: umlsl   za.s[w8, 10:11], z22.h, z14.h
+// CHECK-ENCODING: [0xdd,0x0e,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0edd <unknown>
+
+umlsl   za.s[w11, 4:5], z9.h, z1.h  // 11000001-01100001-01101101-00111010
+// CHECK-INST: umlsl   za.s[w11, 4:5], z9.h, z1.h
+// CHECK-ENCODING: [0x3a,0x6d,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1616d3a <unknown>
+
+umlsl   za.s[w9, 14:15], z12.h, z11.h  // 11000001-01101011-00101101-10011111
+// CHECK-INST: umlsl   za.s[w9, 14:15], z12.h, z11.h
+// CHECK-ENCODING: [0x9f,0x2d,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b2d9f <unknown>
+
+
+umlsl   za.s[w8, 0:1], z0.h, z0.h[0]  // 11000001-11000000-00010000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1], z0.h, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01018 <unknown>
+
+umlsl   za.s[w10, 10:11], z10.h, z5.h[1]  // 11000001-11000101-01010101-01011101
+// CHECK-INST: umlsl   za.s[w10, 10:11], z10.h, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x55,0xc5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c5555d <unknown>
+
+umlsl   za.s[w11, 14:15], z13.h, z8.h[7]  // 11000001-11001000-11111101-10111111
+// CHECK-INST: umlsl   za.s[w11, 14:15], z13.h, z8.h[7]
+// CHECK-ENCODING: [0xbf,0xfd,0xc8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c8fdbf <unknown>
+
+umlsl   za.s[w11, 14:15], z31.h, z15.h[7]  // 11000001-11001111-11111111-11111111
+// CHECK-INST: umlsl   za.s[w11, 14:15], z31.h, z15.h[7]
+// CHECK-ENCODING: [0xff,0xff,0xcf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cfffff <unknown>
+
+umlsl   za.s[w8, 10:11], z17.h, z0.h[3]  // 11000001-11000000-00011110-00111101
+// CHECK-INST: umlsl   za.s[w8, 10:11], z17.h, z0.h[3]
+// CHECK-ENCODING: [0x3d,0x1e,0xc0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c01e3d <unknown>
+
+umlsl   za.s[w8, 2:3], z1.h, z14.h[5]  // 11000001-11001110-10010100-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3], z1.h, z14.h[5]
+// CHECK-ENCODING: [0x39,0x94,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce9439 <unknown>
+
+umlsl   za.s[w10, 0:1], z19.h, z4.h[1]  // 11000001-11000100-01010110-01111000
+// CHECK-INST: umlsl   za.s[w10, 0:1], z19.h, z4.h[1]
+// CHECK-ENCODING: [0x78,0x56,0xc4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c45678 <unknown>
+
+umlsl   za.s[w8, 0:1], z12.h, z2.h[2]  // 11000001-11000010-00011001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1], z12.h, z2.h[2]
+// CHECK-ENCODING: [0x98,0x19,0xc2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c21998 <unknown>
+
+umlsl   za.s[w10, 2:3], z1.h, z10.h[6]  // 11000001-11001010-11011000-00111001
+// CHECK-INST: umlsl   za.s[w10, 2:3], z1.h, z10.h[6]
+// CHECK-ENCODING: [0x39,0xd8,0xca,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cad839 <unknown>
+
+umlsl   za.s[w8, 10:11], z22.h, z14.h[2]  // 11000001-11001110-00011010-11011101
+// CHECK-INST: umlsl   za.s[w8, 10:11], z22.h, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x1a,0xce,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ce1add <unknown>
+
+umlsl   za.s[w11, 4:5], z9.h, z1.h[5]  // 11000001-11000001-11110101-00111010
+// CHECK-INST: umlsl   za.s[w11, 4:5], z9.h, z1.h[5]
+// CHECK-ENCODING: [0x3a,0xf5,0xc1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1c1f53a <unknown>
+
+umlsl   za.s[w9, 14:15], z12.h, z11.h[6]  // 11000001-11001011-10111001-10011111
+// CHECK-INST: umlsl   za.s[w9, 14:15], z12.h, z11.h[6]
+// CHECK-ENCODING: [0x9f,0xb9,0xcb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1cbb99f <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h  // 11000001, 01100000, 00001000, 00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600818 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h  // 11000001-01100000-00001000-00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600818 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h  // 11000001, 01100101, 01001001, 01011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654959 <unknown>
+
+umlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h  // 11000001-01100101-01001001-01011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1654959 <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z13.h, z14.h}, z8.h  // 11000001, 01101000, 01101001, 10111011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869bb <unknown>
+
+umlsl   za.s[w11, 6:7], {z13.h - z14.h}, z8.h  // 11000001-01101000-01101001-10111011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16869bb <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z31.h, z0.h}, z15.h  // 11000001, 01101111, 01101011, 11111011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6bfb <unknown>
+
+umlsl   za.s[w11, 6:7], {z31.h - z0.h}, z15.h  // 11000001-01101111-01101011-11111011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16f6bfb <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z17.h, z18.h}, z0.h  // 11000001, 01100000, 00001010, 00111001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a39 <unknown>
+
+umlsl   za.s[w8, 2:3], {z17.h - z18.h}, z0.h  // 11000001-01100000-00001010-00111001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1600a39 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z1.h, z2.h}, z14.h  // 11000001, 01101110, 00001000, 00111001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0839 <unknown>
+
+umlsl   za.s[w8, 2:3], {z1.h - z2.h}, z14.h  // 11000001-01101110-00001000-00111001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0839 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx2], {z19.h, z20.h}, z4.h  // 11000001, 01100100, 01001010, 01111000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a78 <unknown>
+
+umlsl   za.s[w10, 0:1], {z19.h - z20.h}, z4.h  // 11000001-01100100-01001010-01111000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x64,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1644a78 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h  // 11000001, 01100010, 00001001, 10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h  // 11000001-01100010-00001001-10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x62,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1620998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z1.h, z2.h}, z10.h  // 11000001, 01101010, 01001000, 00111001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4839 <unknown>
+
+umlsl   za.s[w10, 2:3], {z1.h - z2.h}, z10.h  // 11000001-01101010-01001000-00111001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x6a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16a4839 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h  // 11000001, 01101110, 00001010, 11011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ad9 <unknown>
+
+umlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h  // 11000001-01101110-00001010-11011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x6e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16e0ad9 <unknown>
+
+umlsl   za.s[w11, 4:5, vgx2], {z9.h, z10.h}, z1.h  // 11000001, 01100001, 01101001, 00111010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c161693a <unknown>
+
+umlsl   za.s[w11, 4:5], {z9.h - z10.h}, z1.h  // 11000001-01100001-01101001-00111010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c161693a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h  // 11000001, 01101011, 00101001, 10011011
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b299b <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h  // 11000001-01101011-00101001-10011011
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x6b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16b299b <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, z0.h[0]  // 11000001, 11010000, 00010000, 00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01018 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z1.h}, z0.h[0]  // 11000001-11010000-00010000-00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01018 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, z5.h[3]  // 11000001, 11010101, 01010101, 01011101
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x5d,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5555d <unknown>
+
+umlsl   za.s[w10, 2:3], {z10.h - z11.h}, z5.h[3]  // 11000001-11010101-01010101-01011101
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x5d,0x55,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5555d <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, z8.h[7]  // 11000001, 11011000, 01111101, 10011111
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d9f <unknown>
+
+umlsl   za.s[w11, 6:7], {z12.h - z13.h}, z8.h[7]  // 11000001-11011000-01111101-10011111
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0x7d,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d87d9f <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, z15.h[7]  // 11000001, 11011111, 01111111, 11011111
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xdf,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fdf <unknown>
+
+umlsl   za.s[w11, 6:7], {z30.h - z31.h}, z15.h[7]  // 11000001-11011111-01111111-11011111
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]
+// CHECK-ENCODING: [0xdf,0x7f,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df7fdf <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, z0.h[7]  // 11000001, 11010000, 00011110, 00011101
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e1d <unknown>
+
+umlsl   za.s[w8, 2:3], {z16.h - z17.h}, z0.h[7]  // 11000001-11010000-00011110-00011101
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x1e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d01e1d <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, z14.h[2]  // 11000001, 11011110, 00010100, 00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1419 <unknown>
+
+umlsl   za.s[w8, 2:3], {z0.h - z1.h}, z14.h[2]  // 11000001-11011110-00010100-00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x14,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1419 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, z4.h[2]  // 11000001, 11010100, 01010110, 01011000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x58,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45658 <unknown>
+
+umlsl   za.s[w10, 0:1], {z18.h - z19.h}, z4.h[2]  // 11000001-11010100-01010110-01011000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x58,0x56,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d45658 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, z2.h[4]  // 11000001, 11010010, 00011001, 10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z13.h}, z2.h[4]  // 11000001-11010010-00011001-10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x19,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d21998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, z10.h[4]  // 11000001, 11011010, 01011000, 00011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5819 <unknown>
+
+umlsl   za.s[w10, 2:3], {z0.h - z1.h}, z10.h[4]  // 11000001-11011010-01011000-00011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0x58,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da5819 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, z14.h[5]  // 11000001, 11011110, 00011010, 11011101
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xdd,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1add <unknown>
+
+umlsl   za.s[w8, 2:3], {z22.h - z23.h}, z14.h[5]  // 11000001-11011110-00011010-11011101
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]
+// CHECK-ENCODING: [0xdd,0x1a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de1add <unknown>
+
+umlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, z1.h[2]  // 11000001, 11010001, 01110101, 00011010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1751a <unknown>
+
+umlsl   za.s[w11, 4:5], {z8.h - z9.h}, z1.h[2]  // 11000001-11010001-01110101-00011010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0x75,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1751a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, z11.h[5]  // 11000001, 11011011, 00111001, 10011111
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db399f <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z13.h}, z11.h[5]  // 11000001-11011011-00111001-10011111
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0x39,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db399f <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx2], {z0.h, z1.h}, {z0.h, z1.h}  // 11000001, 11100000, 00001000, 00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x18,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00818 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z1.h}, {z0.h - z1.h}  // 11000001-11100000-00001000-00011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x18,0x08,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e00818 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z10.h, z11.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001001, 01011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x59,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44959 <unknown>
+
+umlsl   za.s[w10, 2:3], {z10.h - z11.h}, {z20.h - z21.h}  // 11000001-11110100-01001001-01011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x59,0x49,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44959 <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z12.h, z13.h}, {z8.h, z9.h}  // 11000001, 11101000, 01101001, 10011011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x9b,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8699b <unknown>
+
+umlsl   za.s[w11, 6:7], {z12.h - z13.h}, {z8.h - z9.h}  // 11000001-11101000-01101001-10011011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x9b,0x69,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8699b <unknown>
+
+umlsl   za.s[w11, 6:7, vgx2], {z30.h, z31.h}, {z30.h, z31.h}  // 11000001, 11111110, 01101011, 11011011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdb,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bdb <unknown>
+
+umlsl   za.s[w11, 6:7], {z30.h - z31.h}, {z30.h - z31.h}  // 11000001-11111110-01101011-11011011
+// CHECK, INST: umlsl   za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdb,0x6b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe6bdb <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z16.h, z17.h}, {z16.h, z17.h}  // 11000001, 11110000, 00001010, 00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x19,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a19 <unknown>
+
+umlsl   za.s[w8, 2:3], {z16.h - z17.h}, {z16.h - z17.h}  // 11000001-11110000-00001010-00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }
+// CHECK-ENCODING: [0x19,0x0a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f00a19 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z0.h, z1.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001000, 00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0819 <unknown>
+
+umlsl   za.s[w8, 2:3], {z0.h - z1.h}, {z30.h - z31.h}  // 11000001-11111110-00001000-00011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0819 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx2], {z18.h, z19.h}, {z20.h, z21.h}  // 11000001, 11110100, 01001010, 01011000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x58,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a58 <unknown>
+
+umlsl   za.s[w10, 0:1], {z18.h - z19.h}, {z20.h - z21.h}  // 11000001-11110100-01001010-01011000
+// CHECK, INST: umlsl   za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x58,0x4a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f44a58 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx2], {z12.h, z13.h}, {z2.h, z3.h}  // 11000001, 11100010, 00001001, 10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z13.h}, {z2.h - z3.h}  // 11000001-11100010-00001001-10011000
+// CHECK, INST: umlsl   za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e20998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx2], {z0.h, z1.h}, {z26.h, z27.h}  // 11000001, 11111010, 01001000, 00011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4819 <unknown>
+
+umlsl   za.s[w10, 2:3], {z0.h - z1.h}, {z26.h - z27.h}  // 11000001-11111010-01001000-00011001
+// CHECK, INST: umlsl   za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa4819 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx2], {z22.h, z23.h}, {z30.h, z31.h}  // 11000001, 11111110, 00001010, 11011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd9,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ad9 <unknown>
+
+umlsl   za.s[w8, 2:3], {z22.h - z23.h}, {z30.h - z31.h}  // 11000001-11111110-00001010-11011001
+// CHECK, INST: umlsl   za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xd9,0x0a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe0ad9 <unknown>
+
+umlsl   za.s[w11, 4:5, vgx2], {z8.h, z9.h}, {z0.h, z1.h}  // 11000001, 11100000, 01101001, 00011010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x1a,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0691a <unknown>
+
+umlsl   za.s[w11, 4:5], {z8.h - z9.h}, {z0.h - z1.h}  // 11000001-11100000-01101001-00011010
+// CHECK, INST: umlsl   za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x1a,0x69,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0691a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx2], {z12.h, z13.h}, {z10.h, z11.h}  // 11000001, 11101010, 00101001, 10011011
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea299b <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z13.h}, {z10.h - z11.h}  // 11000001-11101010-00101001-10011011
+// CHECK, INST: umlsl   za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea299b <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700818 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h  // 11000001-01110000-00001000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x18,0x08,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700818 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754959 <unknown>
+
+umlsl   za.s[w10, 2:3], {z10.h - z13.h}, z5.h  // 11000001-01110101-01001001-01011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h
+// CHECK-ENCODING: [0x59,0x49,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1754959 <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10111011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869bb <unknown>
+
+umlsl   za.s[w11, 6:7], {z13.h - z16.h}, z8.h  // 11000001-01111000-01101001-10111011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h
+// CHECK-ENCODING: [0xbb,0x69,0x78,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17869bb <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11111011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6bfb <unknown>
+
+umlsl   za.s[w11, 6:7], {z31.h, z0.h, z1.h, z2.h}, z15.h  // 11000001-01111111-01101011-11111011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h
+// CHECK-ENCODING: [0xfb,0x6b,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17f6bfb <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a39 <unknown>
+
+umlsl   za.s[w8, 2:3], {z17.h - z20.h}, z0.h  // 11000001-01110000-00001010-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h
+// CHECK-ENCODING: [0x39,0x0a,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1700a39 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0839 <unknown>
+
+umlsl   za.s[w8, 2:3], {z1.h - z4.h}, z14.h  // 11000001-01111110-00001000-00111001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h
+// CHECK-ENCODING: [0x39,0x08,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0839 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx4], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01111000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a78 <unknown>
+
+umlsl   za.s[w10, 0:1], {z19.h - z22.h}, z4.h  // 11000001-01110100-01001010-01111000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h
+// CHECK-ENCODING: [0x78,0x4a,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1744a78 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h  // 11000001-01110010-00001001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h
+// CHECK-ENCODING: [0x98,0x09,0x72,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1720998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00111001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4839 <unknown>
+
+umlsl   za.s[w10, 2:3], {z1.h - z4.h}, z10.h  // 11000001-01111010-01001000-00111001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h
+// CHECK-ENCODING: [0x39,0x48,0x7a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17a4839 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ad9 <unknown>
+
+umlsl   za.s[w8, 2:3], {z22.h - z25.h}, z14.h  // 11000001-01111110-00001010-11011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h
+// CHECK-ENCODING: [0xd9,0x0a,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17e0ad9 <unknown>
+
+umlsl   za.s[w11, 4:5, vgx4], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00111010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c171693a <unknown>
+
+umlsl   za.s[w11, 4:5], {z9.h - z12.h}, z1.h  // 11000001-01110001-01101001-00111010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h
+// CHECK-ENCODING: [0x3a,0x69,0x71,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c171693a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10011011
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b299b <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h  // 11000001-01111011-00101001-10011011
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h
+// CHECK-ENCODING: [0x9b,0x29,0x7b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17b299b <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09018 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z3.h}, z0.h[0]  // 11000001-11010000-10010000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09018 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00011101
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x1d,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d51d <unknown>
+
+umlsl   za.s[w10, 2:3], {z8.h - z11.h}, z5.h[3]  // 11000001-11010101-11010101-00011101
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]
+// CHECK-ENCODING: [0x1d,0xd5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5d51d <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10011111
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd9f <unknown>
+
+umlsl   za.s[w11, 6:7], {z12.h - z15.h}, z8.h[7]  // 11000001-11011000-11111101-10011111
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]
+// CHECK-ENCODING: [0x9f,0xfd,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8fd9f <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10011111
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x9f,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff9f <unknown>
+
+umlsl   za.s[w11, 6:7], {z28.h - z31.h}, z15.h[7]  // 11000001-11011111-11111111-10011111
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]
+// CHECK-ENCODING: [0x9f,0xff,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfff9f <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00011101
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e1d <unknown>
+
+umlsl   za.s[w8, 2:3], {z16.h - z19.h}, z0.h[7]  // 11000001-11010000-10011110-00011101
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]
+// CHECK-ENCODING: [0x1d,0x9e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d09e1d <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9419 <unknown>
+
+umlsl   za.s[w8, 2:3], {z0.h - z3.h}, z14.h[2]  // 11000001-11011110-10010100-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]
+// CHECK-ENCODING: [0x19,0x94,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9419 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00011000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x18,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d618 <unknown>
+
+umlsl   za.s[w10, 0:1], {z16.h - z19.h}, z4.h[2]  // 11000001-11010100-11010110-00011000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]
+// CHECK-ENCODING: [0x18,0xd6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4d618 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z15.h}, z2.h[4]  // 11000001-11010010-10011001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]
+// CHECK-ENCODING: [0x98,0x99,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d29998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad819 <unknown>
+
+umlsl   za.s[w10, 2:3], {z0.h - z3.h}, z10.h[4]  // 11000001-11011010-11011000-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]
+// CHECK-ENCODING: [0x19,0xd8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dad819 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10011101
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x9d,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a9d <unknown>
+
+umlsl   za.s[w8, 2:3], {z20.h - z23.h}, z14.h[5]  // 11000001-11011110-10011010-10011101
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]
+// CHECK-ENCODING: [0x9d,0x9a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de9a9d <unknown>
+
+umlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00011010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f51a <unknown>
+
+umlsl   za.s[w11, 4:5], {z8.h - z11.h}, z1.h[2]  // 11000001-11010001-11110101-00011010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]
+// CHECK-ENCODING: [0x1a,0xf5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1f51a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10011111
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb99f <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z15.h}, z11.h[5]  // 11000001-11011011-10111001-10011111
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]
+// CHECK-ENCODING: [0x9f,0xb9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dbb99f <unknown>
+
+
+umlsl   za.s[w8, 0:1, vgx4], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x18,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10818 <unknown>
+
+umlsl   za.s[w8, 0:1], {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-11100001-00001000-00011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x18,0x08,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10818 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x19,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54919 <unknown>
+
+umlsl   za.s[w10, 2:3], {z8.h - z11.h}, {z20.h - z23.h}  // 11000001-11110101-01001001-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x19,0x49,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54919 <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10011011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9699b <unknown>
+
+umlsl   za.s[w11, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-01101001-10011011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x69,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9699b <unknown>
+
+umlsl   za.s[w11, 6:7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10011011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9b,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b9b <unknown>
+
+umlsl   za.s[w11, 6:7], {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-11111101-01101011-10011011
+// CHECK-INST: umlsl   za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9b,0x6b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd6b9b <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x19,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a19 <unknown>
+
+umlsl   za.s[w8, 2:3], {z16.h - z19.h}, {z16.h - z19.h}  // 11000001-11110001-00001010-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }
+// CHECK-ENCODING: [0x19,0x0a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f10a19 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0819 <unknown>
+
+umlsl   za.s[w8, 2:3], {z0.h - z3.h}, {z28.h - z31.h}  // 11000001-11111101-00001000-00011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x19,0x08,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0819 <unknown>
+
+umlsl   za.s[w10, 0:1, vgx4], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00011000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x18,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a18 <unknown>
+
+umlsl   za.s[w10, 0:1], {z16.h - z19.h}, {z20.h - z23.h}  // 11000001-11110101-01001010-00011000
+// CHECK-INST: umlsl   za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x18,0x4a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f54a18 <unknown>
+
+umlsl   za.s[w8, 0:1, vgx4], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10998 <unknown>
+
+umlsl   za.s[w8, 0:1], {z12.h - z15.h}, {z0.h - z3.h}  // 11000001-11100001-00001001-10011000
+// CHECK-INST: umlsl   za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x98,0x09,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e10998 <unknown>
+
+umlsl   za.s[w10, 2:3, vgx4], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94819 <unknown>
+
+umlsl   za.s[w10, 2:3], {z0.h - z3.h}, {z24.h - z27.h}  // 11000001-11111001-01001000-00011001
+// CHECK-INST: umlsl   za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }
+// CHECK-ENCODING: [0x19,0x48,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f94819 <unknown>
+
+umlsl   za.s[w8, 2:3, vgx4], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x99,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a99 <unknown>
+
+umlsl   za.s[w8, 2:3], {z20.h - z23.h}, {z28.h - z31.h}  // 11000001-11111101-00001010-10011001
+// CHECK-INST: umlsl   za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x99,0x0a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd0a99 <unknown>
+
+umlsl   za.s[w11, 4:5, vgx4], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00011010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x1a,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1691a <unknown>
+
+umlsl   za.s[w11, 4:5], {z8.h - z11.h}, {z0.h - z3.h}  // 11000001-11100001-01101001-00011010
+// CHECK-INST: umlsl   za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x1a,0x69,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1691a <unknown>
+
+umlsl   za.s[w9, 6:7, vgx4], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10011011
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9299b <unknown>
+
+umlsl   za.s[w9, 6:7], {z12.h - z15.h}, {z8.h - z11.h}  // 11000001-11101001-00101001-10011011
+// CHECK-INST: umlsl   za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x9b,0x29,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9299b <unknown>
+