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Differential D137420

[AArch64][SVE2] Add the SVE2.1 integer quadword min/max reduction instructions
AbandonedPublic

Authored by david-arm on Nov 4 2022, 6:14 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
CarolineConcatto
kmclaughlin
efriedma
Summary

This patch adds the assembly/disassembly for the following instructions:

smaxqv : Signed maximum reduction of quadword vector segments
sminqv : Signed minimum reduction of quadword vector segments
umaxqv : Unsigned maximum reduction of quadword vector segments
uminqv : Unsigned minimum reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Unit TestsFailed

TimeTest
60,050 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

david-arm created this revision.Nov 4 2022, 6:14 AM
Herald added a reviewer: efriedma. · View Herald TranscriptNov 4 2022, 6:14 AM
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Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Nov 4 2022, 6:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2022, 6:14 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
david-arm added a parent revision: D137419: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions.Nov 4 2022, 6:14 AM
Harbormaster completed remote builds in B196128: Diff 473210.Nov 4 2022, 7:01 AM
paulwalker-arm added inline comments.Nov 4 2022, 9:30 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9285

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

Matt added a subscriber: Matt.Nov 5 2022, 8:34 PM
david-arm abandoned this revision.Nov 9 2022, 4:55 AM
david-arm mentioned this in D137411: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions.

Now covered by D137411

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
27 lines
test/
MC/
AArch64/
SVE2p1/
30 lines
115 lines
30 lines
115 lines
30 lines
115 lines
30 lines
115 lines

Diff 473210

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,701 Lines • ▼ Show 20 Lines
defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">; defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">;
defm ANDQV : sve2p1_log_reduction_q<0b10, "andqv">; defm ANDQV : sve2p1_log_reduction_q<0b10, "andqv">;
defm ADDQV : sve2p1_add_reduction_q<0b01, "addqv">; defm ADDQV : sve2p1_add_reduction_q<0b01, "addqv">;
defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv">; defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv">;
defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">; defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">;
defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">; defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">;
defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">; defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">; defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">;
defm SMAXQV : sve2p1_minmax_reduction_q<0b00, "smaxqv">;
defm UMAXQV : sve2p1_minmax_reduction_q<0b01, "umaxqv">;
defm SMINQV : sve2p1_minmax_reduction_q<0b10, "sminqv">;
defm UMINQV : sve2p1_minmax_reduction_q<0b11, "uminqv">;
} }

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,273 Lines • ▼ Show 20 Linesclass sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
let Inst{4-0} = Vd; let Inst{4-0} = Vd;
} }
multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> { multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> {
def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">; def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">; def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">; def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
} }
// SVE integer min/max reduction (quadwords)
class sve2p1_minmax_reduction_q<bits<2> sz, bits<2> opc, string mnemonic,
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

paulwalker-arm: As per my comment on D137411, can you use a similar class hierarchy as use by the normal…
RegisterOperand zpr_ty, string vec_sfx>
: I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
"", []>, Sched<[]> {
bits<5> Vd;
bits<5> Zn;
bits<3> Pg;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz;
let Inst{21-18} = 0b0011;
let Inst{17-16} = opc;
let Inst{15-13} = 0b001;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Vd;
}
multiclass sve2p1_minmax_reduction_q<bits<2> opc, string mnemonic> {
def _B : sve2p1_minmax_reduction_q<0b00, opc, mnemonic, ZPR8, "16b">;
def _H : sve2p1_minmax_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_minmax_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_minmax_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
}

llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
smaxqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smaxqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
smaxqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smaxqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smaxqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smaxqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
smaxqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smaxqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/smaxqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
smaxqv v0.8h, p0, z0.h // 00000100-01001100-00100000-00000000
// CHECK-INST: smaxqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c2000 <unknown>
smaxqv v21.8h, p5, z10.h // 00000100-01001100-00110101-01010101
// CHECK-INST: smaxqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c3555 <unknown>
smaxqv v23.8h, p3, z13.h // 00000100-01001100-00101101-10110111
// CHECK-INST: smaxqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c2db7 <unknown>
smaxqv v31.8h, p7, z31.h // 00000100-01001100-00111111-11111111
// CHECK-INST: smaxqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c3fff <unknown>
smaxqv v0.4s, p0, z0.s // 00000100-10001100-00100000-00000000
// CHECK-INST: smaxqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c2000 <unknown>
smaxqv v21.4s, p5, z10.s // 00000100-10001100-00110101-01010101
// CHECK-INST: smaxqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c3555 <unknown>
smaxqv v23.4s, p3, z13.s // 00000100-10001100-00101101-10110111
// CHECK-INST: smaxqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c2db7 <unknown>
smaxqv v31.4s, p7, z31.s // 00000100-10001100-00111111-11111111
// CHECK-INST: smaxqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c3fff <unknown>
smaxqv v0.2d, p0, z0.d // 00000100-11001100-00100000-00000000
// CHECK-INST: smaxqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc2000 <unknown>
smaxqv v21.2d, p5, z10.d // 00000100-11001100-00110101-01010101
// CHECK-INST: smaxqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc3555 <unknown>
smaxqv v23.2d, p3, z13.d // 00000100-11001100-00101101-10110111
// CHECK-INST: smaxqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc2db7 <unknown>
smaxqv v31.2d, p7, z31.d // 00000100-11001100-00111111-11111111
// CHECK-INST: smaxqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc3fff <unknown>
smaxqv v0.16b, p0, z0.b // 00000100-00001100-00100000-00000000
// CHECK-INST: smaxqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c2000 <unknown>
smaxqv v21.16b, p5, z10.b // 00000100-00001100-00110101-01010101
// CHECK-INST: smaxqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c3555 <unknown>
smaxqv v23.16b, p3, z13.b // 00000100-00001100-00101101-10110111
// CHECK-INST: smaxqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c2db7 <unknown>
smaxqv v31.16b, p7, z31.b // 00000100-00001100-00111111-11111111
// CHECK-INST: smaxqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
sminqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sminqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
sminqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sminqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sminqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sminqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
sminqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sminqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sminqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sminqv v0.8h, p0, z0.h // 00000100-01001110-00100000-00000000
// CHECK-INST: sminqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e2000 <unknown>
sminqv v21.8h, p5, z10.h // 00000100-01001110-00110101-01010101
// CHECK-INST: sminqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e3555 <unknown>
sminqv v23.8h, p3, z13.h // 00000100-01001110-00101101-10110111
// CHECK-INST: sminqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e2db7 <unknown>
sminqv v31.8h, p7, z31.h // 00000100-01001110-00111111-11111111
// CHECK-INST: sminqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e3fff <unknown>
sminqv v0.4s, p0, z0.s // 00000100-10001110-00100000-00000000
// CHECK-INST: sminqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e2000 <unknown>
sminqv v21.4s, p5, z10.s // 00000100-10001110-00110101-01010101
// CHECK-INST: sminqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e3555 <unknown>
sminqv v23.4s, p3, z13.s // 00000100-10001110-00101101-10110111
// CHECK-INST: sminqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e2db7 <unknown>
sminqv v31.4s, p7, z31.s // 00000100-10001110-00111111-11111111
// CHECK-INST: sminqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e3fff <unknown>
sminqv v0.2d, p0, z0.d // 00000100-11001110-00100000-00000000
// CHECK-INST: sminqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce2000 <unknown>
sminqv v21.2d, p5, z10.d // 00000100-11001110-00110101-01010101
// CHECK-INST: sminqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce3555 <unknown>
sminqv v23.2d, p3, z13.d // 00000100-11001110-00101101-10110111
// CHECK-INST: sminqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce2db7 <unknown>
sminqv v31.2d, p7, z31.d // 00000100-11001110-00111111-11111111
// CHECK-INST: sminqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce3fff <unknown>
sminqv v0.16b, p0, z0.b // 00000100-00001110-00100000-00000000
// CHECK-INST: sminqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e2000 <unknown>
sminqv v21.16b, p5, z10.b // 00000100-00001110-00110101-01010101
// CHECK-INST: sminqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e3555 <unknown>
sminqv v23.16b, p3, z13.b // 00000100-00001110-00101101-10110111
// CHECK-INST: sminqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e2db7 <unknown>
sminqv v31.16b, p7, z31.b // 00000100-00001110-00111111-11111111
// CHECK-INST: sminqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
umaxqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umaxqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
umaxqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umaxqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umaxqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umaxqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
umaxqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umaxqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/umaxqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
umaxqv v0.8h, p0, z0.h // 00000100-01001101-00100000-00000000
// CHECK-INST: umaxqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d2000 <unknown>
umaxqv v21.8h, p5, z10.h // 00000100-01001101-00110101-01010101
// CHECK-INST: umaxqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d3555 <unknown>
umaxqv v23.8h, p3, z13.h // 00000100-01001101-00101101-10110111
// CHECK-INST: umaxqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d2db7 <unknown>
umaxqv v31.8h, p7, z31.h // 00000100-01001101-00111111-11111111
// CHECK-INST: umaxqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d3fff <unknown>
umaxqv v0.4s, p0, z0.s // 00000100-10001101-00100000-00000000
// CHECK-INST: umaxqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d2000 <unknown>
umaxqv v21.4s, p5, z10.s // 00000100-10001101-00110101-01010101
// CHECK-INST: umaxqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d3555 <unknown>
umaxqv v23.4s, p3, z13.s // 00000100-10001101-00101101-10110111
// CHECK-INST: umaxqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d2db7 <unknown>
umaxqv v31.4s, p7, z31.s // 00000100-10001101-00111111-11111111
// CHECK-INST: umaxqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d3fff <unknown>
umaxqv v0.2d, p0, z0.d // 00000100-11001101-00100000-00000000
// CHECK-INST: umaxqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd2000 <unknown>
umaxqv v21.2d, p5, z10.d // 00000100-11001101-00110101-01010101
// CHECK-INST: umaxqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd3555 <unknown>
umaxqv v23.2d, p3, z13.d // 00000100-11001101-00101101-10110111
// CHECK-INST: umaxqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd2db7 <unknown>
umaxqv v31.2d, p7, z31.d // 00000100-11001101-00111111-11111111
// CHECK-INST: umaxqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd3fff <unknown>
umaxqv v0.16b, p0, z0.b // 00000100-00001101-00100000-00000000
// CHECK-INST: umaxqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d2000 <unknown>
umaxqv v21.16b, p5, z10.b // 00000100-00001101-00110101-01010101
// CHECK-INST: umaxqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d3555 <unknown>
umaxqv v23.16b, p3, z13.b // 00000100-00001101-00101101-10110111
// CHECK-INST: umaxqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d2db7 <unknown>
umaxqv v31.16b, p7, z31.b // 00000100-00001101-00111111-11111111
// CHECK-INST: umaxqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
uminqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uminqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
uminqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uminqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uminqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uminqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
uminqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uminqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uminqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uminqv v0.8h, p0, z0.h // 00000100-01001111-00100000-00000000
// CHECK-INST: uminqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f2000 <unknown>
uminqv v21.8h, p5, z10.h // 00000100-01001111-00110101-01010101
// CHECK-INST: uminqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f3555 <unknown>
uminqv v23.8h, p3, z13.h // 00000100-01001111-00101101-10110111
// CHECK-INST: uminqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f2db7 <unknown>
uminqv v31.8h, p7, z31.h // 00000100-01001111-00111111-11111111
// CHECK-INST: uminqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f3fff <unknown>
uminqv v0.4s, p0, z0.s // 00000100-10001111-00100000-00000000
// CHECK-INST: uminqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f2000 <unknown>
uminqv v21.4s, p5, z10.s // 00000100-10001111-00110101-01010101
// CHECK-INST: uminqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f3555 <unknown>
uminqv v23.4s, p3, z13.s // 00000100-10001111-00101101-10110111
// CHECK-INST: uminqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f2db7 <unknown>
uminqv v31.4s, p7, z31.s // 00000100-10001111-00111111-11111111
// CHECK-INST: uminqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f3fff <unknown>
uminqv v0.2d, p0, z0.d // 00000100-11001111-00100000-00000000
// CHECK-INST: uminqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf2000 <unknown>
uminqv v21.2d, p5, z10.d // 00000100-11001111-00110101-01010101
// CHECK-INST: uminqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf3555 <unknown>
uminqv v23.2d, p3, z13.d // 00000100-11001111-00101101-10110111
// CHECK-INST: uminqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf2db7 <unknown>
uminqv v31.2d, p7, z31.d // 00000100-11001111-00111111-11111111
// CHECK-INST: uminqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf3fff <unknown>
uminqv v0.16b, p0, z0.b // 00000100-00001111-00100000-00000000
// CHECK-INST: uminqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f2000 <unknown>
uminqv v21.16b, p5, z10.b // 00000100-00001111-00110101-01010101
// CHECK-INST: uminqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f3555 <unknown>
uminqv v23.16b, p3, z13.b // 00000100-00001111-00101101-10110111
// CHECK-INST: uminqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f2db7 <unknown>
uminqv v31.16b, p7, z31.b // 00000100-00001111-00111111-11111111
// CHECK-INST: uminqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f3fff <unknown>