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[RISCV] Add MC support of RISCV zcmp Extension
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Authored by VincentWu on Aug 28 2022, 8:24 PM.

Details

Summary

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise mv inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Diff Detail

Event Timeline

VincentWu created this revision.Aug 28 2022, 8:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 28 2022, 8:24 PM
VincentWu requested review of this revision.Aug 28 2022, 8:24 PM
llvm/lib/Target/RISCV/RISCVFrameLowering.h
49 ↗(On Diff #456238)

Where is the implementation of this function?

VincentWu marked an inline comment as done.

clear patch

Herald added a project: Restricted Project. · View Herald TranscriptAug 29 2022, 10:33 PM
Herald added a subscriber: cfe-commits. · View Herald Transcript

I found a lot of ZCE/zce, do we need to change ZCE to ZCMP?

VincentWu updated this revision to Diff 459617.Sep 12 2022, 6:34 PM
VincentWu edited the summary of this revision. (Show Details)
VincentWu added a reviewer: asb.

address comments

VincentWu updated this revision to Diff 459620.Sep 12 2022, 6:35 PM

add newline at end of file

craig.topper added inline comments.Sep 26 2022, 9:55 AM
llvm/lib/Support/RISCVISAInfo.cpp
139

Why is zcb mixed into this patch?

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
327

Capitalize

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
197

Can we generate this more programmatically than having 12 unique strings?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
214

Capitalize variables

220

assert(rlistVal != 16 && "Incorrect rlist.");

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
497

assert(Imm >= 4 && "EABI is currently not implemented");

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
1077 ↗(On Diff #459620)

This is not MC layer and there's no caller in this patch.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
9

This isn't completely accurace since Zca is in RISCVInstrInfoC.td

136

too much indentation

llvm/lib/Target/RISCV/RISCVRegisterInfo.td
187

Where is this used?

VincentWu updated this revision to Diff 463134.Sep 27 2022, 1:02 AM
VincentWu marked 9 inline comments as done.

address comments

VincentWu updated this revision to Diff 496985.Feb 13 2023, 7:41 AM

add doc & update to v1.0

craig.topper added inline comments.Feb 13 2023, 2:01 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
337

Is this IsRV64 field used?

342

Is this IsRV64 field used?

1137

getRoundingMode shouldn't be in this patch

2357

FixMe -> FIXME

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
453

This comment looks copy/pasted from somewhere else?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
230

Does this work?

OS << "-s" << (SlistEncode - 5);
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
510

Should use this define instead writing 16 in several places? Or maybe rename this so it's obviously invalid?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
223

Combine the if into an assert?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
97

What are these functions?

llvm/lib/Target/RISCV/RISCVFeatures.td
359

Line AssemblerPredicate up with the "Subtarget on the previous line.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
70

Extra space before isShiftedUInt

125

These lines were deleted when the Zcb patch was merged.

250

What happened here?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td
178

Zc -> Zcmp?

llvm/lib/Target/RISCV/RISCVSchedRocket.td
21 ↗(On Diff #496985)

While this is probably correct, since it says Zcb and not Zcmp, it doesn't belong in this patch.

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
18 ↗(On Diff #496985)

Same

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
83 ↗(On Diff #496985)

????

llvm/test/MC/RISCV/attribute-arch.s
213

??????

VincentWu marked 19 inline comments as done.

address comments

VincentWu updated this revision to Diff 510661.Apr 3 2023, 6:58 PM

rename FeatureExtZcmp -> FeatureStdExtZcmp

jrtc27 added inline comments.Apr 11 2023, 11:28 AM
clang/test/Preprocessor/riscv-target-features.c
51

Does this really belong in an MC patch?

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
2317

What's UABI, a term that I've only really seen in the Linux community, got to do with assembly?

asb added inline comments.Apr 12 2023, 1:45 AM
clang/test/Preprocessor/riscv-target-features.c
51

We typically do include this test change in the initial MC layer patch on the basis that the change becomes testable as soon as MC layer support is introduced (and indeed might be used for e.g. ifdefing inline assembler, so isn't really only useful in the presence of codegen/intrinsics support).

VincentWu updated this revision to Diff 516042.Apr 22 2023, 1:13 AM
VincentWu marked an inline comment as done.

address comment, remove wrong comments

kito-cheng added inline comments.Apr 24 2023, 3:06 AM
llvm/test/CodeGen/RISCV/O0-pipeline.ll
66–67 ↗(On Diff #516042)

This should split out into separated patch?

llvm/test/CodeGen/RISCV/O3-pipeline.ll
179–180 ↗(On Diff #516042)

This should split out into separated patch?

VincentWu updated this revision to Diff 516435.Apr 24 2023, 9:16 AM
VincentWu marked 2 inline comments as done.

remove testcse of Codegen & rebase

Need to update RISCVUsage.rst

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
968

Why curly braces when everything else uses < and >?

1056

Capitalize spimm

2337

Should we be using ParseFail with more specific error messages instead of NoMatch once we start calling Lex() on tokens? If you use NoMatch, I think we need to unwind the tokens that have been lexed.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
513

isCInst and IsRV32E are unused.

515

Get rid of the lambda. Create a variable and assign to it in the switch.

550

Capitalize variable names

554

Drop curly braces around single line if

602

Capitalize variable names

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
494

immidiate -> immediate

llvm/lib/Target/RISCV/RISCVFeatures.td
356

Drop the . after reduction

360

Drop the . after reduction

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
132

This isn't used

174

ZCMP -> Zcmp

llvm/test/CodeGen/RISCV/attributes.ll
73 ↗(On Diff #516435)

Drop this change

llvm/test/MC/RISCV/rv32zcmp-invalid.s
6

Do we need to check that we don't except mvsa01 s0, s0? The spec says the two s registers must be different.

kito-cheng added inline comments.Apr 24 2023, 7:40 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
2406

parseZcSpimm -> parseZcmpSpimm

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
477

decodeZcRlist -> decodeZcmpRlist

486

decodeZcSpimm -> decodeZcmpSpimm

VincentWu marked 18 inline comments as done.

address comments
check invalid mvsa01 s0, s0

craig.topper added inline comments.Apr 26 2023, 10:09 AM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
1466

like -> be

"operand must be '{ra [, s0[-sN]]}' or '{x1 [, x8[-x9][, x18[-xN]]]}'"
2365

Need to call Error before returning ParseFail

2435

You can check this in validateInstruction instead of during parsing. Then you don't need a custom parser.

VincentWu updated this revision to Diff 517494.Apr 27 2023, 2:28 AM
VincentWu marked 3 inline comments as done.

address comments

craig.topper added inline comments.Apr 27 2023, 10:14 AM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
3147

mast -> must

craig.topper added inline comments.Apr 27 2023, 10:35 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
1048

Drop IsRV64

1056

Drop IsRV64

1472

Drop the word "This" from the beginning. Drop the word "Please".

Something like

stack adjustment is invalid for this instruction and register; refer to Zc spec for a detailed range of stack adjustment

2321

Rlist -> register list

2321

General comment, error messages should not start with capitalized words.

2350

registers -> register

2367

This sentence is awkward.

Something like

"contiguous register list for EABI can only be 's0-1' or 'x8-x9'"

2379

XRlist -> register list

2393

XRList -> register list

2423

Rlist -> register list

2433

Don't capitalize Register

VincentWu updated this revision to Diff 518662.May 2 2023, 2:48 AM
VincentWu marked 12 inline comments as done.

address comment

craig.topper accepted this revision.May 2 2023, 10:48 AM

LGTM with the last 4 few comments addressed.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
550

assert(RlistVal != RLISTENCODE::INVALID_RLIST && "{ra, s0-s10} is not supported, s11 must be included.")

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
494

This wasn't fixed. immediate is still misspelled

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
47

I think you can drop the ImmLeaf. That's only needed if this is used in an isel pattern, but I don't think it ever will be.

62

I think you can drop ImmLeaf. That's only needed for isel patterns.

This revision is now accepted and ready to land.May 2 2023, 10:48 AM
VincentWu updated this revision to Diff 519423.May 4 2023, 3:45 AM
VincentWu marked 4 inline comments as done.

address comments.

A Decoding Conflict error of zcmt was reported when I rebase to upstream.

refer to patch https://reviews.llvm.org/D149839

craig.topper requested changes to this revision.May 4 2023, 1:49 PM

The instructions need a DecoderNamespace to separate them from c.fsdsp. See D149891 for how I've done it for Zcmt.

This revision now requires changes to proceed.May 4 2023, 1:49 PM
VincentWu updated this revision to Diff 520046.May 6 2023, 1:43 AM

rebase & address comments

craig.topper added inline comments.May 6 2023, 12:38 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
3389

Why is this needed?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
208

This needs to obey ArchRegNames and print x1 instead of ra, x8 instead of s0 etc. when requested.

224

Spimm = -Spimm;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
493

const MCOperand &

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
58

Inconsistent spacing around >= and <=

174

These need to be in a DecoderNamespace like I did for Zcmt.

craig.topper requested changes to this revision.May 6 2023, 12:38 PM
This revision now requires changes to proceed.May 6 2023, 12:38 PM
VincentWu updated this revision to Diff 520170.May 7 2023, 5:42 AM
VincentWu marked 6 inline comments as done.

address comments

craig.topper added inline comments.May 7 2023, 11:19 AM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
3166

Drop this change

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
643

This description is from Zcmt.

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
228

This brace only closes Predicates = [HasStdExtZcmp]. The DecoderNamespace ended on line 189. It's only covering CM_MVA01S and CM_MVSA01.

VincentWu updated this revision to Diff 520253.May 7 2023, 10:24 PM
VincentWu marked 3 inline comments as done.

address comments

This revision is now accepted and ready to land.May 7 2023, 10:43 PM
This revision was landed with ongoing or failed builds.May 7 2023, 11:29 PM
This revision was automatically updated to reflect the committed changes.
MaskRay added inline comments.Jun 15 2023, 11:46 AM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
2441

Ignoring AsmToken::Minus looks suspicious.

evandro removed a subscriber: evandro.Jun 20 2023, 1:12 PM