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[RISCV] Add zihintntl instructions
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Authored by sunshaoce on Mar 15 2022, 12:07 AM.

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llvm/lib/Target/RISCV/RISCV.td
53

zihintpause?

s commandeered this revision.Mar 15 2022, 11:37 AM
s updated this revision to Diff 415703.Mar 15 2022, 11:03 PM

Add preprocessor test

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Rebase

sunshaoce commandeered this revision.Jun 20 2022, 11:09 PM
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This revision is now accepted and ready to land.Aug 21 2022, 7:49 PM
This revision was landed with ongoing or failed builds.Aug 21 2022, 9:06 PM
This revision was automatically updated to reflect the committed changes.

It seems that llvm implementation is different from Binutils/GCC. Binutils didn't regard ntl instructions as aliases of add since encoding space is reserved for HINT instructions.

asb added a comment.Mar 14 2023, 3:09 AM

It seems that llvm implementation is different from Binutils/GCC. Binutils didn't regard ntl instructions as aliases of add since encoding space is reserved for HINT instructions.

How does this different implementation approach show up in terms of user-visible behaviour?

Looking at the ISA spec, I think the use of the term "reserved" with respect to hint instructions is unfortunate, because I don't think the intended meaning isn't that they are considered a "reserved" encoding as defined in the categories of instructions, as otherwise it would be legal for implementations to trap when encountering a hint, making them impossible to deploy in a backward compatible way.

asb added a comment.Mar 14 2023, 3:31 AM

I've created a PR on the ISA manual to try to clarify the confusing overloaded use of the term "reserved" https://github.com/riscv/riscv-isa-manual/pull/990