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It seems that llvm implementation is different from Binutils/GCC. Binutils didn't regard ntl instructions as aliases of add since encoding space is reserved for HINT instructions.

Herald added subscribers: jobnoorman, luke. · View Herald TranscriptMar 14 2023, 2:39 AM

In D121670#4192158, @joshua-arch1 wrote:

It seems that llvm implementation is different from Binutils/GCC. Binutils didn't regard ntl instructions as aliases of add since encoding space is reserved for HINT instructions.

How does this different implementation approach show up in terms of user-visible behaviour?

Looking at the ISA spec, I think the use of the term "reserved" with respect to hint instructions is unfortunate, because I don't think the intended meaning isn't that they are considered a "reserved" encoding as defined in the categories of instructions, as otherwise it would be legal for implementations to trap when encountering a hint, making them impossible to deploy in a backward compatible way.

I've created a PR on the ISA manual to try to clarify the confusing overloaded use of the term "reserved" https://github.com/riscv/riscv-isa-manual/pull/990

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

[RISCV] Add zihintntl instructions
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Diff 454370

clang/test/Preprocessor/riscv-target-features.c

llvm/lib/Support/RISCVISAInfo.cpp

llvm/lib/Target/RISCV/RISCV.td

llvm/lib/Target/RISCV/RISCVInstrInfo.td

llvm/lib/Target/RISCV/RISCVSubtarget.h

llvm/test/CodeGen/RISCV/attributes.ll

llvm/test/MC/RISCV/rv32zihintntl-valid.s

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

[RISCV] Add zihintntl instructionsClosedPublicActions

Details

Diff Detail

Event Timeline

Revision ContentsChangeset List

Diff 454370

clang/test/Preprocessor/riscv-target-features.c

llvm/lib/Support/RISCVISAInfo.cpp

llvm/lib/Target/RISCV/RISCV.td

llvm/lib/Target/RISCV/RISCVInstrInfo.td

llvm/lib/Target/RISCV/RISCVSubtarget.h

llvm/test/CodeGen/RISCV/attributes.ll

llvm/test/MC/RISCV/rv32zihintntl-valid.s

[RISCV] Add zihintntl instructions
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