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Differential D119688

[RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics.
ClosedPublic

Authored by khchen on Feb 13 2022, 9:03 PM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
kito-cheng
arcbbb
monkchiang
eopXD
Commits
rGeeb7754f6853: [RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics.
Summary

Add the passthru operand for
VMV_V_X_VL, VFMV_V_F_VL and SPLAT_VECTOR_SPLIT_I64_VL also.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

Diff Detail

Revision Contents

PathSize
clang/
include/
clang/
Basic/
4 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
106 lines
rvv-intrinsics/
30 lines
206 lines
llvm/
include/
llvm/
IR/
21 lines
lib/
Target/
RISCV/
41 lines
7 lines
173 lines
32 lines
2 lines
43 lines
test/
CodeGen/
RISCV/
rvv/
6 lines
6 lines
109 lines
45 lines
74 lines
74 lines
70 lines
66 lines
20 lines
12 lines

Diff 408324

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 1,749 Lines • ▼ Show 20 Lineslet HasMask = false, HasPolicy = false,
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "csil", defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "csil",
[["vvm", "v", "vmvv"], [["vvm", "v", "vmvv"],
["vxm", "v", "vmve"], ["vxm", "v", "vmve"],
["vvm", "Uv", "UvmUvUv"], ["vvm", "Uv", "UvmUvUv"],
["vxm", "Uv", "UvmUvUe"]]>; ["vxm", "Uv", "UvmUvUe"]]>;
} }
// 12.16. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
let HasMask = false, HasPolicy = false in { let HasMask = false, HasNoMaskPolicy = true, HasPolicy = false in {
let MangledName = "vmv_v" in { let MangledName = "vmv_v" in {
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil", defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil",
[["v", "Uv", "UvUv"]]>; [["v", "Uv", "UvUv"]]>;
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd", defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd",
[["v", "v", "vv"]]>; [["v", "v", "vv"]]>;
} }
let HasNoMaskedOverloaded = false in let HasNoMaskedOverloaded = false in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil", defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lineslet HasMask = false, HasPolicy = false,
}] in { }] in {
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "xfd", defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "xfd",
[["vvm", "v", "vmvv"]]>; [["vvm", "v", "vmvv"]]>;
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vfm", "v", "vmve"]]>; [["vfm", "v", "vmve"]]>;
} }
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
let HasMask = false, HasNoMaskedOverloaded = false, HasPolicy = false in let HasMask = false, HasNoMaskPolicy = true, HasNoMaskedOverloaded = false, HasPolicy = false in
defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd", defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
[["f", "v", "ve"]]>; [["f", "v", "ve"]]>;
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
let HasNoMaskPolicy = true in { let HasNoMaskPolicy = true in {
def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">; def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">;
def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">; def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">;
def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">; def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) { vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) { vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) { vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) { return vmv_v(src, vl); } vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) { return vmv_v(src, vl); }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) { return vmv_v(src, vl); } vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) { return vmv_v(src, vl); }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) { return vmv_v(src, vl); } vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) { return vmv_v(src, vl); }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) { return vmv_v(src, vl); } vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) { return vmv_v(src, vl); }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) { vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) { vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) { vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) { vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) { vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) { vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) { vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) { vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) { vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) { vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) { vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) { vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) { vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) { vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) { vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) { vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) { vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) { vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) { vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) { vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) { vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) { vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) { vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) { vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) { vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) { vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) { vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) { vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) { vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) { vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) { vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) { vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) { vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) { vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) { vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) { vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) { vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) { vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) { vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) { vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) { vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) { vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) { vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) { vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) { vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) { vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) {
return vmv_v(src, vl); return vmv_v(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8( // CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2( // CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmv_v_f_f32mf2(float src, size_t vl) { vfloat32mf2_t test_vfmv_v_f_f32mf2(float src, size_t vl) {
return vfmv_v_f_f32mf2(src, vl); return vfmv_v_f_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m1( // CHECK-RV64-LABEL: @test_vfmv_v_f_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmv_v_f_f32m1(float src, size_t vl) { vfloat32m1_t test_vfmv_v_f_f32m1(float src, size_t vl) {
return vfmv_v_f_f32m1(src, vl); return vfmv_v_f_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m2( // CHECK-RV64-LABEL: @test_vfmv_v_f_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmv_v_f_f32m2(float src, size_t vl) { vfloat32m2_t test_vfmv_v_f_f32m2(float src, size_t vl) {
return vfmv_v_f_f32m2(src, vl); return vfmv_v_f_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m4( // CHECK-RV64-LABEL: @test_vfmv_v_f_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmv_v_f_f32m4(float src, size_t vl) { vfloat32m4_t test_vfmv_v_f_f32m4(float src, size_t vl) {
return vfmv_v_f_f32m4(src, vl); return vfmv_v_f_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f32m8( // CHECK-RV64-LABEL: @test_vfmv_v_f_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(float [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmv_v_f_f32m8(float src, size_t vl) { vfloat32m8_t test_vfmv_v_f_f32m8(float src, size_t vl) {
return vfmv_v_f_f32m8(src, vl); return vfmv_v_f_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m1( // CHECK-RV64-LABEL: @test_vfmv_v_f_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> undef, double [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmv_v_f_f64m1(double src, size_t vl) { vfloat64m1_t test_vfmv_v_f_f64m1(double src, size_t vl) {
return vfmv_v_f_f64m1(src, vl); return vfmv_v_f_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m2( // CHECK-RV64-LABEL: @test_vfmv_v_f_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> undef, double [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmv_v_f_f64m2(double src, size_t vl) { vfloat64m2_t test_vfmv_v_f_f64m2(double src, size_t vl) {
return vfmv_v_f_f64m2(src, vl); return vfmv_v_f_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m4( // CHECK-RV64-LABEL: @test_vfmv_v_f_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> undef, double [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmv_v_f_f64m4(double src, size_t vl) { vfloat64m4_t test_vfmv_v_f_f64m4(double src, size_t vl) {
return vfmv_v_f_f64m4(src, vl); return vfmv_v_f_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f64m8( // CHECK-RV64-LABEL: @test_vfmv_v_f_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.i64(double [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.i64(<vscale x 8 x double> undef, double [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmv_v_f_f64m8(double src, size_t vl) { vfloat64m8_t test_vfmv_v_f_f64m8(double src, size_t vl) {
return vfmv_v_f_f64m8(src, vl); return vfmv_v_f_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32( // CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmv_s_f_f64m8(vfloat64m8_t dst, double src, size_t vl) { vfloat64m8_t test_vfmv_s_f_f64m8(vfloat64m8_t dst, double src, size_t vl) {
return vfmv_s_f_f64m8(dst, src, vl); return vfmv_s_f_f64m8(dst, src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16mf4( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmv_v_f_f16mf4 (_Float16 src, size_t vl) { vfloat16mf4_t test_vfmv_v_f_f16mf4 (_Float16 src, size_t vl) {
return vfmv_v_f_f16mf4(src, vl); return vfmv_v_f_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16mf2( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmv_v_f_f16mf2 (_Float16 src, size_t vl) { vfloat16mf2_t test_vfmv_v_f_f16mf2 (_Float16 src, size_t vl) {
return vfmv_v_f_f16mf2(src, vl); return vfmv_v_f_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16m1( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmv_v_f_f16m1 (_Float16 src, size_t vl) { vfloat16m1_t test_vfmv_v_f_f16m1 (_Float16 src, size_t vl) {
return vfmv_v_f_f16m1(src, vl); return vfmv_v_f_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16m2( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmv_v_f_f16m2 (_Float16 src, size_t vl) { vfloat16m2_t test_vfmv_v_f_f16m2 (_Float16 src, size_t vl) {
return vfmv_v_f_f16m2(src, vl); return vfmv_v_f_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16m4( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmv_v_f_f16m4 (_Float16 src, size_t vl) { vfloat16m4_t test_vfmv_v_f_f16m4 (_Float16 src, size_t vl) {
return vfmv_v_f_f16m4(src, vl); return vfmv_v_f_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_v_f_f16m8( // CHECK-RV64-LABEL: @test_vfmv_v_f_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(half [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> undef, half [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmv_v_f_f16m8 (_Float16 src, size_t vl) { vfloat16m8_t test_vfmv_v_f_f16m8 (_Float16 src, size_t vl) {
return vfmv_v_f_f16m8(src, vl); return vfmv_v_f_f16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16mf4_f16( // CHECK-RV64-LABEL: @test_vfmv_f_s_f16mf4_f16(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) { vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) {
return vmv_v_v_i8mf8(src, vl); return vmv_v_v_i8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf8( // CHECK-RV64-LABEL: @test_vmv_v_x_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmv_v_x_i8mf8(int8_t src, size_t vl) { vint8mf8_t test_vmv_v_x_i8mf8(int8_t src, size_t vl) {
return vmv_v_x_i8mf8(src, vl); return vmv_v_x_i8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) { vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) {
return vmv_v_v_i8mf4(src, vl); return vmv_v_v_i8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf4( // CHECK-RV64-LABEL: @test_vmv_v_x_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmv_v_x_i8mf4(int8_t src, size_t vl) { vint8mf4_t test_vmv_v_x_i8mf4(int8_t src, size_t vl) {
return vmv_v_x_i8mf4(src, vl); return vmv_v_x_i8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) { vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) {
return vmv_v_v_i8mf2(src, vl); return vmv_v_v_i8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmv_v_x_i8mf2(int8_t src, size_t vl) { vint8mf2_t test_vmv_v_x_i8mf2(int8_t src, size_t vl) {
return vmv_v_x_i8mf2(src, vl); return vmv_v_x_i8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) { vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) {
return vmv_v_v_i8m1(src, vl); return vmv_v_v_i8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8m1( // CHECK-RV64-LABEL: @test_vmv_v_x_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmv_v_x_i8m1(int8_t src, size_t vl) { vint8m1_t test_vmv_v_x_i8m1(int8_t src, size_t vl) {
return vmv_v_x_i8m1(src, vl); return vmv_v_x_i8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) { vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) {
return vmv_v_v_i8m2(src, vl); return vmv_v_v_i8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8m2( // CHECK-RV64-LABEL: @test_vmv_v_x_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmv_v_x_i8m2(int8_t src, size_t vl) { vint8m2_t test_vmv_v_x_i8m2(int8_t src, size_t vl) {
return vmv_v_x_i8m2(src, vl); return vmv_v_x_i8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) { vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) {
return vmv_v_v_i8m4(src, vl); return vmv_v_v_i8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8m4( // CHECK-RV64-LABEL: @test_vmv_v_x_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmv_v_x_i8m4(int8_t src, size_t vl) { vint8m4_t test_vmv_v_x_i8m4(int8_t src, size_t vl) {
return vmv_v_x_i8m4(src, vl); return vmv_v_x_i8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i8m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) { vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) {
return vmv_v_v_i8m8(src, vl); return vmv_v_v_i8m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i8m8( // CHECK-RV64-LABEL: @test_vmv_v_x_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(<vscale x 64 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmv_v_x_i8m8(int8_t src, size_t vl) { vint8m8_t test_vmv_v_x_i8m8(int8_t src, size_t vl) {
return vmv_v_x_i8m8(src, vl); return vmv_v_x_i8m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) { vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) {
return vmv_v_v_i16mf4(src, vl); return vmv_v_v_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16mf4( // CHECK-RV64-LABEL: @test_vmv_v_x_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(<vscale x 1 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmv_v_x_i16mf4(int16_t src, size_t vl) { vint16mf4_t test_vmv_v_x_i16mf4(int16_t src, size_t vl) {
return vmv_v_x_i16mf4(src, vl); return vmv_v_x_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) { vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) {
return vmv_v_v_i16mf2(src, vl); return vmv_v_v_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(<vscale x 2 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmv_v_x_i16mf2(int16_t src, size_t vl) { vint16mf2_t test_vmv_v_x_i16mf2(int16_t src, size_t vl) {
return vmv_v_x_i16mf2(src, vl); return vmv_v_x_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) { vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) {
return vmv_v_v_i16m1(src, vl); return vmv_v_v_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16m1( // CHECK-RV64-LABEL: @test_vmv_v_x_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(<vscale x 4 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmv_v_x_i16m1(int16_t src, size_t vl) { vint16m1_t test_vmv_v_x_i16m1(int16_t src, size_t vl) {
return vmv_v_x_i16m1(src, vl); return vmv_v_x_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) { vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) {
return vmv_v_v_i16m2(src, vl); return vmv_v_v_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16m2( // CHECK-RV64-LABEL: @test_vmv_v_x_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(<vscale x 8 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmv_v_x_i16m2(int16_t src, size_t vl) { vint16m2_t test_vmv_v_x_i16m2(int16_t src, size_t vl) {
return vmv_v_x_i16m2(src, vl); return vmv_v_x_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) { vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) {
return vmv_v_v_i16m4(src, vl); return vmv_v_v_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16m4( // CHECK-RV64-LABEL: @test_vmv_v_x_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(<vscale x 16 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmv_v_x_i16m4(int16_t src, size_t vl) { vint16m4_t test_vmv_v_x_i16m4(int16_t src, size_t vl) {
return vmv_v_x_i16m4(src, vl); return vmv_v_x_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i16m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) { vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) {
return vmv_v_v_i16m8(src, vl); return vmv_v_v_i16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i16m8( // CHECK-RV64-LABEL: @test_vmv_v_x_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(<vscale x 32 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmv_v_x_i16m8(int16_t src, size_t vl) { vint16m8_t test_vmv_v_x_i16m8(int16_t src, size_t vl) {
return vmv_v_x_i16m8(src, vl); return vmv_v_x_i16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) { vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) {
return vmv_v_v_i32mf2(src, vl); return vmv_v_v_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmv_v_x_i32mf2(int32_t src, size_t vl) { vint32mf2_t test_vmv_v_x_i32mf2(int32_t src, size_t vl) {
return vmv_v_x_i32mf2(src, vl); return vmv_v_x_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) { vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) {
return vmv_v_v_i32m1(src, vl); return vmv_v_v_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i32m1( // CHECK-RV64-LABEL: @test_vmv_v_x_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(<vscale x 2 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmv_v_x_i32m1(int32_t src, size_t vl) { vint32m1_t test_vmv_v_x_i32m1(int32_t src, size_t vl) {
return vmv_v_x_i32m1(src, vl); return vmv_v_x_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) { vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) {
return vmv_v_v_i32m2(src, vl); return vmv_v_v_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i32m2( // CHECK-RV64-LABEL: @test_vmv_v_x_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(<vscale x 4 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmv_v_x_i32m2(int32_t src, size_t vl) { vint32m2_t test_vmv_v_x_i32m2(int32_t src, size_t vl) {
return vmv_v_x_i32m2(src, vl); return vmv_v_x_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) { vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) {
return vmv_v_v_i32m4(src, vl); return vmv_v_v_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i32m4( // CHECK-RV64-LABEL: @test_vmv_v_x_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(<vscale x 8 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmv_v_x_i32m4(int32_t src, size_t vl) { vint32m4_t test_vmv_v_x_i32m4(int32_t src, size_t vl) {
return vmv_v_x_i32m4(src, vl); return vmv_v_x_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) { vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) {
return vmv_v_v_i32m8(src, vl); return vmv_v_v_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i32m8( // CHECK-RV64-LABEL: @test_vmv_v_x_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(<vscale x 16 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmv_v_x_i32m8(int32_t src, size_t vl) { vint32m8_t test_vmv_v_x_i32m8(int32_t src, size_t vl) {
return vmv_v_x_i32m8(src, vl); return vmv_v_x_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) { vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) {
return vmv_v_v_i64m1(src, vl); return vmv_v_v_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i64m1( // CHECK-RV64-LABEL: @test_vmv_v_x_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(<vscale x 1 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmv_v_x_i64m1(int64_t src, size_t vl) { vint64m1_t test_vmv_v_x_i64m1(int64_t src, size_t vl) {
return vmv_v_x_i64m1(src, vl); return vmv_v_x_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) { vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) {
return vmv_v_v_i64m2(src, vl); return vmv_v_v_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i64m2( // CHECK-RV64-LABEL: @test_vmv_v_x_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(<vscale x 2 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmv_v_x_i64m2(int64_t src, size_t vl) { vint64m2_t test_vmv_v_x_i64m2(int64_t src, size_t vl) {
return vmv_v_x_i64m2(src, vl); return vmv_v_x_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) { vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) {
return vmv_v_v_i64m4(src, vl); return vmv_v_v_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i64m4( // CHECK-RV64-LABEL: @test_vmv_v_x_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(<vscale x 4 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmv_v_x_i64m4(int64_t src, size_t vl) { vint64m4_t test_vmv_v_x_i64m4(int64_t src, size_t vl) {
return vmv_v_x_i64m4(src, vl); return vmv_v_x_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_i64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) { vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) {
return vmv_v_v_i64m8(src, vl); return vmv_v_v_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_i64m8( // CHECK-RV64-LABEL: @test_vmv_v_x_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(<vscale x 8 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmv_v_x_i64m8(int64_t src, size_t vl) { vint64m8_t test_vmv_v_x_i64m8(int64_t src, size_t vl) {
return vmv_v_x_i64m8(src, vl); return vmv_v_x_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) { vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) {
return vmv_v_v_u8mf8(src, vl); return vmv_v_v_u8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf8( // CHECK-RV64-LABEL: @test_vmv_v_x_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmv_v_x_u8mf8(uint8_t src, size_t vl) { vuint8mf8_t test_vmv_v_x_u8mf8(uint8_t src, size_t vl) {
return vmv_v_x_u8mf8(src, vl); return vmv_v_x_u8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) { vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) {
return vmv_v_v_u8mf4(src, vl); return vmv_v_v_u8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf4( // CHECK-RV64-LABEL: @test_vmv_v_x_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmv_v_x_u8mf4(uint8_t src, size_t vl) { vuint8mf4_t test_vmv_v_x_u8mf4(uint8_t src, size_t vl) {
return vmv_v_x_u8mf4(src, vl); return vmv_v_x_u8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) { vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) {
return vmv_v_v_u8mf2(src, vl); return vmv_v_v_u8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmv_v_x_u8mf2(uint8_t src, size_t vl) { vuint8mf2_t test_vmv_v_x_u8mf2(uint8_t src, size_t vl) {
return vmv_v_x_u8mf2(src, vl); return vmv_v_x_u8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) { vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) {
return vmv_v_v_u8m1(src, vl); return vmv_v_v_u8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8m1( // CHECK-RV64-LABEL: @test_vmv_v_x_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmv_v_x_u8m1(uint8_t src, size_t vl) { vuint8m1_t test_vmv_v_x_u8m1(uint8_t src, size_t vl) {
return vmv_v_x_u8m1(src, vl); return vmv_v_x_u8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) { vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) {
return vmv_v_v_u8m2(src, vl); return vmv_v_v_u8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8m2( // CHECK-RV64-LABEL: @test_vmv_v_x_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmv_v_x_u8m2(uint8_t src, size_t vl) { vuint8m2_t test_vmv_v_x_u8m2(uint8_t src, size_t vl) {
return vmv_v_x_u8m2(src, vl); return vmv_v_x_u8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) { vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) {
return vmv_v_v_u8m4(src, vl); return vmv_v_v_u8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8m4( // CHECK-RV64-LABEL: @test_vmv_v_x_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmv_v_x_u8m4(uint8_t src, size_t vl) { vuint8m4_t test_vmv_v_x_u8m4(uint8_t src, size_t vl) {
return vmv_v_x_u8m4(src, vl); return vmv_v_x_u8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u8m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) { vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) {
return vmv_v_v_u8m8(src, vl); return vmv_v_v_u8m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u8m8( // CHECK-RV64-LABEL: @test_vmv_v_x_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(i8 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(<vscale x 64 x i8> undef, i8 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmv_v_x_u8m8(uint8_t src, size_t vl) { vuint8m8_t test_vmv_v_x_u8m8(uint8_t src, size_t vl) {
return vmv_v_x_u8m8(src, vl); return vmv_v_x_u8m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) { vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) {
return vmv_v_v_u16mf4(src, vl); return vmv_v_v_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16mf4( // CHECK-RV64-LABEL: @test_vmv_v_x_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(<vscale x 1 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmv_v_x_u16mf4(uint16_t src, size_t vl) { vuint16mf4_t test_vmv_v_x_u16mf4(uint16_t src, size_t vl) {
return vmv_v_x_u16mf4(src, vl); return vmv_v_x_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) { vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) {
return vmv_v_v_u16mf2(src, vl); return vmv_v_v_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(<vscale x 2 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmv_v_x_u16mf2(uint16_t src, size_t vl) { vuint16mf2_t test_vmv_v_x_u16mf2(uint16_t src, size_t vl) {
return vmv_v_x_u16mf2(src, vl); return vmv_v_x_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) { vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) {
return vmv_v_v_u16m1(src, vl); return vmv_v_v_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16m1( // CHECK-RV64-LABEL: @test_vmv_v_x_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(<vscale x 4 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmv_v_x_u16m1(uint16_t src, size_t vl) { vuint16m1_t test_vmv_v_x_u16m1(uint16_t src, size_t vl) {
return vmv_v_x_u16m1(src, vl); return vmv_v_x_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) { vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) {
return vmv_v_v_u16m2(src, vl); return vmv_v_v_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16m2( // CHECK-RV64-LABEL: @test_vmv_v_x_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(<vscale x 8 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmv_v_x_u16m2(uint16_t src, size_t vl) { vuint16m2_t test_vmv_v_x_u16m2(uint16_t src, size_t vl) {
return vmv_v_x_u16m2(src, vl); return vmv_v_x_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) { vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) {
return vmv_v_v_u16m4(src, vl); return vmv_v_v_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16m4( // CHECK-RV64-LABEL: @test_vmv_v_x_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(<vscale x 16 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmv_v_x_u16m4(uint16_t src, size_t vl) { vuint16m4_t test_vmv_v_x_u16m4(uint16_t src, size_t vl) {
return vmv_v_x_u16m4(src, vl); return vmv_v_x_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u16m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) { vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) {
return vmv_v_v_u16m8(src, vl); return vmv_v_v_u16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u16m8( // CHECK-RV64-LABEL: @test_vmv_v_x_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(i16 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(<vscale x 32 x i16> undef, i16 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmv_v_x_u16m8(uint16_t src, size_t vl) { vuint16m8_t test_vmv_v_x_u16m8(uint16_t src, size_t vl) {
return vmv_v_x_u16m8(src, vl); return vmv_v_x_u16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) { vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) {
return vmv_v_v_u32mf2(src, vl); return vmv_v_v_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2( // CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmv_v_x_u32mf2(uint32_t src, size_t vl) { vuint32mf2_t test_vmv_v_x_u32mf2(uint32_t src, size_t vl) {
return vmv_v_x_u32mf2(src, vl); return vmv_v_x_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) { vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) {
return vmv_v_v_u32m1(src, vl); return vmv_v_v_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u32m1( // CHECK-RV64-LABEL: @test_vmv_v_x_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(<vscale x 2 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmv_v_x_u32m1(uint32_t src, size_t vl) { vuint32m1_t test_vmv_v_x_u32m1(uint32_t src, size_t vl) {
return vmv_v_x_u32m1(src, vl); return vmv_v_x_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) { vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) {
return vmv_v_v_u32m2(src, vl); return vmv_v_v_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u32m2( // CHECK-RV64-LABEL: @test_vmv_v_x_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(<vscale x 4 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmv_v_x_u32m2(uint32_t src, size_t vl) { vuint32m2_t test_vmv_v_x_u32m2(uint32_t src, size_t vl) {
return vmv_v_x_u32m2(src, vl); return vmv_v_x_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) { vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) {
return vmv_v_v_u32m4(src, vl); return vmv_v_v_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u32m4( // CHECK-RV64-LABEL: @test_vmv_v_x_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(<vscale x 8 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmv_v_x_u32m4(uint32_t src, size_t vl) { vuint32m4_t test_vmv_v_x_u32m4(uint32_t src, size_t vl) {
return vmv_v_x_u32m4(src, vl); return vmv_v_x_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) { vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) {
return vmv_v_v_u32m8(src, vl); return vmv_v_v_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u32m8( // CHECK-RV64-LABEL: @test_vmv_v_x_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(i32 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(<vscale x 16 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmv_v_x_u32m8(uint32_t src, size_t vl) { vuint32m8_t test_vmv_v_x_u32m8(uint32_t src, size_t vl) {
return vmv_v_x_u32m8(src, vl); return vmv_v_x_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) { vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) {
return vmv_v_v_u64m1(src, vl); return vmv_v_v_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u64m1( // CHECK-RV64-LABEL: @test_vmv_v_x_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(<vscale x 1 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmv_v_x_u64m1(uint64_t src, size_t vl) { vuint64m1_t test_vmv_v_x_u64m1(uint64_t src, size_t vl) {
return vmv_v_x_u64m1(src, vl); return vmv_v_x_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) { vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) {
return vmv_v_v_u64m2(src, vl); return vmv_v_v_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u64m2( // CHECK-RV64-LABEL: @test_vmv_v_x_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(<vscale x 2 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmv_v_x_u64m2(uint64_t src, size_t vl) { vuint64m2_t test_vmv_v_x_u64m2(uint64_t src, size_t vl) {
return vmv_v_x_u64m2(src, vl); return vmv_v_x_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) { vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) {
return vmv_v_v_u64m4(src, vl); return vmv_v_v_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u64m4( // CHECK-RV64-LABEL: @test_vmv_v_x_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(<vscale x 4 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmv_v_x_u64m4(uint64_t src, size_t vl) { vuint64m4_t test_vmv_v_x_u64m4(uint64_t src, size_t vl) {
return vmv_v_x_u64m4(src, vl); return vmv_v_x_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_u64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) { vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) {
return vmv_v_v_u64m8(src, vl); return vmv_v_v_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_x_u64m8( // CHECK-RV64-LABEL: @test_vmv_v_x_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(i64 [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(<vscale x 8 x i64> undef, i64 [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmv_v_x_u64m8(uint64_t src, size_t vl) { vuint64m8_t test_vmv_v_x_u64m8(uint64_t src, size_t vl) {
return vmv_v_x_u64m8(src, vl); return vmv_v_x_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) { vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) {
return vmv_v_v_f32mf2(src, vl); return vmv_v_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m1( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) { vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) {
return vmv_v_v_f32m1(src, vl); return vmv_v_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m2( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) { vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) {
return vmv_v_v_f32m2(src, vl); return vmv_v_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m4( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) { vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) {
return vmv_v_v_f32m4(src, vl); return vmv_v_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f32m8( // CHECK-RV64-LABEL: @test_vmv_v_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) { vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) {
return vmv_v_v_f32m8(src, vl); return vmv_v_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m1( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) { vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) {
return vmv_v_v_f64m1(src, vl); return vmv_v_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m2( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) { vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) {
return vmv_v_v_f64m2(src, vl); return vmv_v_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m4( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) { vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) {
return vmv_v_v_f64m4(src, vl); return vmv_v_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f64m8( // CHECK-RV64-LABEL: @test_vmv_v_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) { vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) {
return vmv_v_v_f64m8(src, vl); return vmv_v_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8( // CHECK-RV64-LABEL: @test_vmv_x_s_i8mf8_i8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmv_s_x_u64m8(vuint64m8_t dst, uint64_t src, size_t vl) { vuint64m8_t test_vmv_s_x_u64m8(vuint64m8_t dst, uint64_t src, size_t vl) {
return vmv_s_x_u64m8(dst, src, vl); return vmv_s_x_u64m8(dst, src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16mf4( // CHECK-RV64-LABEL: @test_vmv_v_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vmv_v_v_f16mf4 (vfloat16mf4_t src, size_t vl) { vfloat16mf4_t test_vmv_v_v_f16mf4 (vfloat16mf4_t src, size_t vl) {
return vmv_v_v_f16mf4(src, vl); return vmv_v_v_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16mf2( // CHECK-RV64-LABEL: @test_vmv_v_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vmv_v_v_f16mf2 (vfloat16mf2_t src, size_t vl) { vfloat16mf2_t test_vmv_v_v_f16mf2 (vfloat16mf2_t src, size_t vl) {
return vmv_v_v_f16mf2(src, vl); return vmv_v_v_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16m1( // CHECK-RV64-LABEL: @test_vmv_v_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vmv_v_v_f16m1 (vfloat16m1_t src, size_t vl) { vfloat16m1_t test_vmv_v_v_f16m1 (vfloat16m1_t src, size_t vl) {
return vmv_v_v_f16m1(src, vl); return vmv_v_v_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16m2( // CHECK-RV64-LABEL: @test_vmv_v_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vmv_v_v_f16m2 (vfloat16m2_t src, size_t vl) { vfloat16m2_t test_vmv_v_v_f16m2 (vfloat16m2_t src, size_t vl) {
return vmv_v_v_f16m2(src, vl); return vmv_v_v_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16m4( // CHECK-RV64-LABEL: @test_vmv_v_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vmv_v_v_f16m4 (vfloat16m4_t src, size_t vl) { vfloat16m4_t test_vmv_v_v_f16m4 (vfloat16m4_t src, size_t vl) {
return vmv_v_v_f16m4(src, vl); return vmv_v_v_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vmv_v_v_f16m8( // CHECK-RV64-LABEL: @test_vmv_v_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vmv_v_v_f16m8 (vfloat16m8_t src, size_t vl) { vfloat16m8_t test_vmv_v_v_f16m8 (vfloat16m8_t src, size_t vl) {
return vmv_v_v_f16m8(src, vl); return vmv_v_v_f16m8(src, vl);
} }

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 1,260 Lines • ▼ Show 20 Lines
defm vsaddu : RISCVSaturatingBinaryAAX; defm vsaddu : RISCVSaturatingBinaryAAX;
defm vsadd : RISCVSaturatingBinaryAAX; defm vsadd : RISCVSaturatingBinaryAAX;
defm vssubu : RISCVSaturatingBinaryAAX; defm vssubu : RISCVSaturatingBinaryAAX;
defm vssub : RISCVSaturatingBinaryAAX; defm vssub : RISCVSaturatingBinaryAAX;
defm vmerge : RISCVBinaryWithV0; defm vmerge : RISCVBinaryWithV0;
// Output: (vector)
// Input: (passthru, vector_in, vl)
def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty], def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// Output: (vector)
// Input: (passthru, scalar, vl)
def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty], def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty],
[LLVMVectorElementType<0>, llvm_anyint_ty], [LLVMMatchType<0>, LLVMVectorElementType<0>,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// Output: (vector)
// Input: (passthru, scalar, vl)
def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty], def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty],
[LLVMVectorElementType<0>,llvm_anyint_ty], [LLVMMatchType<0>, LLVMVectorElementType<0>,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>], def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>],
[llvm_anyint_ty], [llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic; [IntrNoMem]>, RISCVVIntrinsic;
def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty], def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMVectorElementType<0>, [LLVMMatchType<0>, LLVMVectorElementType<0>,
llvm_anyint_ty], llvm_anyint_ty],
▲ Show 20 Lines • Show All 290 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
// Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point // Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point
// SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden. // SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden.
if (N->getOpcode() == ISD::SPLAT_VECTOR) { if (N->getOpcode() == ISD::SPLAT_VECTOR) {
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
unsigned Opc = unsigned Opc =
VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL; VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL;
SDLoc DL(N); SDLoc DL(N);
SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()); SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());
SDValue Result = CurDAG->getNode(Opc, DL, VT, N->getOperand(0), VL); SDValue Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT),
N->getOperand(0), VL);
--I; --I;
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
++I; ++I;
CurDAG->DeleteNode(N); CurDAG->DeleteNode(N);
continue; continue;
} }
// Lower SPLAT_VECTOR_SPLIT_I64 to two scalar stores and a stride 0 vector // Lower SPLAT_VECTOR_SPLIT_I64 to two scalar stores and a stride 0 vector
// load. Done after lowering and combining so that we have a chance to // load. Done after lowering and combining so that we have a chance to
// optimize this to VMV_V_X_VL when the upper bits aren't needed. // optimize this to VMV_V_X_VL when the upper bits aren't needed.
if (N->getOpcode() != RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) if (N->getOpcode() != RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL)
continue; continue;
assert(N->getNumOperands() == 3 && "Unexpected number of operands"); assert(N->getNumOperands() == 4 && "Unexpected number of operands");
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
SDValue Lo = N->getOperand(0); SDValue Passthru = N->getOperand(0);
SDValue Hi = N->getOperand(1); SDValue Lo = N->getOperand(1);
SDValue VL = N->getOperand(2); SDValue Hi = N->getOperand(2);
SDValue VL = N->getOperand(3);
assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() &&
Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 && Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 &&
"Unexpected VTs!"); "Unexpected VTs!");
MachineFunction &MF = CurDAG->getMachineFunction(); MachineFunction &MF = CurDAG->getMachineFunction();
RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>(); RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
SDLoc DL(N); SDLoc DL(N);
// We use the same frame index we use for moving two i32s into 64-bit FPR. // We use the same frame index we use for moving two i32s into 64-bit FPR.
Show All 14 Lines for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); SDVTList VTs = CurDAG->getVTList({VT, MVT::Other});
SDValue IntID = SDValue IntID =
CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64); CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64);
SDValue Ops[] = {Chain, SDValue Ops[] = {Chain,
IntID, IntID,
CurDAG->getUNDEF(VT), Passthru,
StackSlot, StackSlot,
CurDAG->getRegister(RISCV::X0, MVT::i64), CurDAG->getRegister(RISCV::X0, MVT::i64),
VL}; VL};
SDValue Result = CurDAG->getMemIntrinsicNode( SDValue Result = CurDAG->getMemIntrinsicNode(
ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64, MPI, Align(8), ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64, MPI, Align(8),
MachineMemOperand::MOLoad); MachineMemOperand::MOLoad);
▲ Show 20 Lines • Show All 1,501 Lines • ▼ Show 20 Lines#undef CASE_VMXOR_VMANDN_VMAND_OPCODES
case ISD::SPLAT_VECTOR: case ISD::SPLAT_VECTOR:
case RISCVISD::VMV_S_X_VL: case RISCVISD::VMV_S_X_VL:
case RISCVISD::VFMV_S_F_VL: case RISCVISD::VFMV_S_F_VL:
case RISCVISD::VMV_V_X_VL: case RISCVISD::VMV_V_X_VL:
case RISCVISD::VFMV_V_F_VL: { case RISCVISD::VFMV_V_F_VL: {
// Try to match splat of a scalar load to a strided load with stride of x0. // Try to match splat of a scalar load to a strided load with stride of x0.
bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL || bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
Node->getOpcode() == RISCVISD::VFMV_S_F_VL; Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
if (IsScalarMove && !Node->getOperand(0).isUndef()) bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
break; break;
SDValue Src = IsScalarMove ? Node->getOperand(1) : Node->getOperand(0); SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
auto *Ld = dyn_cast<LoadSDNode>(Src); auto *Ld = dyn_cast<LoadSDNode>(Src);
if (!Ld) if (!Ld)
break; break;
EVT MemVT = Ld->getMemoryVT(); EVT MemVT = Ld->getMemoryVT();
// The memory VT should be the same size as the element type. // The memory VT should be the same size as the element type.
if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize()) if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize())
break; break;
if (!IsProfitableToFold(Src, Node, Node) || if (!IsProfitableToFold(Src, Node, Node) ||
!IsLegalToFold(Src, Node, Node, TM.getOptLevel())) !IsLegalToFold(Src, Node, Node, TM.getOptLevel()))
break; break;
SDValue VL; SDValue VL;
if (Node->getOpcode() == ISD::SPLAT_VECTOR) if (Node->getOpcode() == ISD::SPLAT_VECTOR)
VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, DL, XLenVT); VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, DL, XLenVT);
else if (IsScalarMove) { else if (IsScalarMove) {
// We could deal with more VL if we update the VSETVLI insert pass to // We could deal with more VL if we update the VSETVLI insert pass to
// avoid introducing more VSETVLI. // avoid introducing more VSETVLI.
if (!isOneConstant(Node->getOperand(2))) if (!isOneConstant(Node->getOperand(2)))
break; break;
selectVLOp(Node->getOperand(2), VL); selectVLOp(Node->getOperand(2), VL);
} else } else
selectVLOp(Node->getOperand(1), VL); selectVLOp(Node->getOperand(2), VL);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT);
SDValue Operands[] = {Ld->getBasePtr(), SDValue Operands[] = {Ld->getBasePtr(),
CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW, CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW,
Ld->getChain()}; Ld->getChain()};
▲ Show 20 Lines • Show All 259 Lines • ▼ Show 20 Linesbool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
} else { } else {
VL = N; VL = N;
} }
return true; return true;
} }
bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) { bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
if (N.getOpcode() != RISCVISD::VMV_V_X_VL) if (N.getOpcode() != RISCVISD::VMV_V_X_VL || !N.getOperand(0).isUndef())
return false; return false;
SplatVal = N.getOperand(0); SplatVal = N.getOperand(1);
return true; return true;
} }
using ValidateFn = bool (*)(int64_t); using ValidateFn = bool (*)(int64_t);
static bool selectVSplatSimmHelper(SDValue N, SDValue &SplatVal, static bool selectVSplatSimmHelper(SDValue N, SDValue &SplatVal,
SelectionDAG &DAG, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget, const RISCVSubtarget &Subtarget,
ValidateFn ValidateImm) { ValidateFn ValidateImm) {
if (N.getOpcode() != RISCVISD::VMV_V_X_VL || if (N.getOpcode() != RISCVISD::VMV_V_X_VL || !N.getOperand(0).isUndef() ||
!isa<ConstantSDNode>(N.getOperand(0))) !isa<ConstantSDNode>(N.getOperand(1)))
return false; return false;
int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue(); int64_t SplatImm =
cast<ConstantSDNode>(N.getOperand(1))->getSExtValue();
// The semantics of RISCVISD::VMV_V_X_VL is that when the operand // The semantics of RISCVISD::VMV_V_X_VL is that when the operand
// type is wider than the resulting vector element type: an implicit // type is wider than the resulting vector element type: an implicit
// truncation first takes place. Therefore, perform a manual // truncation first takes place. Therefore, perform a manual
// truncation/sign-extension in order to ignore any truncated bits and catch // truncation/sign-extension in order to ignore any truncated bits and catch
// any zero-extended immediate. // any zero-extended immediate.
// For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first // For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first
// sign-extending to (XLenVT -1). // sign-extending to (XLenVT -1).
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
assert(XLenVT == N.getOperand(0).getSimpleValueType() && assert(XLenVT == N.getOperand(1).getSimpleValueType() &&
"Unexpected splat operand type"); "Unexpected splat operand type");
MVT EltVT = N.getSimpleValueType().getVectorElementType(); MVT EltVT = N.getSimpleValueType().getVectorElementType();
if (EltVT.bitsLT(XLenVT)) if (EltVT.bitsLT(XLenVT))
SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits()); SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());
if (!ValidateImm(SplatImm)) if (!ValidateImm(SplatImm))
return false; return false;
Show All 16 Linesbool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
SDValue &SplatVal) { SDValue &SplatVal) {
return selectVSplatSimmHelper( return selectVSplatSimmHelper(
N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) { N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) {
return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16); return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
}); });
} }
bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) { bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
if (N.getOpcode() != RISCVISD::VMV_V_X_VL || if (N.getOpcode() != RISCVISD::VMV_V_X_VL || !N.getOperand(0).isUndef() ||
!isa<ConstantSDNode>(N.getOperand(0))) !isa<ConstantSDNode>(N.getOperand(1)))
return false; return false;
int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue(); int64_t SplatImm =
cast<ConstantSDNode>(N.getOperand(1))->getSExtValue();
if (!isUInt<5>(SplatImm)) if (!isUInt<5>(SplatImm))
return false; return false;
SplatVal = SplatVal =
CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT()); CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT());
return true; return true;
▲ Show 20 Lines • Show All 281 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
// into the value in rs1. The upper bits of rs2 control the length of the bit // into the value in rs1. The upper bits of rs2 control the length of the bit
// field and target position. The layout of rs2 is chosen in a way that makes // field and target position. The layout of rs2 is chosen in a way that makes
// it possible to construct rs2 easily using pack[h] instructions and/or // it possible to construct rs2 easily using pack[h] instructions and/or
// andi/lui. // andi/lui.
BFP, BFP,
BFPW, BFPW,
// Vector Extension // Vector Extension
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
// for the VL value to be used for the operation. // for the VL value to be used for the operation. The first operand is
// passthru operand.
VMV_V_X_VL, VMV_V_X_VL,
// VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
// for the VL value to be used for the operation. // for the VL value to be used for the operation. The first operand is
// passthru operand.
VFMV_V_F_VL, VFMV_V_F_VL,
// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
// extended from the vector element size. // extended from the vector element size.
VMV_X_S, VMV_X_S,
// VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
VMV_S_X_VL, VMV_S_X_VL,
// VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
VFMV_S_F_VL, VFMV_S_F_VL,
// Splats an 64-bit value that has been split into two i32 parts. This is // Splats an 64-bit value that has been split into two i32 parts. This is
// expanded late to two scalar stores and a stride 0 vector load. // expanded late to two scalar stores and a stride 0 vector load.
// The first operand is passthru operand.
SPLAT_VECTOR_SPLIT_I64_VL, SPLAT_VECTOR_SPLIT_I64_VL,
// Read VLENB CSR // Read VLENB CSR
READ_VLENB, READ_VLENB,
// Truncates a RVV integer vector by one power-of-two. Carries both an extra // Truncates a RVV integer vector by one power-of-two. Carries both an extra
// mask and VL operand. // mask and VL operand.
TRUNCATE_VECTOR_VL, TRUNCATE_VECTOR_VL,
// Matches the semantics of vslideup/vslidedown. The first operand is the // Matches the semantics of vslideup/vslidedown. The first operand is the
// pass-thru operand, the second is the source vector, the third is the // pass-thru operand, the second is the source vector, the third is the
▲ Show 20 Lines • Show All 550 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,901 Lines • ▼ Show 20 Linesstatic SDValue lowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG,
MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
SDLoc DL(Op); SDLoc DL(Op);
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
unsigned Opc = unsigned Opc =
VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL; VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL;
SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, Op.getOperand(0), VL); SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
Op.getOperand(0), VL);
return convertFromScalableVector(VT, Splat, DAG, Subtarget); return convertFromScalableVector(VT, Splat, DAG, Subtarget);
} }
struct VIDSequence { struct VIDSequence {
int64_t StepNumerator; int64_t StepNumerator;
unsigned StepDenominator; unsigned StepDenominator;
int64_t Addend; int64_t Addend;
}; };
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines if (VT.getVectorElementType() == MVT::i1) {
return DAG.getSetCC(DL, VT, WideVec, VecZero, ISD::SETNE); return DAG.getSetCC(DL, VT, WideVec, VecZero, ISD::SETNE);
} }
if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) { if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
if (auto Gather = matchSplatAsGather(Splat, VT, DL, DAG, Subtarget)) if (auto Gather = matchSplatAsGather(Splat, VT, DL, DAG, Subtarget))
return Gather; return Gather;
unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL
: RISCVISD::VMV_V_X_VL; : RISCVISD::VMV_V_X_VL;
Splat = DAG.getNode(Opc, DL, ContainerVT, Splat, VL); Splat =
DAG.getNode(Opc, DL, ContainerVT, DAG.getUNDEF(ContainerVT), Splat, VL);
return convertFromScalableVector(VT, Splat, DAG, Subtarget); return convertFromScalableVector(VT, Splat, DAG, Subtarget);
} }
// Try and match index sequences, which we can lower to the vid instruction // Try and match index sequences, which we can lower to the vid instruction
// with optional modifications. An all-undef vector is matched by // with optional modifications. An all-undef vector is matched by
// getSplatValue, above. // getSplatValue, above.
if (auto SimpleVID = isSimpleVIDSequence(Op)) { if (auto SimpleVID = isSimpleVIDSequence(Op)) {
int64_t StepNumerator = SimpleVID->StepNumerator; int64_t StepNumerator = SimpleVID->StepNumerator;
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines assert((ViaIntVT.bitsLE(XLenVT) ||
"Unexpected bitcast sequence"); "Unexpected bitcast sequence");
if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) {
SDValue ViaVL = SDValue ViaVL =
DAG.getConstant(ViaVecVT.getVectorNumElements(), DL, XLenVT); DAG.getConstant(ViaVecVT.getVectorNumElements(), DL, XLenVT);
MVT ViaContainerVT = MVT ViaContainerVT =
getContainerForFixedLengthVector(DAG, ViaVecVT, Subtarget); getContainerForFixedLengthVector(DAG, ViaVecVT, Subtarget);
SDValue Splat = SDValue Splat =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ViaContainerVT, DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ViaContainerVT,
DAG.getUNDEF(ViaContainerVT),
DAG.getConstant(SplatValue, DL, XLenVT), ViaVL); DAG.getConstant(SplatValue, DL, XLenVT), ViaVL);
Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget); Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget);
return DAG.getBitcast(VT, Splat); return DAG.getBitcast(VT, Splat);
} }
} }
// Try and optimize BUILD_VECTORs with "dominant values" - these are values // Try and optimize BUILD_VECTORs with "dominant values" - these are values
// which constitute a large proportion of the elements. In such cases we can // which constitute a large proportion of the elements. In such cases we can
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines if (!DAG.shouldOptForSize() && NumScalarLoads < NumElts &&
} }
return Vec; return Vec;
} }
return SDValue(); return SDValue();
} }
static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo, static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
SDValue Hi, SDValue VL, SelectionDAG &DAG) { SDValue Lo, SDValue Hi, SDValue VL,
SelectionDAG &DAG) {
bool HasPassthru = Passthru && !Passthru.isUndef();
if (!HasPassthru && !Passthru)
Passthru = DAG.getUNDEF(VT);
if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) { if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue(); int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue(); int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
// If Hi constant is all the same sign bit as Lo, lower this as a custom // If Hi constant is all the same sign bit as Lo, lower this as a custom
// node in order to try and match RVV vector/scalar instructions. // node in order to try and match RVV vector/scalar instructions.
if ((LoC >> 31) == HiC) if ((LoC >> 31) == HiC)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL); return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Lo, VL);
// If vl is equal to XLEN_MAX and Hi constant is equal to Lo, we could use // If vl is equal to XLEN_MAX and Hi constant is equal to Lo, we could use
// vmv.v.x whose EEW = 32 to lower it. // vmv.v.x whose EEW = 32 to lower it.
auto *Const = dyn_cast<ConstantSDNode>(VL); auto *Const = dyn_cast<ConstantSDNode>(VL);
if (LoC == HiC && Const && Const->isAllOnesValue()) { if (LoC == HiC && Const && Const->isAllOnesValue()) {
MVT InterVT = MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2); MVT InterVT = MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2);
// TODO: if vl <= min(VLMAX), we can also do this. But we could not // TODO: if vl <= min(VLMAX), we can also do this. But we could not
// access the subtarget here now. // access the subtarget here now.
auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT, Lo, auto InterVec = DAG.getNode(
RISCVISD::VMV_V_X_VL, DL, InterVT, DAG.getUNDEF(InterVT), Lo,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
return DAG.getNode(ISD::BITCAST, DL, VT, InterVec); return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
} }
} }
// Fall back to a stack store and stride x0 vector load. // Fall back to a stack store and stride x0 vector load.
return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Lo, Hi, VL); return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Passthru, Lo,
Hi, VL);
} }
// Called by type legalization to handle splat of i64 on RV32. // Called by type legalization to handle splat of i64 on RV32.
// FIXME: We can optimize this when the type has sign or zero bits in one // FIXME: We can optimize this when the type has sign or zero bits in one
// of the halves. // of the halves.
static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
SDValue VL, SelectionDAG &DAG) { SDValue Scalar, SDValue VL,
SelectionDAG &DAG) {
assert(Scalar.getValueType() == MVT::i64 && "Unexpected VT!"); assert(Scalar.getValueType() == MVT::i64 && "Unexpected VT!");
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, DL, MVT::i32));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, DL, MVT::i32));
return splatPartsI64WithVL(DL, VT, Lo, Hi, VL, DAG); return splatPartsI64WithVL(DL, VT, Passthru, Lo, Hi, VL, DAG);
} }
// This function lowers a splat of a scalar operand Splat with the vector // This function lowers a splat of a scalar operand Splat with the vector
// length VL. It ensures the final sequence is type legal, which is useful when // length VL. It ensures the final sequence is type legal, which is useful when
// lowering a splat after type legalization. // lowering a splat after type legalization.
static SDValue lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,
SelectionDAG &DAG, MVT VT, SDLoc DL, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) { const RISCVSubtarget &Subtarget) {
bool HasPassthru = Passthru && !Passthru.isUndef();
if (!HasPassthru && !Passthru)
Passthru = DAG.getUNDEF(VT);
if (VT.isFloatingPoint()) { if (VT.isFloatingPoint()) {
// If VL is 1, we could use vfmv.s.f. // If VL is 1, we could use vfmv.s.f.
if (isOneConstant(VL)) if (isOneConstant(VL))
return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, VT, DAG.getUNDEF(VT), return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, VT, Passthru, Scalar, VL);
Scalar, VL); return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, VT, Passthru, Scalar, VL);
return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, VT, Scalar, VL);
} }
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
// Simplest case is that the operand needs to be promoted to XLenVT. // Simplest case is that the operand needs to be promoted to XLenVT.
if (Scalar.getValueType().bitsLE(XLenVT)) { if (Scalar.getValueType().bitsLE(XLenVT)) {
// If the operand is a constant, sign extend to increase our chances // If the operand is a constant, sign extend to increase our chances
// of being able to use a .vi instruction. ANY_EXTEND would become a // of being able to use a .vi instruction. ANY_EXTEND would become a
// a zero extend and the simm5 check in isel would fail. // a zero extend and the simm5 check in isel would fail.
// FIXME: Should we ignore the upper bits in isel instead? // FIXME: Should we ignore the upper bits in isel instead?
unsigned ExtOpc = unsigned ExtOpc =
isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar); ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
// If VL is 1 and the scalar value won't benefit from immediate, we could // If VL is 1 and the scalar value won't benefit from immediate, we could
// use vmv.s.x. // use vmv.s.x.
if (isOneConstant(VL) && if (isOneConstant(VL) &&
(!Const || isNullConstant(Scalar) || !isInt<5>(Const->getSExtValue()))) (!Const || isNullConstant(Scalar) || !isInt<5>(Const->getSExtValue())))
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT), Scalar, return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
VL); return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar, VL);
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Scalar, VL);
} }
assert(XLenVT == MVT::i32 && Scalar.getValueType() == MVT::i64 && assert(XLenVT == MVT::i32 && Scalar.getValueType() == MVT::i64 &&
"Unexpected scalar for splat lowering!"); "Unexpected scalar for splat lowering!");
if (isOneConstant(VL) && isNullConstant(Scalar)) if (isOneConstant(VL) && isNullConstant(Scalar))
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT), return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru,
DAG.getConstant(0, DL, XLenVT), VL); DAG.getConstant(0, DL, XLenVT), VL);
// Otherwise use the more complicated splatting algorithm. // Otherwise use the more complicated splatting algorithm.
return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); return splatSplitI64WithVL(DL, VT, Passthru, Scalar, VL, DAG);
} }
// Is the mask a slidedown that shifts in undefs. // Is the mask a slidedown that shifts in undefs.
static int matchShuffleAsSlideDown(ArrayRef<int> Mask) { static int matchShuffleAsSlideDown(ArrayRef<int> Mask) {
int Size = Mask.size(); int Size = Mask.size();
// Elements shifted in should be undef. // Elements shifted in should be undef.
auto CheckUndefs = [&](int Shift) { auto CheckUndefs = [&](int Shift) {
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines if (Lane >= 0) {
V = DAG.getExtLoad(ISD::SEXTLOAD, DL, XLenVT, Ld->getChain(), NewAddr, V = DAG.getExtLoad(ISD::SEXTLOAD, DL, XLenVT, Ld->getChain(), NewAddr,
Ld->getPointerInfo().getWithOffset(Offset), SVT, Ld->getPointerInfo().getWithOffset(Offset), SVT,
Ld->getOriginalAlign(), Ld->getOriginalAlign(),
Ld->getMemOperand()->getFlags()); Ld->getMemOperand()->getFlags());
DAG.makeEquivalentMemoryOrdering(Ld, V); DAG.makeEquivalentMemoryOrdering(Ld, V);
unsigned Opc = unsigned Opc =
VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL; VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL;
SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, V, VL); SDValue Splat =
DAG.getNode(Opc, DL, ContainerVT, DAG.getUNDEF(ContainerVT), V, VL);
return convertFromScalableVector(VT, Splat, DAG, Subtarget); return convertFromScalableVector(VT, Splat, DAG, Subtarget);
} }
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
assert(Lane < (int)NumElts && "Unexpected lane!"); assert(Lane < (int)NumElts && "Unexpected lane!");
SDValue Gather = SDValue Gather =
DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, V1, DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, V1,
DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL); DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL);
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines MVT MaskVT =
MVT::getVectorVT(MVT::i1, HalfContainerVT.getVectorElementCount()); MVT::getVectorVT(MVT::i1, HalfContainerVT.getVectorElementCount());
TrueMask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); TrueMask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
// Widen V1 and V2 with 0s and add one copy of V2 to V1. // Widen V1 and V2 with 0s and add one copy of V2 to V1.
SDValue Add = DAG.getNode(RISCVISD::VWADDU_VL, DL, WideIntContainerVT, V1, SDValue Add = DAG.getNode(RISCVISD::VWADDU_VL, DL, WideIntContainerVT, V1,
V2, TrueMask, VL); V2, TrueMask, VL);
// Create 2^eltbits - 1 copies of V2 by multiplying by the largest integer. // Create 2^eltbits - 1 copies of V2 by multiplying by the largest integer.
SDValue Multiplier = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntHalfVT, SDValue Multiplier = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntHalfVT,
DAG.getUNDEF(IntHalfVT),
DAG.getAllOnesConstant(DL, XLenVT)); DAG.getAllOnesConstant(DL, XLenVT));
SDValue WidenMul = DAG.getNode(RISCVISD::VWMULU_VL, DL, WideIntContainerVT, SDValue WidenMul = DAG.getNode(RISCVISD::VWMULU_VL, DL, WideIntContainerVT,
V2, Multiplier, TrueMask, VL); V2, Multiplier, TrueMask, VL);
// Add the new copies to our previous addition giving us 2^eltbits copies of // Add the new copies to our previous addition giving us 2^eltbits copies of
// V2. This is equivalent to shifting V2 left by eltbits. This should // V2. This is equivalent to shifting V2 left by eltbits. This should
// combine with the vwmulu.vv above to form vwmaccu.vv. // combine with the vwmulu.vv above to form vwmaccu.vv.
Add = DAG.getNode(RISCVISD::ADD_VL, DL, WideIntContainerVT, Add, WidenMul, Add = DAG.getNode(RISCVISD::ADD_VL, DL, WideIntContainerVT, Add, WidenMul,
TrueMask, VL); TrueMask, VL);
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesstatic SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
MVT IndexContainerVT = MVT IndexContainerVT =
ContainerVT.changeVectorElementType(IndexVT.getScalarType()); ContainerVT.changeVectorElementType(IndexVT.getScalarType());
SDValue Gather; SDValue Gather;
// TODO: This doesn't trigger for i64 vectors on RV32, since there we // TODO: This doesn't trigger for i64 vectors on RV32, since there we
// encounter a bitcasted BUILD_VECTOR with low/high i32 values. // encounter a bitcasted BUILD_VECTOR with low/high i32 values.
if (SDValue SplatValue = DAG.getSplatValue(V1, /*LegalTypes*/ true)) { if (SDValue SplatValue = DAG.getSplatValue(V1, /*LegalTypes*/ true)) {
Gather = lowerScalarSplat(SplatValue, VL, ContainerVT, DL, DAG, Subtarget); Gather = lowerScalarSplat(SDValue(), SplatValue, VL, ContainerVT, DL, DAG,
Subtarget);
} else { } else {
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
// If only one index is used, we can use a "splat" vrgather. // If only one index is used, we can use a "splat" vrgather.
// TODO: We can splat the most-common index and fix-up any stragglers, if // TODO: We can splat the most-common index and fix-up any stragglers, if
// that's beneficial. // that's beneficial.
if (LHSIndexCounts.size() == 1) { if (LHSIndexCounts.size() == 1) {
int SplatIndex = LHSIndexCounts.begin()->getFirst(); int SplatIndex = LHSIndexCounts.begin()->getFirst();
Gather = Gather =
▲ Show 20 Lines • Show All 1,355 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
if (VecVT.isFixedLengthVector()) { if (VecVT.isFixedLengthVector()) {
MVT ContainerVT = getContainerForFixedLengthVector(VecVT); MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
SDLoc DL(Op); SDLoc DL(Op);
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = std::tie(Mask, VL) =
getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SDValue Res = splatPartsI64WithVL(DL, ContainerVT, Lo, Hi, VL, DAG); SDValue Res =
splatPartsI64WithVL(DL, ContainerVT, SDValue(), Lo, Hi, VL, DAG);
return convertFromScalableVector(VecVT, Res, DAG, Subtarget); return convertFromScalableVector(VecVT, Res, DAG, Subtarget);
} }
if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) { if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue(); int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue(); int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
// If Hi constant is all the same sign bit as Lo, lower this as a custom // If Hi constant is all the same sign bit as Lo, lower this as a custom
// node in order to try and match RVV vector/scalar instructions. // node in order to try and match RVV vector/scalar instructions.
if ((LoC >> 31) == HiC) if ((LoC >> 31) == HiC)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, Lo, return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
DAG.getRegister(RISCV::X0, MVT::i32)); Lo, DAG.getRegister(RISCV::X0, MVT::i32));
} }
// Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended. // Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo && if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
isa<ConstantSDNode>(Hi.getOperand(1)) && isa<ConstantSDNode>(Hi.getOperand(1)) &&
Hi.getConstantOperandVal(1) == 31) Hi.getConstantOperandVal(1) == 31)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, Lo, return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
// Fall back to use a stack store and stride x0 vector load. Use X0 as VL. // Fall back to use a stack store and stride x0 vector load. Use X0 as VL.
return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT, Lo, Hi, return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT,
DAG.getUNDEF(VecVT), Lo, Hi,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
} }
// Custom-lower extensions from mask vectors by using a vselect either with 1 // Custom-lower extensions from mask vectors by using a vselect either with 1
// for zero/any-extension or -1 for sign-extension: // for zero/any-extension or -1 for sign-extension:
// (vXiN = (s|z)ext vXi1:vmask) -> (vXiN = vselect vmask, (-1 or 1), 0) // (vXiN = (s|z)ext vXi1:vmask) -> (vXiN = vselect vmask, (-1 or 1), 0)
// Note that any-extension is lowered identically to zero-extension. // Note that any-extension is lowered identically to zero-extension.
SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
Show All 16 Lines if (VecVT.isScalableVector()) {
// sign-extended 32-bit values, we use VMV_V_X_VL directly. // sign-extended 32-bit values, we use VMV_V_X_VL directly.
bool IsRV32E64 = bool IsRV32E64 =
!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64;
if (!IsRV32E64) { if (!IsRV32E64) {
SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero); SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero);
SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal); SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal);
} else { } else {
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, SplatZero, SplatZero =
DAG.getRegister(RISCV::X0, XLenVT)); DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
SplatTrueVal = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, SplatTrueVal, SplatZero, DAG.getRegister(RISCV::X0, XLenVT));
DAG.getRegister(RISCV::X0, XLenVT)); SplatTrueVal =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
SplatTrueVal, DAG.getRegister(RISCV::X0, XLenVT));
} }
return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero);
} }
MVT ContainerVT = getContainerForFixedLengthVector(VecVT); MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
MVT I1ContainerVT = MVT I1ContainerVT =
MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount()); MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
SDValue CC = convertToScalableVector(I1ContainerVT, Src, DAG, Subtarget); SDValue CC = convertToScalableVector(I1ContainerVT, Src, DAG, Subtarget);
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, SplatZero, VL); SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
SplatTrueVal = DAG.getUNDEF(ContainerVT), SplatZero, VL);
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, SplatTrueVal, VL); SplatTrueVal = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatTrueVal, VL);
SDValue Select = DAG.getNode(RISCVISD::VSELECT_VL, DL, ContainerVT, CC, SDValue Select = DAG.getNode(RISCVISD::VSELECT_VL, DL, ContainerVT, CC,
SplatTrueVal, SplatZero, VL); SplatTrueVal, SplatZero, VL);
return convertFromScalableVector(VecVT, Select, DAG, Subtarget); return convertFromScalableVector(VecVT, Select, DAG, Subtarget);
} }
SDValue RISCVTargetLowering::lowerFixedLengthVectorExtendToRVV( SDValue RISCVTargetLowering::lowerFixedLengthVectorExtendToRVV(
SDValue Op, SelectionDAG &DAG, unsigned ExtendOpc) const { SDValue Op, SelectionDAG &DAG, unsigned ExtendOpc) const {
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
if (VecVT.isFixedLengthVector()) { if (VecVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VecVT); ContainerVT = getContainerForFixedLengthVector(VecVT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget); Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
} }
SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT()); SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT());
SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
SplatOne = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, SplatOne); SplatOne = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, SplatZero); DAG.getUNDEF(ContainerVT), SplatOne);
SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatZero);
if (VecVT.isScalableVector()) { if (VecVT.isScalableVector()) {
SDValue Trunc = DAG.getNode(ISD::AND, DL, VecVT, Src, SplatOne); SDValue Trunc = DAG.getNode(ISD::AND, DL, VecVT, Src, SplatOne);
return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE); return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE);
} }
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines if (IsLegalInsert) {
MVT I32ContainerVT = MVT I32ContainerVT =
MVT::getVectorVT(MVT::i32, ContainerVT.getVectorElementCount() * 2); MVT::getVectorVT(MVT::i32, ContainerVT.getVectorElementCount() * 2);
SDValue I32Mask = SDValue I32Mask =
getDefaultScalableVLOps(I32ContainerVT, DL, DAG, Subtarget).first; getDefaultScalableVLOps(I32ContainerVT, DL, DAG, Subtarget).first;
// Limit the active VL to two. // Limit the active VL to two.
SDValue InsertI64VL = DAG.getConstant(2, DL, XLenVT); SDValue InsertI64VL = DAG.getConstant(2, DL, XLenVT);
// Note: We can't pass a UNDEF to the first VSLIDE1UP_VL since an untied // Note: We can't pass a UNDEF to the first VSLIDE1UP_VL since an untied
// undef doesn't obey the earlyclobber constraint. Just splat a zero value. // undef doesn't obey the earlyclobber constraint. Just splat a zero value.
ValInVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, I32ContainerVT, Zero, ValInVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, I32ContainerVT,
InsertI64VL); DAG.getUNDEF(I32ContainerVT), Zero, InsertI64VL);
// First slide in the hi value, then the lo in underneath it. // First slide in the hi value, then the lo in underneath it.
ValInVec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32ContainerVT, ValInVec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32ContainerVT,
DAG.getUNDEF(I32ContainerVT), ValInVec, ValHi, DAG.getUNDEF(I32ContainerVT), ValInVec, ValHi,
I32Mask, InsertI64VL); I32Mask, InsertI64VL);
ValInVec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32ContainerVT, ValInVec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32ContainerVT,
DAG.getUNDEF(I32ContainerVT), ValInVec, ValLo, DAG.getUNDEF(I32ContainerVT), ValInVec, ValLo,
I32Mask, InsertI64VL); I32Mask, InsertI64VL);
// Bitcast back to the right container type. // Bitcast back to the right container type.
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines if (auto *CVal = dyn_cast<ConstantSDNode>(ScalarOp)) {
} }
} }
// We need to convert the scalar to a splat vector. // We need to convert the scalar to a splat vector.
// FIXME: Can we implicitly truncate the scalar if it is known to // FIXME: Can we implicitly truncate the scalar if it is known to
// be sign extended? // be sign extended?
SDValue VL = getVLOperand(Op); SDValue VL = getVLOperand(Op);
assert(VL.getValueType() == XLenVT); assert(VL.getValueType() == XLenVT);
ScalarOp = splatSplitI64WithVL(DL, VT, ScalarOp, VL, DAG); ScalarOp = splatSplitI64WithVL(DL, VT, SDValue(), ScalarOp, VL, DAG);
return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands); return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands);
} }
SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
unsigned IntNo = Op.getConstantOperandVal(0); unsigned IntNo = Op.getConstantOperandVal(0);
SDLoc DL(Op); SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines case Intrinsic::riscv_fsr:
return DAG.getNode(RISCVISD::FSR, DL, XLenVT, Op.getOperand(1), return DAG.getNode(RISCVISD::FSR, DL, XLenVT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3)); Op.getOperand(2), Op.getOperand(3));
case Intrinsic::riscv_vmv_x_s: case Intrinsic::riscv_vmv_x_s:
assert(Op.getValueType() == XLenVT && "Unexpected VT!"); assert(Op.getValueType() == XLenVT && "Unexpected VT!");
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
Op.getOperand(1)); Op.getOperand(1));
case Intrinsic::riscv_vmv_v_x: case Intrinsic::riscv_vmv_v_x:
return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2), return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),
Op.getSimpleValueType(), DL, DAG, Subtarget); Op.getOperand(3), Op.getSimpleValueType(), DL, DAG,
Subtarget);
case Intrinsic::riscv_vfmv_v_f: case Intrinsic::riscv_vfmv_v_f:
return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, Op.getValueType(), return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, Op.getValueType(),
Op.getOperand(1), Op.getOperand(2)); Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
case Intrinsic::riscv_vmv_s_x: { case Intrinsic::riscv_vmv_s_x: {
SDValue Scalar = Op.getOperand(2); SDValue Scalar = Op.getOperand(2);
if (Scalar.getValueType().bitsLE(XLenVT)) { if (Scalar.getValueType().bitsLE(XLenVT)) {
Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Scalar); Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Scalar);
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, Op.getValueType(), return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, Op.getValueType(),
Op.getOperand(1), Scalar, Op.getOperand(3)); Op.getOperand(1), Scalar, Op.getOperand(3));
} }
Show All 14 Lines case Intrinsic::riscv_vmv_s_x: {
// //
// vid.v vVid // vid.v vVid
// vmseq.vx mMask, vVid, 0 // vmseq.vx mMask, vVid, 0
// vmerge.vvm vDest, vSrc, vVal, mMask // vmerge.vvm vDest, vSrc, vVal, mMask
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
SDValue Vec = Op.getOperand(1); SDValue Vec = Op.getOperand(1);
SDValue VL = getVLOperand(Op); SDValue VL = getVLOperand(Op);
SDValue SplattedVal = splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); SDValue SplattedVal = splatSplitI64WithVL(DL, VT, SDValue(), Scalar, VL, DAG);
SDValue SplattedIdx = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, SDValue SplattedIdx =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
DAG.getConstant(0, DL, MVT::i32), VL); DAG.getConstant(0, DL, MVT::i32), VL);
MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL); SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL);
SDValue SelectCond = SDValue SelectCond =
DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, VID, SplattedIdx, DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, VID, SplattedIdx,
DAG.getCondCode(ISD::SETEQ), Mask, VL); DAG.getCondCode(ISD::SETEQ), Mask, VL);
return DAG.getNode(RISCVISD::VSELECT_VL, DL, VT, SelectCond, SplattedVal, return DAG.getNode(RISCVISD::VSELECT_VL, DL, VT, SelectCond, SplattedVal,
▲ Show 20 Lines • Show All 358 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
MVT M1VT = getLMUL1VT(ContainerVT); MVT M1VT = getLMUL1VT(ContainerVT);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SDValue NeutralElem = SDValue NeutralElem =
DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags());
SDValue IdentitySplat = lowerScalarSplat( SDValue IdentitySplat =
NeutralElem, DAG.getConstant(1, DL, XLenVT), M1VT, DL, DAG, Subtarget); lowerScalarSplat(SDValue(), NeutralElem, DAG.getConstant(1, DL, XLenVT),
M1VT, DL, DAG, Subtarget);
SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), Vec, SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), Vec,
IdentitySplat, Mask, VL); IdentitySplat, Mask, VL);
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction, SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction,
DAG.getConstant(0, DL, XLenVT)); DAG.getConstant(0, DL, XLenVT));
return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType()); return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());
} }
// Given a reduction op, this function returns the matching reduction opcode, // Given a reduction op, this function returns the matching reduction opcode,
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerFPVECREDUCE(SDValue Op,
} }
MVT M1VT = getLMUL1VT(VectorVal.getSimpleValueType()); MVT M1VT = getLMUL1VT(VectorVal.getSimpleValueType());
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SDValue ScalarSplat = lowerScalarSplat( SDValue ScalarSplat =
ScalarVal, DAG.getConstant(1, DL, XLenVT), M1VT, DL, DAG, Subtarget); lowerScalarSplat(SDValue(), ScalarVal, DAG.getConstant(1, DL, XLenVT),
M1VT, DL, DAG, Subtarget);
SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT),
VectorVal, ScalarSplat, Mask, VL); VectorVal, ScalarSplat, Mask, VL);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction, return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction,
DAG.getConstant(0, DL, XLenVT)); DAG.getConstant(0, DL, XLenVT));
} }
static unsigned getRVVVPReductionOp(unsigned ISDOpcode) { static unsigned getRVVVPReductionOp(unsigned ISDOpcode) {
switch (ISDOpcode) { switch (ISDOpcode) {
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerVPREDUCE(SDValue Op,
SDValue VL = Op.getOperand(3); SDValue VL = Op.getOperand(3);
SDValue Mask = Op.getOperand(2); SDValue Mask = Op.getOperand(2);
MVT M1VT = getLMUL1VT(ContainerVT); MVT M1VT = getLMUL1VT(ContainerVT);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
MVT ResVT = !VecVT.isInteger() || VecEltVT.bitsGE(XLenVT) ? VecEltVT : XLenVT; MVT ResVT = !VecVT.isInteger() || VecEltVT.bitsGE(XLenVT) ? VecEltVT : XLenVT;
SDValue StartSplat = SDValue StartSplat = lowerScalarSplat(SDValue(), Op.getOperand(0),
lowerScalarSplat(Op.getOperand(0), DAG.getConstant(1, DL, XLenVT), M1VT, DAG.getConstant(1, DL, XLenVT), M1VT,
DL, DAG, Subtarget); DL, DAG, Subtarget);
SDValue Reduction = SDValue Reduction =
DAG.getNode(RVVOpcode, DL, M1VT, StartSplat, Vec, StartSplat, Mask, VL); DAG.getNode(RVVOpcode, DL, M1VT, StartSplat, Vec, StartSplat, Mask, VL);
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Reduction, SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Reduction,
DAG.getConstant(0, DL, XLenVT)); DAG.getConstant(0, DL, XLenVT));
if (!VecVT.isInteger()) if (!VecVT.isInteger())
return Elt0; return Elt0;
return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType()); return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());
} }
▲ Show 20 Lines • Show All 285 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
SDValue StepVec = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL); SDValue StepVec = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL);
uint64_t StepValImm = Op.getConstantOperandVal(0); uint64_t StepValImm = Op.getConstantOperandVal(0);
if (StepValImm != 1) { if (StepValImm != 1) {
if (isPowerOf2_64(StepValImm)) { if (isPowerOf2_64(StepValImm)) {
SDValue StepVal = SDValue StepVal =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
DAG.getConstant(Log2_64(StepValImm), DL, XLenVT)); DAG.getConstant(Log2_64(StepValImm), DL, XLenVT));
StepVec = DAG.getNode(ISD::SHL, DL, VT, StepVec, StepVal); StepVec = DAG.getNode(ISD::SHL, DL, VT, StepVec, StepVal);
} else { } else {
SDValue StepVal = lowerScalarSplat( SDValue StepVal = lowerScalarSplat(
DAG.getConstant(StepValImm, DL, VT.getVectorElementType()), VL, VT, SDValue(), DAG.getConstant(StepValImm, DL, VT.getVectorElementType()),
DL, DAG, Subtarget); VL, VT, DL, DAG, Subtarget);
StepVec = DAG.getNode(ISD::MUL, DL, VT, StepVec, StepVal); StepVec = DAG.getNode(ISD::MUL, DL, VT, StepVec, StepVal);
} }
} }
return StepVec; return StepVec;
} }
// Implement vector_reverse using vrgather.vv with indices determined by // Implement vector_reverse using vrgather.vv with indices determined by
// subtracting the id of each element from (VLMAX-1). This will convert // subtracting the id of each element from (VLMAX-1). This will convert
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
// Splat VLMAX-1 taking care to handle SEW==64 on RV32. // Splat VLMAX-1 taking care to handle SEW==64 on RV32.
bool IsRV32E64 = bool IsRV32E64 =
!Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64; !Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64;
SDValue SplatVL; SDValue SplatVL;
if (!IsRV32E64) if (!IsRV32E64)
SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1); SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1);
else else
SplatVL = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT, VLMinus1, SplatVL = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT, DAG.getUNDEF(IntVT),
DAG.getRegister(RISCV::X0, XLenVT)); VLMinus1, DAG.getRegister(RISCV::X0, XLenVT));
SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL); SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL);
SDValue Indices = SDValue Indices =
DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL); DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL);
return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices, Mask, VL); return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices, Mask, VL);
} }
▲ Show 20 Lines • Show All 237 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerABS(SDValue Op, SelectionDAG &DAG) const {
assert(VT.isFixedLengthVector() && "Unexpected type"); assert(VT.isFixedLengthVector() && "Unexpected type");
MVT ContainerVT = getContainerForFixedLengthVector(VT); MVT ContainerVT = getContainerForFixedLengthVector(VT);
X = convertToScalableVector(ContainerVT, X, DAG, Subtarget); X = convertToScalableVector(ContainerVT, X, DAG, Subtarget);
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
SDValue SplatZero = SDValue SplatZero = DAG.getNode(
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
DAG.getConstant(0, DL, Subtarget.getXLenVT())); DAG.getConstant(0, DL, Subtarget.getXLenVT()));
SDValue NegX = SDValue NegX =
DAG.getNode(RISCVISD::SUB_VL, DL, ContainerVT, SplatZero, X, Mask, VL); DAG.getNode(RISCVISD::SUB_VL, DL, ContainerVT, SplatZero, X, Mask, VL);
SDValue Max = SDValue Max =
DAG.getNode(RISCVISD::SMAX_VL, DL, ContainerVT, X, NegX, Mask, VL); DAG.getNode(RISCVISD::SMAX_VL, DL, ContainerVT, X, NegX, Mask, VL);
return convertFromScalableVector(VT, Max, DAG, Subtarget); return convertFromScalableVector(VT, Max, DAG, Subtarget);
} }
▲ Show 20 Lines • Show All 895 Lines • ▼ Show 20 Lines case ISD::EXTRACT_VECTOR_ELT: {
} }
// Extract the lower XLEN bits of the correct vector element. // Extract the lower XLEN bits of the correct vector element.
SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec);
// To extract the upper XLEN bits of the vector element, shift the first // To extract the upper XLEN bits of the vector element, shift the first
// element right by 32 bits and re-extract the lower XLEN bits. // element right by 32 bits and re-extract the lower XLEN bits.
SDValue ThirtyTwoV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, SDValue ThirtyTwoV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT),
DAG.getConstant(32, DL, XLenVT), VL); DAG.getConstant(32, DL, XLenVT), VL);
SDValue LShr32 = DAG.getNode(RISCVISD::SRL_VL, DL, ContainerVT, Vec, SDValue LShr32 = DAG.getNode(RISCVISD::SRL_VL, DL, ContainerVT, Vec,
ThirtyTwoV, Mask, VL); ThirtyTwoV, Mask, VL);
SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32); SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32);
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi));
break; break;
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines case Intrinsic::riscv_vmv_x_s: {
// First extract the lower XLEN bits of the element. // First extract the lower XLEN bits of the element.
SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec);
// To extract the upper XLEN bits of the vector element, shift the first // To extract the upper XLEN bits of the vector element, shift the first
// element right by 32 bits and re-extract the lower XLEN bits. // element right by 32 bits and re-extract the lower XLEN bits.
SDValue VL = DAG.getConstant(1, DL, XLenVT); SDValue VL = DAG.getConstant(1, DL, XLenVT);
MVT MaskVT = MVT::getVectorVT(MVT::i1, VecVT.getVectorElementCount()); MVT MaskVT = MVT::getVectorVT(MVT::i1, VecVT.getVectorElementCount());
SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
SDValue ThirtyTwoV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, SDValue ThirtyTwoV =
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
DAG.getConstant(32, DL, XLenVT), VL); DAG.getConstant(32, DL, XLenVT), VL);
SDValue LShr32 = SDValue LShr32 =
DAG.getNode(RISCVISD::SRL_VL, DL, VecVT, Vec, ThirtyTwoV, Mask, VL); DAG.getNode(RISCVISD::SRL_VL, DL, VecVT, Vec, ThirtyTwoV, Mask, VL);
SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32); SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32);
Results.push_back( Results.push_back(
DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi));
break; break;
} }
▲ Show 20 Lines • Show All 791 Lines • ▼ Show 20 Linesstatic SDValue combineVWADD_W_VL_VWSUB_W_VL(SDNode *N, SelectionDAG &DAG) {
} }
bool IsAdd = N->getOpcode() == RISCVISD::VWADD_W_VL || bool IsAdd = N->getOpcode() == RISCVISD::VWADD_W_VL ||
N->getOpcode() == RISCVISD::VWADDU_W_VL; N->getOpcode() == RISCVISD::VWADDU_W_VL;
// Look for splats on the left hand side of a vwadd(u).wv. We might be able // Look for splats on the left hand side of a vwadd(u).wv. We might be able
// to commute and use a vwadd(u).vx instead. // to commute and use a vwadd(u).vx instead.
if (IsAdd && Op0.getOpcode() == RISCVISD::VMV_V_X_VL && if (IsAdd && Op0.getOpcode() == RISCVISD::VMV_V_X_VL &&
Op0.getOperand(1) == VL) { Op0.getOperand(0).isUndef() && Op0.getOperand(2) == VL) {
Op0 = Op0.getOperand(0); Op0 = Op0.getOperand(1);
// See if have enough sign bits or zero bits in the scalar to use a // See if have enough sign bits or zero bits in the scalar to use a
// widening add/sub by splatting to smaller element size. // widening add/sub by splatting to smaller element size.
unsigned EltBits = VT.getScalarSizeInBits(); unsigned EltBits = VT.getScalarSizeInBits();
unsigned ScalarBits = Op0.getValueSizeInBits(); unsigned ScalarBits = Op0.getValueSizeInBits();
// Make sure we're getting all element bits from the scalar register. // Make sure we're getting all element bits from the scalar register.
// FIXME: Support implicit sign extension of vmv.v.x? // FIXME: Support implicit sign extension of vmv.v.x?
if (ScalarBits < EltBits) if (ScalarBits < EltBits)
return SDValue(); return SDValue();
if (IsSigned) { if (IsSigned) {
if (DAG.ComputeNumSignBits(Op0) <= (ScalarBits - NarrowSize)) if (DAG.ComputeNumSignBits(Op0) <= (ScalarBits - NarrowSize))
return SDValue(); return SDValue();
} else { } else {
APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize); APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize);
if (!DAG.MaskedValueIsZero(Op0, Mask)) if (!DAG.MaskedValueIsZero(Op0, Mask))
return SDValue(); return SDValue();
} }
Op0 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT, Op0, VL); Op0 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT,
DAG.getUNDEF(NarrowVT), Op0, VL);
return DAG.getNode(VOpc, DL, VT, Op1, Op0, Mask, VL); return DAG.getNode(VOpc, DL, VT, Op1, Op0, Mask, VL);
} }
return SDValue(); return SDValue();
} }
// Try to form VWMUL, VWMULU or VWMULSU. // Try to form VWMUL, VWMULU or VWMULSU.
// TODO: Support VWMULSU.vx with a sign extend Op and a splat of scalar Op. // TODO: Support VWMULSU.vx with a sign extend Op and a splat of scalar Op.
Show All 35 Lines if (IsVWMULSU || Op0.getOpcode() == Op1.getOpcode()) {
// Make sure the mask and VL match. // Make sure the mask and VL match.
if (Op1.getOperand(1) != Mask || Op1.getOperand(2) != VL) if (Op1.getOperand(1) != Mask || Op1.getOperand(2) != VL)
return SDValue(); return SDValue();
Op1 = Op1.getOperand(0); Op1 = Op1.getOperand(0);
} else if (Op1.getOpcode() == RISCVISD::VMV_V_X_VL) { } else if (Op1.getOpcode() == RISCVISD::VMV_V_X_VL) {
// The operand is a splat of a scalar. // The operand is a splat of a scalar.
// The pasthru must be undef for tail agnostic
if (!Op1.getOperand(0).isUndef())
return SDValue();
// The VL must be the same. // The VL must be the same.
if (Op1.getOperand(1) != VL) if (Op1.getOperand(2) != VL)
return SDValue(); return SDValue();
// Get the scalar value. // Get the scalar value.
Op1 = Op1.getOperand(0); Op1 = Op1.getOperand(1);
// See if have enough sign bits or zero bits in the scalar to use a // See if have enough sign bits or zero bits in the scalar to use a
// widening multiply by splatting to smaller element size. // widening multiply by splatting to smaller element size.
unsigned EltBits = VT.getScalarSizeInBits(); unsigned EltBits = VT.getScalarSizeInBits();
unsigned ScalarBits = Op1.getValueSizeInBits(); unsigned ScalarBits = Op1.getValueSizeInBits();
// Make sure we're getting all element bits from the scalar register. // Make sure we're getting all element bits from the scalar register.
// FIXME: Support implicit sign extension of vmv.v.x? // FIXME: Support implicit sign extension of vmv.v.x?
if (ScalarBits < EltBits) if (ScalarBits < EltBits)
return SDValue(); return SDValue();
if (IsSignExt) { if (IsSignExt) {
if (DAG.ComputeNumSignBits(Op1) <= (ScalarBits - NarrowSize)) if (DAG.ComputeNumSignBits(Op1) <= (ScalarBits - NarrowSize))
return SDValue(); return SDValue();
} else { } else {
APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize); APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize);
if (!DAG.MaskedValueIsZero(Op1, Mask)) if (!DAG.MaskedValueIsZero(Op1, Mask))
return SDValue(); return SDValue();
} }
Op1 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT, Op1, VL); Op1 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT,
DAG.getUNDEF(NarrowVT), Op1, VL);
} else } else
return SDValue(); return SDValue();
Op0 = Op0.getOperand(0); Op0 = Op0.getOperand(0);
// Re-introduce narrower extends if needed. // Re-introduce narrower extends if needed.
unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL;
if (Op0.getValueType() != NarrowVT) if (Op0.getValueType() != NarrowVT)
▲ Show 20 Lines • Show All 555 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case RISCVISD::SRL_VL: case RISCVISD::SRL_VL:
case RISCVISD::SHL_VL: { case RISCVISD::SHL_VL: {
SDValue ShAmt = N->getOperand(1); SDValue ShAmt = N->getOperand(1);
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
// We don't need the upper 32 bits of a 64-bit element for a shift amount. // We don't need the upper 32 bits of a 64-bit element for a shift amount.
SDLoc DL(N); SDLoc DL(N);
SDValue VL = N->getOperand(3); SDValue VL = N->getOperand(3);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
ShAmt = ShAmt = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, ShAmt.getOperand(0), VL); ShAmt.getOperand(1), VL);
return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt, return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt,
N->getOperand(2), N->getOperand(3)); N->getOperand(2), N->getOperand(3));
} }
break; break;
} }
case ISD::SRA: case ISD::SRA:
case ISD::SRL: case ISD::SRL:
case ISD::SHL: { case ISD::SHL: {
SDValue ShAmt = N->getOperand(1); SDValue ShAmt = N->getOperand(1);
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
// We don't need the upper 32 bits of a 64-bit element for a shift amount. // We don't need the upper 32 bits of a 64-bit element for a shift amount.
SDLoc DL(N); SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
ShAmt = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, ShAmt.getOperand(0), ShAmt = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
ShAmt.getOperand(1),
DAG.getRegister(RISCV::X0, Subtarget.getXLenVT())); DAG.getRegister(RISCV::X0, Subtarget.getXLenVT()));
return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt); return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt);
} }
break; break;
} }
case RISCVISD::ADD_VL: case RISCVISD::ADD_VL:
if (SDValue V = combineADDSUB_VLToVWADDSUB_VL(N, DAG, /*Commute*/ false)) if (SDValue V = combineADDSUB_VLToVWADDSUB_VL(N, DAG, /*Commute*/ false))
return V; return V;
▲ Show 20 Lines • Show All 3,031 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 853 Lines • ▼ Show 20 Linesclass VPseudoUnaryNoDummyMask<VReg RetClass,
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoUnaryNoDummyMaskTU<VReg RetClass,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoNullaryNoMask<VReg RegClass>: class VPseudoNullaryNoMask<VReg RegClass>:
Pseudo<(outs RegClass:$rd), Pseudo<(outs RegClass:$rd),
(ins AVL:$vl, ixlenimm:$sew), (ins AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo { []>, RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
▲ Show 20 Lines • Show All 1,125 Lines • ▼ Show 20 Linesmulticlass VPseudoUnaryVMV_V_X_I {
foreach m = MxList in { foreach m = MxList in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>, def "_V_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV, ReadVIMovV]>; Sched<[WriteVIMovV, ReadVIMovV]>;
def "_X_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, GPR>, def "_X_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, GPR>,
Sched<[WriteVIMovX, ReadVIMovX]>; Sched<[WriteVIMovX, ReadVIMovX]>;
def "_I_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, simm5>, def "_I_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, simm5>,
Sched<[WriteVIMovI]>; Sched<[WriteVIMovI]>;
def "_V_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV, ReadVIMovV]>;
def "_X_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, GPR>,
Sched<[WriteVIMovX, ReadVIMovX]>;
def "_I_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, simm5>,
Sched<[WriteVIMovI]>;
} }
} }
} }
multiclass VPseudoVMV_F { multiclass VPseudoVMV_F {
foreach f = FPList in { foreach f = FPList in {
foreach m = f.MxList in { foreach m = f.MxList in {
let VLMul = m.value in { let VLMul = m.value in {
def "_" # f.FX # "_" # m.MX : def "_" # f.FX # "_" # m.MX :
VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>, VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV, ReadVFMovF]>; Sched<[WriteVFMovV, ReadVFMovF]>;
def "_" # f.FX # "_" # m.MX # "_TU":
VPseudoUnaryNoDummyMaskTU<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV, ReadVFMovF]>;
} }
} }
} }
} }
multiclass VPseudoVCLS_V { multiclass VPseudoVCLS_V {
foreach m = MxListF in { foreach m = MxListF in {
let VLMul = m.value in { let VLMul = m.value in {
▲ Show 20 Lines • Show All 3,044 Lines • ▼ Show 20 Lines
// 12.15. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.16. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach vti = AllVectors in { foreach vti = AllVectors in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
$rs1, GPR:$vl, vti.Log2SEW)>; $rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru),
(vti.Vector vti.RegClass:$rs1),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX#"_TU")
$passthru, $rs1, GPR:$vl, vti.Log2SEW)>;
// vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td // vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.1. Vector Single-Width Saturating Add and Subtract // 13.1. Vector Single-Width Saturating Add and Subtract
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>; defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>;
▲ Show 20 Lines • Show All 369 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 578 Lines • ▼ Show 20 Lines
// 12.6. Vector Single-Width Bit Shift Instructions // 12.6. Vector Single-Width Bit Shift Instructions
defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>; defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>; defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>; defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster. // Emit shift by 1 as an add since it might be faster.
def : Pat<(shl (vti.Vector vti.RegClass:$rs1), def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
(vti.Vector (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)))), (vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
} }
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">; defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">; defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
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llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

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def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>, SDTCisSameAs<0, 2>,
SDTCisVec<0>, SDTCisFP<0>, SDTCisVec<0>, SDTCisFP<0>,
SDTCVecEltisVT<3, i1>, SDTCVecEltisVT<3, i1>,
SDTCisSameNumEltsAs<0, 3>, SDTCisSameNumEltsAs<0, 3>,
SDTCisVT<4, XLenVT>]>; SDTCisVT<4, XLenVT>]>;
def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,
SDTCisVT<1, XLenVT>, SDTCisSameAs<0, 1>,
SDTCisVT<2, XLenVT>]>>; SDTCisVT<2, XLenVT>,
SDTCisVT<3, XLenVT>]>>;
def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
SDTCisEltOfVec<1, 0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, XLenVT>]>>; SDTCisEltOfVec<2, 0>,
SDTCisVT<3, XLenVT>]>>;
def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
SDTCisInt<0>, SDTCisInt<0>,
SDTCisVT<2, XLenVT>, SDTCisVT<2, XLenVT>,
SDTCisVT<3, XLenVT>]>>; SDTCisVT<3, XLenVT>]>>;
def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
SDTCisFP<0>, SDTCisFP<0>,
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def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>;
def SplatPat_simm5_plus1 def SplatPat_simm5_plus1
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>;
def SplatPat_simm5_plus1_nonzero def SplatPat_simm5_plus1_nonzero
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>;
// Ignore the vl operand. // Ignore the vl operand.
def SplatFPOp : PatFrag<(ops node:$op), def SplatFPOp : PatFrag<(ops node:$op),
(riscv_vfmv_v_f_vl node:$op, srcvalue)>; (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>;
def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>;
def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
multiclass VPatBinaryVL_V<SDNode vop, multiclass VPatBinaryVL_V<SDNode vop,
string instruction_name, string instruction_name,
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// 12.6. Vector Single-Width Bit Shift Instructions // 12.6. Vector Single-Width Bit Shift Instructions
defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;
defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;
defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster. // Emit shift by 1 as an add since it might be faster.
def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),
(riscv_vmv_v_x_vl 1, (XLenVT srcvalue)), (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag), VLOpFrag),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
} }
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">; defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">;
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU")
vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
// 12.16. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, VLOpFrag)), def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
$rs2, GPR:$vl, vti.Log2SEW)>; $rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU")
$passthru, $rs2, GPR:$vl, vti.Log2SEW)>;
defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5), def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU")
$passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;
} }
// 12.1. Vector Single-Width Saturating Add and Subtract // 12.1. Vector Single-Width Saturating Add and Subtract
defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">;
defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">;
defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">;
defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">;
▲ Show 20 Lines • Show All 267 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU")
fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0),
GPR:$vl, fvti.Log2SEW)>; GPR:$vl, fvti.Log2SEW)>;
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
// If we're splatting fpimm0, use vmv.v.x vd, x0. // If we're splatting fpimm0, use vmv.v.x vd, x0.
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Scalar (fpimm0)), VLOpFrag)), (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, GPR:$vl, fvti.Log2SEW)>; 0, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU")
$passthru, 0, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX) fvti.LMul.MX)
(fvti.Scalar fvti.ScalarRegClass:$rs2), (fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.Log2SEW)>; GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX # "_TU")
$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.Log2SEW)>;
// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">;
defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">;
defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
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llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

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; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8, i32); declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8>, i8, i32);
; Test that we don't optimize ult x, 0 -> ule x, -1 ; Test that we don't optimize ult x, 0 -> ule x, -1
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i32 %vl) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i32 %vl) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_5: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v0, v8, zero ; CHECK-NEXT: vmsltu.vx v0, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i32 %vl) %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i32 %vl)
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_ule_vv_nxv8i8: ; CHECK-LABEL: icmp_ule_vv_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i32 %vl) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i32 %vl) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i32 %vl) %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i32 %vl)
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-LABEL: icmp_ult_vv_nxv8i16: ; CHECK-LABEL: icmp_ult_vv_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

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define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i64 %vl) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i64 %vl) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i64 %vl) %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i64 %vl)
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_ult_vv_nxv8i8: ; CHECK-LABEL: icmp_ult_vv_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
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; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8, i64); declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8>, i8, i64);
; Test that we don't optimize ult x, 0 -> ule x, -1 ; Test that we don't optimize ult x, 0 -> ule x, -1
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i64 %vl) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, i64 %vl) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_5: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v0, v8, zero ; CHECK-NEXT: vmsltu.vx v0, v8, zero
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i64 %vl) %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(<vscale x 8 x i8> undef, i8 0, i64 %vl)
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_ule_vv_nxv8i8: ; CHECK-LABEL: icmp_ule_vv_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
▲ Show 20 Lines • Show All 2,531 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

Show First 20 Lines • Show All 3,218 Lines • ▼ Show 20 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half zeroinitializer, half zeroinitializer,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vmv.v.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
iXLen);
define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; RV64-NEXT: vmv.v.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
iXLen %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64>,
i64,
iXLen);
define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> %0,
i64 %1,
iXLen %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(
<vscale x 1 x float>,
float,
iXLen);
define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfmv.v.f_f_nxv1f32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; RV32-NEXT: vfmv.v.f v8, fa0
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfmv.v.f_f_nxv1f32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; RV64-NEXT: vfmv.v.f v8, fa0
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(
<vscale x 1 x float> %0,
float %1,
iXLen %2)
ret <vscale x 1 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
<vscale x 1 x half>,
half, half,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
<vscale x 1 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(
<vscale x 2 x half>,
half, half,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(
<vscale x 2 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(
<vscale x 4 x half>,
half, half,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(
<vscale x 4 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(
<vscale x 8 x half>,
half, half,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(
<vscale x 8 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(
<vscale x 16 x half>,
half, half,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(
<vscale x 16 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(
<vscale x 32 x half>,
half, half,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(
<vscale x 32 x half> undef,
half %0, half %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(
<vscale x 1 x float>,
float, float,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(float %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(float %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(
<vscale x 1 x float> undef,
float %0, float %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32(
<vscale x 2 x float>,
float, float,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32(float %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32(float %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32(
<vscale x 2 x float> undef,
float %0, float %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32(
<vscale x 4 x float>,
float, float,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32(float %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32(float %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32(
<vscale x 4 x float> undef,
float %0, float %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32(
<vscale x 8 x float>,
float, float,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32(float %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32(float %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32(
<vscale x 8 x float> undef,
float %0, float %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32(
<vscale x 16 x float>,
float, float,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32(float %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32(float %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32(
<vscale x 16 x float> undef,
float %0, float %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(
<vscale x 1 x double>,
double, double,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64(double %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64(double %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(
<vscale x 1 x double> undef,
double %0, double %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64(
<vscale x 2 x double>,
double, double,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64(double %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64(double %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64(
<vscale x 2 x double> undef,
double %0, double %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64(
<vscale x 4 x double>,
double, double,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64(double %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64(double %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64(
<vscale x 4 x double> undef,
double %0, double %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(
<vscale x 8 x double>,
double, double,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64(double %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64(double %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64: ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(
<vscale x 8 x double> undef,
double %0, double %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16(iXLen %0) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
<vscale x 1 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vmv.v.i_zero_nxv2f16(iXLen %0) nounwind { define <vscale x 2 x half> @intrinsic_vmv.v.i_zero_nxv2f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(
<vscale x 2 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vmv.v.i_zero_nxv4f16(iXLen %0) nounwind { define <vscale x 4 x half> @intrinsic_vmv.v.i_zero_nxv4f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(
<vscale x 4 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vmv.v.i_zero_nxv8f16(iXLen %0) nounwind { define <vscale x 8 x half> @intrinsic_vmv.v.i_zero_nxv8f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(
<vscale x 8 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vmv.v.i_zero_nxv16f16(iXLen %0) nounwind { define <vscale x 16 x half> @intrinsic_vmv.v.i_zero_nxv16f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(
<vscale x 16 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 32 x half> @intrinsic_vmv.v.i_zero_nxv32f16(iXLen %0) nounwind { define <vscale x 32 x half> @intrinsic_vmv.v.i_zero_nxv32f16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(
<vscale x 32 x half> undef,
half 0.0, half 0.0,
iXLen %0) iXLen %0)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
define <vscale x 1 x float> @intrinsic_vmv.v.i_zero_nxv1f32(iXLen %0) nounwind { define <vscale x 1 x float> @intrinsic_vmv.v.i_zero_nxv1f32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(
<vscale x 1 x float> undef,
float 0.0, float 0.0,
iXLen %0) iXLen %0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vmv.v.i_zero_nxv2f32(iXLen %0) nounwind { define <vscale x 2 x float> @intrinsic_vmv.v.i_zero_nxv2f32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32(
<vscale x 2 x float> undef,
float 0.0, float 0.0,
iXLen %0) iXLen %0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vmv.v.i_zero_nxv4f32(iXLen %0) nounwind { define <vscale x 4 x float> @intrinsic_vmv.v.i_zero_nxv4f32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32(
<vscale x 4 x float> undef,
float 0.0, float 0.0,
iXLen %0) iXLen %0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vmv.v.i_zero_nxv8f32(iXLen %0) nounwind { define <vscale x 8 x float> @intrinsic_vmv.v.i_zero_nxv8f32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32(
<vscale x 8 x float> undef,
float 0.0, float 0.0,
iXLen %0) iXLen %0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 16 x float> @intrinsic_vmv.v.i_zero_nxv16f32(iXLen %0) nounwind { define <vscale x 16 x float> @intrinsic_vmv.v.i_zero_nxv16f32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32(
<vscale x 16 x float> undef,
float 0.0, float 0.0,
iXLen %0) iXLen %0)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
define <vscale x 1 x double> @intrinsic_vmv.v.i_zero_nxv1f64(iXLen %0) nounwind { define <vscale x 1 x double> @intrinsic_vmv.v.i_zero_nxv1f64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(
<vscale x 1 x double> undef,
double 0.0, double 0.0,
iXLen %0) iXLen %0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vmv.v.i_zero_nxv2f64(iXLen %0) nounwind { define <vscale x 2 x double> @intrinsic_vmv.v.i_zero_nxv2f64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64(
<vscale x 2 x double> undef,
double 0.0, double 0.0,
iXLen %0) iXLen %0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vmv.v.i_zero_nxv4f64(iXLen %0) nounwind { define <vscale x 4 x double> @intrinsic_vmv.v.i_zero_nxv4f64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64(
<vscale x 4 x double> undef,
double 0.0, double 0.0,
iXLen %0) iXLen %0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 8 x double> @intrinsic_vmv.v.i_zero_nxv8f64(iXLen %0) nounwind { define <vscale x 8 x double> @intrinsic_vmv.v.i_zero_nxv8f64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64: ; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(
<vscale x 8 x double> undef,
double 0.0, double 0.0,
iXLen %0) iXLen %0)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i32 %1) nounwind { define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
i32 %1) i32 %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i32 %1) nounwind { define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
i32 %1) i32 %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i32 %1) nounwind { define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
i32 %1) i32 %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i32 %1) nounwind { define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
i32 %1) i32 %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i32 %1) nounwind { define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
i32 %1) i32 %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i32 %1) nounwind { define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
i32 %1) i32 %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i32 %1) nounwind { define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
i32 %1) i32 %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i32 %1) nounwind { define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
i32 %1) i32 %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i32 %1) nounwind { define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
i32 %1) i32 %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i32 %1) nounwind { define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
i32 %1) i32 %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i32 %1) nounwind { define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
i32 %1) i32 %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i32 %1) nounwind { define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
i32 %1) i32 %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i32 %1) nounwind { define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
i32 %1) i32 %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i32 %1) nounwind { define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
i32 %1) i32 %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i32 %1) nounwind { define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
i32 %1) i32 %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind { define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
i64 %1) i64 %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i64 %1) nounwind { define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
i64 %1) i64 %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i64 %1) nounwind { define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
i64 %1) i64 %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i64 %1) nounwind { define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
i64 %1) i64 %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i64 %1) nounwind { define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
i64 %1) i64 %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i64 %1) nounwind { define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
i64 %1) i64 %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind { define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
i64 %1) i64 %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i64 %1) nounwind { define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
i64 %1) i64 %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i64 %1) nounwind { define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
i64 %1) i64 %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i64 %1) nounwind { define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
i64 %1) i64 %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i64 %1) nounwind { define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
i64 %1) i64 %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind { define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
i64 %1) i64 %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i64 %1) nounwind { define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
i64 %1) i64 %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i64 %1) nounwind { define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
i64 %1) i64 %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i64 %1) nounwind { define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.v v8, v8 ; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
i64 %1) i64 %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8>,
i8, i8,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8>,
i8, i8,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8>,
i8, i8,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8>,
i8, i8,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8>,
i8, i8,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8>,
i8, i8,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8>,
i8, i8,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8> undef,
i8 %0, i8 %0,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16>,
i16, i16,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16>,
i16, i16,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16>,
i16, i16,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16>,
i16, i16,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16>,
i16, i16,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16>,
i16, i16,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16> undef,
i16 %0, i16 %0,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32> undef,
i32 %0, i32 %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32> undef,
i32 %0, i32 %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32> undef,
i32 %0, i32 %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32> undef,
i32 %0, i32 %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32> undef,
i32 %0, i32 %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64>,
i64, i64,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(i32 %0) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(i32 %0) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(i32 %0) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(i32 %0) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(i32 %0) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(i32 %0) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(i32 %0) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8> undef,
i8 9, i8 9,
i32 %0) i32 %0)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(i32 %0) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(i32 %0) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(i32 %0) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(i32 %0) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(i32 %0) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(i32 %0) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16> undef,
i16 9, i16 9,
i32 %0) i32 %0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(i32 %0) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32> undef,
i32 9, i32 9,
i32 %0) i32 %0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(i32 %0) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32> undef,
i32 9, i32 9,
i32 %0) i32 %0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(i32 %0) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32> undef,
i32 9, i32 9,
i32 %0) i32 %0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(i32 %0) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32> undef,
i32 9, i32 9,
i32 %0) i32 %0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(i32 %0) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32> undef,
i32 9, i32 9,
i32 %0) i32 %0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(i32 %0) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef,
i64 9, i64 9,
i32 %0) i32 %0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(i32 %0) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef,
i64 9, i64 9,
i32 %0) i32 %0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(i32 %0) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef,
i64 9, i64 9,
i32 %0) i32 %0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(i32 %0) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(i32 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef,
i64 9, i64 9,
i32 %0) i32 %0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_vlmax() nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_vlmax: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef,
i64 12884901891, i64 12884901891,
i32 -1) i32 -1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_vlmax() nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_vlmax: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef,
i64 12884901891, i64 12884901891,
i32 -1) i32 -1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_vlmax() nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_vlmax: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef,
i64 12884901891, i64 12884901891,
i32 -1) i32 -1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_vlmax() nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_vlmax: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef,
i64 12884901891, i64 12884901891,
i32 -1) i32 -1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8>,
i8, i8,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8>,
i8, i8,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8>,
i8, i8,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8>,
i8, i8,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8>,
i8, i8,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8>,
i8, i8,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8>,
i8, i8,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8> undef,
i8 %0, i8 %0,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16>,
i16, i16,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16>,
i16, i16,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16>,
i16, i16,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16>,
i16, i16,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16>,
i16, i16,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16>,
i16, i16,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16> undef,
i16 %0, i16 %0,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32>,
i32, i32,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32> undef,
i32 %0, i32 %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32>,
i32, i32,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32> undef,
i32 %0, i32 %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32>,
i32, i32,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32> undef,
i32 %0, i32 %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32>,
i32, i32,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32> undef,
i32 %0, i32 %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32>,
i32, i32,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32> undef,
i32 %0, i32 %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef,
i64 %0, i64 %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef,
i64 %0, i64 %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef,
i64 %0, i64 %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef,
i64 %0, i64 %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(i64 %0) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
<vscale x 1 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(i64 %0) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
<vscale x 2 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(i64 %0) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
<vscale x 4 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(i64 %0) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
<vscale x 8 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(i64 %0) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
<vscale x 16 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(i64 %0) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
<vscale x 32 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(i64 %0) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
<vscale x 64 x i8> undef,
i8 9, i8 9,
i64 %0) i64 %0)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(i64 %0) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
<vscale x 1 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(i64 %0) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
<vscale x 2 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(i64 %0) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
<vscale x 4 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(i64 %0) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
<vscale x 8 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(i64 %0) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
<vscale x 16 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(i64 %0) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
<vscale x 32 x i16> undef,
i16 9, i16 9,
i64 %0) i64 %0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(i64 %0) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
<vscale x 1 x i32> undef,
i32 9, i32 9,
i64 %0) i64 %0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(i64 %0) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
<vscale x 2 x i32> undef,
i32 9, i32 9,
i64 %0) i64 %0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(i64 %0) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
<vscale x 4 x i32> undef,
i32 9, i32 9,
i64 %0) i64 %0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(i64 %0) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
<vscale x 8 x i32> undef,
i32 9, i32 9,
i64 %0) i64 %0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(i64 %0) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
<vscale x 16 x i32> undef,
i32 9, i32 9,
i64 %0) i64 %0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(i64 %0) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef,
i64 9, i64 9,
i64 %0) i64 %0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(i64 %0) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef,
i64 9, i64 9,
i64 %0) i64 %0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(i64 %0) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef,
i64 9, i64 9,
i64 %0) i64 %0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(i64 %0) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(i64 %0) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 9 ; CHECK-NEXT: vmv.v.i v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef,
i64 9, i64 9,
i64 %0) i64 %0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s ; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
; The following tests check whether inserting VSETVLI avoids inserting ; The following tests check whether inserting VSETVLI avoids inserting
; unneeded vsetvlis across basic blocks. ; unneeded vsetvlis across basic blocks.
declare i64 @llvm.riscv.vsetvli(i64, i64, i64) declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64) declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)
declare <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) declare <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64)
declare <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64) declare <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)
declare <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64) declare <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)
declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double, i64) declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double>, double, i64)
declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float, i64) declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float>, float, i64)
declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64) declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64) declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64)
define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 1.000000e+00, i64 %avl) %0 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 1.000000e+00, i64 %avl)
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 2.000000e+00, i64 %avl) %1 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 2.000000e+00, i64 %avl)
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %avl) %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %avl)
%3 = bitcast i8* @scratch to <vscale x 1 x double>* %3 = bitcast i8* @scratch to <vscale x 1 x double>*
tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %2, <vscale x 1 x double>* %3, i64 %avl) tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %2, <vscale x 1 x double>* %3, i64 %avl)
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
%4 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 1.000000e+00, i64 %avl) %4 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(<vscale x 2 x float> undef, float 1.000000e+00, i64 %avl)
%5 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 2.000000e+00, i64 %avl) %5 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(<vscale x 2 x float> undef, float 2.000000e+00, i64 %avl)
%6 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> %4, <vscale x 2 x float> %5, i64 %avl) %6 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> %4, <vscale x 2 x float> %5, i64 %avl)
%7 = bitcast i8* @scratch to <vscale x 2 x float>* %7 = bitcast i8* @scratch to <vscale x 2 x float>*
tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %6, <vscale x 2 x float>* %7, i64 %avl) tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %6, <vscale x 2 x float>* %7, i64 %avl)
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl) %8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl)
ret <vscale x 1 x double> %8 ret <vscale x 1 x double> %8
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if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ] %c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
%and2 = and i32 %conv, 2 %and2 = and i32 %conv, 2
%tobool3 = icmp eq i32 %and2, 0 %tobool3 = icmp eq i32 %and2, 0
br i1 %tobool3, label %if.else5, label %if.then4 br i1 %tobool3, label %if.else5, label %if.then4
if.then4: ; preds = %if.end if.then4: ; preds = %if.end
%3 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %3 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%4 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 1.000000e+00, i64 %3) %4 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 1.000000e+00, i64 %3)
%5 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 2.000000e+00, i64 %3) %5 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 2.000000e+00, i64 %3)
%6 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %4, <vscale x 1 x double> %5, i64 %3) %6 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %4, <vscale x 1 x double> %5, i64 %3)
%7 = bitcast i8* @scratch to <vscale x 1 x double>* %7 = bitcast i8* @scratch to <vscale x 1 x double>*
tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %6, <vscale x 1 x double>* %7, i64 %3) tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %6, <vscale x 1 x double>* %7, i64 %3)
br label %if.end10 br label %if.end10
if.else5: ; preds = %if.end if.else5: ; preds = %if.end
%8 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0) %8 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
%9 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 1.000000e+00, i64 %8) %9 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(<vscale x 2 x float> undef, float 1.000000e+00, i64 %8)
%10 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 2.000000e+00, i64 %8) %10 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float> undef, float 2.000000e+00, i64 %8)
%11 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> %9, <vscale x 2 x float> %10, i64 %8) %11 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> %9, <vscale x 2 x float> %10, i64 %8)
%12 = bitcast i8* @scratch to <vscale x 2 x float>* %12 = bitcast i8* @scratch to <vscale x 2 x float>*
tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %11, <vscale x 2 x float>* %12, i64 %8) tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %11, <vscale x 2 x float>* %12, i64 %8)
br label %if.end10 br label %if.end10
if.end10: ; preds = %if.else5, %if.then4 if.end10: ; preds = %if.else5, %if.then4
%13 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %c.0, <vscale x 1 x double> %c.0, i64 %0) %13 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %c.0, <vscale x 1 x double> %c.0, i64 %0)
ret <vscale x 1 x double> %13 ret <vscale x 1 x double> %13
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llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
; RUN: -verify-machineinstrs < %s \ ; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>)
declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>)
declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>)
declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(half, i64); declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(<vscale x 1 x half>, half, i64);
declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(float, i64); declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float>, float, i64);
declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(double, i64); declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double>, double, i64);
define <vscale x 1 x half> @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fsh ft0, 14(sp) # 2-byte Folded Spill ; CHECK-NEXT: fsh ft0, 14(sp) # 2-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: flh ft0, 14(sp) # 2-byte Folded Reload ; CHECK-NEXT: flh ft0, 14(sp) # 2-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, ft0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0) %a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(half %a, i64 %1) %b = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(<vscale x 1 x half> undef, half %a, i64 %1)
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
define <vscale x 1 x float> @intrinsic_vfmv.f.s_s_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind { define <vscale x 1 x float> @intrinsic_vfmv.f.s_s_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, ft0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0) %a = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(float %a, i64 %1) %b = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(<vscale x 1 x float> undef, float %a, i64 %1)
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
define <vscale x 1 x double> @intrinsic_vfmv.f.s_s_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind { define <vscale x 1 x double> @intrinsic_vfmv.f.s_s_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64: ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: vfmv.v.f v8, ft0 ; CHECK-NEXT: vfmv.v.f v8, ft0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0) %a = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"() tail call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
%b = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(double %a, i64 %1) %b = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(<vscale x 1 x double> undef, double %a, i64 %1)
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }