[RISCV] Fix incorrect codegen introduced by D119688.

[khchen]

Summary

We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x

In D119688:

-    if (IsScalarMove && !Node->getOperand(0).isUndef())
+    bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
+    if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
       break;

The IsScalarMove check in the if statement had been changed.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

#undef CASE_VMXOR_VMANDN_VMAND_OPCODES
   case RISCVISD::VMV_S_X_VL:
   case RISCVISD::VFMV_S_F_VL:
   case RISCVISD::VMV_V_X_VL:
   case RISCVISD::VFMV_V_F_VL: {
     // Try to match splat of a scalar load to a strided load with stride of x0.
     bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
                         Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
     bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
-    if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
+    if (HasPassthruOperand && !Node->getOperand(0).isUndef())
       break;
     SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
     auto *Ld = dyn_cast<LoadSDNode>(Src);
     if (!Ld)
       break;
     EVT MemVT = Ld->getMemoryVT();
     // The memory VT should be the same size as the element type.
     if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize())

llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll

entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2)
   ret <vscale x 8 x i64> %a
 }
 
 ; We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x
 define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64_bug(<vscale x 1 x i64> %0, i64* %1) nounwind {
 ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT:    vlse64.v v8, (a0), zero
+; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, tu, mu
+; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    ret
 entry:
   %a = load i64, i64* %1, align 8
   %b = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %a, i64 1)
   ret <vscale x 1 x i64> %b
 }