[AsmPrinter] Loop over bundles in generic code

[sebastian-ne]

Summary

Every target, except Hexagon, iterates over bundles and prints the
contents like every other instruction.

A part of instruction printing is done in the for-loop in the
AsmPrinter, e.g. handling debug or kill instructions, which had to be
reimplemented in every target to support bundles.

With this patch, iterating over instruction bundles is taken out of the
targets and moved into the generic AsmPrinter.
For Hexagon, the bundles are still printed when encountering the bundle
instruction. Further instructions inside bundles are ignored.

Mips has a test change for some debug data. I hope this is just some
moved metadata and doesn't change behavior.

[foad]

I guess if you re-auto-generated test checks, there would be millions of changes due to extra comments at the end of lines? But they don't show up as failures because the generated checks don't end with {{$}}?

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1275–1290

Can't you change this loop to iterate over MBB.instrs(), instead of adding another nested loop?

[sebastian-ne]

Good idea to use .instrs(), it looks better now.

I guess if you re-auto-generated test checks, there would be millions of changes due to extra comments at the end of lines? But they don't show up as failures because the generated checks don't end with {{$}}?

Right, they don’t show up as failures. I hope it wouldn’t be millions, the comment is only new for spills inside bundles/clauses. I can search for such cases and regenerate the tests if you think it makes sense?

[foad]

I can search for such cases and regenerate the tests if you think it makes sense?

I think it would be nice, to avoid spurious changes the next time someone has to regenerate the checks, but I won't insist.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1275

Much nicer! :)

[foad]

Mips has a test change for some debug data. I hope this is just some
moved metadata and doesn't change behavior.

Unfortunately I think you have broken the delay slot stuff that was added in D78107, which was meant to ensure that the "label after a call follows the delay slot instruction". The diff from your change on the mips test case looks like this:

 	jal	f1
-	addiu	$4, $zero, 10
 $tmp2:
+	addiu	$4, $zero, 10

so the label $tmp2 now points to the addiu which is in the delay slot of the jal (call).

It looks like D78107 relies on some dubious bundle-without-a-BUNDLE-insn constrructs like this:

JAL @f1, <regmask $fp $ra $d10 $d11 $d12 $d13 $d14 $d15 $f20 $f21 $f22 $f23 $f24 $f25 $f26 $f27 $f28 $f29 $f30 $f31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7>, implicit-def dead $ra, implicit killed $a0, implicit-def $sp, debug-location !17; m.c:0 {
  $a0 = ADDiu $zero, 10, debug-location !17; m.c:0
}

so maybe you just need to be careful to handle these correctly?

[arsenm]

I think letting generic code inspect individual instructions inside bundles violates the spirit of what bundles, which should generally be opaque to generic code. I wouldn't be surprised if this breaks some out of tree target using bundles

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

761

No else after return

[sebastian-ne]

I think letting generic code inspect individual instructions inside bundles violates the spirit of what bundles, which should generally be opaque to generic code. I wouldn't be surprised if this breaks some out of tree target using bundles

In that case, I’ll abandon this.

[foad]

I think letting generic code inspect individual instructions inside bundles violates the spirit of what bundles, which should generally be opaque to generic code. I wouldn't be surprised if this breaks some out of tree target using bundles

Well it seems OK to me, given that it simplifies all the in-tree emitInstruction implementations.

Maybe the API of emitInstruction could change to take a reference to an iterator, and update the iterator to indicate how many instructions it has emitted? That way all the in-tree implementations could emit a single MachineInstr but your hypothetical out-of-tree implementation could emit an entire bundle at once.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::emitFunctionBody() {
   bool HasAnyRealCode = false;
   int NumInstsInFunction = 0;
 
   bool CanDoExtraAnalysis = ORE->allowExtraAnalysis(DEBUG_TYPE);
   for (auto &MBB : *MF) {
     // Print a label for the basic block.
     emitBasicBlockStart(MBB);
     DenseMap<StringRef, unsigned> MnemonicCounts;
-    for (auto &MI : MBB) {
+    for (auto &MI : MBB.instrs()) {
       // Print the assembly for the instruction.
       if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() &&
           !MI.isDebugInstr()) {
         HasAnyRealCode = true;
         ++NumInstsInFunction;
       }
 
       // If there is a pre-instruction symbol, emit a label for it here.
       if (MCSymbol *S = MI.getPreInstrSymbol())
         OutStreamer->emitLabel(S);
 
       for (const HandlerInfo &HI : Handlers) {
         NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName,
                            HI.TimerGroupDescription, TimePassesIsEnabled);
         HI.Handler->beginInstruction(&MI);
       }
 
       if (isVerbose())
         emitComments(MI, OutStreamer->GetCommentOS());
 
       switch (MI.getOpcode()) {
       case TargetOpcode::CFI_INSTRUCTION:
         emitCFIInstruction(MI);

llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
 
   StringRef Err;
   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
     C.emitError("Illegal instruction detected: " + Err);
     MI->print(errs());
   }
 
-  if (MI->isBundle()) {
-    const MachineBasicBlock *MBB = MI->getParent();
-    MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
-    while (I != MBB->instr_end() && I->isInsideBundle()) {
-      emitInstruction(&*I);
-      ++I;
-    }
-  } else {
-    // We don't want these pseudo instructions encoded. They are
-    // placeholder terminator instructions and should only be printed as
-    // comments.
-    if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
-      if (isVerbose())
-        OutStreamer->emitRawComment(" return to shader part epilog");
-      return;
-    }
+  // Ignore the pseudo instruction
+  if (MI->isBundle())
+    return;
+
 
-    if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
-      if (isVerbose())
-        OutStreamer->emitRawComment(" wave barrier");
-      return;
-    }
 
-    if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
-      if (isVerbose())
-        OutStreamer->emitRawComment(" divergent unreachable");
-      return;
-    }
 
-    MCInst TmpInst;
-    MCInstLowering.lower(MI, TmpInst);
-    EmitToStreamer(*OutStreamer, TmpInst);
 
 #ifdef EXPENSIVE_CHECKS
-    // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
-    // work correctly for the generic CPU).
-    //
-    // The isPseudo check really shouldn't be here, but unfortunately there are
-    // some negative lit tests that depend on being able to continue through
-    // here even when pseudo instructions haven't been lowered.
-    //
-    // We also overestimate branch sizes with the offset bug.
-    if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
-        (!STI.hasOffset3fBug() || !MI->isBranch())) {
-      SmallVector<MCFixup, 4> Fixups;
-      SmallVector<char, 16> CodeBytes;
-      raw_svector_ostream CodeStream(CodeBytes);
 
-      std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
-          *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
-      InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
 
-      assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
-    }
 #endif
 
-    if (DumpCodeInstEmitter) {
-      // Disassemble instruction/operands to text
-      DisasmLines.resize(DisasmLines.size() + 1);
-      std::string &DisasmLine = DisasmLines.back();
-      raw_string_ostream DisasmStream(DisasmLine);
 
-      AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
-                                    *STI.getRegisterInfo());
-      InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
 
-      // Disassemble instruction/operands to hex representation.
-      SmallVector<MCFixup, 4> Fixups;
-      SmallVector<char, 16> CodeBytes;
-      raw_svector_ostream CodeStream(CodeBytes);
 
-      DumpCodeInstEmitter->encodeInstruction(
-          TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
-      HexLines.resize(HexLines.size() + 1);
-      std::string &HexLine = HexLines.back();
-      raw_string_ostream HexStream(HexLine);
+    DumpCodeInstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups,
+                                           MF->getSubtarget<MCSubtargetInfo>());
 
-      for (size_t i = 0; i < CodeBytes.size(); i += 4) {
-        unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
-        HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
-      }
 
-      DisasmStream.flush();
-      DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
-    }
-  }
-}
 
 R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
                                  const AsmPrinter &AP) :
         AMDGPUMCInstLower(Ctx, ST, AP) { }
 
 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
   for (const MachineOperand &MO : MI->explicit_operands()) {

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

void HexagonAsmPrinter::emitInstruction(const MachineInstr *MI) {
 
   if (MI->isBundle()) {
     const MachineBasicBlock* MBB = MI->getParent();
     MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
 
     for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
       if (!MII->isDebugInstr() && !MII->isImplicitDef())
         HexagonLowerToMC(MCII, &*MII, MCB, *this);
+  } else if (MI->isInsideBundle()) {
+    // Already handled when the bundle was emitted
+    return;
   } else {
     HexagonLowerToMC(MCII, MI, MCB, *this);
   }
 
   const MachineFunction &MF = *MI->getParent()->getParent();
   const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   if (MI->isBundle() && HII.getBundleNoShuf(*MI))
     HexagonMCInstrInfo::setMemReorderDisabled(MCB);
 

llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp

void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) {
   LanaiMCInstLower MCInstLowering(OutContext, *this);
   MCSubtargetInfo STI = getSubtargetInfo();
   MCInst TmpInst;
   MCInstLowering.Lower(MI, TmpInst);
   OutStreamer->emitInstruction(TmpInst, STI);
 }
 
 void LanaiAsmPrinter::emitInstruction(const MachineInstr *MI) {
-  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
-  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
-
-  do {
-    if (I->isCall()) {
-      emitCallInstruction(&*I);
-      continue;
-    }
+  if (MI->isCall()) {
+    emitCallInstruction(MI);
+    return;
 
-    customEmitInstruction(&*I);
-  } while ((++I != E) && I->isInsideBundle());
+  customEmitInstruction(MI);
 }
 
 // isBlockOnlyReachableByFallthough - Return true if the basic block has
 // exactly one predecessor and the control transfer mechanism between
 // the predecessor and this block is a fall-through.
 // FIXME: could the overridden cases be handled in analyzeBranch?
 bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
     const MachineBasicBlock *MBB) const {

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

case Mips::PATCHABLE_TAIL_CALL:
     return;
   }
 
   if (EmitJalrReloc &&
       (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) {
     emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget);
   }
 
-  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
-  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
-
-  do {
-    // Do any auto-generated pseudo lowerings.
-    if (emitPseudoExpansionLowering(*OutStreamer, &*I))
-      continue;
+  if (emitPseudoExpansionLowering(*OutStreamer, MI))
+    return;
 
-    // Skip the BUNDLE pseudo instruction and lower the contents
-    if (I->isBundle())
-      continue;
+  if (MI->isBundle())
+    return;
 
-    if (I->getOpcode() == Mips::PseudoReturn ||
-        I->getOpcode() == Mips::PseudoReturn64 ||
-        I->getOpcode() == Mips::PseudoIndirectBranch ||
-        I->getOpcode() == Mips::PseudoIndirectBranch64 ||
-        I->getOpcode() == Mips::TAILCALLREG ||
-        I->getOpcode() == Mips::TAILCALLREG64) {
-      emitPseudoIndirectBranch(*OutStreamer, &*I);
-      continue;
-    }
+  if (MI->getOpcode() == Mips::PseudoReturn ||
+      MI->getOpcode() == Mips::PseudoReturn64 ||
+      MI->getOpcode() == Mips::PseudoIndirectBranch ||
+      MI->getOpcode() == Mips::PseudoIndirectBranch64 ||
+      MI->getOpcode() == Mips::TAILCALLREG ||
+      MI->getOpcode() == Mips::TAILCALLREG64) {
+    emitPseudoIndirectBranch(*OutStreamer, MI);
+    return;
 
-    // The inMips16Mode() test is not permanent.
-    // Some instructions are marked as pseudo right now which
-    // would make the test fail for the wrong reason but
-    // that will be fixed soon. We need this here because we are
-    // removing another test for this situation downstream in the
-    // callchain.
-    //
-    if (I->isPseudo() && !Subtarget->inMips16Mode()
-        && !isLongBranchPseudo(I->getOpcode()))
-      llvm_unreachable("Pseudo opcode found in emitInstruction()");
+  if (MI->isPseudo() && !Subtarget->inMips16Mode() &&
+      !isLongBranchPseudo(MI->getOpcode()))
 
-    MCInst TmpInst0;
-    MCInstLowering.Lower(&*I, TmpInst0);
-    EmitToStreamer(*OutStreamer, TmpInst0);
-  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
+  MCInstLowering.Lower(MI, TmpInst0);
 }
 
 //===----------------------------------------------------------------------===//
 //
 //  Mips Asm Directives
 //
 //  -- Frame directive "frame Stackpointer, Stacksize, RARegister"
 //  Describe the stack frame.

llvm/lib/Target/Sparc/SparcAsmPrinter.cpp

void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) {
   default: break;
   case TargetOpcode::DBG_VALUE:
     // FIXME: Debug Value.
     return;
   case SP::GETPCX:
     LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
     return;
   }
-  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
-  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
-  do {
-    MCInst TmpInst;
-    LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
-    EmitToStreamer(*OutStreamer, TmpInst);
-  } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
+  LowerSparcMachineInstrToMCInst(MI, TmpInst, *this);
 }
 
 void SparcAsmPrinter::emitFunctionBodyStart() {
   if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
     return;
 
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };

llvm/lib/Target/VE/VEAsmPrinter.cpp

void VEAsmPrinter::emitInstruction(const MachineInstr *MI) {
   case VE::GETFUNPLT:
     lowerGETFunPLTAndEmitMCInsts(MI, getSubtargetInfo());
     return;
   case VE::GETTLSADDR:
     lowerGETTLSAddrAndEmitMCInsts(MI, getSubtargetInfo());
     return;
   }
 
-  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
-  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
-  do {
-    MCInst TmpInst;
-    LowerVEMachineInstrToMCInst(&*I, TmpInst, *this);
-    EmitToStreamer(*OutStreamer, TmpInst);
-  } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
+  LowerVEMachineInstrToMCInst(MI, TmpInst, *this);
 }
 
 void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                 raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNum);
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

 ; GFX10-NEXT: v_mov_b32_e32 v44, v13
 ; GFX10-NEXT: v_mov_b32_e32 v45, v12
 ; GFX10-NEXT: s_waitcnt vmcnt(0)
 ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
 ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], [v45, v44, v43, v42, v41], s[36:43], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
 
-; GFX10: buffer_load_dword v45, off, s[0:3], s33{{$}}
+; GFX10: buffer_load_dword v45, off, s[0:3], s33 ; 4-byte Folded Reload{{$}}
 ; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:4
 ; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:8
 ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:12
 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:16
 ; GFX10: buffer_load_dword v40, off, s[0:3], s32 offset:20
 ; GFX10: s_setpc_b64 s[4:5]
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)

llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll

 ; CHECK-NEXT:     r29 = and(r29,#-256)
 ; CHECK-NEXT:     memd(r30+#-8) = r17:16
 ; CHECK-NEXT:    } // 8-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v0 = vsplat(r16)
 ; CHECK-NEXT:     r2 = add(r29,#2048)
 ; CHECK-NEXT:     memd(r30+#-16) = r19:18
 ; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    // 8-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     q0 = vand(v0,r0)
 ; CHECK-NEXT:     r18 = ##-2147483648
 ; CHECK-NEXT:     vmem(r2+#-7) = v0
-; CHECK-NEXT:    } // 128-byte Folded Spill
+; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    // 128-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v0 = vand(q0,r17)
 ; CHECK-NEXT:     r0 = ##g1
 ; CHECK-NEXT:     memd(r30+#-24) = r21:20
-; CHECK-NEXT:    } // 8-byte Folded Spill
+; CHECK-NEXT:    } // 128-byte Folded Spill
+; CHECK-NEXT:    // 8-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r19 = ##g0+128
 ; CHECK-NEXT:     vmem(r2+#-6) = v0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v3:2.h = vadd(v0.ub,v1.ub)
 ; CHECK-NEXT:     r20 = ##g0
 ; CHECK-NEXT:     vmem(r29+#5) = v1
 ; CHECK-NEXT:    } // 128-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     vmem(r29+#6) = v2
-; CHECK-NEXT:    } // 256-byte Folded Spill
+; CHECK-NEXT:    } // 128-byte Folded Spill
+; CHECK-NEXT:    // 256-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v31:30.uw = vrmpy(v3:2.ub,r18.ub,#0)
 ; CHECK-NEXT:     vmem(r29+#7) = v3
 ; CHECK-NEXT:    } // 256-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     vmem(r19+#0) = v31
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {

 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.h = vadd(v0.ub,v0.ub)
 ; CHECK-NEXT:     r0 = ##g2
 ; CHECK-NEXT:     vmem(r29+#2) = v0.new
 ; CHECK-NEXT:    } // 256-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     vmem(r29+#3) = v1
 ; CHECK-NEXT:    } // 256-byte Folded Spill
+; CHECK-NEXT:    // 256-byte Folded Spill
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.uw = vrmpy(v1:0.ub,r17.ub,#0)
 ; CHECK-NEXT:     vmem(r19+#0) = v1.new
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     call f1
 ; CHECK-NEXT:     vmem(r20+#0) = v0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = ##2147483647
 ; CHECK-NEXT:     v0 = vmem(r29+#2)
 ; CHECK-NEXT:    } // 256-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1 = vmem(r29+#3)
 ; CHECK-NEXT:    } // 256-byte Folded Reload
+; CHECK-NEXT:    // 256-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.uw = vrmpy(v1:0.ub,r0.ub,#1)
 ; CHECK-NEXT:     r0 = ##g3
 ; CHECK-NEXT:     vmem(r19+#0) = v1.new
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     call f1
 ; CHECK-NEXT:     vmem(r20+#0) = v0

 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = #0
 ; CHECK-NEXT:     v0 = vmem(r29+#6)
 ; CHECK-NEXT:    } // 256-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1 = vmem(r29+#7)
 ; CHECK-NEXT:    } // 256-byte Folded Reload
+; CHECK-NEXT:    // 256-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.uw = vrmpy(v1:0.ub,r0.ub,#1)
 ; CHECK-NEXT:     vmem(r19+#0) = v1.new
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     call f0
 ; CHECK-NEXT:     vmem(r20+#0) = v0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = add(r29,#2048)
 ; CHECK-NEXT:     v1 = vmem(r29+#5)
 ; CHECK-NEXT:    } // 128-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v0 = vmem(r0+#-7)
 ; CHECK-NEXT:    } // 128-byte Folded Reload
+; CHECK-NEXT:    // 128-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.h = vadd(v0.ub,v1.ub)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.uw = vrmpy(v1:0.ub,r16.ub,#1)
 ; CHECK-NEXT:     r17:16 = memd(r30+#-8)
 ; CHECK-NEXT:     vmem(r19+#0) = v1.new
 ; CHECK-NEXT:    } // 8-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r19:18 = memd(r30+#-16)
 ; CHECK-NEXT:     vmem(r20+#0) = v0
 ; CHECK-NEXT:    } // 8-byte Folded Reload
+; CHECK-NEXT:    // 8-byte Folded Reload
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r21:20 = memd(r30+#-24)
 ; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
 ; CHECK-NEXT:    } // 8-byte Folded Reload
 b0:
   %v0 = alloca <32 x i32>, align 128
   %v1 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1)
   %v2 = call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %v1, i32 16843009)

llvm/test/DebugInfo/Mips/dbg-call-site-low-pc.ll

 ;;   return ++x;
 ;; }
 ;; Command: clang -g -O2 -target mips-linux-gnu -S -emit-llvm m.c -c
 ;; Confirm that DW_AT_low_pc (call return address) points to instruction after call delay slot.
 
 ;; Test mips, mipsel, mips64, mips64el:
 ; CHECK:        DW_TAG_GNU_call_site
 ; CHECK-NEXT:     DW_AT_abstract_origin {{.*}} "f1"
-; CHECK-NEXT:     DW_AT_low_pc (0x{{(00000000)?}}00000010)
+; CHECK-NEXT:     DW_AT_low_pc (0x{{(00000000)?}}0000000c)
 
 ; ModuleID = 'm.c'
 source_filename = "m.c"
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips-unknown-linux-gnu"
 
 ; Function Attrs: noinline nounwind
 define dso_local i32 @main() local_unnamed_addr !dbg !12 {