[Aarch64] Adding support for Armv9-A Realm Management Extension

[pratlucas]

Summary

This adds support for Armv9-A's Realm Management Extension, including
three new system registers - MFAR_EL3, GPCCR_EL3 and GPTBR_EL3 - and
four new TLBI instructions.

The reference for the Realm Management Extension can be found at: https://developer.arm.com/documentation/ddi0615/aa.

Based on patches by Victor Campos.

[pratlucas]

Adding RME support to release notes.

[pratlucas]

Rebasing.

[dmgreen]

llvm/lib/Target/AArch64/AArch64SystemOperands.td

478

Should these be in a different Requires block, for RME?

755

Is this register writable?

[pratlucas]

Adding subtarget feature to control RME availability.

[pratlucas]

llvm/lib/Target/AArch64/AArch64SystemOperands.td

755

Yes, according to RME's reference this is a writable register.

[dmgreen]

OK Thanks. LGTM then.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

755

Oh yeah, so it does. It doesn't look like there would be much to write to it.

llvm/docs/ReleaseNotes.rst

 
 * The build system now supports building multiple distributions, so that you can
   e.g. have one distribution containing just tools and another for libraries (to
   enable development). See :ref:`Multi-distribution configurations` for details.
 
 Changes to TableGen
 -------------------
 
+Changes to the AArch64 Backend
+--------------------------
+
+* Introduced support for Armv9-A's Realm Management Extension.
+
 Changes to the ARM Backend
 --------------------------
 
 During this release ...
 
 Changes to the MIPS Target
 --------------------------
 

llvm/lib/Target/AArch64/AArch64.td

 
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension">;
 
 def FeatureEnhancedCounterVirtualization :
       SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
       "true", "Enable enhanced counter virtualization extension">;
 
+def FeatureRME : SubtargetFeature<"rme", "HasRME",
+    "true", "Enable Realm Management Extension">;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
   FeaturePAN, FeatureLOR, FeatureVH]>;
 

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
 
   // Arm SVE2 extensions
   bool HasSVE2 = false;
   bool HasSVE2AES = false;
   bool HasSVE2SM4 = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
+  // Armv9-A Extensions
+  bool HasRME = false;
+
   // Future architecture extensions.
   bool HasETE = false;
   bool HasTRBE = false;
   bool HasBRBE = false;
   bool HasPAUTH = false;
   bool HasSPE_EEF = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 defm : TLBI<"ASIDE1",       0b000, 0b1000, 0b0111, 0b010>;
 defm : TLBI<"VAAE1",        0b000, 0b1000, 0b0111, 0b011>;
 defm : TLBI<"ALLE1",        0b100, 0b1000, 0b0111, 0b100, 0>;
 defm : TLBI<"VALE1",        0b000, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VALE2",        0b100, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VALE3",        0b110, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VMALLS12E1",   0b100, 0b1000, 0b0111, 0b110, 0>;
 defm : TLBI<"VAALE1",       0b000, 0b1000, 0b0111, 0b111>;
 
 // Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
 let Requires = ["AArch64::FeatureTLB_RMI"] in {
 // Armv8.4-A Outer Sharable TLB Maintenance instructions:
 //                         op1    CRn     CRm     op2
 defm : TLBI<"VMALLE1OS",    0b000, 0b1000, 0b0001, 0b000, 0>;
 defm : TLBI<"VAE1OS",       0b000, 0b1000, 0b0001, 0b001>;
 defm : TLBI<"ASIDE1OS",     0b000, 0b1000, 0b0001, 0b010>;
 defm : TLBI<"VAAE1OS",      0b000, 0b1000, 0b0001, 0b011>;

 defm : TLBI<"RVAE3",        0b110, 0b1000, 0b0110, 0b001>;
 defm : TLBI<"RVALE3",       0b110, 0b1000, 0b0110, 0b101>;
 defm : TLBI<"RVAE3IS",      0b110, 0b1000, 0b0010, 0b001>;
 defm : TLBI<"RVALE3IS",     0b110, 0b1000, 0b0010, 0b101>;
 defm : TLBI<"RVAE3OS",      0b110, 0b1000, 0b0101, 0b001>;
 defm : TLBI<"RVALE3OS",     0b110, 0b1000, 0b0101, 0b101>;
 } //FeatureTLB_RMI
 
+// Armv9-A Realm Management Extention TLBI Instructions
+let Requires = ["AArch64::FeatureRME"] in {
+defm : TLBI<"RPAOS",        0b110, 0b1000, 0b0100, 0b011>;
+defm : TLBI<"RPALOS",       0b110, 0b1000, 0b0100, 0b111>;
+defm : TLBI<"PAALLOS",      0b110, 0b1000, 0b0001, 0b100, 0>;
+defm : TLBI<"PAALL",        0b110, 0b1000, 0b0111, 0b100, 0>;
+}
+
 // Armv8.5-A Prediction Restriction by Context instruction options:
 class PRCTX<string name, bits<4> crm> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
   bits<11> Encoding;
   let Encoding{10-4} = 0b0110111;

 let Requires = [{ {AArch64::FeatureSpecRestrict} }] in {
 def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
 }
 
+// v9a Realm Management Extension registers
+let Requires = [{ {AArch64::FeatureRME} }] in {
+def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
+def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
+}
+
 //===----------------------
 // Write-only regs
 //===----------------------
 
 //                                 Op0    Op1     CRn     CRm    Op2
 def : WOSysReg<"DBGDTRTX_EL0",       0b10, 0b011, 0b0000, 0b0101, 0b000>;
 def : WOSysReg<"OSLAR_EL1",          0b10, 0b000, 0b0001, 0b0000, 0b100>;
 def : WOSysReg<"PMSWINC_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b100>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

const FeatureBitset Features;
     {"sve2-aes", {AArch64::FeatureSVE2AES}},
     {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
     {"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
     {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
     {"ls64", {AArch64::FeatureLS64}},
     {"xs", {AArch64::FeatureXS}},
     {"pauth", {AArch64::FeaturePAuth}},
     {"flagm", {AArch64::FeatureFlagM}},
+    {"rme", {AArch64::FeatureRME}},
     // FIXME: Unsupported extensions
     {"lor", {}},
     {"rdma", {}},
     {"profile", {}},
 };
 
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   if (FBS[AArch64::HasV8_1aOps])

llvm/test/MC/AArch64/armv9a-rme.s

+// RUN: not llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -show-encoding %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-arm-none-eabi -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK-NO-RME %s
+// RUN: FileCheck --check-prefix=CHECK-NO-RME-ERROR %s < %t
+
+msr MFAR_EL3, x0
+msr GPCCR_EL3, x0
+msr GPTBR_EL3, x0
+mrs x0, MFAR_EL3
+mrs x0, GPCCR_EL3
+mrs x0, GPTBR_EL3
+// CHECK: msr MFAR_EL3,  x0   // encoding: [0xa0,0x60,0x1e,0xd5]
+// CHECK: msr GPCCR_EL3, x0   // encoding: [0xc0,0x21,0x1e,0xd5]
+// CHECK: msr GPTBR_EL3, x0   // encoding: [0x80,0x21,0x1e,0xd5]
+// CHECK: mrs x0, MFAR_EL3    // encoding: [0xa0,0x60,0x3e,0xd5]
+// CHECK: mrs x0, GPCCR_EL3   // encoding: [0xc0,0x21,0x3e,0xd5]
+// CHECK: mrs x0, GPTBR_EL3   // encoding: [0x80,0x21,0x3e,0xd5]
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+
+tlbi rpaos, x0
+tlbi rpalos, x0
+tlbi paallos
+tlbi paall
+// CHECK: tlbi rpaos, x0      // encoding: [0x60,0x84,0x0e,0xd5]
+// CHECK: tlbi rpalos, x0     // encoding: [0xe0,0x84,0x0e,0xd5]
+// CHECK: tlbi paallos        // encoding: [0x9f,0x81,0x0e,0xd5]
+// CHECK: tlbi paall          // encoding: [0x9f,0x87,0x0e,0xd5]
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI RPAOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI RPALOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI PAALLOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-8]]:6: error: TLBI PAALL requires: rme
+
+tlbi RPAOS
+tlbi RPALOS
+tlbi PAALLOS, x25
+tlbi PAALL, x25
+// CHECK-ERROR: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPAOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPALOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALLOS, x25
+// CHECK-ERROR-NEXT:                       ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALL, x25
+// CHECK-ERROR-NEXT:                    ^
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI RPAOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI RPALOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI PAALLOS requires: rme
+// CHECK-NO-RME-ERROR: [[@LINE-16]]:6: error: TLBI PAALL requires: rme
+
+sys #6, c8, c4, #3
+sys #6, c8, c4, #7
+sys #6, c8, c1, #4
+sys #6, c8, c7, #4
+// CHECK: tlbi rpaos
+// CHECK: tlbi rpalos
+// CHECK: tlbi paallos
+// CHECK: tlbi paall
+// CHECK-NO-RME: sys #6, c8, c4, #3
+// CHECK-NO-RME: sys #6, c8, c4, #7
+// CHECK-NO-RME: sys #6, c8, c1, #4
+// CHECK-NO-RME: sys #6, c8, c7, #4

llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt

+# RUN: llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -disassemble %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-RME %s
+
+[0xa0,0x60,0x3e,0xd5]
+[0xc0,0x21,0x3e,0xd5]
+[0x80,0x21,0x3e,0xd5]
+# CHECK: mrs x0, MFAR_EL3
+# CHECK: mrs x0, GPCCR_EL3
+# CHECK: mrs x0, GPTBR_EL3
+# CHECK-NO-RME: mrs x0, S3_6_C6_C0_5
+# CHECK-NO-RME: mrs x0, S3_6_C2_C1_6
+# CHECK-NO-RME: mrs x0, S3_6_C2_C1_4
+
+[0x60,0x84,0x0e,0xd5]
+[0xe0,0x84,0x0e,0xd5]
+[0x9f,0x81,0x0e,0xd5]
+[0x9f,0x87,0x0e,0xd5]
+# CHECK: tlbi rpaos, x0
+# CHECK: tlbi rpalos, x0
+# CHECK: tlbi paallos
+# CHECK: tlbi paall
+# CHECK-NO-RME: sys #6, c8, c4, #3
+# CHECK-NO-RME: sys #6, c8, c4, #7
+# CHECK-NO-RME: sys #6, c8, c1, #4
+# CHECK-NO-RME: sys #6, c8, c7, #4
 No newline at end of file