[Aarch64] Adding support for Armv9-A Realm Management Extension

[pratlucas]

Summary

This adds support for Armv9-A's Realm Management Extension, including
three new system registers - MFAR_EL3, GPCCR_EL3 and GPTBR_EL3 - and
four new TLBI instructions.

The reference for the Realm Management Extension can be found at: https://developer.arm.com/documentation/ddi0615/aa.

Based on patches by Victor Campos.

[pratlucas]

Adding RME support to release notes.

[pratlucas]

Rebasing.

[dmgreen]

llvm/lib/Target/AArch64/AArch64SystemOperands.td

478

Should these be in a different Requires block, for RME?

751

Is this register writable?

[pratlucas]

Adding subtarget feature to control RME availability.

[pratlucas]

llvm/lib/Target/AArch64/AArch64SystemOperands.td

751

Yes, according to RME's reference this is a writable register.

[dmgreen]

OK Thanks. LGTM then.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

751

Oh yeah, so it does. It doesn't look like there would be much to write to it.

llvm/docs/ReleaseNotes.rst

 
 * The build system now supports building multiple distributions, so that you can
   e.g. have one distribution containing just tools and another for libraries (to
   enable development). See :ref:`Multi-distribution configurations` for details.
 
 Changes to TableGen
 -------------------
 
+Changes to the AArch64 Backend
+--------------------------
+
+* Introduced support for Armv9-A's Realm Management Extension.
+
 Changes to the ARM Backend
 --------------------------
 
 During this release ...
 
 Changes to the MIPS Target
 --------------------------
 

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 defm : TLBI<"ASIDE1",       0b000, 0b1000, 0b0111, 0b010>;
 defm : TLBI<"VAAE1",        0b000, 0b1000, 0b0111, 0b011>;
 defm : TLBI<"ALLE1",        0b100, 0b1000, 0b0111, 0b100, 0>;
 defm : TLBI<"VALE1",        0b000, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VALE2",        0b100, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VALE3",        0b110, 0b1000, 0b0111, 0b101>;
 defm : TLBI<"VMALLS12E1",   0b100, 0b1000, 0b0111, 0b110, 0>;
 defm : TLBI<"VAALE1",       0b000, 0b1000, 0b0111, 0b111>;
+defm : TLBI<"RPAOS",        0b110, 0b1000, 0b0100, 0b011>;
+defm : TLBI<"RPALOS",       0b110, 0b1000, 0b0100, 0b111>;
+defm : TLBI<"PAALLOS",      0b110, 0b1000, 0b0001, 0b100, 0>;
+defm : TLBI<"PAALL",        0b110, 0b1000, 0b0111, 0b100, 0>;
 
 // Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
 let Requires = ["AArch64::FeatureTLB_RMI"] in {
 // Armv8.4-A Outer Sharable TLB Maintenance instructions:
 //                         op1    CRn     CRm     op2
 defm : TLBI<"VMALLE1OS",    0b000, 0b1000, 0b0001, 0b000, 0>;
 defm : TLBI<"VAE1OS",       0b000, 0b1000, 0b0001, 0b001>;
 defm : TLBI<"ASIDE1OS",     0b000, 0b1000, 0b0001, 0b010>;

 let Requires = [{ {AArch64::FeatureSpecRestrict} }] in {
 def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
 }
 
+// v9a Realm Management Extension registers
+def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
+def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
+
 //===----------------------
 // Write-only regs
 //===----------------------
 
 //                                 Op0    Op1     CRn     CRm    Op2
 def : WOSysReg<"DBGDTRTX_EL0",       0b10, 0b011, 0b0000, 0b0101, 0b000>;
 def : WOSysReg<"OSLAR_EL1",          0b10, 0b000, 0b0001, 0b0000, 0b100>;
 def : WOSysReg<"PMSWINC_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b100>;

llvm/test/MC/AArch64/arm64-aliases.s

; CHECK: tlbi ipas2le1
   sys #4, c8, c0, #1
 ; CHECK: tlbi ipas2e1is
   sys #4, c8, c0, #5
 ; CHECK: tlbi ipas2le1is
   sys #4, c8, c7, #6
 ; CHECK: tlbi vmalls12e1
   sys #4, c8, c3, #6
 ; CHECK: tlbi vmalls12e1is
+  sys #6, c8, c4, #3
+; CHECK: tlbi rpaos
+  sys #6, c8, c4, #7
+; CHECK: tlbi rpalos
+  sys #6, c8, c1, #4
+; CHECK: tlbi paallos
+  sys #6, c8, c7, #4
+; CHECK: tlbi paall
 
   ic ialluis
 ; CHECK: ic ialluis                 ; encoding: [0x1f,0x71,0x08,0xd5]
   ic iallu
 ; CHECK: ic iallu                   ; encoding: [0x1f,0x75,0x08,0xd5]
   ic ivau, x0
 ; CHECK: ic ivau, x0                ; encoding: [0x20,0x75,0x0b,0xd5]
 
; CHECK: tlbi ipas2le1, x0          ; encoding: [0xa0,0x84,0x0c,0xd5]
   tlbi ipas2e1is, x0
 ; CHECK: tlbi ipas2e1is, x0         ; encoding: [0x20,0x80,0x0c,0xd5]
   tlbi ipas2le1is, x0
 ; CHECK: tlbi ipas2le1is, x0        ; encoding: [0xa0,0x80,0x0c,0xd5]
   tlbi vmalls12e1
 ; CHECK: tlbi vmalls12e1            ; encoding: [0xdf,0x87,0x0c,0xd5]
   tlbi vmalls12e1is
 ; CHECK: tlbi vmalls12e1is          ; encoding: [0xdf,0x83,0x0c,0xd5]
+  tlbi rpaos, x0
+; CHECK: tlbi rpaos, x0             ; encoding: [0x60,0x84,0x0e,0xd5]
+  tlbi rpalos, x0
+; CHECK: tlbi rpalos, x0            ; encoding: [0xe0,0x84,0x0e,0xd5]
+  tlbi paallos
+; CHECK: tlbi paallos               ; encoding: [0x9f,0x81,0x0e,0xd5]
+  tlbi paall
+; CHECK: tlbi paall                 ; encoding: [0x9f,0x87,0x0e,0xd5]
 
 ;-----------------------------------------------------------------------------
 ; 5.8.5 Vector Arithmetic aliases
 ;-----------------------------------------------------------------------------
 
   cmls.8b v0, v2, v1
   cmls.16b v0, v2, v1
   cmls.4h v0, v2, v1

llvm/test/MC/AArch64/armv9a-rme.s

+# RUN: llvm-mc -triple aarch64-arm-none-eabi -show-encoding %s 2>&1 | FileCheck %s
+
+# CHECK: msr MFAR_EL3,  x0 // encoding: [0xa0,0x60,0x1e,0xd5]
+# CHECK: msr GPCCR_EL3, x0 // encoding: [0xc0,0x21,0x1e,0xd5]
+# CHECK: msr GPTBR_EL3, x0 // encoding: [0x80,0x21,0x1e,0xd5]
+msr MFAR_EL3, x0
+msr GPCCR_EL3, x0
+msr GPTBR_EL3, x0
+
+# CHECK: mrs x0, MFAR_EL3  // encoding: [0xa0,0x60,0x3e,0xd5]
+# CHECK: mrs x0, GPCCR_EL3 // encoding: [0xc0,0x21,0x3e,0xd5]
+# CHECK: mrs x0, GPTBR_EL3 // encoding: [0x80,0x21,0x3e,0xd5]
+mrs x0, MFAR_EL3
+mrs x0, GPCCR_EL3
+mrs x0, GPTBR_EL3

llvm/test/MC/AArch64/basic-a64-diagnostics.s

// CHECK-ERROR-NEXT:            ^
         tlbi ASIDE1
         tlbi VAAE1
         tlbi ALLE1, x25
         tlbi VALE1
         tlbi VALE2
         tlbi VALE3
         tlbi VMALLS12E1, x15
         tlbi VAALE1
+        tlbi RPAOS
+        tlbi RPALOS
+        tlbi PAALLOS, x25
+        tlbi PAALL, x25
 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
 // CHECK-ERROR-NEXT:         tlbi IPAS2E1IS
 // CHECK-ERROR-NEXT:              ^
 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
 // CHECK-ERROR-NEXT:         tlbi IPAS2LE1IS
 // CHECK-ERROR-NEXT:              ^
 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
 // CHECK-ERROR-NEXT:         tlbi VMALLE1IS, x12

 // CHECK-ERROR-NEXT:         tlbi VALE3
 // CHECK-ERROR-NEXT:              ^
 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
 // CHECK-ERROR-NEXT:         tlbi VMALLS12E1, x15
 // CHECK-ERROR-NEXT:                          ^
 // CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
 // CHECK-ERROR-NEXT:         tlbi VAALE1
 // CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPAOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register
+// CHECK-ERROR-NEXT:         tlbi RPALOS
+// CHECK-ERROR-NEXT:              ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALLOS, x25
+// CHECK-ERROR-NEXT:                       ^
+// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register
+// CHECK-ERROR-NEXT:         tlbi PAALL, x25
+// CHECK-ERROR-NEXT:                    ^
 
 // For the MSR/MRS instructions, first make sure read-only and
 // write-only registers actually are.
         msr MDCCSR_EL0, x12
         msr DBGDTRRX_EL0, x12
         msr MDRAR_EL1, x12
         msr OSLSR_EL1, x12
         msr DBGAUTHSTATUS_EL1, x12

llvm/test/MC/AArch64/basic-a64-instructions.s

// CHECK: at      s12e0w, x20             // encoding: [0xf4,0x78,0x0c,0xd5]
         tlbi ASIDE1, x20
         tlbi VAAE1, x21
         tlbi ALLE1
         tlbi VALE1, x22
         tlbi VALE2, x23
         tlbi VALE3, x24
         tlbi VMALLS12E1
         tlbi VAALE1, x25
+        tlbi RPAOS, x0
+        tlbi RPALOS, x0
+        tlbi PAALLOS
+        tlbi PAALL
 // CHECK: tlbi    ipas2e1is, x4           // encoding: [0x24,0x80,0x0c,0xd5]
 // CHECK: tlbi    ipas2le1is, x9          // encoding: [0xa9,0x80,0x0c,0xd5]
 // CHECK: tlbi    vmalle1is               // encoding: [0x1f,0x83,0x08,0xd5]
 // CHECK: tlbi    alle2is                 // encoding: [0x1f,0x83,0x0c,0xd5]
 // CHECK: tlbi    alle3is                 // encoding: [0x1f,0x83,0x0e,0xd5]
 // CHECK: tlbi    vae1is, x1              // encoding: [0x21,0x83,0x08,0xd5]
 // CHECK: tlbi    vae2is, x2              // encoding: [0x22,0x83,0x0c,0xd5]
 // CHECK: tlbi    vae3is, x3              // encoding: [0x23,0x83,0x0e,0xd5]

 // CHECK: tlbi    aside1, x20             // encoding: [0x54,0x87,0x08,0xd5]
 // CHECK: tlbi    vaae1, x21              // encoding: [0x75,0x87,0x08,0xd5]
 // CHECK: tlbi    alle1                   // encoding: [0x9f,0x87,0x0c,0xd5]
 // CHECK: tlbi    vale1, x22              // encoding: [0xb6,0x87,0x08,0xd5]
 // CHECK: tlbi    vale2, x23              // encoding: [0xb7,0x87,0x0c,0xd5]
 // CHECK: tlbi    vale3, x24              // encoding: [0xb8,0x87,0x0e,0xd5]
 // CHECK: tlbi    vmalls12e1              // encoding: [0xdf,0x87,0x0c,0xd5]
 // CHECK: tlbi    vaale1, x25             // encoding: [0xf9,0x87,0x08,0xd5]
+// CHECK: tlbi    rpaos, x0               // encoding: [0x60,0x84,0x0e,0xd5]
+// CHECK: tlbi    rpalos, x0              // encoding: [0xe0,0x84,0x0e,0xd5]
+// CHECK: tlbi    paallos                 // encoding: [0x9f,0x81,0x0e,0xd5]
+// CHECK: tlbi    paall                   // encoding: [0x9f,0x87,0x0e,0xd5]
 
   msr TEECR32_EL1, x12
   msr OSDTRRX_EL1, x12
   msr MDCCINT_EL1, x12
   msr MDSCR_EL1, x12
   msr OSDTRTX_EL1, x12
   msr DBGDTR_EL0, x12
   msr DBGDTRTX_EL0, x12

llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt

+# RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck %s
+
+# CHECK: mrs x0, MFAR_EL3
+# CHECK: mrs x0, GPCCR_EL3
+# CHECK: mrs x0, GPTBR_EL3
+[0xa0,0x60,0x3e,0xd5]
+[0xc0,0x21,0x3e,0xd5]
+[0x80,0x21,0x3e,0xd5]