labrinea (Alexandros Lamprineas)
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User Since
Jun 10 2015, 2:25 AM (158 w, 1 d)

Recent Activity

Today

labrinea added inline comments to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Thu, Jun 21, 1:49 AM

Yesterday

labrinea created D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Wed, Jun 20, 8:27 AM

Wed, Jun 13

labrinea added a comment to D48122: [SimplifyCFG] Hoist common if-then-else code if used by two-entry PHI nodes.

My argument would be that this change is fairly small. To be honest I don't know what is the status of GVN-Hoist. If it is in a good shape, then enabling it is the best way to go. If there are a few bugs to fix I am happy to help, but if it is far from being in a good shape then a workaround like this should be acceptable.

Wed, Jun 13, 8:50 AM
labrinea created D48122: [SimplifyCFG] Hoist common if-then-else code if used by two-entry PHI nodes.
Wed, Jun 13, 6:34 AM

Wed, May 30

labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Bail the optimization if the memory alignment is not power of two. Added a test to cover this case.

Wed, May 30, 5:39 AM

Tue, May 22

labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
  • Restrict the optimization to table lookups returning a <8 x i8> vector type. It's only beneficial for the mask {7,6,5,4,3,2,1,0} anyway.
  • Bail out if the constant mask contains an index out of range. The second argument of the new shufflevector is always going to be <undef> so the range is [0 ~ NumElts-1], not [0 ~ 2*NumElts-1], like @efriedma noticed.
  • Replaced getZExtValue() with getLimitedValue() for getting the value of a ConstantInt.
  • Simplified the retrieval of mask indices by using ConstantDataVector::get instead of ConstantVector::get.
  • Added testcases where the transform bails out.
  • Autogenerated the Filecheck patterns using the script utils/update_test_checks.py
Tue, May 22, 8:27 AM

May 22 2018

labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Using getLimitedValue() instead of getZExtValue() for the ConstantInt representing the memory alignment of the load instruction. Updated the tests: alignment in now expressed in bytes instead of bits.

May 22 2018, 2:49 AM

May 17 2018

labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Ping?

May 17 2018, 1:35 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

Ping?

May 17 2018, 1:35 AM

May 11 2018

labrinea added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Please update your diff file in order to contain all the file content. Thanks.

May 11 2018, 5:32 AM

May 10 2018

labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

@efriedma, ping.

May 10 2018, 3:03 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

@efriedma, ping. Any perf results on this?

May 10 2018, 3:02 AM

May 3 2018

labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Sure! Thanks again for the review :)

May 3 2018, 9:18 AM
labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

I've actually used the utils/update_test_checks.py to auto-generate Filecheck assertions for the unit test. @spatel, this script is very practical but I am bit sceptical about it. We must be very careful when using it. The checks may not impose the desired compiler behaviour when auto-generated.

May 3 2018, 8:12 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

@spatel, how cool! Thanks for pointing that out. I wasn't aware of that script. I'll update my test shortly.

May 3 2018, 7:54 AM
labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Changes to the test file:

  • Made the RUN line redirect the input file to opt.
  • Added a NOTE to enable autogenerated assertions.
May 3 2018, 1:56 AM

May 2 2018

labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.
May 2 2018, 6:33 AM
labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
May 2 2018, 6:14 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

The dynamic cast check for the alignment parameter of the intrinsic is necessary. I could bail the optimization if it's not constant and let the backend crash later on. There are plenty of intrinsics where some arguments need to be constant, but IR has no way to enforce that. Clang will guarantee for it. The rest of the suggestions sound sensible. I'll update my patch accordingly.

May 2 2018, 3:59 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

Good catch. The current patch hits the assertion when handling the llvm.aarch64.neon.tbl1.v16i8 inrinsic, because NumElts is 16. Does it make sense to perform the transformation in this case? I could get rid of the assert and bail the optimization if NumElts neither 8 nor 16 (or just 8).

May 2 2018, 3:59 AM

May 1 2018

labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

I've moved the constant folding to a new revision: https://reviews.llvm.org/D46273. I've also added comments to the tests explaining the reason of this transformation.

May 1 2018, 5:22 AM
labrinea added inline comments to D46273: [InstCombine, ARM] Convert vld1 to llvm load.
May 1 2018, 4:11 AM

Apr 30 2018

labrinea created D46273: [InstCombine, ARM] Convert vld1 to llvm load.
Apr 30 2018, 10:06 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

@efriedma I am going to create a new revision for converting a vld1 into an llvm load. I'll then update this revision to keep only the tbl1~>shufflevector conversion. I'll also make the patch accept any constant mask pattern.

Apr 30 2018, 6:22 AM

Apr 27 2018

labrinea added inline comments to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 27 2018, 1:55 AM

Apr 26 2018

labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

The constant folding of the vld1 intrinsic might worth moving in lib/Analysis/ConstantFolding.cpp as a separate patch, but I wasn't sure whether we always want to fold vld1, even when it's not used as a table lookup mask. I've asked about the matter in llvm-dev.

Apr 26 2018, 9:57 AM
labrinea created D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 26 2018, 9:52 AM

Jun 28 2017

labrinea added a dependency for D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions: D34220: [AArch64] Prefer B.cond to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free".
Jun 28 2017, 1:46 AM
labrinea added a dependent revision for D34220: [AArch64] Prefer B.cond to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free": D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions.
Jun 28 2017, 1:46 AM
labrinea created D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions.
Jun 28 2017, 1:45 AM

Jun 19 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

The Address Sanitizer caught a stack-use-after-scope of a Twine variable. This is now fixed by passing the Twine directly as a function parameter.

Jun 19 2017, 1:19 AM
labrinea reopened D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

I've upset a buildbot which runs the address sanitizer:
ERROR: AddressSanitizer:
stack-use-after-scope lib/Target/ARM/ARMISelLowering.cpp:2690
That Twine variable is used illegally. I am reopening the revision.

Jun 19 2017, 1:17 AM

Jun 14 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

I've renamed the constant pool labels as suggested.

Jun 14 2017, 5:25 AM
labrinea added a comment to D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Actually I was inspired by getPICLabel in ARMAsmPrinter.cpp but I can change it to 'CP' if it makes more sense.

Jun 14 2017, 3:17 AM

Jun 13 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Hi Christof,

Jun 13 2017, 8:29 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

It's unfortunate that we cannot share the globals across basic blocks. However, lowering a constant pool as a global variable guarantees that execute-only plays well with all the position-independent addressing modes out of the box. In order to support those with execute-only we would need to add new instruction patterns and logic to handle them in various places, which might introduce new bugs. I've switched back to the previous approach and added a few more checks to verify the CodeGen with position-independent addressing modes. I've also removed few more unreachable checks that can now be reached with PIC. Christof are you happy with it?

Jun 13 2017, 2:46 AM

Jun 9 2017

labrinea added a comment to D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

If find my original approach in diff1 less ad-hock than the latest one diff5. Lowering a Constant Pool as a Global Variable at the DAG level seems to me more legitimate than printing movw/movt for a LEApcrel machine instruction and then using the generic asm printer for the constant pool itself.

Jun 9 2017, 3:16 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Fixed the way we materialise the address of a constant pool when generating execute-only code. Use movw/movt instead of pc-relative access.

Jun 9 2017, 3:02 AM

Jun 8 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Oops, I forgot to remove the llvm_unreachable() check from ARMISelLowering.

Jun 8 2017, 3:01 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

When generating execute-only code invoke the generic AsmPrinter in order to place the literals in the data section, otherwise handle Constant Pools in EmitInstruction.

Jun 8 2017, 2:40 AM

Jun 6 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Instead of suppressing this particular reproducer, teach the compiler to lower constant pools as global values (literals in the data section) when generating execute-only code.

Jun 6 2017, 6:35 AM

Jun 1 2017

labrinea created D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.
Jun 1 2017, 5:22 AM

Dec 6 2016

labrinea abandoned D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.

Abandoning this on the base that Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values has been abandoned. Apologies and thank you for reviewing this.

Dec 6 2016, 2:26 AM
labrinea abandoned D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.

Hi Renato, apologies for the long silence. Unfortunately this work is more complicated than I initially thought. We'll have to rethink about it thoroughly. I am going to abandon the patch for now. Thank you for reviewing this.

Dec 6 2016, 2:24 AM

Nov 22 2016

labrinea updated the diff for D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.

Added the fallback logic for backwards compatibility.

Nov 22 2016, 8:19 AM
labrinea added a comment to D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.

Your suggestion that if all four options are mutually exclusive, then they should be a single integer option, totally makes sense to me. We could use a single integer option and make the old boolean flags deprecated (i.e. map '-fshort-enums' and 'fno-short enums' to the new integer option). My concern is that we have to be GCC compatible. I will communicate this to the GNU community.

Nov 22 2016, 8:16 AM
labrinea added inline comments to D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 6:29 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:52 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:52 AM
labrinea updated D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:50 AM
labrinea updated D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:50 AM
labrinea retitled D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values from to [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:47 AM
labrinea retitled D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values from [ARM] Add Driver support for emmitting the missing Tag_ABI_enum_size build attribute values to [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:46 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:41 AM
labrinea retitled D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values from to [ARM] Add Driver support for emmitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:40 AM

Nov 8 2016

labrinea added a comment to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

Ping @efriedma

Nov 8 2016, 1:44 AM

Nov 3 2016

labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 3 2016, 3:37 AM
labrinea retitled D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb. from [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb if the LLVM-IR is not in LCSSA form. to [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 3 2016, 3:35 AM

Nov 2 2016

labrinea added inline comments to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 2 2016, 1:59 AM

Nov 1 2016

labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

Accidentally uploaded a diff with too few context. Uploaded again.

Nov 1 2016, 11:07 AM
labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

An Affine AddRec always has a Step which is invariant. This is the right thing to check instead of the Step itself.

Nov 1 2016, 11:04 AM
labrinea added a comment to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

The test I have added is a reproducer that triggers the assertion in the absence of these checks. What would be a proper fix if these checks are useless?

Nov 1 2016, 10:18 AM
labrinea retitled D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb. from to [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb if the LLVM-IR is not in LCSSA form..
Nov 1 2016, 6:48 AM

Oct 10 2016

labrinea added a comment to D25281: [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON.

Committed as r283763.

Oct 10 2016, 9:38 AM
labrinea closed D25281: [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON.
Oct 10 2016, 9:37 AM
labrinea updated the diff for D25281: [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON.

Added a new codegen test for <2 x double> load/store as suggested.

Oct 10 2016, 6:42 AM

Oct 7 2016

labrinea added a comment to D18086: Fix default processor name for armv6k..

@LordHoto can you be more specific when saying that invalid instructions are generated when targeting armv6k? I am afraid that using the same cpu-name as the key for two different entries of the table is a wrong approach.

Oct 7 2016, 7:17 AM

Oct 5 2016

labrinea retitled D25281: [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON from to [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON.
Oct 5 2016, 7:45 AM

Jan 28 2016

labrinea added inline comments to D16684: [ARM] Emit trap instruction using .inst directive.
Jan 28 2016, 7:25 AM
labrinea retitled D16684: [ARM] Emit trap instruction using .inst directive from to [ARM] Emit trap instruction using .inst directive.
Jan 28 2016, 7:21 AM

Jan 4 2016

labrinea updated the diff for D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..

Disabled optimizers.

Jan 4 2016, 6:37 AM

Dec 14 2015

labrinea added a comment to D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..

Hi Eric,

Dec 14 2015, 9:14 AM

Dec 8 2015

labrinea added inline comments to D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..
Dec 8 2015, 3:14 AM

Dec 7 2015

labrinea updated the diff for D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..

ASM tests have been removed.

Dec 7 2015, 2:00 AM

Dec 4 2015

labrinea updated D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..
Dec 4 2015, 5:52 AM
labrinea retitled D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics. from to [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics..
Dec 4 2015, 2:38 AM

Nov 27 2015

labrinea updated the diff for D14982: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract..

@t.p.northover you were right, my patch was missing predefined guard macros for the instrinsics. I've now updated the patch.

Nov 27 2015, 10:11 AM

Nov 25 2015

labrinea updated D14982: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract..
Nov 25 2015, 5:04 AM
labrinea retitled D14982: ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract. from to ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract..
Nov 25 2015, 4:28 AM

Nov 5 2015

labrinea retitled D14384: [ARM] Clang gives unintended warning message for 'mthumb' + M-profiles from to [ARM] Clang gives unintended warning message for 'mthumb' + M-profiles.
Nov 5 2015, 8:57 AM

Oct 28 2015

labrinea updated the diff for D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.

I think the patch is now in it's final shape:

  • kept TY_PP_Asm check
  • added darwin and armv7m in checks in tests
  • cached IsMProfile
  • used ARM::parseArchVersion
Oct 28 2015, 1:25 AM

Oct 27 2015

labrinea added a comment to D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.

If you're on Linux or something you need "clang -target x86_64-apple-darwin -arch armv7 -c tmp.s". Another mess I keep meaning to fix.

I suspect the reason for this hack is that we've already changed the triple to "thumbv7-apple-iosN" by this point (because -arch armv7 compiles to Thumb), so it needs undoing for .s files. It might be reasonably easy to push the TY_PP_Asm check back into the Darwin codepath, or it might be horrible. So much has changed since 2011.

Oct 27 2015, 11:08 AM
labrinea added a comment to D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.

Is this revision valid after all? I am confused by Tim's comment. I did not see any regressions locally.

Oct 27 2015, 10:48 AM
labrinea added a comment to D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.

It seems I missed your comments before updating the patch.
@t.p.northover: What is the exact command? "clang -arch armv7 -c tmp.s" didn't work for me.

Oct 27 2015, 10:39 AM
labrinea updated the diff for D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.
Oct 27 2015, 10:31 AM
labrinea added inline comments to D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.
Oct 27 2015, 9:40 AM
labrinea updated subscribers of D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.
Oct 27 2015, 9:39 AM
labrinea updated the diff for D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as.
Oct 27 2015, 9:22 AM
labrinea retitled D14121: Thumb state not being passed through to LLVM triple when using clang -cc1as from to Thumb state not being passed through to LLVM triple when using clang -cc1as.
Oct 27 2015, 8:20 AM

Oct 9 2015

labrinea closed D11590: Arch extensions and default target features in TargetParser.

committed as r246930

Oct 9 2015, 3:55 AM
labrinea closed D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets.

committed as r246768

Oct 9 2015, 3:52 AM
labrinea abandoned D10357: SROA produces miscompiled code for bitfield access on big-endian targets.
Oct 9 2015, 3:42 AM
labrinea closed D12692: LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.

committed as r247136

Oct 9 2015, 3:41 AM

Oct 5 2015

labrinea updated the diff for D13011: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm".

AArch64DAGToDAGISel::SelectWriteRegister updated.

Oct 5 2015, 4:07 AM
labrinea added inline comments to D13011: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm".
Oct 5 2015, 3:34 AM
labrinea added inline comments to D13011: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm".
Oct 5 2015, 3:07 AM

Oct 4 2015

labrinea added inline comments to D13217: [ARM] The Driver does not set the +strict-align flag when targeting armv6m + netbsd.
Oct 4 2015, 12:51 PM
labrinea added inline comments to D13011: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm".
Oct 4 2015, 12:35 PM

Oct 2 2015

labrinea added inline comments to D13217: [ARM] The Driver does not set the +strict-align flag when targeting armv6m + netbsd.
Oct 2 2015, 7:20 PM
labrinea updated the diff for D13011: [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for "msr pan, #imm".

Reimplemented via a generic instruction definition that allows all encoding values and then assembly aliases that have more restricted operand sets.

Oct 2 2015, 4:47 AM