labrinea (Alexandros Lamprineas)
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Jun 10 2015, 2:25 AM (166 w, 6 d)

Recent Activity

Fri, Aug 10

labrinea added inline comments to D50323: [GVNHoist] Prune out useless CHI insertions.
Fri, Aug 10, 5:42 AM
labrinea added inline comments to D50323: [GVNHoist] Prune out useless CHI insertions.
Fri, Aug 10, 5:30 AM

Thu, Aug 9

labrinea added a comment to D50323: [GVNHoist] Prune out useless CHI insertions.

So, is everyone happy with this change?

Thu, Aug 9, 1:36 AM

Tue, Aug 7

labrinea added inline comments to D50323: [GVNHoist] Prune out useless CHI insertions.
Tue, Aug 7, 3:07 AM

Mon, Aug 6

labrinea added inline comments to D50323: [GVNHoist] Prune out useless CHI insertions.
Mon, Aug 6, 6:28 AM
labrinea planned changes to D49858: [RFC] re-enable GVNHoist by default.
Mon, Aug 6, 3:11 AM
labrinea reopened D49858: [RFC] re-enable GVNHoist by default.

This got reverted because of an out-of-memory error on an ubsan buildbot. Details and fix here -> https://reviews.llvm.org/D50323. I'll update the tests upon rebase.

Mon, Aug 6, 3:10 AM
labrinea created D50323: [GVNHoist] Prune out useless CHI insertions.
Mon, Aug 6, 1:46 AM

Mon, Jul 30

labrinea added a comment to D49858: [RFC] re-enable GVNHoist by default.

Did you test it with some benchmarks? Results?

I am running lnt, spec2000 and spec2006 on AArch64 at the moment. I'll post results soon.

Mon, Jul 30, 3:14 AM

Thu, Jul 26

labrinea created D49858: [RFC] re-enable GVNHoist by default.
Thu, Jul 26, 8:30 AM

Mon, Jul 23

labrinea added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Mon, Jul 23, 7:38 AM
labrinea added a reviewer for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value: labrinea.
Mon, Jul 23, 7:11 AM
labrinea added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Mon, Jul 23, 7:10 AM

Jul 20 2018

labrinea updated the diff for D49425: [MemorySSAUpdater] Update Phi operands after trivial Phi elimination.

Changes to prior revision.

  • Removed the update loop for PhiOps and used TrackingVH<MemoryAccess> instead.
  • Replaced the Bitcode reproducer with IR using -preserve-ll-uselistorder.
Jul 20 2018, 3:59 AM

Jul 19 2018

labrinea added a comment to D49425: [MemorySSAUpdater] Update Phi operands after trivial Phi elimination.

If the bitcode is crashing but the textual IR isn't, you're probably getting bitten by use-list ordering. You can use the preserve-ll-uselistorder option for "opt" to preserve it in IR.

Jul 19 2018, 9:46 AM
labrinea created D49555: [GVNHoist] safeToHoistLdSt incorrectly checks whether a defining access dominates the insertion point.
Jul 19 2018, 9:40 AM

Jul 18 2018

labrinea added a comment to D49425: [MemorySSAUpdater] Update Phi operands after trivial Phi elimination.

Does the original test-case crash reliably as IR for you? If so, please use that instead. (Phab won't let me download the attached bitcode, but with asan, I see use-after-free crashes 100% of the time in the original repro).

It does, but using opt -S -O3 ./tc_memphi_gvnhoist.ll -enable-gvn-hoist. Using bugpoint on that command you get the bitcode I uploaded.

Jul 18 2018, 3:05 AM

Jul 17 2018

labrinea added a comment to D49425: [MemorySSAUpdater] Update Phi operands after trivial Phi elimination.

A few remarks:

  • SmallVector<WeakVH, 8> PhiOps fixes the bug on its own (without the rest changes) and I am wondering why..
  • When we mark a block as visited why do we cache it? When the recursion ends we might trivially remove the Phi. In that case the second cache insertion for the same key block should fail, no?
  • Do we ever reach the PHIExistsButNeedsUpdate case? Is it when a Phi existed beforehand, meaning we did not create it? I can't think of another way to reach that state.
  • Interestingly enough the reproducer only made opt crash in bitcode form and not in IR form.
Jul 17 2018, 7:16 AM
labrinea created D49425: [MemorySSAUpdater] Update Phi operands after trivial Phi elimination.
Jul 17 2018, 7:08 AM

Jul 13 2018

labrinea updated the diff for D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.

Ok, I've convinced myself that using WeakVH is the most straightforward fix for now. We shouldn't be spending more time on this.

Jul 13 2018, 5:04 AM

Jul 12 2018

labrinea added a comment to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.

Replacing MemoryPhi * with WeakVH won't work out of the box; it requires typecasts and null checks upon iteration. It also adds and additional overhead (similar to AssertingVH though). In general, the idea of keeping null references in the ADT instead of actually deleting them seems like a workaround to me. I don't see why we should be afraid of making non trivial changes in the code if there's a fundamental bug. On that note I still believe the line 303 of the original revision is wrong since we push_back() when adding new elements:

FixupList.append(InsertedPHIs.end() - StartingPHISize, InsertedPHIs.end());

Shouldn't it be like this?

FixupList.append(InsertedPHIs.begin() + StartingPHISize, InsertedPHIs.end());

Answering some inline comments:

Jul 12 2018, 10:23 AM

Jul 10 2018

labrinea updated the diff for D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.

Changes to the prior revision:

  • I've used std::set for InsertedPHIs to avoid linear cost lookups upon deletion.
  • I've refactored insertDef() so that it no longer relies on insertion order iteration over InsertedPHIs.
Jul 10 2018, 10:41 AM
labrinea added a comment to D49030: Add OrderedSet, with constant-time insertion and removal, and random access iteration..

Personally, I'd be in favour of changing MapVector to just do this, since it already has an index. I'd also be in favour of adding an index to SetVector to match. There'd be some work to do in auditing/updating users, but I doubt there are many calls to erase() and I'm skeptical that anyone relies on the current order for something other than determinism.

I think we should not change MapVector. Its underlying data structure is a vector with <key,value> pairs but we only need to store a single value. Moreover, both MapVector and SetVector provide insertion order iteration and their users might rely on that. I am not sure we should change that. SmallSet might be a good alternative for lower insertion/deletion complexity, but at the moment it does not provide iteration over the underlying data structures. It uses a SmallVector for small data sets and expands it to an std::set if it grows too much. Is there a way to abstract those underlying iterators? If not I think we should keep this new ADT and rename/document it properly.

Jul 10 2018, 2:18 AM

Jul 8 2018

labrinea added inline comments to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jul 8 2018, 4:07 PM

Jul 7 2018

labrinea added a comment to D49030: Add OrderedSet, with constant-time insertion and removal, and random access iteration..

We already have SetVector which is widely used for these patterns. If we need both, we need a clear explanation of the difference and why we need both (IE, why users of one can't use the other).

The remove operation on a SetVector can cost linear time and this might be an issue in some cases. Please have a look at the review comments of https://reviews.llvm.org/D48372

Jul 7 2018, 6:32 AM

Jul 6 2018

labrinea updated the diff for D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.

Added back the header file for SmallPtrSet that was accidentally removed.

Jul 6 2018, 9:32 AM
labrinea updated the diff for D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.

Used the ADT from https://reviews.llvm.org/D49030

Jul 6 2018, 9:28 AM
labrinea added a dependent revision for D49030: Add OrderedSet, with constant-time insertion and removal, and random access iteration.: D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jul 6 2018, 8:59 AM
labrinea added a dependency for D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset: D49030: Add OrderedSet, with constant-time insertion and removal, and random access iteration..
Jul 6 2018, 8:59 AM
labrinea added a comment to D48504: [WIP] Add InsertionOrderSet, with constant-time insertion and removal..

I've accidentally edited the revision instead of just adding a new diff. Anyway, I've reset it to the original content and created https://reviews.llvm.org/D49030 with my changes for review.

Jul 6 2018, 8:54 AM
labrinea retitled D48504: [WIP] Add InsertionOrderSet, with constant-time insertion and removal. from Add OrderedSet, with constant-time insertion and removal, and random access iteration. to [WIP] Add InsertionOrderSet, with constant-time insertion and removal..
Jul 6 2018, 8:51 AM
labrinea created D49030: Add OrderedSet, with constant-time insertion and removal, and random access iteration..
Jul 6 2018, 8:44 AM
labrinea retitled D48504: [WIP] Add InsertionOrderSet, with constant-time insertion and removal. from [WIP] Add InsertionOrderSet, with constant-time insertion and removal. to Add OrderedSet, with constant-time insertion and removal, and random access iteration..
Jul 6 2018, 8:41 AM

Jun 26 2018

labrinea added a comment to D48504: [WIP] Add InsertionOrderSet, with constant-time insertion and removal..

Another thing to consider maybe is the complexity of iteration over the vector. Imagine the case where we insert N elements and we erase M with M being almost the size of N. The iteration will be O(N) and not O(N-M).

Jun 26 2018, 2:48 AM

Jun 25 2018

labrinea added a comment to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jun 25 2018, 3:39 AM
labrinea added inline comments to D48504: [WIP] Add InsertionOrderSet, with constant-time insertion and removal..
Jun 25 2018, 3:27 AM

Jun 22 2018

labrinea added inline comments to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jun 22 2018, 6:40 AM

Jun 21 2018

labrinea added inline comments to D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jun 21 2018, 1:49 AM

Jun 20 2018

labrinea created D48372: [MemorySSAUpdater] Remove deleted trivial Phis from active workset.
Jun 20 2018, 8:27 AM

Jun 13 2018

labrinea added a comment to D48122: [SimplifyCFG] Hoist common if-then-else code if used by two-entry PHI nodes.

My argument would be that this change is fairly small. To be honest I don't know what is the status of GVN-Hoist. If it is in a good shape, then enabling it is the best way to go. If there are a few bugs to fix I am happy to help, but if it is far from being in a good shape then a workaround like this should be acceptable.

Jun 13 2018, 8:50 AM
labrinea created D48122: [SimplifyCFG] Hoist common if-then-else code if used by two-entry PHI nodes.
Jun 13 2018, 6:34 AM

May 30 2018

labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Bail the optimization if the memory alignment is not power of two. Added a test to cover this case.

May 30 2018, 5:39 AM

May 22 2018

labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
  • Restrict the optimization to table lookups returning a <8 x i8> vector type. It's only beneficial for the mask {7,6,5,4,3,2,1,0} anyway.
  • Bail out if the constant mask contains an index out of range. The second argument of the new shufflevector is always going to be <undef> so the range is [0 ~ NumElts-1], not [0 ~ 2*NumElts-1], like @efriedma noticed.
  • Replaced getZExtValue() with getLimitedValue() for getting the value of a ConstantInt.
  • Simplified the retrieval of mask indices by using ConstantDataVector::get instead of ConstantVector::get.
  • Added testcases where the transform bails out.
  • Autogenerated the Filecheck patterns using the script utils/update_test_checks.py
May 22 2018, 8:27 AM
labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Using getLimitedValue() instead of getZExtValue() for the ConstantInt representing the memory alignment of the load instruction. Updated the tests: alignment in now expressed in bytes instead of bits.

May 22 2018, 2:49 AM

May 17 2018

labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Ping?

May 17 2018, 1:35 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

Ping?

May 17 2018, 1:35 AM

May 11 2018

labrinea added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Please update your diff file in order to contain all the file content. Thanks.

May 11 2018, 5:32 AM

May 10 2018

labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

@efriedma, ping.

May 10 2018, 3:03 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

@efriedma, ping. Any perf results on this?

May 10 2018, 3:02 AM

May 3 2018

labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Sure! Thanks again for the review :)

May 3 2018, 9:18 AM
labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

I've actually used the utils/update_test_checks.py to auto-generate Filecheck assertions for the unit test. @spatel, this script is very practical but I am bit sceptical about it. We must be very careful when using it. The checks may not impose the desired compiler behaviour when auto-generated.

May 3 2018, 8:12 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

@spatel, how cool! Thanks for pointing that out. I wasn't aware of that script. I'll update my test shortly.

May 3 2018, 7:54 AM
labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.

Changes to the test file:

  • Made the RUN line redirect the input file to opt.
  • Added a NOTE to enable autogenerated assertions.
May 3 2018, 1:56 AM

May 2 2018

labrinea updated the diff for D46273: [InstCombine, ARM] Convert vld1 to llvm load.
May 2 2018, 6:33 AM
labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
May 2 2018, 6:14 AM
labrinea added a comment to D46273: [InstCombine, ARM] Convert vld1 to llvm load.

The dynamic cast check for the alignment parameter of the intrinsic is necessary. I could bail the optimization if it's not constant and let the backend crash later on. There are plenty of intrinsics where some arguments need to be constant, but IR has no way to enforce that. Clang will guarantee for it. The rest of the suggestions sound sensible. I'll update my patch accordingly.

May 2 2018, 3:59 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

Good catch. The current patch hits the assertion when handling the llvm.aarch64.neon.tbl1.v16i8 inrinsic, because NumElts is 16. Does it make sense to perform the transformation in this case? I could get rid of the assert and bail the optimization if NumElts neither 8 nor 16 (or just 8).

May 2 2018, 3:59 AM

May 1 2018

labrinea updated the diff for D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

I've moved the constant folding to a new revision: https://reviews.llvm.org/D46273. I've also added comments to the tests explaining the reason of this transformation.

May 1 2018, 5:22 AM
labrinea added inline comments to D46273: [InstCombine, ARM] Convert vld1 to llvm load.
May 1 2018, 4:11 AM

Apr 30 2018

labrinea created D46273: [InstCombine, ARM] Convert vld1 to llvm load.
Apr 30 2018, 10:06 AM
labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

@efriedma I am going to create a new revision for converting a vld1 into an llvm load. I'll then update this revision to keep only the tbl1~>shufflevector conversion. I'll also make the patch accept any constant mask pattern.

Apr 30 2018, 6:22 AM

Apr 27 2018

labrinea added inline comments to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 27 2018, 1:55 AM

Apr 26 2018

labrinea added a comment to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.

The constant folding of the vld1 intrinsic might worth moving in lib/Analysis/ConstantFolding.cpp as a separate patch, but I wasn't sure whether we always want to fold vld1, even when it's not used as a table lookup mask. I've asked about the matter in llvm-dev.

Apr 26 2018, 9:57 AM
labrinea created D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 26 2018, 9:52 AM

Jun 28 2017

labrinea added a dependency for D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions: D34220: [AArch64] Prefer B.cond to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free".
Jun 28 2017, 1:46 AM
labrinea added a dependent revision for D34220: [AArch64] Prefer B.cond to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free": D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions.
Jun 28 2017, 1:46 AM
labrinea created D34743: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions.
Jun 28 2017, 1:45 AM

Jun 19 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

The Address Sanitizer caught a stack-use-after-scope of a Twine variable. This is now fixed by passing the Twine directly as a function parameter.

Jun 19 2017, 1:19 AM
labrinea reopened D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

I've upset a buildbot which runs the address sanitizer:
ERROR: AddressSanitizer:
stack-use-after-scope lib/Target/ARM/ARMISelLowering.cpp:2690
That Twine variable is used illegally. I am reopening the revision.

Jun 19 2017, 1:17 AM

Jun 14 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

I've renamed the constant pool labels as suggested.

Jun 14 2017, 5:25 AM
labrinea added a comment to D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Actually I was inspired by getPICLabel in ARMAsmPrinter.cpp but I can change it to 'CP' if it makes more sense.

Jun 14 2017, 3:17 AM

Jun 13 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Hi Christof,

Jun 13 2017, 8:29 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

It's unfortunate that we cannot share the globals across basic blocks. However, lowering a constant pool as a global variable guarantees that execute-only plays well with all the position-independent addressing modes out of the box. In order to support those with execute-only we would need to add new instruction patterns and logic to handle them in various places, which might introduce new bugs. I've switched back to the previous approach and added a few more checks to verify the CodeGen with position-independent addressing modes. I've also removed few more unreachable checks that can now be reached with PIC. Christof are you happy with it?

Jun 13 2017, 2:46 AM

Jun 9 2017

labrinea added a comment to D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

If find my original approach in diff1 less ad-hock than the latest one diff5. Lowering a Constant Pool as a Global Variable at the DAG level seems to me more legitimate than printing movw/movt for a LEApcrel machine instruction and then using the generic asm printer for the constant pool itself.

Jun 9 2017, 3:16 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Fixed the way we materialise the address of a constant pool when generating execute-only code. Use movw/movt instead of pc-relative access.

Jun 9 2017, 3:02 AM

Jun 8 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Oops, I forgot to remove the llvm_unreachable() check from ARMISelLowering.

Jun 8 2017, 3:01 AM
labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

When generating execute-only code invoke the generic AsmPrinter in order to place the literals in the data section, otherwise handle Constant Pools in EmitInstruction.

Jun 8 2017, 2:40 AM

Jun 6 2017

labrinea updated the diff for D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.

Instead of suppressing this particular reproducer, teach the compiler to lower constant pools as global values (literals in the data section) when generating execute-only code.

Jun 6 2017, 6:35 AM

Jun 1 2017

labrinea created D33773: [ARM] llc -arm-execute-only with floating point runs into UNREACHABLE.
Jun 1 2017, 5:22 AM

Dec 6 2016

labrinea abandoned D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.

Abandoning this on the base that Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values has been abandoned. Apologies and thank you for reviewing this.

Dec 6 2016, 2:26 AM
labrinea abandoned D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.

Hi Renato, apologies for the long silence. Unfortunately this work is more complicated than I initially thought. We'll have to rethink about it thoroughly. I am going to abandon the patch for now. Thank you for reviewing this.

Dec 6 2016, 2:24 AM

Nov 22 2016

labrinea updated the diff for D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.

Added the fallback logic for backwards compatibility.

Nov 22 2016, 8:19 AM
labrinea added a comment to D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.

Your suggestion that if all four options are mutually exclusive, then they should be a single integer option, totally makes sense to me. We could use a single integer option and make the old boolean flags deprecated (i.e. map '-fshort-enums' and 'fno-short enums' to the new integer option). My concern is that we have to be GCC compatible. I will communicate this to the GNU community.

Nov 22 2016, 8:16 AM
labrinea added inline comments to D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 6:29 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:52 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:52 AM
labrinea updated D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:50 AM
labrinea updated D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:50 AM
labrinea retitled D26969: [ARM] Emit the missing Tag_ABI_enum_size build attribute values from to [ARM] Emit the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:47 AM
labrinea retitled D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values from [ARM] Add Driver support for emmitting the missing Tag_ABI_enum_size build attribute values to [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:46 AM
labrinea updated D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:41 AM
labrinea retitled D26968: [ARM] Add Driver support for emitting the missing Tag_ABI_enum_size build attribute values from to [ARM] Add Driver support for emmitting the missing Tag_ABI_enum_size build attribute values.
Nov 22 2016, 5:40 AM

Nov 8 2016

labrinea added a comment to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

Ping @efriedma

Nov 8 2016, 1:44 AM

Nov 3 2016

labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 3 2016, 3:37 AM
labrinea retitled D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb. from [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb if the LLVM-IR is not in LCSSA form. to [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 3 2016, 3:35 AM

Nov 2 2016

labrinea added inline comments to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..
Nov 2 2016, 1:59 AM

Nov 1 2016

labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

Accidentally uploaded a diff with too few context. Uploaded again.

Nov 1 2016, 11:07 AM
labrinea updated the diff for D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

An Affine AddRec always has a Step which is invariant. This is the right thing to check instead of the Step itself.

Nov 1 2016, 11:04 AM
labrinea added a comment to D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb..

The test I have added is a reproducer that triggers the assertion in the absence of these checks. What would be a proper fix if these checks are useless?

Nov 1 2016, 10:18 AM
labrinea retitled D26185: [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb. from to [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb if the LLVM-IR is not in LCSSA form..
Nov 1 2016, 6:48 AM