[RISCV] [2/2] Add intrinsic for Zbr extension

[LevyHsu]

Summary

Implementation for RISC-V Zbr extension intrinsics.

Head files are included in the second patch in case the name needs to be changed

RV32 / 64:

crc32b
crc32h
crc32w
crc32cb
crc32ch
crc32cw

RV64 Only:

crc32d
crc32cd

[craig.topper]

Please note I asked that this patch be separate from D99009 because the rvintrin.h file name may not be the final filename we want to use. This https://github.com/riscv/riscv-c-api-doc/pull/14 suggests it should be riscv_intrinsic.h. So I wanted to separate any discussion about how it should be exposed to the user from the implementation of the IR intrinsics and clang builtins.

[LevyHsu]

1. Format fix
2. rvintrin.c is moved to the second part of the pach

[LevyHsu]

in clang/test/Headers/rvintrin.c
RUN: -target-feature +experimental-zbr %s

[craig.topper]

clang/lib/Headers/riscv_zbr_intrin.h

9 ↗

(On Diff #333219)

Please add

#ifndef __RVINTRIN_H                                                                                                                                                                                                                                                              
#error "Never use <riscv_zbr_intrin.h> directly; include <rvintrin.h> instead."
#endif

This file doesn't work if you include it by itself because it references int_xlen_t and __DEFAULT_FN_ATTRS which aren't defined in this file.

[LevyHsu]

1. clang/lib/Headers/riscv_zbr_intrin.h
   • Fix coding style issues
   • Added error messages to alert user not include this headfile directly.
2. clang/lib/Headers/rvintrin.h
   • Fix coding style issues.

clang/include/clang/Basic/BuiltinsRISCV.def

 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+// zbr extension
+TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/DiagnosticSemaKinds.td

   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
 
-// RISC-V V-extension
-def err_riscvv_builtin_requires_v : Error<
-   "builtin requires 'V' extension support to be enabled">;
+// RISC-V experimental extension
+def err_riscv_builtin_requires_extension : Error<
+  "builtin requires %0 extension support to be enabled">;
 } // end of sema component.

clang/lib/CodeGen/CGBuiltin.cpp

   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+  // Zbr
+  case RISCV::BI__builtin_riscv_crc32_b:
+    ID = Intrinsic::riscv_crc32_b;  
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_h:
+    ID = Intrinsic::riscv_crc32_h;  
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_w:
+    ID = Intrinsic::riscv_crc32_w;  
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_b:
+    ID = Intrinsic::riscv_crc32c_b; 
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_h:
+    ID = Intrinsic::riscv_crc32c_h; 
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_w:
+    ID = Intrinsic::riscv_crc32c_w; 
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_d:
+    ID = Intrinsic::riscv_crc32_d;  
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_d:
+    ID = Intrinsic::riscv_crc32c_d; 
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  default: {
+    llvm_unreachable("unexpected builtin ID");
+    return nullptr;
+   } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);

clang/lib/Sema/SemaChecking.cpp

   // CodeGenFunction can also detect this, but this gives a better error
   // message.
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  if (Features.find("experimental-v") != StringRef::npos &&
-      !TI.hasFeature("experimental-v"))
-    return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
-           << TheCall->getSourceRange();
+  
+  if (!TI.hasFeature(Features))
+  {
+    Features.consume_front("experimental-");
+    return Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+           << TheCall->getSourceRange()
+           << Features;
+  }
+
 
   return false;
 }

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBR
+
+#include <rvintrin.h>
+
+// RV32ZBR-LABEL: @crc32b(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32b(long a)
+{
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32h(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32h(long a)
+{
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32w(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32w(long a)
+{
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV32ZBR-LABEL: @crc32cb(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32cb(long a)
+{
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32ch(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32ch(long a)
+{
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32cw(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32cw(long a)
+{
+  return __builtin_riscv_crc32c_w(a);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBR
+
+#include <rvintrin.h>
+
+// RV64ZBR-LABEL: @crc32b(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.b.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32b(long a)
+{
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32h(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.h.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32h(long a)
+{
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32w(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.w.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32w(long a)
+{
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32cb(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.b.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cb(long a)
+{
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32ch(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.h.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32ch(long a)
+{
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32cw(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.w.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cw(long a)
+{
+  return __builtin_riscv_crc32c_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32d(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.d.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32d(long a)
+{
+  return __builtin_riscv_crc32_d(a);
+}
+
+// RV64ZBR-LABEL: @crc32cd(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.d.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cd(long a)
+{
+  return __builtin_riscv_crc32c_d(a);
+}

clang/test/Headers/rvintrin.c

+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only \
+// RUN:   -target-feature +experimental-v %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only \
+// RUN:   -target-feature +experimental-v %s
+// expected-no-diagnostics
+
+#include <rvintrin.h>

llvm/include/llvm/IR/IntrinsicsRISCV.td

 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbr extension part
+
+let TargetPrefix = "riscv" in {
+  
+    class BitMan_GPR_Intrinsics
+        : Intrinsic<[llvm_any_ty],[llvm_any_ty],
+                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+  
+    def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
 //===----------------------------------------------------------------------===//
 // Atomics
 

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 /// Generic pattern classes
 
+class PatGpr<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

                    (SRLIWPat GPR:$rs1, (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbr] in {
+def : PatGpr<int_riscv_crc32_b,CRC32B>;
+def : PatGpr<int_riscv_crc32_h,CRC32H>;
+def : PatGpr<int_riscv_crc32_w,CRC32W>;
+def : PatGpr<int_riscv_crc32c_b,CRC32CB>;
+def : PatGpr<int_riscv_crc32c_h,CRC32CH>;
+def : PatGpr<int_riscv_crc32c_w,CRC32CW>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+def : PatGpr<int_riscv_crc32_d,CRC32D>;
+def : PatGpr<int_riscv_crc32c_d,CRC32CD>;
+} // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32Zbr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.b.i32(i32)
+
+define i32 @crc32cb(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cb:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.h.i32(i32)
+
+define i32 @crc32ch(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32ch:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.w.i32(i32)
+
+define i32 @crc32cw(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cw:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.w.i32(i32 %a)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64Zbr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}