[RISCV] Add Zba feature and move add.uw and slli.uw to it.

[craig.topper]

Summary

Still need to add SH*ADD instructions.

[frasercrmck]

LGTM

[craig.topper]

Rebase

[asb]

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

60–61

Nit: clang-format's suggested reformatting seems sensible here

[craig.topper]

clang-format

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

 //===--- RISCV.cpp - RISCV Helpers for Tools --------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
static StringRef getExtensionType(StringRef Ext) {
   if (Ext.startswith("z"))
     return "z";
   return StringRef();
 }
 
 // If the extension is supported as experimental, return the version of that
 // extension that the compiler currently supports.
 static Optional<RISCVExtensionVersion>
 isExperimentalExtension(StringRef Ext) {
-  if (Ext == "b" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" ||
-      Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
-      Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+  if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
+      Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
+      Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
     return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
     return RISCVExtensionVersion{"0", "9"};
   if (Ext == "zfh")
     return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 

clang/test/Driver/riscv-arch.c

 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
 // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
 // RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p92zbp0p92', multi-character extensions must be separated by underscores
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izba0p92 -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
+// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
 // RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOVERS %s
 // RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<(all_of FeatureStdExtC),
                            "'C' (Compressed Instructions)">;
 
+def FeatureExtZba
+    : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
+                       "'Zba' (Base 'B' Instructions)">;
+def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
+                             AssemblerPredicate<(all_of FeatureExtZba),
+                             "'Zba' (Address calculation 'B' Instructions)">;
+
 def FeatureExtZbb
     : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
                        "'Zbb' (Base 'B' Instructions)">;
 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
                              AssemblerPredicate<(all_of FeatureExtZbb),
                              "'Zbb' (Base 'B' Instructions)">;
 
 def FeatureExtZbc
: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
                        "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
                            AssemblerPredicate<(all_of FeatureExtZbproposedc),
                            "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 
 def FeatureStdExtB
     : SubtargetFeature<"experimental-b", "HasStdExtB", "true",
                        "'B' (Bit Manipulation Instructions)",
-                       [FeatureExtZbb,
+                       [FeatureExtZba,
+                        FeatureExtZbb,
                         FeatureExtZbc,
                         FeatureExtZbe,
                         FeatureExtZbf,
                         FeatureExtZbm,
                         FeatureExtZbp,
                         FeatureExtZbr,
                         FeatureExtZbs,
                         FeatureExtZbt]>;

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 let Predicates = [HasStdExtZbf] in
 def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
 
 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
 def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZba, IsRV64] in {
 def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
 def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def SLOW   : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>;
 def SROW   : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
def : Pat<(or (or (and (shl GPR:$rs1, (i64 2)), (i64 0x3030303030303030)),
               (and (srl GPR:$rs1, (i64 2)), (i64 0x0C0C0C0C0C0C0C0C))),
           (SHFLI GPR:$rs1, (i64 2))>;
 def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)),
                   (and GPR:$rs1, (i64 0x9999999999999999))),
               (and (srl GPR:$rs1, (i64 1)), (i64 0x2222222222222222))),
           (SHFLI GPR:$rs1, (i64 1))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
+}
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
           (SLOW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
           (SROW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2),

llvm/lib/Target/RISCV/RISCVSubtarget.h

 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtB = false;
+  bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
public:
   }
   bool enableMachineScheduler() const override { return true; }
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtB() const { return HasStdExtB; }
+  bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZbb() const { return HasStdExtZbb; }
   bool hasStdExtZbc() const { return HasStdExtZbc; }
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }

llvm/test/CodeGen/RISCV/rv64Zba.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBA
+
+define i64 @slliuw(i64 %a) nounwind {
+; RV64I-LABEL: slliuw:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    slli a1, a1, 33
+; RV64I-NEXT:    addi a1, a1, -2
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: slliuw:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli.uw a0, a0, 1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: slliuw:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    slli.uw a0, a0, 1
+; RV64IBA-NEXT:    ret
+  %conv1 = shl i64 %a, 1
+  %shl = and i64 %conv1, 8589934590
+  ret i64 %shl
+}
+
+define i128 @slliuw_2(i32 signext %0, i128* %1) {
+; RV64I-LABEL: slliuw_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    add a1, a1, a0
+; RV64I-NEXT:    ld a0, 0(a1)
+; RV64I-NEXT:    ld a1, 8(a1)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: slliuw_2:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    slli.uw a0, a0, 4
+; RV64IB-NEXT:    add a1, a1, a0
+; RV64IB-NEXT:    ld a0, 0(a1)
+; RV64IB-NEXT:    ld a1, 8(a1)
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: slliuw_2:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    slli.uw a0, a0, 4
+; RV64IBA-NEXT:    add a1, a1, a0
+; RV64IBA-NEXT:    ld a0, 0(a1)
+; RV64IBA-NEXT:    ld a1, 8(a1)
+; RV64IBA-NEXT:    ret
+  %3 = zext i32 %0 to i64
+  %4 = getelementptr inbounds i128, i128* %1, i64 %3
+  %5 = load i128, i128* %4
+  ret i128 %5
+}
+
+define i64 @adduw(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: adduw:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: adduw:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    add.uw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: adduw:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    add.uw a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %and = and i64 %b, 4294967295
+  %add = add i64 %and, %a
+  ret i64 %add
+}
+
+define signext i8 @adduw_2(i32 signext %0, i8* %1) {
+; RV64I-LABEL: adduw_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    lb a0, 0(a0)
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: adduw_2:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    add.uw a0, a1, a0
+; RV64IB-NEXT:    lb a0, 0(a0)
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: adduw_2:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    add.uw a0, a1, a0
+; RV64IBA-NEXT:    lb a0, 0(a0)
+; RV64IBA-NEXT:    ret
+  %3 = zext i32 %0 to i64
+  %4 = getelementptr inbounds i8, i8* %1, i64 %3
+  %5 = load i8, i8* %4
+  ret i8 %5
+}

llvm/test/CodeGen/RISCV/rv64Zbb.ll

 ; RV64IBB-LABEL: abs_i64:
 ; RV64IBB:       # %bb.0:
 ; RV64IBB-NEXT:    neg a1, a0
 ; RV64IBB-NEXT:    max a0, a0, a1
 ; RV64IBB-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   ret i64 %abs
 }
-
-define i64 @slliuw(i64 %a) nounwind {
-; RV64I-LABEL: slliuw:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 1
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 33
-; RV64I-NEXT:    addi a1, a1, -2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: slliuw:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slli.uw a0, a0, 1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: slliuw:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slli.uw a0, a0, 1
-; RV64IBB-NEXT:    ret
-  %conv1 = shl i64 %a, 1
-  %shl = and i64 %conv1, 8589934590
-  ret i64 %shl
-}
-
-define i128 @slliuw_2(i32 signext %0, i128* %1) {
-; RV64I-LABEL: slliuw_2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a0, a0, 4
-; RV64I-NEXT:    add a1, a1, a0
-; RV64I-NEXT:    ld a0, 0(a1)
-; RV64I-NEXT:    ld a1, 8(a1)
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: slliuw_2:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slli.uw a0, a0, 4
-; RV64IB-NEXT:    add a1, a1, a0
-; RV64IB-NEXT:    ld a0, 0(a1)
-; RV64IB-NEXT:    ld a1, 8(a1)
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: slliuw_2:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slli.uw a0, a0, 4
-; RV64IBB-NEXT:    add a1, a1, a0
-; RV64IBB-NEXT:    ld a0, 0(a1)
-; RV64IBB-NEXT:    ld a1, 8(a1)
-; RV64IBB-NEXT:    ret
-  %3 = zext i32 %0 to i64
-  %4 = getelementptr inbounds i128, i128* %1, i64 %3
-  %5 = load i128, i128* %4
-  ret i128 %5
-}
-
-define i64 @adduw(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: adduw:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: adduw:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: adduw:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    add.uw a0, a0, a1
-; RV64IBB-NEXT:    ret
-  %and = and i64 %b, 4294967295
-  %add = add i64 %and, %a
-  ret i64 %add
-}
-
-define signext i8 @adduw_2(i32 signext %0, i8* %1) {
-; RV64I-LABEL: adduw_2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    lb a0, 0(a0)
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: adduw_2:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a1, a0
-; RV64IB-NEXT:    lb a0, 0(a0)
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: adduw_2:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    add.uw a0, a1, a0
-; RV64IBB-NEXT:    lb a0, 0(a0)
-; RV64IBB-NEXT:    ret
-  %3 = zext i32 %0 to i64
-  %4 = getelementptr inbounds i8, i8* %1, i64 %3
-  %5 = load i8, i8* %4
-  ret i8 %5
-}

llvm/test/MC/RISCV/rv64zba-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zba < %s 2>&1 | FileCheck %s
+
+# Too few operands
+slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Immediate operand out of range
+slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+# Too few operands
+add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zba-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zba -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
+slli.uw t0, t1, 0
+# CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
+add.uw t0, t1, t2

llvm/test/MC/RISCV/rv64zbb-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
 
 # Too few operands
-slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Immediate operand out of range
-slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
-slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
-# Too few operands
-add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
 slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 sloiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 sloiw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbb-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip base extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbb -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
-# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
-slli.uw t0, t1, 0
-# CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
-add.uw t0, t1, t2
 # CHECK-ASM-AND-OBJ: slow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
 slow t0, t1, t2
 # CHECK-ASM-AND-OBJ: srow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
 srow t0, t1, t2
 # CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]