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[RISCV] Add zext.h instruction to Zbb.
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Authored by craig.topper on Jan 15 2021, 12:49 PM.

Details

Summary

zext.h uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.

I've added two new instructions with these specific encodings with
predicates that enable them when either Zbb or Zbp is enabled.

The pack spelling will only be accepted with Zbp. The disassembler
will use the zext.h instruction when either feature is enabled.

Using the pack spelling will print as pack when llvm-mc is emitting text. We could fix this with some custom code in processInstruction if this is important, but I'm not sure it is.

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Event Timeline

craig.topper created this revision.Jan 15 2021, 12:49 PM
craig.topper requested review of this revision.Jan 15 2021, 12:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 12:49 PM
Herald added a subscriber: MaskRay. · View Herald Transcript

Check operands of zext.h in rv32zbb-valid.s

Modify to use the same approach as rev8 and orc.b patch

This revision is now accepted and ready to land.Jan 21 2021, 4:03 AM
asb accepted this revision.Jan 22 2021, 10:26 AM
This revision was automatically updated to reflect the committed changes.