[RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec.

[frasercrmck]

LGTM. I take it the patterns can come later?

[craig.topper]

In D94637#2509271, @frasercrmck wrote:

LGTM. I take it the patterns can come later?

I was trying to get through the MC layer changes hoping to intercept the LLVM 12 branch. I might go add them now that I think all the patches are done.

[craig.topper]

Rebase

[craig.topper]

Rebase

[asb]

Not a blocker as I think this is just something that bitmanip has been less complete with vs the standard extensions, and you're just the last person to touch this, but we should probably be testing that rv32zba rejects rv64-only instructions and that rv64zba accepts the rv32 instructions. See rv64f-valid.s and rv32f-valid.s.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def ANDN  : ALU_rr<0b0100000, 0b111, "andn">, Sched<[]>;
 def ORN   : ALU_rr<0b0100000, 0b110, "orn">, Sched<[]>;
 def XNOR  : ALU_rr<0b0100000, 0b100, "xnor">, Sched<[]>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
+let Predicates = [HasStdExtZba] in {
+def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">, Sched<[]>;
+def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">, Sched<[]>;
+def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">, Sched<[]>;
+} // Predicates = [HasStdExtZba]
+
 let Predicates = [HasStdExtZbb] in {
 def SLO  : ALU_rr<0b0010000, 0b001, "slo">, Sched<[]>;
 def SRO  : ALU_rr<0b0010000, 0b101, "sro">, Sched<[]>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def ROL   : ALU_rr<0b0110000, 0b001, "rol">, Sched<[]>;
 def ROR   : ALU_rr<0b0110000, 0b101, "ror">, Sched<[]>;

 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
 def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
 def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>;
+def SH1ADDUW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">, Sched<[]>;
+def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">, Sched<[]>;
+def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def SLOW   : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>;
 def SROW   : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {

llvm/test/MC/RISCV/rv32zba-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zba < %s 2>&1 | FileCheck %s
+
+# Too few operands
+sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32zba-valid.s

+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zba -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sh1add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x20]
+sh1add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh2add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x20]
+sh2add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh3add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x20]
+sh3add t0, t1, t2

llvm/test/MC/RISCV/rv64zba-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zba < %s 2>&1 | FileCheck %s
 
 # Too few operands
 slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 # Too few operands
 add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh1add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh2add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh3add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zba-valid.s

 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
 slli.uw t0, t1, 0
 # CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
 add.uw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh1add.uw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x20]
+sh1add.uw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh2add.uw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x20]
+sh2add.uw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh3add.uw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x20]
+sh3add.uw t0, t1, t2