[RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec.

[craig.topper]

Summary

This is the first of probably multiple patches to bring our 0.92
implementation up to 0.93.

Should we hold them all and commit them together while also
changing the command line parsing in the frontend to only
accept 0.93?

[kito-cheng]

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

However it's also a milestone for B-ext, since this version claim zba, zbb and zbc is frozen, maybe those 3 sub-ext. could be removed from the umbrella of -menable-experimental-extension ?

@asb What do you think about this?

[simoncook]

In D94568#2495052, @kito-cheng wrote:

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

However it's also a milestone for B-ext, since this version claim zba, zbb and zbc is frozen, maybe those 3 sub-ext. could be removed from the umbrella of -menable-experimental-extension ?

@asb What do you think about this?

I think it only makes sense to mark it as not experimental when the sub extensions get marked as frozen in the main isa spec document.

As far as this change is concerned, it looks good to me, but I think this should only land when all parts are 0.93 compatible. Given we support this extension via clang and require 0.92 to be set, I'm reluctant to have the compiler in a half-0.92/half-0.93 state, especially so close to LLVM 12 branching.

[asb]

In D94568#2495052, @kito-cheng wrote:

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

However it's also a milestone for B-ext, since this version claim zba, zbb and zbc is frozen, maybe those 3 sub-ext. could be removed from the umbrella of -menable-experimental-extension ?

@asb What do you think about this?

In terms of handling the 0.92=>0.93 switchover I think it would be better to land 0.93 in one go if feasible (whether that's a single patch or a single series of patches that are committed all together). Given we're behind an experimental feature flag anyway we have more flexibility than we would otherwise, but being in some in-between state won't be useful for many people.

For Zba/Zbb/Zbc, the language is "the extensions are expected to be unchanged in the official version." which is somewhat weaker than those sub-extensions being frozen, especially given it still needs to go through ratification. It feels early to me to remove the experimental feature flag unless there's some stronger statement elsewhere about these specs not changing in future.

[frasercrmck]

LGTM from a change point of view. I can't really add to the discussion about how/when to switch from 0.92 to 0.93 so I'm not saying "merge right away" :)

[craig.topper]

Rebase

[asb]

Straight forward change, LGTM. It seems there's nothing contentious in the patchset, so I'd expect the series can land basically all at once, to minimise the time we support a weird 0.92/0.93 hybrid.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
                           "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbb] in {
 def CLZ  : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">,
            Sched<[]>;
 def CTZ  : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0010011>, "ctz">,
            Sched<[]>;
-def PCNT : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "pcnt">,
+def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "cpop">,
            Sched<[]>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbm, IsRV64] in
 def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, RISCVOpcode<0b0010011>,
                         "bmatflip">, Sched<[]>;
 
 let Predicates = [HasStdExtZbb] in {
def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
                            "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def CLZW   : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
                       "clzw">, Sched<[]>;
 def CTZW   : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
                       "ctzw">, Sched<[]>;
-def PCNTW  : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
-                      "pcntw">, Sched<[]>;
+def CPOPW  : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
+                      "cpopw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbc, IsRV64] in {
 def CLMULW  : ALUW_rr<0b0000101, 0b001, "clmulw">, Sched<[]>;
 def CLMULRW : ALUW_rr<0b0000101, 0b010, "clmulrw">, Sched<[]>;
 def CLMULHW : ALUW_rr<0b0000101, 0b011, "clmulhw">, Sched<[]>;
 } // Predicates = [HasStdExtZbc, IsRV64]
 

 // XLen and swap the operands.
 def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
           (FSRI GPR:$rs1, GPR:$rs3, (ImmROTL2R uimmlog2xlen:$shamt))>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>;
 def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
-def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
+def : Pat<(ctpop GPR:$rs1), (CPOP GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
 def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
 }
 
 let Predicates = [HasStdExtZbb] in {
def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
           (CLZW GPR:$rs1)>;
 // computeKnownBits can't figure out that the and mask on the add result is
 // unnecessary so we need to pattern match it away.
 def : Pat<(and (add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
                (i64 0xFFFFFFFF)),
           (CLZW GPR:$rs1)>;
 def : Pat<(cttz (or GPR:$rs1, (i64 0x100000000))),
           (CTZW GPR:$rs1)>;
-def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;
+def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (CPOPW GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)),
                           (and GPR:$rs1, 0x000000000000FFFF)),
                       i32),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
               (srl (and GPR:$rs1, 0x00000000FFFF0000),
                    (i64 16))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]

llvm/test/CodeGen/RISCV/rv32Zbb.ll

 ; RV32I-NEXT:    call __mulsi3@plt
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: ctpop_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    pcnt a0, a0
+; RV32IB-NEXT:    cpop a0, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: ctpop_i32:
 ; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    pcnt a0, a0
+; RV32IBB-NEXT:    cpop a0, a0
 ; RV32IBB-NEXT:    ret
   %1 = call i32 @llvm.ctpop.i32(i32 %a)
   ret i32 %1
 }
 
 declare i64 @llvm.ctpop.i64(i64)
 
 define i64 @ctpop_i64(i64 %a) nounwind {

 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: ctpop_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    pcnt a1, a1
-; RV32IB-NEXT:    pcnt a0, a0
+; RV32IB-NEXT:    cpop a1, a1
+; RV32IB-NEXT:    cpop a0, a0
 ; RV32IB-NEXT:    add a0, a0, a1
 ; RV32IB-NEXT:    mv a1, zero
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: ctpop_i64:
 ; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    pcnt a1, a1
-; RV32IBB-NEXT:    pcnt a0, a0
+; RV32IBB-NEXT:    cpop a1, a1
+; RV32IBB-NEXT:    cpop a0, a0
 ; RV32IBB-NEXT:    add a0, a0, a1
 ; RV32IBB-NEXT:    mv a1, zero
 ; RV32IBB-NEXT:    ret
   %1 = call i64 @llvm.ctpop.i64(i64 %a)
   ret i64 %1
 }
 
 define i32 @sextb_i32(i32 %a) nounwind {

llvm/test/CodeGen/RISCV/rv64Zbb.ll

 ; RV64I-NEXT:    call __muldi3@plt
 ; RV64I-NEXT:    srli a0, a0, 56
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: ctpop_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    pcntw a0, a0
+; RV64IB-NEXT:    cpopw a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: ctpop_i32:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    pcntw a0, a0
+; RV64IBB-NEXT:    cpopw a0, a0
 ; RV64IBB-NEXT:    ret
   %1 = call i32 @llvm.ctpop.i32(i32 %a)
   ret i32 %1
 }
 
 declare i64 @llvm.ctpop.i64(i64)
 
 define i64 @ctpop_i64(i64 %a) nounwind {

 ; RV64I-NEXT:    call __muldi3@plt
 ; RV64I-NEXT:    srli a0, a0, 56
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: ctpop_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    pcnt a0, a0
+; RV64IB-NEXT:    cpop a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: ctpop_i64:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    pcnt a0, a0
+; RV64IBB-NEXT:    cpop a0, a0
 ; RV64IBB-NEXT:    ret
   %1 = call i64 @llvm.ctpop.i64(i64 %a)
   ret i64 %1
 }
 
 define signext i32 @sextb_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: sextb_i32:
 ; RV64I:       # %bb.0:

llvm/test/MC/RISCV/rv32zbb-invalid.s

 # Immediate operand out of range
 sroi t0, t1, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
 sroi t0, t1, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
 # Too many operands
 clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 # Too many operands
 ctz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 # Too many operands
-pcnt t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+cpop t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands
 sext.b t0, t1, t2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
 # Too many operands
 sext.h t0, t1, t2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
 # Too few operands
 min t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 max t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 minu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 maxu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32zbb-valid.s

 # CHECK-ASM: encoding: [0x93,0x52,0x03,0x20]
 sroi t0, t1, 0
 # CHECK-ASM-AND-OBJ: clz t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
 clz t0, t1
 # CHECK-ASM-AND-OBJ: ctz t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
 ctz t0, t1
-# CHECK-ASM-AND-OBJ: pcnt t0, t1
+# CHECK-ASM-AND-OBJ: cpop t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
-pcnt t0, t1
+cpop t0, t1
 # CHECK-ASM-AND-OBJ: sext.b t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
 sext.b t0, t1
 # CHECK-ASM-AND-OBJ: sext.h t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
 sext.h t0, t1
 # CHECK-ASM-AND-OBJ: min t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]

llvm/test/MC/RISCV/rv64zbb-invalid.s

 # Immediate operand out of range
 sroiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 sroiw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 # Too many operands
 clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands
 ctzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands
-pcntw t0, t1, t2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+cpopw t0, t1, t2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zbb-valid.s

 # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x20]
 sroiw t0, t1, 0
 # CHECK-ASM-AND-OBJ: clzw t0, t1
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
 clzw t0, t1
 # CHECK-ASM-AND-OBJ: ctzw t0, t1
 # CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
 ctzw t0, t1
-# CHECK-ASM-AND-OBJ: pcntw t0, t1
+# CHECK-ASM-AND-OBJ: cpopw t0, t1
 # CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
-pcntw t0, t1
+cpopw t0, t1