[XRay] Change mips to use version 2 sled (PC-relative address)

[MaskRay]

Summary

Follow-up to D78590. All targets use PC-relative addresses now.

[MaskRay]

Update recordSled

[dberris]

LGTM

[atanasyan]

LGTM

compiler-rt/lib/xray/xray_mips.cpp

inline static bool patchSled(const bool Enable, const uint32_t FuncId,
   // Replacement of the first 4-byte instruction should be the last and atomic
   // operation, so that the user code which reaches the sled concurrently
   // either jumps over the whole sled, or executes the whole sled when the
   // latter is ready.
   //
   // When |Enable|==false, we set back the first instruction in the sled to be
   //   B #44
 
+  uint32_t *Address = reinterpret_cast<uint32_t *>(Sled.address());
   if (Enable) {
     uint32_t LoTracingHookAddr =
         reinterpret_cast<int32_t>(TracingHook) & 0xffff;
     uint32_t HiTracingHookAddr =
         (reinterpret_cast<int32_t>(TracingHook) >> 16) & 0xffff;
     uint32_t LoFunctionID = FuncId & 0xffff;
     uint32_t HiFunctionID = (FuncId >> 16) & 0xffff;
-    *reinterpret_cast<uint32_t *>(Sled.Address + 8) = encodeInstruction(
-        PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 12) = encodeInstruction(
-        PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 16) = encodeInstruction(
-        PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 20) = encodeInstruction(
-        PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 24) = encodeInstruction(
-        PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 28) = encodeSpecialInstruction(
-        PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 32) = encodeInstruction(
-        PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 36) = encodeInstruction(
-        PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 40) = encodeInstruction(
-        PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 44) = encodeInstruction(
-        PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0x8);
+    Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP,
+                                   RegNum::RN_RA, 0x4);
+    Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP,
+                                   RegNum::RN_T9, 0x0);
+    Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9,
+                                   HiTracingHookAddr);
+    Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9,
+                                   RegNum::RN_T9, LoTracingHookAddr);
+    Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0,
+                                   HiFunctionID);
+    Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9,
+                                          0x0, RegNum::RN_RA, 0X0);
+    Address[8] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T0,
+                                   RegNum::RN_T0, LoFunctionID);
+    Address[9] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP,
+                                   RegNum::RN_T9, 0x0);
+    Address[10] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP,
+                                    RegNum::RN_RA, 0x4);
+    Address[11] = encodeInstruction(PatchOpcodes::PO_ADDIU, RegNum::RN_SP,
+                                    RegNum::RN_SP, 0x8);
     uint32_t CreateStackSpaceInstr = encodeInstruction(
         PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xFFF8);
     std::atomic_store_explicit(
-        reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
+        reinterpret_cast<std::atomic<uint32_t> *>(Address),
         uint32_t(CreateStackSpaceInstr), std::memory_order_release);
   } else {
     std::atomic_store_explicit(
-        reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
+        reinterpret_cast<std::atomic<uint32_t> *>(Address),
         uint32_t(PatchOpcodes::PO_B44), std::memory_order_release);
   }
   return true;
 }
 
 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
                         const XRaySledEntry &Sled,
                         void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {

compiler-rt/lib/xray/xray_mips64.cpp

inline static bool patchSled(const bool Enable, const uint32_t FuncId,
   // Replacement of the first 4-byte instruction should be the last and atomic
   // operation, so that the user code which reaches the sled concurrently
   // either jumps over the whole sled, or executes the whole sled when the
   // latter is ready.
   //
   // When |Enable|==false, we set back the first instruction in the sled to be
   //   B #60
 
+  uint32_t *Address = reinterpret_cast<uint32_t *>(Sled.address());
   if (Enable) {
     uint32_t LoTracingHookAddr =
         reinterpret_cast<int64_t>(TracingHook) & 0xffff;
     uint32_t HiTracingHookAddr =
         (reinterpret_cast<int64_t>(TracingHook) >> 16) & 0xffff;
     uint32_t HigherTracingHookAddr =
         (reinterpret_cast<int64_t>(TracingHook) >> 32) & 0xffff;
     uint32_t HighestTracingHookAddr =
         (reinterpret_cast<int64_t>(TracingHook) >> 48) & 0xffff;
     uint32_t LoFunctionID = FuncId & 0xffff;
     uint32_t HiFunctionID = (FuncId >> 16) & 0xffff;
-    *reinterpret_cast<uint32_t *>(Sled.Address + 8) = encodeInstruction(
-        PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 12) = encodeInstruction(
-        PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 16) = encodeInstruction(
-        PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 20) =
-        encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9,
-                          HigherTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 24) = encodeSpecialInstruction(
-        PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 28) = encodeInstruction(
-        PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, HiTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 32) = encodeSpecialInstruction(
-        PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 36) = encodeInstruction(
-        PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 40) = encodeInstruction(
-        PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 44) = encodeSpecialInstruction(
-        PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 48) = encodeInstruction(
-        PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 52) = encodeInstruction(
-        PatchOpcodes::PO_LD, RegNum::RN_SP, RegNum::RN_T9, 0x0);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 56) = encodeInstruction(
-        PatchOpcodes::PO_LD, RegNum::RN_SP, RegNum::RN_RA, 0x8);
-    *reinterpret_cast<uint32_t *>(Sled.Address + 60) = encodeInstruction(
-        PatchOpcodes::PO_DADDIU, RegNum::RN_SP, RegNum::RN_SP, 0x10);
+    Address[2] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP,
+                                   RegNum::RN_RA, 0x8);
+    Address[3] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP,
+                                   RegNum::RN_T9, 0x0);
+    Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9,
+                                   HighestTracingHookAddr);
+    Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9,
+                                   RegNum::RN_T9, HigherTracingHookAddr);
+    Address[6] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0,
+                                          RegNum::RN_T9, RegNum::RN_T9, 0x10);
+    Address[7] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9,
+                                   RegNum::RN_T9, HiTracingHookAddr);
+    Address[8] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0,
+                                          RegNum::RN_T9, RegNum::RN_T9, 0x10);
+    Address[9] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9,
+                                   RegNum::RN_T9, LoTracingHookAddr);
+    Address[10] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0,
+                                    HiFunctionID);
+    Address[11] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9,
+                                           0x0, RegNum::RN_RA, 0X0);
+    Address[12] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T0,
+                                    RegNum::RN_T0, LoFunctionID);
+    Address[13] = encodeInstruction(PatchOpcodes::PO_LD, RegNum::RN_SP,
+                                    RegNum::RN_T9, 0x0);
+    Address[14] = encodeInstruction(PatchOpcodes::PO_LD, RegNum::RN_SP,
+                                    RegNum::RN_RA, 0x8);
+    Address[15] = encodeInstruction(PatchOpcodes::PO_DADDIU, RegNum::RN_SP,
+                                    RegNum::RN_SP, 0x10);
     uint32_t CreateStackSpace = encodeInstruction(
         PatchOpcodes::PO_DADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xfff0);
     std::atomic_store_explicit(
-        reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
-        CreateStackSpace, std::memory_order_release);
+        reinterpret_cast<std::atomic<uint32_t> *>(Address), CreateStackSpace,
+        std::memory_order_release);
   } else {
     std::atomic_store_explicit(
-        reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
+        reinterpret_cast<std::atomic<uint32_t> *>(Address),
         uint32_t(PatchOpcodes::PO_B60), std::memory_order_release);
   }
   return true;
 }
 
 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
                         const XRaySledEntry &Sled,
                         void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::emitXRayTable() {
   if (Sleds.empty())
     return;
 
   auto PrevSection = OutStreamer->getCurrentSectionOnly();
   const Function &F = MF->getFunction();
   MCSection *InstMap = nullptr;
   MCSection *FnSledIndex = nullptr;
   const Triple &TT = TM.getTargetTriple();
-  // Use PC-relative addresses on all targets except MIPS (MIPS64 cannot use
-  // PC-relative addresses because R_MIPS_PC64 does not exist).
-  bool PCRel = !TT.isMIPS();
+  // Use PC-relative addresses on all targets.
   if (TT.isOSBinFormatELF()) {
     auto LinkedToSym = cast<MCSymbolELF>(CurrentFnSym);
     auto Flags = ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER;
-    if (!PCRel)
-      Flags |= ELF::SHF_WRITE;
     StringRef GroupName;
     if (F.hasComdat()) {
       Flags |= ELF::SHF_GROUP;
       GroupName = F.getComdat()->getName();
     }
     InstMap = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS,
                                        Flags, 0, GroupName,
                                        MCSection::NonUniqueID, LinkedToSym);
void AsmPrinter::emitXRayTable() {
   // Now we switch to the instrumentation map section. Because this is done
   // per-function, we are able to create an index entry that will represent the
   // range of sleds associated with a function.
   auto &Ctx = OutContext;
   MCSymbol *SledsStart = OutContext.createTempSymbol("xray_sleds_start", true);
   OutStreamer->SwitchSection(InstMap);
   OutStreamer->emitLabel(SledsStart);
   for (const auto &Sled : Sleds) {
-    if (PCRel) {
-      MCSymbol *Dot = Ctx.createTempSymbol();
-      OutStreamer->emitLabel(Dot);
-      OutStreamer->emitValueImpl(
-          MCBinaryExpr::createSub(MCSymbolRefExpr::create(Sled.Sled, Ctx),
-                                  MCSymbolRefExpr::create(Dot, Ctx), Ctx),
-          WordSizeBytes);
-      OutStreamer->emitValueImpl(
-          MCBinaryExpr::createSub(
-              MCSymbolRefExpr::create(CurrentFnBegin, Ctx),
-              MCBinaryExpr::createAdd(
-                  MCSymbolRefExpr::create(Dot, Ctx),
-                  MCConstantExpr::create(WordSizeBytes, Ctx), Ctx),
-              Ctx),
-          WordSizeBytes);
-    } else {
-      OutStreamer->emitSymbolValue(Sled.Sled, WordSizeBytes);
-      OutStreamer->emitSymbolValue(CurrentFnSym, WordSizeBytes);
-    }
+            MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Dot, Ctx),
+                                    MCConstantExpr::create(WordSizeBytes, Ctx),
+                                    Ctx),
     Sled.emit(WordSizeBytes, OutStreamer.get());
   }
   MCSymbol *SledsEnd = OutContext.createTempSymbol("xray_sleds_end", true);
   OutStreamer->emitLabel(SledsEnd);
 
   // We then emit a single entry in the index per function. We use the symbols
   // that bound the instrumentation map as the range for a specific function.
   // Each entry here will be 2 * word size aligned, as we're writing down two

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
   if (!Subtarget->isGP64bit()) {
     EmitToStreamer(*OutStreamer,
                    MCInstBuilder(Mips::ADDiu)
                        .addReg(Mips::T9)
                        .addReg(Mips::T9)
                        .addImm(0x34));
   }
 
-  recordSled(CurSled, MI, Kind);
+  recordSled(CurSled, MI, Kind, 2);
 }
 
 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
   EmitSled(MI, SledKind::FUNCTION_ENTER);
 }
 
 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
   EmitSled(MI, SledKind::FUNCTION_EXIT);

llvm/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll

 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64-LABEL: .Ltmp2:
 ; CHECK-MIPS32-LABEL: $tmp2:
 ; CHECK-MIPS32:  addiu $25, $25, 52
 }
-; CHECK:  .section xray_instr_map,{{.*}}
-; CHECK-MIPS64: .8byte  .Lxray_sled_0
-; CHECK-MIPS64: .8byte  .Lxray_sled_1
-; CHECK-MIPS32: .4byte  ($xray_sled_0)
-; CHECK-MIPS32: .4byte  ($xray_sled_1)
+; CHECK:             .section xray_instr_map,"ao",@progbits,foo
+; CHECK-MIPS64:      .Ltmp3:
+; CHECK-MIPS64-NEXT:   .8byte  .Lxray_sled_0-.Ltmp3
+; CHECK-MIPS64-NEXT:   .8byte  .Lfunc_begin0-(.Ltmp3+8)
+; CHECK-MIPS32:      $tmp3:
+; CHECK-MIPS32-NEXT:   .4byte  ($xray_sled_0)-($tmp3)
+; CHECK-MIPS32-NEXT:   .4byte  ($func_begin0)-(($tmp3)+4)
 
 ; We test multiple returns in a single function to make sure we're getting all
 ; of them with XRay instrumentation.
 define i32 @bar(i32 %i) nounwind noinline uwtable "function-instrument"="xray-always" {
 ; CHECK:       .p2align 2
 ; CHECK-MIPS64-LABEL: .Lxray_sled_2:
-; CHECK-MIPS64-NEXT:   b .Ltmp4
+; CHECK-MIPS64-NEXT:   b .Ltmp6
 ; CHECK-MIPS32-LABEL: $xray_sled_2:
-; CHECK-MIPS32-NEXT:   b $tmp4
+; CHECK-MIPS32-NEXT:   b $tmp6
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
-; CHECK-MIPS64-LABEL: .Ltmp4:
-; CHECK-MIPS32-LABEL: $tmp4:
+; CHECK-MIPS64-LABEL: .Ltmp6:
+; CHECK-MIPS32-LABEL: $tmp6:
 ; CHECK-MIPS32:  addiu $25, $25, 52
 Test:
   %cond = icmp eq i32 %i, 0
   br i1 %cond, label %IsEqual, label %NotEqual
 IsEqual:
   ret i32 0
 ; CHECK:       .p2align 2
 ; CHECK-MIPS64-LABEL: .Lxray_sled_3:
-; CHECK-MIPS64-NEXT:   b .Ltmp5
+; CHECK-MIPS64-NEXT:   b .Ltmp7
 ; CHECK-MIPS32-LABEL: $xray_sled_3:
-; CHECK-MIPS32-NEXT:   b $tmp5
+; CHECK-MIPS32-NEXT:   b $tmp7
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
-; CHECK-MIPS64-LABEL: .Ltmp5:
-; CHECK-MIPS32-LABEL: $tmp5:
+; CHECK-MIPS64-LABEL: .Ltmp7:
+; CHECK-MIPS32-LABEL: $tmp7:
 ; CHECK-MIPS32:  addiu $25, $25, 52 
 NotEqual:
   ret i32 1
 ; CHECK:       .p2align 2
 ; CHECK-MIPS64-LABEL: .Lxray_sled_4:
-; CHECK-MIPS64-NEXT:   b .Ltmp6
+; CHECK-MIPS64-NEXT:   b .Ltmp8
 ; CHECK-MIPS32-LABEL: $xray_sled_4:
-; CHECK-MIPS32-NEXT:   b $tmp6
+; CHECK-MIPS32-NEXT:   b $tmp8
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
 ; CHECK-MIPS64:  nop
-; CHECK-MIPS64-LABEL: .Ltmp6:
-; CHECK-MIPS32-LABEL: $tmp6:
+; CHECK-MIPS64-LABEL: .Ltmp8:
+; CHECK-MIPS32-LABEL: $tmp8:
 ; CHECK-MIPS32:  addiu $25, $25, 52
 }
 ; CHECK: .section xray_instr_map,{{.*}}
 ; CHECK-MIPS64: .8byte  .Lxray_sled_2
 ; CHECK-MIPS64: .8byte  .Lxray_sled_3
 ; CHECK-MIPS64: .8byte  .Lxray_sled_4
-; CHECK-MIPS32: .4byte  ($xray_sled_2)
-; CHECK-MIPS32: .4byte  ($xray_sled_3)
-; CHECK-MIPS32: .4byte  ($xray_sled_4)
+; CHECK-MIPS32: .4byte  ($xray_sled_2)-($tmp9)
+; CHECK-MIPS32: .4byte  ($xray_sled_3)-($tmp10)
+; CHECK-MIPS32: .4byte  ($xray_sled_4)-($tmp11)

llvm/test/CodeGen/Mips/xray-section-group.ll

 ; RUN: llc -filetype=asm -o - -mtriple=mips-unknown-linux-gnu -function-sections < %s | FileCheck %s
 ; RUN: llc -filetype=asm -o - -mtriple=mipsel-unknown-linux-gnu -function-sections < %s | FileCheck %s
 ; RUN: llc -filetype=obj -o %t -mtriple=mips-unknown-linux-gnu -function-sections < %s
 ; RUN: llvm-readobj --sections %t | FileCheck %s --check-prefix=CHECK-OBJ
 ; RUN: llc -filetype=obj -o %t -mtriple=mipsel-unknown-linux-gnu -function-sections < %s
 ; RUN: llvm-readobj --sections %t | FileCheck %s --check-prefix=CHECK-OBJ
 ; RUN: llc -filetype=asm -o - -mtriple=mips64-unknown-linux-gnu -function-sections < %s | FileCheck %s
 ; RUN: llc -filetype=asm -o - -mtriple=mips64el-unknown-linux-gnu -function-sections < %s | FileCheck %s
 ; RUN: llc -filetype=obj -o %t -mtriple=mips64-unknown-linux-gnu -function-sections < %s
 ; RUN: llvm-readobj --sections %t | FileCheck %s --check-prefix=CHECK-OBJ
 ; RUN: llc -filetype=obj -o %t -mtriple=mips64el-unknown-linux-gnu -function-sections < %s
 ; RUN: llvm-readobj --sections %t | FileCheck %s --check-prefix=CHECK-OBJ
 
 define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
 ; CHECK: .section .text.foo,"ax",@progbits
   ret i32 0
-; CHECK: .section xray_instr_map,"awo",@progbits,foo{{$}}
+; CHECK: .section xray_instr_map,"ao",@progbits,foo{{$}}
 }
 
 ; CHECK-OBJ: Section {
 ; CHECK-OBJ:   Name: xray_instr_map
 
 $bar = comdat any
 define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) {
 ; CHECK: .section .text.bar,"axG",@progbits,bar,comdat
   ret i32 1
-; CHECK: .section xray_instr_map,"aGwo",@progbits,bar,comdat,bar{{$}}
+; CHECK: .section xray_instr_map,"aGo",@progbits,bar,comdat,bar{{$}}
 }
 
 ; CHECK-OBJ: Section {
 ; CHECK-OBJ:   Name: xray_instr_map