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Differential D65962

Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
ClosedPublic

Authored by dsanders on Aug 8 2019, 11:09 AM.

Details

Reviewers
arsenm
bogner
craig.topper
RKSimon
Commits
rG0c476111317c: Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
rL369041: Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary

This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&

Depends on D65919

Diff Detail

Event Timeline

dsanders created this revision.Aug 8 2019, 11:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 8 2019, 11:09 AM
Herald added subscribers: s.egerton, Jim, asbirlea and 40 others. · View Herald Transcript
Harbormaster completed remote builds in B36445: Diff 214196.Aug 8 2019, 11:10 AM
Herald added a subscriber: • wuzish. · View Herald TranscriptAug 8 2019, 11:10 AM
dsanders mentioned this in D65919: [clang-tidy] Add llvm-prefer-register-over-unsigned check and apply it to LLVM.Aug 8 2019, 11:11 AM
aemerson added a subscriber: aemerson.Aug 9 2019, 4:28 PM

LGTM for the AArch64 changes.

aheejin mentioned this in D66064: [WebAssembly] Use Register over unsigned in LateEHPrepare (NFC).Aug 11 2019, 1:31 AM
aheejin added a comment.Aug 11 2019, 1:32 AM

WebAssembly change LGTM.

lenary added a subscriber: lenary.Aug 12 2019, 1:59 AM

The RISC-V backend changes look good to me. There are more changes that could be done, but we can do most of them by hand, or they're in target-independent interfaces that have not yet changed.

dsanders added a comment.Aug 12 2019, 3:41 PM

WebAssembly changes: r368627 (6aa77e740bf)
AArch64 changes: r368628 (b12454126d1)
RISC-V changes: r368629 (51880816fbc)

dsanders added a comment.Aug 12 2019, 3:43 PM

Thanks Amara, Heejin, and Sam. I'll rebase this patch once the monorepo syncs

dsanders updated this revision to Diff 214727.Aug 12 2019, 3:44 PM

Rebase now that AArch64, RISC-V, and WebAssembly portions have landed

dsanders edited the summary of this revision. (Show Details)Aug 12 2019, 3:45 PM
Harbormaster completed remote builds in B36632: Diff 214727.Aug 12 2019, 3:46 PM
arsenm accepted this revision.Aug 13 2019, 9:44 AM

LGTM

This revision is now accepted and ready to land.Aug 13 2019, 9:44 AM
aheejin mentioned this in rL368727: Use Register over unsigned in LateEHPrepare (NFC).Aug 13 2019, 10:35 AM
aheejin mentioned this in rG64517a6419ca: Use Register over unsigned in LateEHPrepare (NFC).
RKSimon added reviewers: craig.topper, RKSimon.Aug 14 2019, 3:34 AM
RKSimon added subscribers: craig.topper, RKSimon.

@craig.topper You might want to look at the x86 changes (and the manual reversions that @dsanders mentions)

craig.topper added a comment.Aug 14 2019, 1:06 PM

X86 changes look good to me. I'll see about addressing some of the reverts after this goes in.

luismarques mentioned this in D66252: [RISCV] Convert registers from unsigned to Register.Aug 14 2019, 1:25 PM
dsanders added a comment.Aug 15 2019, 12:23 PM
In D65962#1630046, @craig.topper wrote:

X86 changes look good to me. I'll see about addressing some of the reverts after this goes in.

Thanks, they should be fairly simple. The only reason they're partial reverts instead of manual fixups was because it wasn't completely trivial and localized and I didn't want to complicate the patch as it was already large

Closed by commit rG0c476111317c: Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM (authored by dsanders). · Explain WhyAug 15 2019, 12:24 PM
This revision was automatically updated to reflect the committed changes.
asbirlea removed a subscriber: asbirlea.Aug 15 2019, 1:27 PM

Large Diff

This large diff affects 280 files. Files without inline comments have been collapsed. Expand All Files

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Diff 214196

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

llvm/lib/CodeGen/BranchFolding.cpp

llvm/lib/CodeGen/BreakFalseDeps.cpp

llvm/lib/CodeGen/CalcSpillWeights.cpp

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

llvm/lib/CodeGen/DetectDeadLanes.cpp

llvm/lib/CodeGen/EarlyIfConversion.cpp

llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

llvm/lib/CodeGen/GlobalISel/Localizer.cpp

llvm/lib/CodeGen/GlobalISel/Utils.cpp

llvm/lib/CodeGen/IfConversion.cpp

llvm/lib/CodeGen/ImplicitNullChecks.cpp

llvm/lib/CodeGen/InlineSpiller.cpp

llvm/lib/CodeGen/LiveDebugValues.cpp

llvm/lib/CodeGen/LiveDebugVariables.cpp

llvm/lib/CodeGen/LiveIntervals.cpp

llvm/lib/CodeGen/LivePhysRegs.cpp

llvm/lib/CodeGen/LiveRangeEdit.cpp

llvm/lib/CodeGen/LiveRangeShrink.cpp

llvm/lib/CodeGen/LiveRegMatrix.cpp

llvm/lib/CodeGen/LiveRegUnits.cpp

llvm/lib/CodeGen/LiveVariables.cpp

llvm/lib/CodeGen/MIRCanonicalizerPass.cpp

llvm/lib/CodeGen/MachineBasicBlock.cpp

llvm/lib/CodeGen/MachineCSE.cpp

llvm/lib/CodeGen/MachineCopyPropagation.cpp

llvm/lib/CodeGen/MachineInstrBundle.cpp

llvm/lib/CodeGen/MachineLICM.cpp

llvm/lib/CodeGen/MachineOperand.cpp

llvm/lib/CodeGen/MachinePipeliner.cpp

llvm/lib/CodeGen/MachineSSAUpdater.cpp

llvm/lib/CodeGen/MachineScheduler.cpp

llvm/lib/CodeGen/MachineSink.cpp

llvm/lib/CodeGen/MachineTraceMetrics.cpp

llvm/lib/CodeGen/MachineVerifier.cpp

llvm/lib/CodeGen/OptimizePHIs.cpp

llvm/lib/CodeGen/PHIElimination.cpp

llvm/lib/CodeGen/PeepholeOptimizer.cpp

llvm/lib/CodeGen/ProcessImplicitDefs.cpp

llvm/lib/CodeGen/RegAllocFast.cpp

llvm/lib/CodeGen/RegAllocGreedy.cpp

llvm/lib/CodeGen/RegisterCoalescer.cpp

llvm/lib/CodeGen/RegisterPressure.cpp

llvm/lib/CodeGen/RegisterScavenging.cpp

llvm/lib/CodeGen/RenameIndependentSubregs.cpp

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

llvm/lib/CodeGen/ShrinkWrap.cpp

llvm/lib/CodeGen/SplitKit.cpp

llvm/lib/CodeGen/StackMaps.cpp

llvm/lib/CodeGen/TailDuplicator.cpp

llvm/lib/CodeGen/TargetInstrInfo.cpp

llvm/lib/CodeGen/TargetSchedule.cpp

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

llvm/lib/CodeGen/UnreachableBlockElim.cpp

llvm/lib/CodeGen/VirtRegMap.cpp

llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp

llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp

llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

llvm/lib/Target/AArch64/AArch64FastISel.cpp

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp

llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp

llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp

llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp

llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

llvm/lib/Target/AMDGPU/R600Packetizer.cpp

llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

llvm/lib/Target/ARC/ARCISelLowering.cpp

llvm/lib/Target/ARC/ARCOptAddrMode.cpp

llvm/lib/Target/ARC/ARCRegisterInfo.cpp

llvm/lib/Target/ARM/A15SDOptimizer.cpp

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

llvm/lib/Target/ARM/ARMCallLowering.cpp

llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

llvm/lib/Target/ARM/ARMFastISel.cpp

llvm/lib/Target/ARM/ARMFrameLowering.cpp

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

llvm/lib/Target/ARM/ARMISelLowering.cpp

llvm/lib/Target/ARM/ARMInstrInfo.cpp

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

llvm/lib/Target/ARM/MLxExpansionPass.cpp

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

llvm/lib/Target/ARM/Thumb2SizeReduction.cpp

llvm/lib/Target/ARM/ThumbRegisterInfo.cpp

llvm/lib/Target/AVR/AVRAsmPrinter.cpp

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

llvm/lib/Target/AVR/AVRFrameLowering.cpp

llvm/lib/Target/AVR/AVRISelLowering.cpp

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp

llvm/lib/Target/BPF/BPFISelLowering.cpp

llvm/lib/Target/BPF/BPFInstrInfo.cpp

llvm/lib/Target/BPF/BPFMIPeephole.cpp

llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp

llvm/lib/Target/BPF/BPFRegisterInfo.cpp

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp

llvm/lib/Target/Hexagon/HexagonBitTracker.cpp

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp

llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

llvm/lib/Target/Hexagon/HexagonGenInsert.cpp

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp

llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp

llvm/lib/Target/Hexagon/HexagonPeephole.cpp

llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp

llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp

llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp

llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

llvm/lib/Target/Hexagon/HexagonVExtract.cpp

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

llvm/lib/Target/Hexagon/RDFGraph.cpp

llvm/lib/Target/Hexagon/RDFLiveness.cpp

llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp

llvm/lib/Target/Lanai/LanaiFrameLowering.cpp

llvm/lib/Target/Lanai/LanaiISelLowering.cpp

llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp

llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp

llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp

llvm/lib/Target/Mips/Mips16ISelLowering.cpp

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

llvm/lib/Target/Mips/MipsExpandPseudo.cpp

llvm/lib/Target/Mips/MipsFastISel.cpp

llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp

llvm/lib/Target/Mips/MipsISelLowering.cpp

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

llvm/lib/Target/Mips/MipsOptimizePICCall.cpp

llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

llvm/lib/Target/Mips/MipsSEISelLowering.cpp

llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

llvm/lib/Target/Mips/MipsSERegisterInfo.cpp

llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

llvm/lib/Target/PowerPC/PPCFastISel.cpp

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp

llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

llvm/lib/Target/PowerPC/PPCVSXCopy.cpp

llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp

llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

llvm/lib/Target/Sparc/DelaySlotFiller.cpp

llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

llvm/lib/Target/Sparc/SparcISelLowering.cpp

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

llvm/lib/Target/Sparc/SparcRegisterInfo.cpp

llvm/lib/Target/SystemZ/SystemZElimCompare.cpp

llvm/lib/Target/SystemZ/SystemZExpandPseudo.cpp

llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

llvm/lib/Target/SystemZ/SystemZShortenInst.cpp

llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp

llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp

llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp

llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp

llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp

llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp

llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp

llvm/lib/Target/X86/X86AsmPrinter.cpp

llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

llvm/lib/Target/X86/X86CallFrameOptimization.cpp

llvm/lib/Target/X86/X86CallLowering.cpp

llvm/lib/Target/X86/X86CmovConversion.cpp

llvm/lib/Target/X86/X86DomainReassignment.cpp

llvm/lib/Target/X86/X86EvexToVex.cpp

llvm/lib/Target/X86/X86ExpandPseudo.cpp

llvm/lib/Target/X86/X86FastISel.cpp

llvm/lib/Target/X86/X86FixupBWInsts.cpp

llvm/lib/Target/X86/X86FixupLEAs.cpp

llvm/lib/Target/X86/X86FixupSetCC.cpp

llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

llvm/lib/Target/X86/X86FloatingPoint.cpp

llvm/lib/Target/X86/X86FrameLowering.cpp

llvm/lib/Target/X86/X86ISelLowering.cpp

llvm/lib/Target/X86/X86InsertPrefetch.cpp

llvm/lib/Target/X86/X86InstrInfo.cpp

llvm/lib/Target/X86/X86InstructionSelector.cpp

llvm/lib/Target/X86/X86MCInstLower.cpp

llvm/lib/Target/X86/X86OptimizeLEAs.cpp

llvm/lib/Target/X86/X86RegisterInfo.cpp

llvm/lib/Target/X86/X86SelectionDAGInfo.cpp

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

llvm/lib/Target/X86/X86WinAllocaExpander.cpp

llvm/lib/Target/XCore/XCoreFrameLowering.cpp

llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp

llvm/lib/Target/XCore/XCoreISelLowering.cpp

llvm/lib/Target/XCore/XCoreRegisterInfo.cpp