[Draft] Make __builtin_cpu builtins target-independent

[nemanjai]

Summary

This is just a proposal patch for a possible direction we can extend these builtins to other targets as well as an implementation for PowerPC.

This adds a new instruction similar to LOAD_STACK_GUARD that is meant to load things from fixed addresses. The new instruction has semantics that are a superset of what LOAD_STACK_GUARD does so the two can be folded into one.

My hope with this patch is to collect feedback from the community about the direction, so please provide any feedback you may have.

[nemanjai]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1785

This probably deserves a comment along the lines of:

// Emit a reference to a symbol exported by versions of GLIBC
// that provide the HWCAP access. If a program built with this
// is run on a system with an old GLIBC, it should cause a
// load-time error rather than loading garbage.

[arsenm]

llvm/include/llvm/IR/Intrinsics.td

903–907

From this description I don't understand what this is supposed to do. What does the input mean? Why does this use an i32 immarg and not a pointer? Why is the result only i32?

905

I think a new intrinsic should be in a separate commit

llvm/include/llvm/Support/TargetOpcodes.def

148

Typo afixed

[nemanjai]

llvm/include/llvm/IR/Intrinsics.td

903–907

That is fair enough. The description is fairly vague. I can try to improve it as per below. The parameter for this is not a pointer (i.e. not an address). It is an immediate that represents the index into the enumeration of values that are provided at a fixed address. The back end is then free to produce the actual fixed address and the load itself.
The choice for the result type was admittedly arbitrary - on PPC, the values provided by GLIBC are 32-bit words.

Proposed comment describing this intrinsic:

// This intrinsic is provided to allow back ends to emit load
// instructions that load a value from a fixed address. The
// parameter to the intrinsic is not an address, but an
// immediate index into an enumeration that contains the
// union of all such values available on all back ends.
// An example is the HWCAP/HWCAP2/CPUID words
// provided by GLIBC on PowerPC to allow fast access
// to commonly used parts of AUXV. These are provided
// at a fixed offset into the TCB (accessible through the
// thread pointer).

905

Sounds good.

llvm/include/llvm/Support/TargetOpcodes.def

148

ACK

[ilinpv]

Thank you for the patch, it comes in the right time - we are also working on AArch64 __builtin_cpu_supports, and I was thinking how to make it more general.
I uploaded our RFC version for review https://reviews.llvm.org/D153153

It would be great to have in __builtin_cpu_supports argument string of plus-separated features. Just SemaBuiltinCpuSupports need to handle this.

[nemanjai]

In D152914#4428692, @ilinpv wrote:

Thank you for the patch, it comes in the right time - we are also working on AArch64 __builtin_cpu_supports, and I was thinking how to make it more general.
I uploaded our RFC version for review https://reviews.llvm.org/D153153

It would be great to have in __builtin_cpu_supports argument string of plus-separated features. Just SemaBuiltinCpuSupports need to handle this.

Hi Pavel,
I took a quick look at your patch. I think it would be preferable to make the builtins target-independent rather than implementing the builtin by the same name for multiple targets. Although I think it is very useful to support a plus-separated list for __builtin_cpu_supports(), I think that's probably something for a subsequent patch. We would need to figure out code generation for that - perhaps that part will have to be completely target specific.

[nemanjai]

@arsenm Has my description adequately addressed your question? Do you think we should move forward with [some version of] this patch or do you have any fundamental objections?

[arsenm]

llvm/include/llvm/IR/Intrinsics.td

903–907

This is baking an a very target specific implementation of device identification. Could you redefine this as something more abstract? Like returns a device ID integer, or a bool that some int input is supported?

[nemanjai]

llvm/include/llvm/IR/Intrinsics.td

903–907

The idea is for this to not be restricted to device ID at all, but to be used for any values that reside in a fixed address for the compiler. For example, STACK_GUARD can be one of the values. How about if the intrinsic returns any integer type (or maybe any type)?
My thinking is that there may be need in the future for various things to be loaded from fixed addresses. The list of possible things that can be loaded this way would be a union of what all targets want and only specific values would make sense on each target.

[arsenm]

llvm/include/llvm/IR/Intrinsics.td

903–907

But you're assuming there's a fixed address this can be loaded from, and not a read from a special register or some other mechanism

[ilinpv]

In D152914#4497599, @nemanjai wrote:

I took a quick look at your patch. I think it would be preferable to make the builtins target-independent rather than implementing the builtin by the same name for multiple targets. Although I think it is very useful to support a plus-separated list for __builtin_cpu_supports(), I think that's probably something for a subsequent patch. We would need to figure out code generation for that - perhaps that part will have to be completely target specific.

I fully agree with you to make __builtin_cpu_supports() target-independent ( and I will update my patch on top of yours ). If plus-separated format is not supported by all targets then I would suggest to make SemaBuiltinCpuSupports target-dependent - it allows to implement plus-separated format on AArch64 keeping __builtin_cpu_supports() target-independent.

[nemanjai]

llvm/include/llvm/IR/Intrinsics.td

903–907

Oh, well sure. My intent was just for those things that are in memory at a fixed address. But I suppose you're right, there is probably not a fundamental reason to restrict it to things at fixed addresses.

What I am trying to avoid here is defining an intrinsic that takes a specific value and returns a bool (i.e. the intrinsic version of __builtin_cpu_{supports|is}. The features/cpus will be different for every target and mapping features to integers is also target specific. So this was an attempt to implement an intrinsic that gets a value (bit vector if you will) that the target can choose how to lower and what to do with the value (i.e. how to mask it).

I suppose each target can define their own intrinsics for accessing CPU identification information since each target has to provide code generation for them anyway.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

6787

This should check useLoadFixedAddr().

[ilinpv]

llvm/include/llvm/IR/Intrinsics.td

903–907

I would not restrict targets to specific instrinsics for feature detection. Please notice that currently CPU identification is more complicated than HWCAPs, including reads from system registers. It is done in compiler-rt library (cpu_model.c), in init_cpu_features_resolver for AArch64 and getAvailableFeatures for X86.

[ilinpv]

Friendly ping, are there any questions remained to proceed with target-independent __builtin_cpu_supports ?

[nemanjai]

In D152914#4602914, @ilinpv wrote:

Friendly ping, are there any questions remained to proceed with target-independent __builtin_cpu_supports ?

Sorry, I have not gotten back to this review in quite some time as I have been relocating to a different country. I'll try to post an updated version of this on GitHub this weekend.

[lei]

HI @nemanjai, Did you get a chance to post this as a github PR?

[nemanjai]

In D152914#4653669, @lei wrote:

HI @nemanjai, Did you get a chance to post this as a github PR?

Long overdue, but I finally have it up at https://github.com/llvm/llvm-project/pull/68919

clang/include/clang/Basic/Builtins.def

 #if defined(BUILTIN) && !defined(LIBBUILTIN)
 #  define LIBBUILTIN(ID, TYPE, ATTRS, HEADER, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #if defined(BUILTIN) && !defined(LANGBUILTIN)
 #  define LANGBUILTIN(ID, TYPE, ATTRS, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+// Builtins for checking CPU features based on the GCC builtins.
+BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
+BUILTIN(__builtin_cpu_is, "bcC*", "nc")
+
 // Standard libc/libm functions:
 BUILTIN(__builtin_atan2 , "ddd"  , "Fne")
 BUILTIN(__builtin_atan2f, "fff"  , "Fne")
 BUILTIN(__builtin_atan2l, "LdLdLd", "Fne")
 BUILTIN(__builtin_atan2f128, "LLdLLdLLd", "Fne")
 BUILTIN(__builtin_abs  , "ii"  , "ncF")
 BUILTIN(__builtin_copysign, "ddd", "ncFE")
 BUILTIN(__builtin_copysignf, "fff", "ncFE")

clang/include/clang/Basic/BuiltinsX86.def

 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #if defined(BUILTIN) && !defined(TARGET_HEADER_BUILTIN)
 #  define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
-// Miscellaneous builtin for checking x86 cpu features.
 // TODO: Make this somewhat generic so that other backends
 // can use it?
 BUILTIN(__builtin_cpu_init, "v", "n")
-BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
-BUILTIN(__builtin_cpu_is, "bcC*", "nc")
 
 // Undefined Values
 //
 TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "")
 TARGET_BUILTIN(__builtin_ia32_undef256, "V4d", "ncV:256:", "")
 TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "")
 
 // FLAGS

clang/include/clang/Basic/TargetInfo.h

bool supportsMultiVersioning() const {
     return getTriple().isX86() || getTriple().isAArch64();
   }
 
   /// Identify whether this target supports IFuncs.
   bool supportsIFunc() const {
     return getTriple().isOSBinFormatELF() && !getTriple().isOSFuchsia();
   }
 
+  // Identify whether this target supports __builtin_cpu_supports and
+  // __builtin_cpu_is.
+  virtual bool supportsCpuSupports() const { return false; }
+  virtual bool supportsCpuIs() const { return false; }
+
   // Validate the contents of the __builtin_cpu_supports(const char*)
   // argument.
   virtual bool validateCpuSupports(StringRef Name) const { return false; }
 
   // Return the target-specific priority for features/cpus/vendors so
   // that they can be properly sorted for checking.
   virtual unsigned multiVersionSortPriority(StringRef Name) const {
     return 0;

clang/lib/Basic/Targets/PPC.h

public:
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
   const char *getIbm128Mangling() const override { return "g"; }
 
   bool hasBitIntType() const override { return true; }
 
   bool isSPRegName(StringRef RegName) const override {
     return RegName.equals("r1") || RegName.equals("x1");
   }
+  // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
+  // have GLIBC since it is GLIBC that provides the HWCAP[2] in the auxv.
+  bool supportsCpuSupports() const override { return getTriple().isOSGlibc(); }
+  bool supportsCpuIs() const override { return getTriple().isOSGlibc(); }
+  bool validateCpuSupports(StringRef Feature) const override;
+  bool validateCpuIs(StringRef Name) const override;
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
 public:
   PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : PPCTargetInfo(Triple, Opts) {
     if (Triple.isOSAIX())
       resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");

clang/lib/Basic/Targets/PPC.cpp

if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI &&
       HasQuadwordAtomics)
     MaxAtomicInlineWidth = 128;
 }
 
 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
   return llvm::ArrayRef(BuiltinInfo,
                         clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
+  return llvm::StringSwitch<bool>(FeatureStr)
+#include "llvm/TargetParser/PPCTargetParser.def"
+      .Default(false);
+}
+
+bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
+#define PPC_CPU(NAME, NUM) .Case(NAME, true)
+  return llvm::StringSwitch<bool>(CPUName)
+#include "llvm/TargetParser/PPCTargetParser.def"
+      .Default(false);
+}

clang/lib/Basic/Targets/X86.h

public:
   }
 
   ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
 
   bool isSPRegName(StringRef RegName) const override {
     return RegName.equals("esp") || RegName.equals("rsp");
   }
 
+  bool supportsCpuSupports() const override { return true; }
+
+  bool supportsCpuIs() const override { return true; }
+
   bool validateCpuSupports(StringRef FeatureStr) const override;
 
   bool validateCpuIs(StringRef FeatureStr) const override;
 
   bool validateCPUSpecificCPUDispatch(StringRef Name) const override;
 
   char CPUSpecificManglingCharacter(StringRef Name) const override;
 

clang/lib/CodeGen/CGBuiltin.cpp

 #include "clang/Basic/TargetBuiltins.h"
 #include "clang/Basic/TargetInfo.h"
 #include "clang/CodeGen/CGFunctionInfo.h"
 #include "clang/Frontend/FrontendDiagnostic.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsAArch64.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/IR/IntrinsicsBPF.h"
if (FeaturesMask != 0) {
     Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
     Result = Builder.CreateAnd(Result, Cmp);
   }
   return Result;
 }
 
 Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
                                            const CallExpr *E) {
-  if (BuiltinID == X86::BI__builtin_cpu_is)
+  if (BuiltinID == Builtin::BI__builtin_cpu_is)
     return EmitX86CpuIs(E);
-  if (BuiltinID == X86::BI__builtin_cpu_supports)
+  if (BuiltinID == Builtin::BI__builtin_cpu_supports)
     return EmitX86CpuSupports(E);
   if (BuiltinID == X86::BI__builtin_cpu_init)
     return EmitX86CpuInit();
 
   // Handle MSVC intrinsics before argument evaluation to prevent double
   // evaluation.
   if (std::optional<MSVCIntrin> MsvcIntId = translateX86ToMsvcIntrin(BuiltinID))
     return EmitMSVCBuiltinExpr(*MsvcIntId, E);
Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   switch (BuiltinID) {
   default: return nullptr;
 
   // __builtin_ppc_get_timebase is GCC 4.8+'s PowerPC-specific name for what we
   // call __builtin_readcyclecounter.
+  case Builtin::BI__builtin_cpu_is: {
+    const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+    StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
+    unsigned NumCPUID = StringSwitch<unsigned>(CPUStr)
+#define PPC_CPU(Name, NumericID) .Case(Name, NumericID)
+#include "llvm/TargetParser/PPCTargetParser.def"
+                            .Default(-1U);
+    Value *Op0 =
+        llvm::ConstantInt::get(Int32Ty, (unsigned)TargetLibraryInfo::FA_CPUID);
+    llvm::Function *F = CGM.getIntrinsic(Intrinsic::fixed_addr_ld);
+    Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_is");
+    return Builder.CreateICmpEQ(TheCall,
+                                llvm::ConstantInt::get(Int32Ty, NumCPUID));
+  }
+  case Builtin::BI__builtin_cpu_supports: {
+    unsigned FeatureWord;
+    unsigned BitMask;
+    const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+    StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
+    std::tie(FeatureWord, BitMask) =
+        StringSwitch<std::pair<unsigned, unsigned>>(CPUStr)
+#define PPC_FEATURE(Name, Description, EnumName, Bitmask, FA_WORD)             \
+  .Case(Name, {(unsigned)TargetLibraryInfo::FA_WORD, Bitmask})
+#include "llvm/TargetParser/PPCTargetParser.def"
+            .Default({0, 0});
+    Value *Op0 = llvm::ConstantInt::get(Int32Ty, FeatureWord);
+    llvm::Function *F = CGM.getIntrinsic(Intrinsic::fixed_addr_ld);
+    Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_supports");
+    Value *Mask =
+        Builder.CreateAnd(TheCall, llvm::ConstantInt::get(Int32Ty, BitMask));
+    return Builder.CreateICmpNE(Mask, llvm::Constant::getNullValue(Int32Ty));
+  }
   case PPC::BI__builtin_ppc_get_timebase:
     return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::readcyclecounter));
 
   // vec_ld, vec_xl_be, vec_lvsl, vec_lvsr
   case PPC::BI__builtin_altivec_lvx:
   case PPC::BI__builtin_altivec_lvxl:
   case PPC::BI__builtin_altivec_lvebx:
   case PPC::BI__builtin_altivec_lvehx:

clang/lib/Sema/SemaChecking.cpp

static bool checkFPMathBuiltinElementType(Sema &S, SourceLocation Loc,
   if (!EltTy->isRealFloatingType()) {
     return S.Diag(Loc, diag::err_builtin_invalid_arg_type)
            << ArgIndex << /* vector or float ty*/ 5 << ArgTy;
   }
 
   return false;
 }
 
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+                                   const TargetInfo *AuxTI, CallExpr *TheCall) {
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuSupports())
+    TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuSupports())
+    TheTI = AuxTI;
+  else
+    return S.Diag(TheCall->getBeginLoc(), diag::warn_builtin_unknown)
+           << "__builtin_cpu_supports";
+
+  // Check if the argument is a string literal.
+  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
+    return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+           << Arg->getSourceRange();
+
+  // Check the contents of the string.
+  StringRef Feature =
+      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
+  if (!TheTI->validateCpuSupports(Feature))
+    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
+           << Arg->getSourceRange();
+  return false;
+}
+
+/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
+/// This checks that the target supports __builtin_cpu_is and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI,
+                             const TargetInfo *AuxTI, CallExpr *TheCall) {
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuIs())
+    TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuIs())
+    TheTI = AuxTI;
+  else
+    return S.Diag(TheCall->getBeginLoc(), diag::warn_builtin_unknown)
+           << "__builtin_cpu_is";
+
+  // Check if the argument is a string literal.
+  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
+    return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+           << Arg->getSourceRange();
+
+  // Check the contents of the string.
+  StringRef Feature =
+      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
+  if (!TheTI->validateCpuIs(Feature))
+    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_is)
+           << Arg->getSourceRange();
+  return false;
+}
+
 ExprResult
 Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
                                CallExpr *TheCall) {
   ExprResult TheCallResult(TheCall);
 
   // Find out if any arguments are required to be integer constant expressions.
   unsigned ICEArguments = 0;
   ASTContext::GetBuiltinTypeError Error;
for (unsigned ArgNo = 0; ICEArguments != 0; ++ArgNo) {
     // diagnostic in checkArgCount(...)
     if (ArgNo < TheCall->getNumArgs() &&
         SemaBuiltinConstantArg(TheCall, ArgNo, Result))
       return true;
     ICEArguments &= ~(1 << ArgNo);
   }
 
   switch (BuiltinID) {
+  case Builtin::BI__builtin_cpu_supports:
+    if (SemaBuiltinCpuSupports(*this, Context.getTargetInfo(),
+                               Context.getAuxTargetInfo(), TheCall))
+      return ExprError();
+    break;
+  case Builtin::BI__builtin_cpu_is:
+    if (SemaBuiltinCpuIs(*this, Context.getTargetInfo(),
+                         Context.getAuxTargetInfo(), TheCall))
+      return ExprError();
+    break;
   case Builtin::BI__builtin___CFStringMakeConstantString:
     // CFStringMakeConstantString is currently not implemented for GOFF (i.e.,
     // on z/OS) and for XCOFF (i.e., on AIX). Emit unsupported
     if (CheckBuiltinTargetNotInUnsupported(
             *this, BuiltinID, TheCall,
             {llvm::Triple::GOFF, llvm::Triple::XCOFF}))
       return ExprError();
     assert(TheCall->getNumArgs() == 1 &&
bool Sema::CheckNVPTXBuiltinFunctionCall(const TargetInfo &TI,
   case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
   case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
     return checkArgCountAtMost(*this, TheCall, 3);
   }
 
   return false;
 }
 
-/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
-/// This checks that the target supports __builtin_cpu_supports and
-/// that the string argument is constant and valid.
-static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
-                                   CallExpr *TheCall) {
-  Expr *Arg = TheCall->getArg(0);
-
-  // Check if the argument is a string literal.
-  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
-           << Arg->getSourceRange();
-
-  // Check the contents of the string.
-  StringRef Feature =
-      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
-  if (!TI.validateCpuSupports(Feature))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
-           << Arg->getSourceRange();
-  return false;
-}
-
-/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
-/// This checks that the target supports __builtin_cpu_is and
-/// that the string argument is constant and valid.
-static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI, CallExpr *TheCall) {
-  Expr *Arg = TheCall->getArg(0);
-
-  // Check if the argument is a string literal.
-  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
-           << Arg->getSourceRange();
-
-  // Check the contents of the string.
-  StringRef Feature =
-      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
-  if (!TI.validateCpuIs(Feature))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_is)
-           << Arg->getSourceRange();
-  return false;
-}
-
 // Check if the rounding mode is legal.
 bool Sema::CheckX86BuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
   // Indicates if this instruction has rounding control or just SAE.
   bool HasRC = false;
 
   unsigned ArgNum = 0;
   switch (BuiltinID) {
   default:
case X86::BI__builtin_ia32_writeeflags_u32:
     return true;
   }
 
   return false;
 }
 
 bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
                                        CallExpr *TheCall) {
-  if (BuiltinID == X86::BI__builtin_cpu_supports)
-    return SemaBuiltinCpuSupports(*this, TI, TheCall);
-
-  if (BuiltinID == X86::BI__builtin_cpu_is)
-    return SemaBuiltinCpuIs(*this, TI, TheCall);
-
   // Check for 32-bit only builtins on a 64-bit target.
   const llvm::Triple &TT = TI.getTriple();
   if (TT.getArch() != llvm::Triple::x86 && isX86_32Builtin(BuiltinID))
     return Diag(TheCall->getCallee()->getBeginLoc(),
                 diag::err_32_bit_builtin_64_bit_tgt);
 
   // If the intrinsic has rounding or SAE make sure its valid.
   if (CheckX86BuiltinRoundingOrSAE(BuiltinID, TheCall))

clang/test/CodeGen/builtin-cpu-supports.c

-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-PPC
 
+#ifndef __PPC__
 // Test that we have the structure definition, the gep offsets, the name of the
 // global, the bit grab, and the icmp correct.
 extern void a(const char *);
 
-// CHECK: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
-// CHECK: @__cpu_features2 = external dso_local global i32
+// CHECK-X86: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
+// CHECK-X86: @__cpu_features2 = external dso_local global i32
 
 int main(void) {
   __builtin_cpu_init();
 
-  // CHECK: call void @__cpu_indicator_init
+  // CHECK-X86: call void @__cpu_indicator_init
 
   if (__builtin_cpu_supports("sse4.2"))
     a("sse4.2");
 
-  // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
-  // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
-  // CHECK: = icmp eq i32 [[AND]], 256
+// CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
+// CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
+// CHECK-X86: = icmp eq i32 [[AND]], 256
 
   if (__builtin_cpu_supports("gfni"))
     a("gfni");
 
-  // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
-  // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
-  // CHECK: = icmp eq i32 [[AND]], 1
+// CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
+// CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
+// CHECK-X86: = icmp eq i32 [[AND]], 1
 
   return 0;
 }
 
-// CHECK: declare dso_local void @__cpu_indicator_init()
+// CHECK-X86: declare dso_local void @__cpu_indicator_init()
+#else
+int test(int a) {
+// CHECK-PPC: [[CPUSUP:%[^ ]+]] = call i32 @llvm.fixed.addr.ld(i32 1)
+// CHECK-PPC: [[AND:%[^ ]+]] = and i32 [[CPUSUP]], 8388608
+// CHECK-PPC: icmp ne i32 [[AND]], 0
+// CHECK-PPC: [[CPUSUP2:%[^ ]+]] = call i32 @llvm.fixed.addr.ld(i32 0)
+// CHECK-PPC: [[AND2:%[^ ]+]] = and i32 [[CPUSUP2]], 67108864
+// CHECK-PPC: icmp ne i32 [[AND2]], 0
+// CHECK-PPC: [[CPUID:%[^ ]+]] = call i32 @llvm.fixed.addr.ld(i32 2)
+// CHECK-PPC: icmp eq i32 [[CPUID]], 39
+  if (__builtin_cpu_supports("arch_3_00")) // HWCAP2
+    return a;
+  else if (__builtin_cpu_supports("mmu"))  // HWCAP
+    return a - 5;
+  else if (__builtin_cpu_is("power7"))     // CPUID
+    return a + a;
+  return a + 5;
+}
+#endif

clang/test/Sema/builtin-cpu-supports.c

 // RUN: %clang_cc1 -fsyntax-only -triple x86_64-pc-linux-gnu -verify %s
-// RUN: %clang_cc1 -fsyntax-only -triple powerpc64le-linux-gnu -verify %s
+// RUN: %clang_cc1 -fsyntax-only -triple aarch64-linux-gnu -verify %s
 
 extern void a(const char *);
 
 extern const char *str;
 
 int main(void) {
 #ifdef __x86_64__
   if (__builtin_cpu_supports("ss")) // expected-error {{invalid cpu feature string}}
     a("sse4.2");
 
   if (__builtin_cpu_supports(str)) // expected-error {{expression is not a string literal}}
     a(str);
 
   if (__builtin_cpu_is("int")) // expected-error {{invalid cpu name for builtin}}
     a("intel");
 
   (void)__builtin_cpu_is("x86-64");    // expected-error {{invalid cpu name for builtin}}
   (void)__builtin_cpu_is("x86-64-v2"); // expected-error {{invalid cpu name for builtin}}
   (void)__builtin_cpu_is("x86-64-v3"); // expected-error {{invalid cpu name for builtin}}
   (void)__builtin_cpu_is("x86-64-v4"); // expected-error {{invalid cpu name for builtin}}
 #else
-  if (__builtin_cpu_supports("vsx")) // expected-error {{use of unknown builtin}}
-    a("vsx");
+  if (__builtin_cpu_supports("aes")) // expected-error {{use of unknown builtin}}
+    a("aes");
 
-  if (__builtin_cpu_is("pwr9")) // expected-error {{use of unknown builtin}}
-    a("pwr9");
+  if (__builtin_cpu_is("cortex-x3")) // expected-error {{use of unknown builtin}}
+    a("cortex-x3");
 #endif
 
   return 0;
 }

llvm/include/llvm/Analysis/TargetLibraryInfo.h

class TargetLibraryInfo {
   /// The global (module level) TLI info.
   const TargetLibraryInfoImpl *Impl;
 
   /// Support for -fno-builtin* options as function attributes, overrides
   /// information in global TargetLibraryInfoImpl.
   BitVector OverrideAsUnavailable;
 
 public:
+  /// Possible values provided by the system library at a fixed address. These
+  /// are values that are set up by the OS, system library or dynamic loader
+  /// that usually provide information about the CPU/System/Environment within
+  /// which the program is being executed.
+  enum FixedAddrType {
+    FA_HWCAP,  // The HWCAP word provided by libc.
+    FA_HWCAP2, // The HWCAP2 word provided by libc.
+    FA_CPUID   // The CPUID word (or string) provided by libc.
+  };
+
   explicit TargetLibraryInfo(const TargetLibraryInfoImpl &Impl,
                              std::optional<const Function *> F = std::nullopt)
       : Impl(&Impl), OverrideAsUnavailable(NumLibFuncs) {
     if (!F)
       return;
     if ((*F)->hasFnAttribute("no-builtins"))
       disableAllFunctions();
     else {

llvm/include/llvm/CodeGen/TargetLowering.h

 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
 #define LLVM_CODEGEN_TARGETLOWERING_H
 
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/CodeGen/ComplexDeinterleavingPass.h"
 #include "llvm/CodeGen/DAGCombine.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/LowLevelTypeUtils.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"

 class MachineInstr;
 class MachineJumpTableInfo;
 class MachineLoop;
 class MachineRegisterInfo;
 class MCContext;
 class MCExpr;
 class Module;
 class ProfileSummaryInfo;
-class TargetLibraryInfo;
 class TargetMachine;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 class TargetTransformInfo;
 class Value;
 
 namespace Sched {
 
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                              SDNode *Node) const;
 
   /// If this function returns true, SelectionDAGBuilder emits a
   /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
   virtual bool useLoadStackGuardNode() const {
     return false;
   }
 
+  /// If this function returns true, SelectionDAGBuilder emits a
+  /// LOAD_FIXED_ADDR for the particular value.
+  virtual bool useLoadFixedAddr(TargetLibraryInfo::FixedAddrType Type) const {
+    return false;
+  }
+
   virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
                                       const SDLoc &DL) const {
     llvm_unreachable("not implemented for this target");
   }
 
   /// Lower TLS global address SDNode for target independent emulated TLS model.
   virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
                                           SelectionDAG &DAG) const;

llvm/include/llvm/IR/Intrinsics.td

def int_experimental_noalias_scope_decl
     : DefaultAttrsIntrinsic<[], [llvm_metadata_ty],
         [IntrInaccessibleMemOnly]>; // blocks LICM and some more
 
 // Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
 // guard to the correct place on the stack frame.
 def int_stackprotector : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
 def int_stackguard : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], []>;
 
+// Load of a value provided by the system library at a fixed address. Used for
+// accessing things like HWCAP word provided by GLIBC.
+def int_fixed_addr_ld
+    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
+                            [IntrInaccessibleMemOnly, ImmArg<ArgIndex<0>>]>;
+
 // A cover for instrumentation based profiling.
 def int_instrprof_cover : Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty,
                                          llvm_i32_ty, llvm_i32_ty]>;
 
 // A counter increment for instrumentation based profiling.
 def int_instrprof_increment : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_i64_ty,
                                          llvm_i32_ty, llvm_i32_ty]>;

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(PATCHPOINT)
 
 /// This pseudo-instruction loads the stack guard value. Targets which need
 /// to prevent the stack guard value or address from being spilled to the
 /// stack should override TargetLowering::emitLoadStackGuardNode and
 /// additionally expand this pseudo after register allocation.
 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
 
+/// This pseudo-instruction loads a value provided by libc at afixed address.
+/// For example, GLIBC provides HWCAP, HWCAP2 and CPUID at a fixed address
+/// on some targets (for example PPC Linux).
+HANDLE_TARGET_OPCODE(LOAD_FIXED_ADDR)
+
 /// These are used to support call sites that must have the stack adjusted
 /// before the call (e.g. to initialize an argument passed by value).
 /// See llvm.call.preallocated.{setup,arg} in the LangRef for more details.
 HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP)
 HANDLE_TARGET_OPCODE(PREALLOCATED_ARG)
 
 /// Call instruction with associated vm state for deoptimization and list
 /// of live pointers for relocation by the garbage collector.  It is

llvm/include/llvm/Target/Target.td

 def LOAD_STACK_GUARD : StandardPseudoInstruction {
   let OutOperandList = (outs ptr_rc:$dst);
   let InOperandList = (ins);
   let mayLoad = true;
   bit isReMaterializable = true;
   let hasSideEffects = false;
   bit isPseudo = true;
 }
+def LOAD_FIXED_ADDR : StandardPseudoInstruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins i32imm:$a);
+  let mayLoad = true;
+  bit isReMaterializable = true;
+  let hasSideEffects = false;
+  bit isPseudo = true;
+}
 def PREALLOCATED_SETUP : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$a);
   let usesCustomInserter = true;
   let hasSideEffects = true;
 }
 def PREALLOCATED_ARG : StandardPseudoInstruction {
   let OutOperandList = (outs ptr_rc:$loc);

llvm/include/llvm/TargetParser/PPCTargetParser.def

+#ifndef PPC_FEATURE
+#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN)
+#endif
+#ifndef PPC_CPU
+#define PPC_CPU(NAME, NUM)
+#endif
+
+// PPC_FEATURE(Name, Description, EnumName, BitMask, FA_WORD)
+PPC_FEATURE("4xxmac","4xx CPU has a Multiply Accumulator",PPCF_4XXMAC,0x02000000,FA_HWCAP)
+PPC_FEATURE("altivec","CPU has a SIMD/Vector Unit",PPCF_ALTIVEC,0x10000000,FA_HWCAP)
+PPC_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",PPCF_ARCH205,0x00001000,FA_HWCAP)
+PPC_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",PPCF_ARCH206,0x00000100,FA_HWCAP)
+PPC_FEATURE("arch_2_07","CPU supports ISA 207 (eg, POWER8)",PPCF_ARCH207,0x80000000,FA_HWCAP2)
+PPC_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",PPCF_ARCH30,0x00800000,FA_HWCAP2)
+PPC_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",PPCF_ARCH31,0x00040000,FA_HWCAP2)
+PPC_FEATURE("archpmu","CPU supports the set of compatible performance monitoring events",PPCF_ARCHPMU,0x00000040,FA_HWCAP)
+PPC_FEATURE("booke","CPU supports the Embedded ISA category",PPCF_BOOKE,0x00008000,FA_HWCAP)
+PPC_FEATURE("cellbe","CPU has a CELL broadband engine",PPCF_CELLBE,0x00010000,FA_HWCAP)
+PPC_FEATURE("darn","CPU supports the darn (deliver a random number) instruction",PPCF_DARN,0x00200000,FA_HWCAP2)
+PPC_FEATURE("dfp","CPU has a decimal floating point unit",PPCF_DFP,0x00000400,FA_HWCAP)
+PPC_FEATURE("dscr","CPU supports the data stream control register",PPCF_DSCR,0x20000000,FA_HWCAP2)
+PPC_FEATURE("ebb","CPU supports event base branching",PPCF_EBB,0x10000000,FA_HWCAP2)
+PPC_FEATURE("efpdouble","CPU has a SPE double precision floating point unit",PPCF_EFPDOUBLE,0x00200000,FA_HWCAP)
+PPC_FEATURE("efpsingle","CPU has a SPE single precision floating point unit",PPCF_EFPSINGLE,0x00400000,FA_HWCAP)
+PPC_FEATURE("fpu","CPU has a floating point unit",PPCF_FPU,0x08000000,FA_HWCAP)
+PPC_FEATURE("htm","CPU has hardware transaction memory instructions",PPCF_HTM,0x40000000,FA_HWCAP2)
+PPC_FEATURE("htm-nosc","Kernel aborts hardware transactions when a syscall is made",PPCF_HTM_NOSC,0x01000000,FA_HWCAP2)
+PPC_FEATURE("htm-no-suspend","CPU supports hardware transaction memory but does not support the tsuspend instruction.",PPCF_HTM_NO_SUSPEND,0x00080000,FA_HWCAP2)
+PPC_FEATURE("ic_snoop","CPU supports icache snooping capabilities",PPCF_IC_SNOOP,0x00002000,FA_HWCAP)
+PPC_FEATURE("ieee128","CPU supports 128-bit IEEE binary floating point instructions",PPCF_IEEE128,0x00400000,FA_HWCAP2)
+PPC_FEATURE("isel","CPU supports the integer select instruction",PPCF_ISEL,0x08000000,FA_HWCAP2)
+PPC_FEATURE("mma","CPU supports the matrix-multiply assist instructions",PPCF_MMA,0x00020000,FA_HWCAP2)
+PPC_FEATURE("mmu","CPU has a memory management unit",PPCF_MMU,0x04000000,FA_HWCAP)
+PPC_FEATURE("notb","CPU does not have a timebase (eg, 601 and 403gx)",PPCF_NOTB,0x00100000,FA_HWCAP)
+PPC_FEATURE("pa6t","CPU supports the PA Semi 6T CORE ISA",PPCF_PA6T,0x00000800,FA_HWCAP)
+PPC_FEATURE("power4","CPU supports ISA 200 (eg, POWER4)",PPCF_POWER4,0x00080000,FA_HWCAP)
+PPC_FEATURE("power5","CPU supports ISA 202 (eg, POWER5)",PPCF_POWER5,0x00040000,FA_HWCAP)
+PPC_FEATURE("power5+","CPU supports ISA 203 (eg, POWER5+)",PPCF_POWER5P,0x00020000,FA_HWCAP)
+PPC_FEATURE("power6x","CPU supports ISA 205 (eg, POWER6) extended opcodes mffgpr and mftgpr.",PPCF_POWER6X,0x00000200,FA_HWCAP)
+PPC_FEATURE("ppc32","CPU supports 32-bit mode execution",PPCF_PPC32,0x80000000,FA_HWCAP)
+PPC_FEATURE("ppc601","CPU supports the old POWER ISA (eg, 601)",PPCF_PPC601,0x20000000,FA_HWCAP)
+PPC_FEATURE("ppc64","CPU supports 64-bit mode execution",PPCF_PPC64,0x40000000,FA_HWCAP)
+PPC_FEATURE("ppcle","CPU supports a little-endian mode that uses address swizzling",PPCF_PPCLE,0x00000001,FA_HWCAP)
+PPC_FEATURE("scv","Kernel supports system call vectored",PPCF_SCV,0x00100000,FA_HWCAP2)
+PPC_FEATURE("smt","CPU support simultaneous multi-threading",PPCF_SMT,0x00004000,FA_HWCAP)
+PPC_FEATURE("spe","CPU has a signal processing extension unit",PPCF_SPE,0x00800000,FA_HWCAP)
+PPC_FEATURE("tar","CPU supports the target address register",PPCF_TAR,0x04000000,FA_HWCAP2)
+PPC_FEATURE("true_le","CPU supports true little-endian mode",PPCF_TRUE_LE,0x00000002,FA_HWCAP)
+PPC_FEATURE("ucache","CPU has unified I/D cache",PPCF_UCACHE,0x01000000,FA_HWCAP)
+PPC_FEATURE("vcrypto","CPU supports the vector cryptography instructions",PPCF_VCRYPTO,0x02000000,FA_HWCAP2)
+PPC_FEATURE("vsx","CPU supports the vector-scalar extension",PPCF_VSX,0x00000080,FA_HWCAP)
+
+// PPC_CPU(Name, NumericID)
+PPC_CPU("power4",32)
+PPC_CPU("ppc970",33)
+PPC_CPU("power5",34)
+PPC_CPU("power5+",35)
+PPC_CPU("power6",36)
+PPC_CPU("ppc-cell-be",37)
+PPC_CPU("power6x",38)
+PPC_CPU("power7",39)
+PPC_CPU("ppca2",40)
+PPC_CPU("ppc405",41)
+PPC_CPU("ppc440",42)
+PPC_CPU("ppc464",43)
+PPC_CPU("ppc476",44)
+PPC_CPU("power8",45)
+PPC_CPU("power9",46)
+PPC_CPU("power10",47)
+#undef PPC_FEATURE
+#undef PPC_CPU

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

MachineMemOperand *MemRef = MF.getMachineMemOperand(
         MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy));
     DAG.setNodeMemRefs(Node, {MemRef});
   }
   if (PtrTy != PtrMemTy)
     return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy);
   return SDValue(Node, 0);
 }
 
+/// Create a LOAD_FIXED_ADDR node, and let it carry the target specific global
+/// variable if there exists one.
+static SDValue getLoadFixedAddr(SelectionDAG &DAG, const SDLoc &DL,
+                                SDValue &Chain,
+                                TargetLibraryInfo::FixedAddrType Type) {
+  MachineSDNode *Node =
+      DAG.getMachineNode(TargetOpcode::LOAD_FIXED_ADDR, DL, MVT::i32,
+                         DAG.getTargetConstant(Type, DL, MVT::i32), Chain);
+  return SDValue(Node, 0);
+}
+
 /// Codegen a new tail for a stack protector check ParentMBB which has had its
 /// tail spliced into a stack protector check success bb.
 ///
 /// For a high level explanation of how this fits into the stack protector
 /// generation see the comment on the declaration of class
 /// StackProtectorDescriptor.
 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
                                                   MachineBasicBlock *ParentBB) {
case Intrinsic::stackprotector: {
     Res = DAG.getStore(
         Chain, sdl, Src, FIN,
         MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
         MaybeAlign(), MachineMemOperand::MOVolatile);
     setValue(&I, Res);
     DAG.setRoot(Res);
     return;
   }
+  case Intrinsic::fixed_addr_ld: {
+    SDValue Chain = getRoot();
+    uint64_t ConstArg = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
+    Res = getLoadFixedAddr(DAG, sdl, Chain,
+                           (TargetLibraryInfo::FixedAddrType)ConstArg);
+    DAG.setRoot(Chain);
+    setValue(&I, Res);
+    return;
+  }
   case Intrinsic::objectsize:
     llvm_unreachable("llvm.objectsize.* should have been lowered already");
 
   case Intrinsic::is_constant:
     llvm_unreachable("llvm.is.constant.* should have been lowered already");
 
   case Intrinsic::annotation:
   case Intrinsic::ptr_annotation:

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 void PPCLinuxAsmPrinter::emitEndOfAsmFile(Module &M) {
   const DataLayout &DL = getDataLayout();
 
   bool isPPC64 = DL.getPointerSizeInBits() == 64;
 
   PPCTargetStreamer *TS =
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
 
+  if (static_cast<const PPCTargetMachine &>(TM).hasGlibcHWCAPAccess())
+    OutStreamer->emitSymbolValue(
+        GetExternalSymbolSymbol("__parse_hwcap_and_convert_at_platform"),
+        MAI->getCodePointerSize());
   emitGNUAttributes(M);
 
   if (!TOC.empty()) {
     const char *Name = isPPC64 ? ".toc" : ".got2";
     MCSectionELF *Section = OutContext.getELFSection(
         Name, ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC);
     OutStreamer->switchSection(Section);
     if (!isPPC64)

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
 
     /// If a physical register, this returns the register that receives the
     /// exception typeid on entry to a landing pad.
     Register
     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 
     /// Override to support customized stack guard loading.
     bool useLoadStackGuardNode() const override;
+    bool useLoadFixedAddr(TargetLibraryInfo::FixedAddrType Type) const override;
     void insertSSPDeclarations(Module &M) const override;
     Value *getSDagStackGuard(const Module &M) const override;
 
     bool isFPImmLegal(const APFloat &Imm, EVT VT,
                       bool ForCodeSize) const override;
 
     unsigned getJumpTableEncoding() const override;
     bool isJumpTableRelative() const override;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

   if (Subtarget.has64BitSupport())
     setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
 
   if (Subtarget.isISA3_1())
     setOperationAction(ISD::SRA, MVT::v1i128, Legal);
 
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
 
+  setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Legal);
+  setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Legal);
   if (!isPPC64) {
     setOperationAction(ISD::ATOMIC_LOAD,  MVT::i64, Expand);
     setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
   }
 
   if (shouldInlineQuadwordAtomics()) {
     setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
     setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);

 
 // Override to enable LOAD_STACK_GUARD lowering on Linux.
 bool PPCTargetLowering::useLoadStackGuardNode() const {
   if (!Subtarget.isTargetLinux())
     return TargetLowering::useLoadStackGuardNode();
   return true;
 }
 
+// Enable LOAD_FIXED_ADDR for the values that are available from
+// libc.
+bool PPCTargetLowering::useLoadFixedAddr(
+    TargetLibraryInfo::FixedAddrType Type) const {
+  if (!Subtarget.isTargetGlibc())
+    return false;
+
+  switch (Type) {
+  case TargetLibraryInfo::FA_HWCAP:
+  case TargetLibraryInfo::FA_HWCAP2:
+  case TargetLibraryInfo::FA_CPUID:
+    return true;
+  }
+  return false;
+}
+
 // Override to disable global variable loading on Linux and insert AIX canary
 // word declaration.
 void PPCTargetLowering::insertSSPDeclarations(Module &M) const {
   if (Subtarget.isAIXABI()) {
     M.getOrInsertGlobal(AIXSSPCanaryWordName,
                         Type::getInt8PtrTy(M.getContext()));
     return;
   }

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isReallyTriviallyReMaterializable(
   case PPC::PLI:
   case PPC::PLI8:
   case PPC::LIS:
   case PPC::LIS8:
   case PPC::ADDIStocHA:
   case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
+  case PPC::LOAD_FIXED_ADDR:
   case PPC::XXLXORz:
   case PPC::XXLXORspz:
   case PPC::XXLXORdpz:
   case PPC::XXLEQVOnes:
   case PPC::XXSPLTI32DX:
   case PPC::XXSPLTIW:
   case PPC::XXSPLTIDP:
   case PPC::V_SET0B:
case TargetOpcode::LOAD_STACK_GUARD: {
     const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
     const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
     MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addImm(Offset)
         .addReg(Reg);
     return true;
   }
+  case TargetOpcode::LOAD_FIXED_ADDR: {
+    assert(Subtarget.isTargetLinux() &&
+           "Only Linux target is expected to contain LOAD_FIXED_ADDR");
+    int64_t Offset = 0;
+    const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
+    MI.setDesc(get(PPC::LWZ));
+    uint64_t FAType = MI.getOperand(1).getImm();
+    // The HWCAP and HWCAP2 word offsets are reversed on big endian Linux.
+    if ((FAType == TargetLibraryInfo::FA_HWCAP && Subtarget.isLittleEndian()) ||
+        (FAType == TargetLibraryInfo::FA_HWCAP2 && !Subtarget.isLittleEndian()))
+      Offset = Subtarget.isPPC64() ? -0x7064 : -0x703C;
+    else if ((FAType == TargetLibraryInfo::FA_HWCAP2 &&
+              Subtarget.isLittleEndian()) ||
+             (FAType == TargetLibraryInfo::FA_HWCAP &&
+              !Subtarget.isLittleEndian()))
+      Offset = Subtarget.isPPC64() ? -0x7068 : -0x7040;
+    else if (FAType == TargetLibraryInfo::FA_CPUID)
+      Offset = Subtarget.isPPC64() ? -0x705C : -0x7034;
+    assert(Offset && "Do not know the offset for this fixed addr load");
+    MI.removeOperand(1);
+    Subtarget.getTargetMachine().setGlibcHWCAPAccess();
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+        .addImm(Offset)
+        .addReg(Reg);
+    return true;
+  }
   case PPC::DFLOADf32:
   case PPC::DFLOADf64:
   case PPC::DFSTOREf32:
   case PPC::DFSTOREf64: {
     assert(Subtarget.hasP9Vector() &&
            "Invalid D-Form Pseudo-ops on Pre-P9 target.");
     assert(MI.getOperand(2).isReg() &&
            isAnImmediateOperand(MI.getOperand(1)) &&

llvm/lib/Target/PowerPC/PPCSubtarget.h

#include "PPCGenSubtargetInfo.inc"
 
   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
+  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
 
   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
   bool isSVR4ABI() const { return !isAIXABI(); }
   bool isELFv2ABI() const;
 
   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
   bool isUsingPCRelativeCalls() const;

llvm/lib/Target/PowerPC/PPCTargetMachine.h

 public:
   enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 };
   enum Endian { NOT_DETECTED, LITTLE, BIG };
 
 private:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   PPCABI TargetABI;
   Endian Endianness = Endian::NOT_DETECTED;
+  mutable bool HasGlibcHWCAPAccess = false;
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    std::optional<Reloc::Model> RM,
                    std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 
   MachineFunctionInfo *
   createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
                             const TargetSubtargetInfo *STI) const override;
 
   bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
+  bool hasGlibcHWCAPAccess() const { return HasGlibcHWCAPAccess; }
+  void setGlibcHWCAPAccess(bool Val = true) const { HasGlibcHWCAPAccess = Val; }
   bool isPPC64() const {
     const Triple &TT = getTargetTriple();
     return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
   };
 
   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
     // Addrspacecasts are always noops.
     return true;

llvm/test/CodeGen/PowerPC/cpu-supports.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
+; RUN:   -mtriple=powerpc64-linux-gnu < %s | FileCheck  %s \
+; RUN:   -check-prefix=BE64
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
+; RUN:   -mtriple=powerpc-linux-gnu < %s | FileCheck  %s \
+; RUN:   -check-prefix=BE32
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
+; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck  %s \
+; RUN:   -check-prefix=LE
+define dso_local signext i32 @test(i32 noundef signext %a) local_unnamed_addr #0 {
+; BE64-LABEL: test:
+; BE64:       # %bb.0: # %entry
+; BE64-NEXT:    lwz r4, -28772(r13)
+; BE64-NEXT:    andis. r4, r4, 128
+; BE64-NEXT:    bne cr0, .LBB0_3
+; BE64-NEXT:  # %bb.1: # %if.else
+; BE64-NEXT:    lwz r4, -28776(r13)
+; BE64-NEXT:    andis. r4, r4, 1024
+; BE64-NEXT:    bne cr0, .LBB0_4
+; BE64-NEXT:  # %bb.2: # %if.else3
+; BE64-NEXT:    lwz r4, -28764(r13)
+; BE64-NEXT:    cmplwi r4, 39
+; BE64-NEXT:    addi r4, r3, 5
+; BE64-NEXT:    slwi r3, r3, 1
+; BE64-NEXT:    iseleq r3, r3, r4
+; BE64-NEXT:  .LBB0_3: # %return
+; BE64-NEXT:    extsw r3, r3
+; BE64-NEXT:    blr
+; BE64-NEXT:  .LBB0_4: # %if.then2
+; BE64-NEXT:    addi r3, r3, -5
+; BE64-NEXT:    extsw r3, r3
+; BE64-NEXT:    blr
+;
+; BE32-LABEL: test:
+; BE32:       # %bb.0: # %entry
+; BE32-NEXT:    lwz r4, -28732(r2)
+; BE32-NEXT:    andis. r4, r4, 128
+; BE32-NEXT:    bnelr cr0
+; BE32-NEXT:  # %bb.1: # %if.else
+; BE32-NEXT:    lwz r4, -28736(r2)
+; BE32-NEXT:    andis. r4, r4, 1024
+; BE32-NEXT:    bne cr0, .LBB0_3
+; BE32-NEXT:  # %bb.2: # %if.else3
+; BE32-NEXT:    lwz r4, -28724(r2)
+; BE32-NEXT:    cmplwi r4, 39
+; BE32-NEXT:    addi r4, r3, 5
+; BE32-NEXT:    slwi r3, r3, 1
+; BE32-NEXT:    iseleq r3, r3, r4
+; BE32-NEXT:    blr
+; BE32-NEXT:  .LBB0_3: # %if.then2
+; BE32-NEXT:    addi r3, r3, -5
+; BE32-NEXT:    blr
+;
+; LE-LABEL: test:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    lwz r4, -28776(r13)
+; LE-NEXT:    andis. r4, r4, 128
+; LE-NEXT:    bne cr0, .LBB0_3
+; LE-NEXT:  # %bb.1: # %if.else
+; LE-NEXT:    lwz r4, -28772(r13)
+; LE-NEXT:    andis. r4, r4, 1024
+; LE-NEXT:    bne cr0, .LBB0_4
+; LE-NEXT:  # %bb.2: # %if.else3
+; LE-NEXT:    lwz r4, -28764(r13)
+; LE-NEXT:    cmplwi r4, 39
+; LE-NEXT:    addi r4, r3, 5
+; LE-NEXT:    slwi r3, r3, 1
+; LE-NEXT:    iseleq r3, r3, r4
+; LE-NEXT:  .LBB0_3: # %return
+; LE-NEXT:    extsw r3, r3
+; LE-NEXT:    blr
+; LE-NEXT:  .LBB0_4: # %if.then2
+; LE-NEXT:    addi r3, r3, -5
+; LE-NEXT:    extsw r3, r3
+; LE-NEXT:    blr
+entry:
+  %cpu_supports = tail call i32 @llvm.fixed.addr.ld(i32 1)
+  %0 = and i32 %cpu_supports, 8388608
+  %.not = icmp eq i32 %0, 0
+  br i1 %.not, label %if.else, label %return
+
+if.else:                                          ; preds = %entry
+  %cpu_supports1 = tail call i32 @llvm.fixed.addr.ld(i32 0)
+  %1 = and i32 %cpu_supports1, 67108864
+  %.not12 = icmp eq i32 %1, 0
+  br i1 %.not12, label %if.else3, label %if.then2
+
+if.then2:                                         ; preds = %if.else
+  %sub = add nsw i32 %a, -5
+  br label %return
+
+if.else3:                                         ; preds = %if.else
+  %cpu_is = tail call i32 @llvm.fixed.addr.ld(i32 2)
+  %2 = icmp eq i32 %cpu_is, 39
+  br i1 %2, label %if.then4, label %if.end6
+
+if.then4:                                         ; preds = %if.else3
+  %add = shl nsw i32 %a, 1
+  br label %return
+
+if.end6:                                          ; preds = %if.else3
+  %add7 = add nsw i32 %a, 5
+  br label %return
+
+return:                                           ; preds = %entry, %if.end6, %if.then4, %if.then2
+  %retval.0 = phi i32 [ %sub, %if.then2 ], [ %add, %if.then4 ], [ %add7, %if.end6 ], [ %a, %entry ]
+  ret i32 %retval.0
+}
+
+declare i32 @llvm.fixed.addr.ld(i32 immarg) #1