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Differential D152421

[RISCV] Introduce the concept of DLEN(data path width) into getLMULCost.
ClosedPublic

Authored by craig.topper on Jun 7 2023, 10:24 PM.

Details

Reviewers
reames
arcbbb
luke
frasercrmck
rogfer01
kito-cheng
Commits
rG6ac2ce7d844c: [RISCV] Introduce the concept of DLEN(data path width) into getLMULCost.
Summary

SiFive's x280 CPU has a vector unit that VLEN/2 bits wide. This
means that LMUL=1 operations take 2 to process all VLEN bits.

This patch adds a DLenFactor tuning parameter and applies it to
TuneSiFive7. getLMULCost has been updated to use this factor in
its calculations. I've added an x280 command line to one cost
model test to demonstrate the effect.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 7 2023, 10:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 7 2023, 10:24 PM
Herald added subscribers: jobnoorman, VincentWu, vkmr and 24 others. · View Herald Transcript
craig.topper requested review of this revision.Jun 7 2023, 10:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 7 2023, 10:24 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B237423: Diff 529504.Jun 7 2023, 11:14 PM
arcbbb accepted this revision.Jun 8 2023, 12:51 AM

LGTM.
The relevant information regarding the 256b ALU pipe can be found in the following link: https://www.sifive.com/cores/intelligence-x280.

This revision is now accepted and ready to land.Jun 8 2023, 12:51 AM
asb added a comment.Jun 12 2023, 7:54 AM

LGTM after you add a doc comment to getDLenFactor.

llvm/lib/Target/RISCV/RISCVSubtarget.h
182

I think we need a comment here to explain the purpose of the method.

reames added inline comments.Jun 12 2023, 7:56 AM
llvm/lib/Target/RISCV/RISCVFeatures.td
808

Can you add a comment here which defines DLEN?

As an organizing principle, I was a bit surprised by the factor description. I was expecting something more along the lines of VLEN (zvlNb) where we have specific sizes and then computed the factor from VLEN/DLEN if needed. Not objecting, just commenting.

835

The default tuning is used for more than the x280, are you sure you want this placement?

llvm/lib/Target/RISCV/RISCVSubtarget.h
182

Needs a comment, and/or a link back to the DLEN definition.

craig.topper added inline comments.Jun 12 2023, 9:51 AM
llvm/lib/Target/RISCV/RISCVFeatures.td
808

Having it as a factor removes the possibility of DLEN > VLEN. It also avoids having one number come from march and one from mtune.

SiFive has 2 CPUs, x280 and p270l, base on the same microarchitecture with different VLEN and DLEN but the factor is 2 for both.

835

We have 2 vector CPUs based on the 7 series microarchitecture. We just haven't put the other in LLVM. They both have factor of 2. So that's what I was thinking when I put this here, but I think I'll move it to x280.

craig.topper planned changes to this revision.Jun 12 2023, 9:51 AM
reames added inline comments.Jun 12 2023, 10:21 AM
llvm/lib/Target/RISCV/RISCVFeatures.td
808

Both pieces make sense, the existence of the sole additional vector cpu with the same property was the context I was missing.

If you want to simply update the comments, I'm fine with the structure given the additional info.

craig.topper updated this revision to Diff 530751.Jun 12 2023, 7:17 PM

Add comments

This revision is now accepted and ready to land.Jun 12 2023, 7:17 PM
Harbormaster completed remote builds in B238375: Diff 530751.Jun 12 2023, 9:08 PM
Closed by commit rG6ac2ce7d844c: [RISCV] Introduce the concept of DLEN(data path width) into getLMULCost. (authored by craig.topper). · Explain WhyJun 13 2023, 4:09 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG6ac2ce7d844c: [RISCV] Introduce the concept of DLEN(data path width) into getLMULCost..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
7 lines
3 lines
8 lines
8 lines
test/
Analysis/
CostModel/
RISCV/
381 lines

Diff 531106

llvm/lib/Target/RISCV/RISCVFeatures.td

Show First 20 Lines • Show All 799 Lines • ▼ Show 20 Lines : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
"true", "Has reasonably performant unaligned vector " "true", "Has reasonably performant unaligned vector "
"loads and stores">; "loads and stores">;
def TuneNoOptimizedZeroStrideLoad def TuneNoOptimizedZeroStrideLoad
: SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad", : SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
"false", "Hasn't optimized (perform fewer memory operations)" "false", "Hasn't optimized (perform fewer memory operations)"
"zero-stride vector load">; "zero-stride vector load">;
// Some vector hardware implementations do not process all VLEN bits in parallel
reamesUnsubmitted
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Can you add a comment here which defines DLEN?

As an organizing principle, I was a bit surprised by the factor description. I was expecting something more along the lines of VLEN (zvlNb) where we have specific sizes and then computed the factor from VLEN/DLEN if needed. Not objecting, just commenting.

reames: Can you add a comment here which defines DLEN? As an organizing principle, I was a bit…
craig.topperAuthorUnsubmitted
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Having it as a factor removes the possibility of DLEN > VLEN. It also avoids having one number come from march and one from mtune.

SiFive has 2 CPUs, x280 and p270l, base on the same microarchitecture with different VLEN and DLEN but the factor is 2 for both.

craig.topper: Having it as a factor removes the possibility of DLEN > VLEN. It also avoids having one number…
reamesUnsubmitted
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Both pieces make sense, the existence of the sole additional vector cpu with the same property was the context I was missing.

If you want to simply update the comments, I'm fine with the structure given the additional info.

reames: Both pieces make sense, the existence of the sole additional vector cpu with the same property…
// and instead split over multiple cycles. DLEN refers to the datapath width
// that can be done in parallel.
def TuneDLenFactor2
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
"Vector unit DLEN(data path width) is half of VLEN">;
def TuneLUIADDIFusion def TuneLUIADDIFusion
: SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion", : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
"true", "Enable LUI+ADDI macrofusion">; "true", "Enable LUI+ADDI macrofusion">;
def TuneNoDefaultUnroll def TuneNoDefaultUnroll
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
"Disable default unroll preference.">; "Disable default unroll preference.">;
// SiFive 7 is able to fuse integer ALU operations with a preceding branch // SiFive 7 is able to fuse integer ALU operations with a preceding branch
// instruction. // instruction.
def TuneShortForwardBranchOpt def TuneShortForwardBranchOpt
: SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt", : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
"true", "Enable short forward branch optimization">; "true", "Enable short forward branch optimization">;
def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors", "SiFive 7-Series processors",
[TuneNoDefaultUnroll, [TuneNoDefaultUnroll,
TuneShortForwardBranchOpt]>; TuneShortForwardBranchOpt]>;
reamesUnsubmitted
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The default tuning is used for more than the x280, are you sure you want this placement?

reames: The default tuning is used for more than the x280, are you sure you want this placement?
craig.topperAuthorUnsubmitted
Done
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We have 2 vector CPUs based on the 7 series microarchitecture. We just haven't put the other in LLVM. They both have factor of 2. So that's what I was thinking when I put this here, but I think I'll move it to x280.

craig.topper: We have 2 vector CPUs based on the 7 series microarchitecture. We just haven't put the other in…
// Assume that lock-free native-width atomics are available, even if the target // Assume that lock-free native-width atomics are available, even if the target
// and operating system combination would not usually provide them. The user // and operating system combination would not usually provide them. The user
// is responsible for providing any necessary __sync implementations. Code // is responsible for providing any necessary __sync implementations. Code
// built with this feature is not ABI-compatible with code built without this // built with this feature is not ABI-compatible with code built without this
// feature, if atomic variables are exposed across the ABI boundary. // feature, if atomic variables are exposed across the ABI boundary.
def FeatureForcedAtomics : SubtargetFeature< def FeatureForcedAtomics : SubtargetFeature<
"forced-atomics", "HasForcedAtomics", "true", "forced-atomics", "HasForcedAtomics", "true",
"Assume that lock-free native-width atomics are available">; "Assume that lock-free native-width atomics are available">;
def HasAtomicLdSt def HasAtomicLdSt
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">; : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals", "AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global " "true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">; "that allows a memory tag in the upper address bits">;

llvm/lib/Target/RISCV/RISCVProcessors.td

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Linesdef SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
FeatureStdExtD, FeatureStdExtD,
FeatureStdExtC, FeatureStdExtC,
FeatureStdExtV, FeatureStdExtV,
FeatureStdExtZvl512b, FeatureStdExtZvl512b,
FeatureStdExtZfh, FeatureStdExtZfh,
FeatureStdExtZvfh, FeatureStdExtZvfh,
FeatureStdExtZba, FeatureStdExtZba,
FeatureStdExtZbb], FeatureStdExtZbb],
[TuneSiFive7]>; [TuneSiFive7,
TuneDLenFactor2]>;
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model, SyntacoreSCR1Model,
[Feature32Bit, [Feature32Bit,
FeatureStdExtZicsr, FeatureStdExtZicsr,
FeatureStdExtZifencei, FeatureStdExtZifencei,
FeatureStdExtC], FeatureStdExtC],
[TuneNoDefaultUnroll]>; [TuneNoDefaultUnroll]>;
Show All 9 Lines

llvm/lib/Target/RISCV/RISCVSubtarget.h

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines#include "RISCVGenSubtargetInfo.inc"
bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
// F16 and F64 both require F32. // F16 and F64 both require F32.
bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
bool hasVInstructionsFullMultiply() const { return HasStdExtV; } bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
unsigned getMaxInterleaveFactor() const { unsigned getMaxInterleaveFactor() const {
return hasVInstructions() ? MaxInterleaveFactor : 1; return hasVInstructions() ? MaxInterleaveFactor : 1;
} }
// Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
asbUnsubmitted
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I think we need a comment here to explain the purpose of the method.

asb: I think we need a comment here to explain the purpose of the method.
reamesUnsubmitted
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Needs a comment, and/or a link back to the DLEN definition.

reames: Needs a comment, and/or a link back to the DLEN definition.
// vector hardware implementation which may be less than VLEN.
unsigned getDLenFactor() const {
if (DLenFactor2)
return 2;
return 1;
}
protected: protected:
// GlobalISel related APIs. // GlobalISel related APIs.
std::unique_ptr<CallLowering> CallLoweringInfo; std::unique_ptr<CallLowering> CallLoweringInfo;
std::unique_ptr<InstructionSelector> InstSelector; std::unique_ptr<InstructionSelector> InstSelector;
std::unique_ptr<LegalizerInfo> Legalizer; std::unique_ptr<LegalizerInfo> Legalizer;
std::unique_ptr<RegisterBankInfo> RegBankInfo; std::unique_ptr<RegisterBankInfo> RegBankInfo;
// Return the known range for the bit length of RVV data registers as set // Return the known range for the bit length of RVV data registers as set
Show All 31 Lines

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show All 33 Lines cl::desc(
"SLP vectorizer. Defaults to 1 which disables SLP."), "SLP vectorizer. Defaults to 1 which disables SLP."),
cl::init(1), cl::Hidden); cl::init(1), cl::Hidden);
InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) { InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) {
// TODO: Here assume reciprocal throughput is 1 for LMUL_1, it is // TODO: Here assume reciprocal throughput is 1 for LMUL_1, it is
// implementation-defined. // implementation-defined.
if (!VT.isVector()) if (!VT.isVector())
return InstructionCost::getInvalid(); return InstructionCost::getInvalid();
unsigned DLenFactor = ST->getDLenFactor();
unsigned Cost; unsigned Cost;
if (VT.isScalableVector()) { if (VT.isScalableVector()) {
unsigned LMul; unsigned LMul;
bool Fractional; bool Fractional;
std::tie(LMul, Fractional) = std::tie(LMul, Fractional) =
RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(VT)); RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(VT));
Cost = Fractional ? 1 : LMul; if (Fractional)
Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1;
else
Cost = (LMul * DLenFactor);
} else { } else {
Cost = divideCeil(VT.getSizeInBits(), ST->getRealMinVLen()); Cost = divideCeil(VT.getSizeInBits(), ST->getRealMinVLen() / DLenFactor);
} }
return Cost; return Cost;
} }
InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
TTI::TargetCostKind CostKind) { TTI::TargetCostKind CostKind) {
assert(Ty->isIntegerTy() && assert(Ty->isIntegerTy() &&
"getIntImmCost can only estimate cost of materialising integers"); "getIntImmCost can only estimate cost of materialising integers");
▲ Show 20 Lines • Show All 1,702 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/RISCV/arith-int.ll

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mcpu=sifive-x280 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefix=SIFIVE-X280
; Check that we don't crash querying costs when vectors are not enabled. ; Check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64
define i32 @add() { define i32 @add() {
; CHECK-LABEL: 'add' ; CHECK-LABEL: 'add'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = add i16 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = add i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = add i32 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = add i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = add i64 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = add i64 undef, undef
Show All 24 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = add <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = add <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = add <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = add <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = add <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = add <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = add <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = add <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = add <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = add <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = add <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = add <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'add'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = add i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = add i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = add i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = add <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = add <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = add <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = add <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = add <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = add <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = add <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = add <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = add <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = add <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = add <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = add <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = add <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = add <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = add <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = add <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = add <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = add <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = add <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = add <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = add <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = add <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = add <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = add <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = add <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = add <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = add <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = add <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = add <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = add <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = add i16 undef, undef %I16 = add i16 undef, undef
%I32 = add i32 undef, undef %I32 = add i32 undef, undef
%I64 = add i64 undef, undef %I64 = add i64 undef, undef
%V1I16 = add <1 x i16> undef, undef %V1I16 = add <1 x i16> undef, undef
%V2I16 = add <2 x i16> undef, undef %V2I16 = add <2 x i16> undef, undef
%V4I16 = add <4 x i16> undef, undef %V4I16 = add <4 x i16> undef, undef
%V8I16 = add <8 x i16> undef, undef %V8I16 = add <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = sub <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = sub <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = sub <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = sub <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sub <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sub <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = sub <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = sub <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = sub <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = sub <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = sub <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = sub <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'sub'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sub i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sub i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = sub i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = sub <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = sub <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = sub <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = sub <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = sub <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = sub <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = sub <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = sub <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = sub <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = sub <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = sub <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = sub <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = sub <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = sub <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = sub <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = sub <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = sub <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = sub <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = sub <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = sub <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = sub <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = sub <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = sub <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = sub <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = sub <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = sub <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = sub <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = sub <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = sub <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = sub <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = sub i16 undef, undef %I16 = sub i16 undef, undef
%I32 = sub i32 undef, undef %I32 = sub i32 undef, undef
%I64 = sub i64 undef, undef %I64 = sub i64 undef, undef
%V1I16 = sub <1 x i16> undef, undef %V1I16 = sub <1 x i16> undef, undef
%V2I16 = sub <2 x i16> undef, undef %V2I16 = sub <2 x i16> undef, undef
%V4I16 = sub <4 x i16> undef, undef %V4I16 = sub <4 x i16> undef, undef
%V8I16 = sub <8 x i16> undef, undef %V8I16 = sub <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = mul <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = mul <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = mul <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = mul <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = mul <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = mul <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = mul <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = mul <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = mul <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = mul <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = mul <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = mul <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'mul'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = mul i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = mul i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = mul i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = mul <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = mul <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = mul <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = mul <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = mul <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = mul <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = mul <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = mul <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = mul <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = mul <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = mul <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = mul <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = mul <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = mul <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = mul <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = mul <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = mul <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = mul <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = mul <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = mul <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = mul <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = mul <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = mul <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = mul <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = mul <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = mul <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = mul <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = mul <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = mul <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = mul <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = mul i16 undef, undef %I16 = mul i16 undef, undef
%I32 = mul i32 undef, undef %I32 = mul i32 undef, undef
%I64 = mul i64 undef, undef %I64 = mul i64 undef, undef
%V1I16 = mul <1 x i16> undef, undef %V1I16 = mul <1 x i16> undef, undef
%V2I16 = mul <2 x i16> undef, undef %V2I16 = mul <2 x i16> undef, undef
%V4I16 = mul <4 x i16> undef, undef %V4I16 = mul <4 x i16> undef, undef
%V8I16 = mul <8 x i16> undef, undef %V8I16 = mul <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = shl <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = shl <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = shl <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = shl <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = shl <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = shl <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = shl <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = shl <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = shl <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = shl <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = shl <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = shl <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'shl'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = shl i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = shl i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = shl i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = shl <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = shl <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = shl <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = shl <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = shl <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = shl <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = shl <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = shl <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = shl <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = shl <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = shl <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = shl <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = shl <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = shl <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = shl <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = shl <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = shl <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = shl <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = shl <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = shl <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = shl <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = shl <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = shl <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = shl <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = shl <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = shl <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = shl <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = shl <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = shl <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = shl <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = shl i16 undef, undef %I16 = shl i16 undef, undef
%I32 = shl i32 undef, undef %I32 = shl i32 undef, undef
%I64 = shl i64 undef, undef %I64 = shl i64 undef, undef
%V1I16 = shl <1 x i16> undef, undef %V1I16 = shl <1 x i16> undef, undef
%V2I16 = shl <2 x i16> undef, undef %V2I16 = shl <2 x i16> undef, undef
%V4I16 = shl <4 x i16> undef, undef %V4I16 = shl <4 x i16> undef, undef
%V8I16 = shl <8 x i16> undef, undef %V8I16 = shl <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = lshr <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = lshr <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = lshr <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = lshr <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = lshr <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = lshr <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = lshr <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = lshr <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = lshr <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = lshr <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = lshr <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = lshr <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'lshr'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = lshr i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = lshr i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = lshr i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = lshr <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = lshr <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = lshr <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = lshr <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = lshr <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = lshr <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = lshr <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = lshr <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = lshr <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = lshr <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = lshr <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = lshr <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = lshr <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = lshr <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = lshr <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = lshr <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = lshr <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = lshr <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = lshr <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = lshr <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = lshr <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = lshr <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = lshr <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = lshr <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = lshr <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = lshr <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = lshr <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = lshr <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = lshr <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = lshr <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = lshr i16 undef, undef %I16 = lshr i16 undef, undef
%I32 = lshr i32 undef, undef %I32 = lshr i32 undef, undef
%I64 = lshr i64 undef, undef %I64 = lshr i64 undef, undef
%V1I16 = lshr <1 x i16> undef, undef %V1I16 = lshr <1 x i16> undef, undef
%V2I16 = lshr <2 x i16> undef, undef %V2I16 = lshr <2 x i16> undef, undef
%V4I16 = lshr <4 x i16> undef, undef %V4I16 = lshr <4 x i16> undef, undef
%V8I16 = lshr <8 x i16> undef, undef %V8I16 = lshr <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = ashr <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = ashr <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = ashr <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = ashr <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = ashr <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = ashr <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = ashr <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I64 = ashr <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = ashr <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I64 = ashr <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = ashr <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I64 = ashr <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'ashr'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = ashr i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = ashr i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = ashr i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I16 = ashr <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I16 = ashr <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I16 = ashr <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = ashr <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = ashr <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = ashr <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = ashr <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = ashr <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4I16 = ashr <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV8I16 = ashr <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV16I16 = ashr <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV32I16 = ashr <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I32 = ashr <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = ashr <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = ashr <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = ashr <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = ashr <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = ashr <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2I32 = ashr <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV4I32 = ashr <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV8I32 = ashr <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV16I32 = ashr <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = ashr <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = ashr <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = ashr <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = ashr <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1I64 = ashr <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2I64 = ashr <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV4I64 = ashr <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %NXV8I64 = ashr <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = ashr i16 undef, undef %I16 = ashr i16 undef, undef
%I32 = ashr i32 undef, undef %I32 = ashr i32 undef, undef
%I64 = ashr i64 undef, undef %I64 = ashr i64 undef, undef
%V1I16 = ashr <1 x i16> undef, undef %V1I16 = ashr <1 x i16> undef, undef
%V2I16 = ashr <2 x i16> undef, undef %V2I16 = ashr <2 x i16> undef, undef
%V4I16 = ashr <4 x i16> undef, undef %V4I16 = ashr <4 x i16> undef, undef
%V8I16 = ashr <8 x i16> undef, undef %V8I16 = ashr <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = udiv <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = udiv <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = udiv <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = udiv <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = udiv <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = udiv <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = udiv <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = udiv <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = udiv <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = udiv <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = udiv <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = udiv <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'udiv'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = udiv <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = udiv <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = udiv <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = udiv <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = udiv <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = udiv <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = udiv <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I16 = udiv <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I16 = udiv <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV32I16 = udiv <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = udiv <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = udiv <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = udiv <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = udiv <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = udiv <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = udiv <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = udiv <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = udiv <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I32 = udiv <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = udiv <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = udiv <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = udiv <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = udiv <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = udiv <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = udiv <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = udiv <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = udiv <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = udiv <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = udiv i16 undef, undef %I16 = udiv i16 undef, undef
%I32 = udiv i32 undef, undef %I32 = udiv i32 undef, undef
%I64 = udiv i64 undef, undef %I64 = udiv i64 undef, undef
%V1I16 = udiv <1 x i16> undef, undef %V1I16 = udiv <1 x i16> undef, undef
%V2I16 = udiv <2 x i16> undef, undef %V2I16 = udiv <2 x i16> undef, undef
%V4I16 = udiv <4 x i16> undef, undef %V4I16 = udiv <4 x i16> undef, undef
%V8I16 = udiv <8 x i16> undef, undef %V8I16 = udiv <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = urem <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = urem <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = urem <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = urem <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = urem <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = urem <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = urem <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = urem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = urem <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = urem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = urem <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = urem <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'urem'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = urem <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = urem <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = urem <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = urem <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = urem <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = urem <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = urem <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I16 = urem <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I16 = urem <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV32I16 = urem <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = urem <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = urem <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = urem <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = urem <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = urem <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = urem <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = urem <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = urem <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I32 = urem <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = urem <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = urem <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = urem <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = urem <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = urem <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = urem <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = urem <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = urem <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = urem <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = urem i16 undef, undef %I16 = urem i16 undef, undef
%I32 = urem i32 undef, undef %I32 = urem i32 undef, undef
%I64 = urem i64 undef, undef %I64 = urem i64 undef, undef
%V1I16 = urem <1 x i16> undef, undef %V1I16 = urem <1 x i16> undef, undef
%V2I16 = urem <2 x i16> undef, undef %V2I16 = urem <2 x i16> undef, undef
%V4I16 = urem <4 x i16> undef, undef %V4I16 = urem <4 x i16> undef, undef
%V8I16 = urem <8 x i16> undef, undef %V8I16 = urem <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = sdiv <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = sdiv <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = sdiv <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = sdiv <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sdiv <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sdiv <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = sdiv <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = sdiv <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = sdiv <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = sdiv <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = sdiv <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = sdiv <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'sdiv'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sdiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sdiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = sdiv i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I16 = sdiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = sdiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = sdiv <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = sdiv <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = sdiv <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = sdiv <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = sdiv <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = sdiv <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = sdiv <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I16 = sdiv <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I16 = sdiv <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV32I16 = sdiv <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = sdiv <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = sdiv <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = sdiv <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = sdiv <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = sdiv <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = sdiv <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = sdiv <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = sdiv <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I32 = sdiv <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = sdiv <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = sdiv <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = sdiv <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = sdiv <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = sdiv <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sdiv <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = sdiv <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = sdiv <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = sdiv <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = sdiv i16 undef, undef %I16 = sdiv i16 undef, undef
%I32 = sdiv i32 undef, undef %I32 = sdiv i32 undef, undef
%I64 = sdiv i64 undef, undef %I64 = sdiv i64 undef, undef
%V1I16 = sdiv <1 x i16> undef, undef %V1I16 = sdiv <1 x i16> undef, undef
%V2I16 = sdiv <2 x i16> undef, undef %V2I16 = sdiv <2 x i16> undef, undef
%V4I16 = sdiv <4 x i16> undef, undef %V4I16 = sdiv <4 x i16> undef, undef
%V8I16 = sdiv <8 x i16> undef, undef %V8I16 = sdiv <8 x i16> undef, undef
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = srem <4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = srem <4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = srem <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = srem <8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = srem <vscale x 1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = srem <vscale x 1 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = srem <vscale x 2 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = srem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = srem <vscale x 4 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = srem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = srem <vscale x 8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = srem <vscale x 8 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
; ;
; SIFIVE-X280-LABEL: 'srem'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = srem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = srem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = srem i64 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I16 = srem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = srem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = srem <4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = srem <8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = srem <16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = srem <32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = srem <vscale x 1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = srem <vscale x 2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = srem <vscale x 4 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I16 = srem <vscale x 8 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I16 = srem <vscale x 16 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV32I16 = srem <vscale x 32 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = srem <1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = srem <2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = srem <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = srem <8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = srem <16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = srem <vscale x 1 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = srem <vscale x 2 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = srem <vscale x 4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I32 = srem <vscale x 8 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = srem <vscale x 16 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = srem <1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = srem <2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = srem <4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = srem <8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = srem <vscale x 1 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = srem <vscale x 2 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = srem <vscale x 4 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV8I64 = srem <vscale x 8 x i64> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%I16 = srem i16 undef, undef %I16 = srem i16 undef, undef
%I32 = srem i32 undef, undef %I32 = srem i32 undef, undef
%I64 = srem i64 undef, undef %I64 = srem i64 undef, undef
%V1I16 = srem <1 x i16> undef, undef %V1I16 = srem <1 x i16> undef, undef
%V2I16 = srem <2 x i16> undef, undef %V2I16 = srem <2 x i16> undef, undef
%V4I16 = srem <4 x i16> undef, undef %V4I16 = srem <4 x i16> undef, undef
%V8I16 = srem <8 x i16> undef, undef %V8I16 = srem <8 x i16> undef, undef
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = add <4 x i32> <i32 0, i32 1, i32 2, i32 3>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = add <4 x i32> <i32 0, i32 1, i32 2, i32 3>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = add <4 x i32> <i32 1, i32 2, i32 3, i32 4>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = add <4 x i32> <i32 1, i32 2, i32 3, i32 4>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = add <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -4>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = add <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -4>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %13 = add <4 x i32> <i32 2, i32 4, i32 6, i32 8>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %13 = add <4 x i32> <i32 2, i32 4, i32 6, i32 8>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %14 = add <4 x i32> <i32 -1, i32 0, i32 2, i32 1>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %14 = add <4 x i32> <i32 -1, i32 0, i32 2, i32 1>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %15 = add <4 x i32> <i32 256, i32 4096, i32 57, i32 1>, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %15 = add <4 x i32> <i32 256, i32 4096, i32 57, i32 1>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
; SIFIVE-X280-LABEL: 'add_of_constant'
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = add <4 x i32> poison, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = add <4 x i32> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = add <4 x i32> zeroinitializer, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = add <2 x i64> zeroinitializer, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = add <4 x i32> <i32 1, i32 1, i32 1, i32 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = add <2 x i64> <i64 1, i64 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = add <4 x i32> <i32 4096, i32 4096, i32 4096, i32 4096>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %8 = add <4 x i32> <i32 1, i32 1, i32 2, i32 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %9 = add <4 x i32> <i32 2, i32 1, i32 1, i32 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = add <4 x i32> <i32 0, i32 1, i32 2, i32 3>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = add <4 x i32> <i32 1, i32 2, i32 3, i32 4>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = add <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -4>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %13 = add <4 x i32> <i32 2, i32 4, i32 6, i32 8>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %14 = add <4 x i32> <i32 -1, i32 0, i32 2, i32 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %15 = add <4 x i32> <i32 256, i32 4096, i32 57, i32 1>, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; poison and undef ; poison and undef
add <4 x i32> poison, undef add <4 x i32> poison, undef
add <4 x i32> undef, undef add <4 x i32> undef, undef
; Various splats ; Various splats
add <4 x i32> zeroinitializer, undef add <4 x i32> zeroinitializer, undef
add <2 x i64> zeroinitializer, undef add <2 x i64> zeroinitializer, undef
Show All 20 Lines