This is an archive of the discontinued LLVM Phabricator instance.

Differential D137419

[AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions
ClosedPublic

Authored by david-arm on Nov 4 2022, 6:05 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
CarolineConcatto
kmclaughlin
efriedma
Commits
rG17813095de17: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

faddqv : Floating-point add recursive reduction of quadword vector segments
fmaxqv : Floating-point maximum reduction of quadword vector segments
fmaxnmqv : Floating-point maximum number recursive reduction of quadword vector segments
fminqv : Floating-point minimum recursive reduction of quadword vector segments
fminnmqv : Floating-point minimum number recursive reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Nov 4 2022, 6:05 AM
Herald added a reviewer: efriedma. · View Herald TranscriptNov 4 2022, 6:05 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Nov 4 2022, 6:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2022, 6:05 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
david-arm added a parent revision: D137412: [AArch64][SVE2] Add the SVE2.1 add quadword reduction instruction.Nov 4 2022, 6:05 AM
david-arm added inline comments.
llvm/lib/Target/AArch64/AArch64.td
646 ↗(On Diff #473209)

These changes were needed for the TSV110 scheduling model.

david-arm added a child revision: D137420: [AArch64][SVE2] Add the SVE2.1 integer quadword min/max reduction instructions.Nov 4 2022, 6:14 AM
Harbormaster completed remote builds in B196127: Diff 473209.Nov 4 2022, 6:52 AM
paulwalker-arm added inline comments.Nov 4 2022, 9:30 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

Matt added a subscriber: Matt.Nov 5 2022, 8:34 PM
david-arm added inline comments.Nov 7 2022, 1:45 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

I'm not sure what you mean to be honest, given these are not integer reductions and have completely different encoding groups to the integer variants. I can't see much reuse here for example:

SVE floating-point recursive reduction (quadwords): bits 31-24: 0b01100100, bits 21-19: 0b010
SVE bitwise logical reduction (quadwords): bits 31-24: 0b00000100, bits 21-19: 0b011

Is there something about the naming scheme instead that you wish to change?

paulwalker-arm accepted this revision.Nov 7 2022, 2:43 AM
paulwalker-arm added inline comments.
llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

Sorry @david-arm , I got carried away with a comment that was only meant for the integer reductions.

This revision is now accepted and ready to land.Nov 7 2022, 2:43 AM
Closed by commit rG17813095de17: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions (authored by david-arm). · Explain WhyNov 8 2022, 1:49 AM
This revision was automatically updated to reflect the committed changes.
david-arm added a commit: rG17813095de17: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
12 lines
3 lines
26 lines
test/
MC/
AArch64/
SVE2p1/
30 lines
90 lines
30 lines
90 lines
30 lines
90 lines
30 lines
90 lines
30 lines
90 lines

Diff 473919

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,742 Lines • ▼ Show 20 Lines
defm BFMLA_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmla", 0b10>; defm BFMLA_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmla", 0b10>;
defm BFMLS_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmls", 0b11>; defm BFMLS_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmls", 0b11>;
defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul">; defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul">;
def BFCLAMP_ZZZ : sve2p1_fclamp<"bfclamp", 0b00, ZPR16>; def BFCLAMP_ZZZ : sve2p1_fclamp<"bfclamp", 0b00, ZPR16>;
} // End HasSVE2p1_or_HasSME2p1, HasB16B16 } // End HasSVE2p1_or_HasSME2p1, HasB16B16
//===----------------------------------------------------------------------===//
// SME2.1 or SVE2.1 instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasSVE2p1_or_HasSME2p1] in {
defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv">;
defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">;
defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">;
defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">;
}

llvm/lib/Target/AArch64/AArch64SchedA64FX.td

Show All 16 Linesdef A64FXModel : SchedMachineModel {
let MispredictPenalty = 12; // Extra cycles for mispredicted branch. let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
// Determined via a mix of micro-arch details and experimentation. // Determined via a mix of micro-arch details and experimentation.
let LoopMicroOpBufferSize = 128; let LoopMicroOpBufferSize = 128;
let PostRAScheduler = 1; // Using PostRA sched. let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = list<Predicate> UnsupportedFeatures =
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth, [HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2]; HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
HasSVE2p1_or_HasSME2p1];
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
} }
let SchedModel = A64FXModel in { let SchedModel = A64FXModel in {
// Define the issue ports. // Define the issue ports.
▲ Show 20 Lines • Show All 2,579 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,277 Lines • ▼ Show 20 Lines
} }
multiclass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty> { multiclass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty> {
def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>; def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>;
def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]", def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]",
(!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>; (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>;
} }
// SVE floating-point recursive reduction (quadwords)
class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

paulwalker-arm: As per my comment on D137411, can you use a similar class hierarchy as use by the normal…
david-armAuthorUnsubmitted
Done
ReplyInline Actions

I'm not sure what you mean to be honest, given these are not integer reductions and have completely different encoding groups to the integer variants. I can't see much reuse here for example:

SVE floating-point recursive reduction (quadwords): bits 31-24: 0b01100100, bits 21-19: 0b010
SVE bitwise logical reduction (quadwords): bits 31-24: 0b00000100, bits 21-19: 0b011

Is there something about the naming scheme instead that you wish to change?

david-arm: I'm not sure what you mean to be honest, given these are not integer reductions and have…
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Sorry @david-arm , I got carried away with a comment that was only meant for the integer reductions.

paulwalker-arm: Sorry @david-arm , I got carried away with a comment that was only meant for the integer…
RegisterOperand zpr_ty, string vec_sfx>
: I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
"", []>, Sched<[]> {
bits<5> Vd;
bits<5> Zn;
bits<3> Pg;
let Inst{31-24} = 0b01100100;
let Inst{23-22} = sz;
let Inst{21-19} = 0b010;
let Inst{18-16} = opc;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Vd;
}
multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> {
def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
}

llvm/test/MC/AArch64/SVE2p1/faddqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
faddqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: faddqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
faddqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: faddqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
faddqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: faddqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
faddqv v0.2d, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: faddqv v0.2d, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/faddqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
faddqv v0.2d, p0, z0.d // 01100100-11010000-10100000-00000000
// CHECK-INST: faddqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd0,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d0a000 <unknown>
faddqv v21.2d, p5, z10.d // 01100100-11010000-10110101-01010101
// CHECK-INST: faddqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0xb5,0xd0,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d0b555 <unknown>
faddqv v23.2d, p3, z13.d // 01100100-11010000-10101101-10110111
// CHECK-INST: faddqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0xad,0xd0,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d0adb7 <unknown>
faddqv v31.2d, p7, z31.d // 01100100-11010000-10111111-11111111
// CHECK-INST: faddqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd0,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d0bfff <unknown>
faddqv v0.8h, p0, z0.h // 01100100-01010000-10100000-00000000
// CHECK-INST: faddqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x50,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6450a000 <unknown>
faddqv v21.8h, p5, z10.h // 01100100-01010000-10110101-01010101
// CHECK-INST: faddqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0xb5,0x50,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6450b555 <unknown>
faddqv v23.8h, p3, z13.h // 01100100-01010000-10101101-10110111
// CHECK-INST: faddqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x50,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6450adb7 <unknown>
faddqv v31.8h, p7, z31.h // 01100100-01010000-10111111-11111111
// CHECK-INST: faddqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x50,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6450bfff <unknown>
faddqv v0.4s, p0, z0.s // 01100100-10010000-10100000-00000000
// CHECK-INST: faddqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x90,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6490a000 <unknown>
faddqv v21.4s, p5, z10.s // 01100100-10010000-10110101-01010101
// CHECK-INST: faddqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0xb5,0x90,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6490b555 <unknown>
faddqv v23.4s, p3, z13.s // 01100100-10010000-10101101-10110111
// CHECK-INST: faddqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0xad,0x90,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6490adb7 <unknown>
faddqv v31.4s, p7, z31.s // 01100100-10010000-10111111-11111111
// CHECK-INST: faddqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x90,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6490bfff <unknown>

llvm/test/MC/AArch64/SVE2p1/fmaxnmqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
fmaxnmqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxnmqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
fmaxnmqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxnmqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxnmqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxnmqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
fmaxnmqv v0.2d, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxnmqv v0.2d, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/fmaxnmqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fmaxnmqv v0.2d, p0, z0.d // 01100100-11010100-10100000-00000000
// CHECK-INST: fmaxnmqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd4,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d4a000 <unknown>
fmaxnmqv v21.2d, p5, z10.d // 01100100-11010100-10110101-01010101
// CHECK-INST: fmaxnmqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0xb5,0xd4,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d4b555 <unknown>
fmaxnmqv v23.2d, p3, z13.d // 01100100-11010100-10101101-10110111
// CHECK-INST: fmaxnmqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0xad,0xd4,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d4adb7 <unknown>
fmaxnmqv v31.2d, p7, z31.d // 01100100-11010100-10111111-11111111
// CHECK-INST: fmaxnmqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd4,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d4bfff <unknown>
fmaxnmqv v0.8h, p0, z0.h // 01100100-01010100-10100000-00000000
// CHECK-INST: fmaxnmqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x54,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6454a000 <unknown>
fmaxnmqv v21.8h, p5, z10.h // 01100100-01010100-10110101-01010101
// CHECK-INST: fmaxnmqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0xb5,0x54,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6454b555 <unknown>
fmaxnmqv v23.8h, p3, z13.h // 01100100-01010100-10101101-10110111
// CHECK-INST: fmaxnmqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x54,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6454adb7 <unknown>
fmaxnmqv v31.8h, p7, z31.h // 01100100-01010100-10111111-11111111
// CHECK-INST: fmaxnmqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x54,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6454bfff <unknown>
fmaxnmqv v0.4s, p0, z0.s // 01100100-10010100-10100000-00000000
// CHECK-INST: fmaxnmqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x94,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6494a000 <unknown>
fmaxnmqv v21.4s, p5, z10.s // 01100100-10010100-10110101-01010101
// CHECK-INST: fmaxnmqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0xb5,0x94,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6494b555 <unknown>
fmaxnmqv v23.4s, p3, z13.s // 01100100-10010100-10101101-10110111
// CHECK-INST: fmaxnmqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0xad,0x94,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6494adb7 <unknown>
fmaxnmqv v31.4s, p7, z31.s // 01100100-10010100-10111111-11111111
// CHECK-INST: fmaxnmqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x94,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6494bfff <unknown>

llvm/test/MC/AArch64/SVE2p1/fmaxqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
fmaxqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
fmaxqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
fmaxqv v0.2d, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxqv v0.2d, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/fmaxqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fmaxqv v0.2d, p0, z0.d // 01100100-11010110-10100000-00000000
// CHECK-INST: fmaxqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd6,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d6a000 <unknown>
fmaxqv v21.2d, p5, z10.d // 01100100-11010110-10110101-01010101
// CHECK-INST: fmaxqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0xb5,0xd6,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d6b555 <unknown>
fmaxqv v23.2d, p3, z13.d // 01100100-11010110-10101101-10110111
// CHECK-INST: fmaxqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0xad,0xd6,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d6adb7 <unknown>
fmaxqv v31.2d, p7, z31.d // 01100100-11010110-10111111-11111111
// CHECK-INST: fmaxqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd6,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d6bfff <unknown>
fmaxqv v0.8h, p0, z0.h // 01100100-01010110-10100000-00000000
// CHECK-INST: fmaxqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x56,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6456a000 <unknown>
fmaxqv v21.8h, p5, z10.h // 01100100-01010110-10110101-01010101
// CHECK-INST: fmaxqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0xb5,0x56,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6456b555 <unknown>
fmaxqv v23.8h, p3, z13.h // 01100100-01010110-10101101-10110111
// CHECK-INST: fmaxqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x56,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6456adb7 <unknown>
fmaxqv v31.8h, p7, z31.h // 01100100-01010110-10111111-11111111
// CHECK-INST: fmaxqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x56,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6456bfff <unknown>
fmaxqv v0.4s, p0, z0.s // 01100100-10010110-10100000-00000000
// CHECK-INST: fmaxqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x96,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6496a000 <unknown>
fmaxqv v21.4s, p5, z10.s // 01100100-10010110-10110101-01010101
// CHECK-INST: fmaxqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0xb5,0x96,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6496b555 <unknown>
fmaxqv v23.4s, p3, z13.s // 01100100-10010110-10101101-10110111
// CHECK-INST: fmaxqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0xad,0x96,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6496adb7 <unknown>
fmaxqv v31.4s, p7, z31.s // 01100100-10010110-10111111-11111111
// CHECK-INST: fmaxqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x96,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6496bfff <unknown>

llvm/test/MC/AArch64/SVE2p1/fminnmqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
fminnmqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminnmqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
fminnmqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminnmqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminnmqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminnmqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
fminnmqv v0.2d, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminnmqv v0.2d, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/fminnmqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fminnmqv v0.2d, p0, z0.d // 01100100-11010101-10100000-00000000
// CHECK-INST: fminnmqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd5,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d5a000 <unknown>
fminnmqv v21.2d, p5, z10.d // 01100100-11010101-10110101-01010101
// CHECK-INST: fminnmqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0xb5,0xd5,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d5b555 <unknown>
fminnmqv v23.2d, p3, z13.d // 01100100-11010101-10101101-10110111
// CHECK-INST: fminnmqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0xad,0xd5,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d5adb7 <unknown>
fminnmqv v31.2d, p7, z31.d // 01100100-11010101-10111111-11111111
// CHECK-INST: fminnmqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd5,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d5bfff <unknown>
fminnmqv v0.8h, p0, z0.h // 01100100-01010101-10100000-00000000
// CHECK-INST: fminnmqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x55,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6455a000 <unknown>
fminnmqv v21.8h, p5, z10.h // 01100100-01010101-10110101-01010101
// CHECK-INST: fminnmqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0xb5,0x55,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6455b555 <unknown>
fminnmqv v23.8h, p3, z13.h // 01100100-01010101-10101101-10110111
// CHECK-INST: fminnmqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x55,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6455adb7 <unknown>
fminnmqv v31.8h, p7, z31.h // 01100100-01010101-10111111-11111111
// CHECK-INST: fminnmqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x55,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6455bfff <unknown>
fminnmqv v0.4s, p0, z0.s // 01100100-10010101-10100000-00000000
// CHECK-INST: fminnmqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x95,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6495a000 <unknown>
fminnmqv v21.4s, p5, z10.s // 01100100-10010101-10110101-01010101
// CHECK-INST: fminnmqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0xb5,0x95,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6495b555 <unknown>
fminnmqv v23.4s, p3, z13.s // 01100100-10010101-10101101-10110111
// CHECK-INST: fminnmqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0xad,0x95,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6495adb7 <unknown>
fminnmqv v31.4s, p7, z31.s // 01100100-10010101-10111111-11111111
// CHECK-INST: fminnmqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x95,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6495bfff <unknown>

llvm/test/MC/AArch64/SVE2p1/fminqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
fminqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
fminqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
fminqv v0.2d, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminqv v0.2d, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/fminqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fminqv v0.2d, p0, z0.d // 01100100-11010111-10100000-00000000
// CHECK-INST: fminqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd7,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d7a000 <unknown>
fminqv v21.2d, p5, z10.d // 01100100-11010111-10110101-01010101
// CHECK-INST: fminqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0xb5,0xd7,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d7b555 <unknown>
fminqv v23.2d, p3, z13.d // 01100100-11010111-10101101-10110111
// CHECK-INST: fminqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0xad,0xd7,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d7adb7 <unknown>
fminqv v31.2d, p7, z31.d // 01100100-11010111-10111111-11111111
// CHECK-INST: fminqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd7,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 64d7bfff <unknown>
fminqv v0.8h, p0, z0.h // 01100100-01010111-10100000-00000000
// CHECK-INST: fminqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x57,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6457a000 <unknown>
fminqv v21.8h, p5, z10.h // 01100100-01010111-10110101-01010101
// CHECK-INST: fminqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0xb5,0x57,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6457b555 <unknown>
fminqv v23.8h, p3, z13.h // 01100100-01010111-10101101-10110111
// CHECK-INST: fminqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x57,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6457adb7 <unknown>
fminqv v31.8h, p7, z31.h // 01100100-01010111-10111111-11111111
// CHECK-INST: fminqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x57,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6457bfff <unknown>
fminqv v0.4s, p0, z0.s // 01100100-10010111-10100000-00000000
// CHECK-INST: fminqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x97,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6497a000 <unknown>
fminqv v21.4s, p5, z10.s // 01100100-10010111-10110101-01010101
// CHECK-INST: fminqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0xb5,0x97,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6497b555 <unknown>
fminqv v23.4s, p3, z13.s // 01100100-10010111-10101101-10110111
// CHECK-INST: fminqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0xad,0x97,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6497adb7 <unknown>
fminqv v31.4s, p7, z31.s // 01100100-10010111-10111111-11111111
// CHECK-INST: fminqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x97,0x64]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 6497bfff <unknown>