[X86][1/2] SUPPORT RAO-INT

[pengfei]

Summary

For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Initial authored by Liu Chen (@LiuChen3)

[pengfei]

Add atomic operations lowering for RAO-INT instructions.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.h

801

very pedantic, but are these likely to get confused with ROR / RAND instructions? Would it be better to use a RAO_ prefix?

llvm/test/CodeGen/X86/atomic-instructions-32.ll

5 ↗

(On Diff #468020)

Is the -O0 necessary?

[craig.topper]

llvm/lib/Target/X86/X86.td

262

Why do these require SSE2?

llvm/lib/Target/X86/X86ISelLowering.h

801

Why not AADD etc to match the instruction names?

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

32019

This should probably be in a separate patch.

[pengfei]

Split atomic operations lowering into D136032.

[pengfei]

llvm/lib/Target/X86/X86.td

262

We need mfence instructions for strong orders. The mfence feature relies on SSE2.
I see your concern, we may need split these features from SSE2. Filed an issue https://github.com/llvm/llvm-project/issues/58388

llvm/lib/Target/X86/X86ISelLowering.h

801

Good ideas, thanks!

llvm/test/CodeGen/X86/atomic-instructions-32.ll

5 ↗

(On Diff #468020)

I missed that, thanks!

[craig.topper]

llvm/lib/Target/X86/X86.td

262

The lowering code for atomics could check SSE2 in addition to the RAO-INT feature. My primary concern was that the RAO-INT feature itself shouldn't require it.

Are there going to be intrinsics for RAO-INT?

[pengfei]

llvm/lib/Target/X86/X86.td

262

I don't think there will be a target supports RAO-INT but no SSE2. All I can think out is for Kernel build that disable vector registers intentionally.

Are there going to be intrinsics for RAO-INT?

This is a good question. In fact we wander whether providing intrinsics or not. The current preference is not. We don't want to add new intrinsics arbitrarily, there're burdens to maintenance and it's always easy to adding per to actual requests than removing afterwards.

[pengfei]

Add intrinsic support first.

[FreddyYe]

clang/docs/ReleaseNotes.rst

611

Add bullets for supported intrinsics.

clang/test/CodeGen/X86/raoint-builtins.c

3

32 bit test coverage.

llvm/lib/Target/X86/X86InstrRAOINT.td

10

RAOINT

[pengfei]

Address review comments; Change intrinsics name from *_si* to *_i*.

[RKSimon]

LGTM

clang/docs/ReleaseNotes.rst

 -----------------------
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for ``-mcpu``.
   Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
 
 X86 Support in Clang
 --------------------
 - Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk.
 - Fix 32-bit ``__fastcall`` and ``__vectorcall`` ABI mismatch with MSVC.
 - Add ISA of ``AMX-FP16`` which support ``_tile_dpfp16ps``.
 - Switch ``AVX512-BF16`` intrinsics types from ``short`` to ``__bf16``.
 - Add support for ``PREFETCHI`` instructions.
 - Support ISA of ``CMPCCXADD``.
   * Support intrinsic of ``__cmpccxadd_epi32``.
   * Support intrinsic of ``__cmpccxadd_epi64``.
+- Add support for ``RAO-INT`` instructions.
+  * Support intrinsic of ``_aadd_i32/64``
+  * Support intrinsic of ``_aand_i32/64``
+  * Support intrinsic of ``_aor_i32/64``
+  * Support intrinsic of ``_axor_i32/64``
 
 WebAssembly Support in Clang
 ----------------------------
 
 The -mcpu=generic configuration now enables sign-ext and mutable-globals. These
 proposals are standardized and available in all major engines.
 
 DWARF Support in Clang

clang/include/clang/Basic/BuiltinsX86.def

 
 // SERIALIZE
 TARGET_BUILTIN(__builtin_ia32_serialize, "v", "n", "serialize")
 
 // TSXLDTRK
 TARGET_BUILTIN(__builtin_ia32_xsusldtrk, "v", "n", "tsxldtrk")
 TARGET_BUILTIN(__builtin_ia32_xresldtrk, "v", "n", "tsxldtrk")
 
+// RAO-INT
+TARGET_BUILTIN(__builtin_ia32_aadd32, "vv*Si", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_aand32, "vv*Si", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_aor32, "vv*Si", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_axor32, "vv*Si", "n", "raoint")
+
 // MSVC
 TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_ReadBarrier,      "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_WriteBarrier,     "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 

clang/include/clang/Basic/BuiltinsX86_64.def

 
 TARGET_BUILTIN(__builtin_ia32_prefetchi, "vvC*Ui", "nc", "prefetchi")
 TARGET_BUILTIN(__builtin_ia32_cmpccxadd32, "Siv*SiSiIi", "n", "cmpccxadd")
 TARGET_BUILTIN(__builtin_ia32_cmpccxadd64, "SLLiv*SLLiSLLiIi", "n", "cmpccxadd")
 
 // AMX_FP16 FP16
 TARGET_BUILTIN(__builtin_ia32_tdpfp16ps, "vIUcIUcIUc", "n", "amx-fp16")
 
+// RAO-INT
+TARGET_BUILTIN(__builtin_ia32_aadd64, "vv*SOi", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_aor64, "vv*SOi", "n", "raoint")
+TARGET_BUILTIN(__builtin_ia32_axor64, "vv*SOi", "n", "raoint")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
 #undef TARGET_HEADER_BUILTIN

clang/include/clang/Driver/Options.td

 def mprefetchi : Flag<["-"], "mprefetchi">, Group<m_x86_Features_Group>;
 def mno_prefetchi : Flag<["-"], "mno-prefetchi">, Group<m_x86_Features_Group>;
 def mprefetchwt1 : Flag<["-"], "mprefetchwt1">, Group<m_x86_Features_Group>;
 def mno_prefetchwt1 : Flag<["-"], "mno-prefetchwt1">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mptwrite : Flag<["-"], "mptwrite">, Group<m_x86_Features_Group>;
 def mno_ptwrite : Flag<["-"], "mno-ptwrite">, Group<m_x86_Features_Group>;
+def mraoint : Flag<["-"], "mraoint">, Group<m_x86_Features_Group>;
+def mno_raoint : Flag<["-"], "mno-raoint">, Group<m_x86_Features_Group>;
 def mrdpid : Flag<["-"], "mrdpid">, Group<m_x86_Features_Group>;
 def mno_rdpid : Flag<["-"], "mno-rdpid">, Group<m_x86_Features_Group>;
 def mrdpru : Flag<["-"], "mrdpru">, Group<m_x86_Features_Group>;
 def mno_rdpru : Flag<["-"], "mno-rdpru">, Group<m_x86_Features_Group>;
 def mrdrnd : Flag<["-"], "mrdrnd">, Group<m_x86_Features_Group>;
 def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasWAITPKG = false;
   bool HasMOVDIRI = false;
   bool HasMOVDIR64B = false;
   bool HasPTWRITE = false;
   bool HasINVPCID = false;
   bool HasENQCMD = false;
   bool HasAMXFP16 = false;
   bool HasCMPCCXADD = false;
+  bool HasRAOINT = false;
   bool HasKL = false;      // For key locker
   bool HasWIDEKL = false; // For wide key locker
   bool HasHRESET = false;
   bool HasAVXVNNI = false;
   bool HasAMXTILE = false;
   bool HasAMXINT8 = false;
   bool HasAMXBF16 = false;
   bool HasSERIALIZE = false;

clang/lib/Basic/Targets/X86.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+amx-fp16") {
       HasAMXFP16 = true;
     } else if (Feature == "+amx-int8") {
       HasAMXINT8 = true;
     } else if (Feature == "+amx-tile") {
       HasAMXTILE = true;
     } else if (Feature == "+cmpccxadd") {
       HasCMPCCXADD = true;
+    } else if (Feature == "+raoint") {
+      HasRAOINT = true;
     } else if (Feature == "+avxvnni") {
       HasAVXVNNI = true;
     } else if (Feature == "+serialize") {
       HasSERIALIZE = true;
     } else if (Feature == "+tsxldtrk") {
       HasTSXLDTRK = true;
     } else if (Feature == "+uintr") {
       HasUINTR = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasAMXINT8)
     Builder.defineMacro("__AMXINT8__");
   if (HasAMXBF16)
     Builder.defineMacro("__AMXBF16__");
   if (HasAMXFP16)
     Builder.defineMacro("__AMXFP16__");
   if (HasCMPCCXADD)
     Builder.defineMacro("__CMPCCXADD__");
+  if (HasRAOINT)
+    Builder.defineMacro("__RAOINT__");
   if (HasAVXVNNI)
     Builder.defineMacro("__AVXVNNI__");
   if (HasSERIALIZE)
     Builder.defineMacro("__SERIALIZE__");
   if (HasTSXLDTRK)
     Builder.defineMacro("__TSXLDTRK__");
   if (HasUINTR)
     Builder.defineMacro("__UINTR__");
return llvm::StringSwitch<bool>(Name)
       .Case("pclmul", true)
       .Case("pconfig", true)
       .Case("pku", true)
       .Case("popcnt", true)
       .Case("prefetchi", true)
       .Case("prefetchwt1", true)
       .Case("prfchw", true)
       .Case("ptwrite", true)
+      .Case("raoint", true)
       .Case("rdpid", true)
       .Case("rdpru", true)
       .Case("rdrnd", true)
       .Case("rdseed", true)
       .Case("rtm", true)
       .Case("sahf", true)
       .Case("serialize", true)
       .Case("sgx", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("pclmul", HasPCLMUL)
       .Case("pconfig", HasPCONFIG)
       .Case("pku", HasPKU)
       .Case("popcnt", HasPOPCNT)
       .Case("prefetchi", HasPREFETCHI)
       .Case("prefetchwt1", HasPREFETCHWT1)
       .Case("prfchw", HasPRFCHW)
       .Case("ptwrite", HasPTWRITE)
+      .Case("raoint", HasRAOINT)
       .Case("rdpid", HasRDPID)
       .Case("rdpru", HasRDPRU)
       .Case("rdrnd", HasRDRND)
       .Case("rdseed", HasRDSEED)
       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
       .Case("rtm", HasRTM)
       .Case("sahf", HasLAHFSAHF)
       .Case("serialize", HasSERIALIZE)

clang/lib/Headers/CMakeLists.txt

# Intrinsics
   nmmintrin.h
   pconfigintrin.h
   pkuintrin.h
   pmmintrin.h
   popcntintrin.h
   prfchiintrin.h
   prfchwintrin.h
   ptwriteintrin.h
+  raointintrin.h
   rdpruintrin.h
   rdseedintrin.h
   rtmintrin.h
   serializeintrin.h
   sgxintrin.h
   shaintrin.h
   smmintrin.h
   tbmintrin.h

clang/lib/Headers/cpuid.h

 #define bit_PCONFIG       0x00040000
 #define bit_IBT           0x00100000
 #define bit_AMXBF16       0x00400000
 #define bit_AVX512FP16    0x00800000
 #define bit_AMXTILE       0x01000000
 #define bit_AMXINT8       0x02000000
 
 /* Features in %eax for leaf 7 sub-leaf 1 */
+#define bit_RAOINT        0x00000008
 #define bit_AVXVNNI       0x00000010
 #define bit_AVX512BF16    0x00000020
 #define bit_CMPCCXADD     0x00000080
 #define bit_AMXFP16       0x00200000
 #define bit_HRESET        0x00400000
 
 /* Features in %edx for leaf 7 sub-leaf 1 */
 #define bit_PREFETCHI     0x00004000

clang/lib/Headers/raointintrin.h

+/*===----------------------- raointintrin.h - RAOINT ------------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __X86GPRINTRIN_H
+#error "Never use <raointintrin.h> directly; include <x86gprintrin.h> instead."
+#endif // __X86GPRINTRIN_H
+
+#ifndef __RAOINTINTRIN_H
+#define __RAOINTINTRIN_H
+
+#define __DEFAULT_FN_ATTRS                                                     \
+  __attribute__((__always_inline__, __nodebug__, __target__("raoint")))
+
+/// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AADD instruction.
+///
+/// \param __A
+///    A pointer to a 32-bit memory location.
+/// \param __B
+///    A 32-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aadd_i32(int *__A, int __B) {
+  __builtin_ia32_aadd32((int *)__A, __B);
+}
+
+/// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AAND instruction.
+///
+/// \param __A
+///    A pointer to a 32-bit memory location.
+/// \param __B
+///    A 32-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aand_i32(int *__A, int __B) {
+  __builtin_ia32_aand32((int *)__A, __B);
+}
+
+/// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AOR instruction.
+///
+/// \param __A
+///    A pointer to a 32-bit memory location.
+/// \param __B
+///    A 32-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aor_i32(int *__A, int __B) {
+  __builtin_ia32_aor32((int *)__A, __B);
+}
+
+/// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AXOR instruction.
+///
+/// \param __A
+///    A pointer to a 32-bit memory location.
+/// \param __B
+///    A 32-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _axor_i32(int *__A, int __B) {
+  __builtin_ia32_axor32((int *)__A, __B);
+}
+
+#ifdef __x86_64__
+/// Atomically add a 64-bit value at memory operand \a __A and a 64-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AADD instruction.
+///
+/// \param __A
+///    A pointer to a 64-bit memory location.
+/// \param __B
+///    A 64-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aadd_i64(long long *__A,
+                                                    long long __B) {
+  __builtin_ia32_aadd64((long long *)__A, __B);
+}
+
+/// Atomically and a 64-bit value at memory operand \a __A and a 64-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AAND instruction.
+///
+/// \param __A
+///    A pointer to a 64-bit memory location.
+/// \param __B
+///    A 64-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aand_i64(long long *__A,
+                                                    long long __B) {
+  __builtin_ia32_aand64((long long *)__A, __B);
+}
+
+/// Atomically or a 64-bit value at memory operand \a __A and a 64-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AOR instruction.
+///
+/// \param __A
+///    A pointer to a 64-bit memory location.
+/// \param __B
+///    A 64-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _aor_i64(long long *__A,
+                                                   long long __B) {
+  __builtin_ia32_aor64((long long *)__A, __B);
+}
+
+/// Atomically xor a 64-bit value at memory operand \a __A and a 64-bit \a __B,
+///    and store the result to the same memory location.
+///
+///    This intrinsic should be used for contention or weak ordering. It may
+///    result in bad performance for hot data used by single thread only.
+///
+/// \headerfile <x86intrin.h>
+///
+/// This intrinsic corresponds to the \c AXOR instruction.
+///
+/// \param __A
+///    A pointer to a 64-bit memory location.
+/// \param __B
+///    A 64-bit integer value.
+///
+/// \code{.operation}
+/// MEM[__A+63:__A] := MEM[__A+63:__A] AOR __B[63:0]
+/// \endcode
+static __inline__ void __DEFAULT_FN_ATTRS _axor_i64(long long *__A,
+                                                    long long __B) {
+  __builtin_ia32_axor64((long long *)__A, __B);
+}
+#endif // __x86_64__
+
+#undef __DEFAULT_FN_ATTRS
+#endif // __RAOINTINTRIN_H

clang/lib/Headers/x86gprintrin.h

 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__CRC32__)
 #include <crc32intrin.h>
 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__PRFCHI__)
 #include <prfchiintrin.h>
+
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
+    defined(__RAOINT__)
+#include <raointintrin.h>
 #endif
 
 #if defined(__i386__)
 #define __SAVE_GPRBX "mov {%%ebx, %%eax |eax, ebx};"
 #define __RESTORE_GPRBX "mov {%%eax, %%ebx |ebx, eax};"
 #define __TMPGPR "eax"
 #else
 // When in 64-bit target, the 32-bit operands generate a 32-bit result,

clang/test/CodeGen/X86/raoint-builtins.c

+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +raoint \
+// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s --check-prefixes=CHECK,X64
+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +raoint \
+// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s --check-prefixes=CHECK
+
+#include <stddef.h>
+#include <x86gprintrin.h>
+
+void test_aadd_i32(int *__A, int __B) {
+  // CHECK-LABEL: @test_aadd_i32(
+  // CHECK: call void @llvm.x86.aadd32(ptr %{{.*}}, i32 %{{.*}})
+  _aadd_i32(__A, __B);
+}
+
+void test_aand_i32(int *__A, int __B) {
+  // CHECK-LABEL: @test_aand_i32(
+  // CHECK: call void @llvm.x86.aand32(ptr %{{.*}}, i32 %{{.*}})
+  _aand_i32(__A, __B);
+}
+
+void test_aor_i32(int *__A, int __B) {
+  // CHECK-LABEL: @test_aor_i32(
+  // CHECK: call void @llvm.x86.aor32(ptr %{{.*}}, i32 %{{.*}})
+  _aor_i32(__A, __B);
+}
+
+void test_axor_i32(int *__A, int __B) {
+  // CHECK-LABEL: @test_axor_i32(
+  // CHECK: call void @llvm.x86.axor32(ptr %{{.*}}, i32 %{{.*}})
+  _axor_i32(__A, __B);
+}
+
+#ifdef __x86_64__
+void test_aadd_i64(long long *__A, long long __B) {
+  // X64-LABEL: @test_aadd_i64(
+  // X64: call void @llvm.x86.aadd64(ptr %{{.*}}, i64 %{{.*}})
+  _aadd_i64(__A, __B);
+}
+
+void test_aand_i64(long long *__A, long long __B) {
+  // X64-LABEL: @test_aand_i64(
+  // X64: call void @llvm.x86.aand64(ptr %{{.*}}, i64 %{{.*}})
+  _aand_i64(__A, __B);
+}
+
+void test_aor_i64(long long *__A, long long __B) {
+  // X64-LABEL: @test_aor_i64(
+  // X64: call void @llvm.x86.aor64(ptr %{{.*}}, i64 %{{.*}})
+  _aor_i64(__A, __B);
+}
+
+void test_axor_i64(long long *__A, long long __B) {
+  // X64-LABEL: @test_axor_i64(
+  // X64: call void @llvm.x86.axor64(ptr %{{.*}}, i64 %{{.*}})
+  _axor_i64(__A, __B);
+}
+#endif

clang/test/Driver/x86-target-features.c

 // AVX512FP16: "-target-feature" "+avx512fp16"
 // NO-AVX512FP16: "-target-feature" "-avx512fp16"
 
 // RUN: %clang --target=x86_64 -mcmpccxadd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=CMPCCXADD %s
 // RUN: %clang --target=x86_64 -mno-cmpccxadd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CMPCCXADD %s
 // CMPCCXADD: "-target-feature" "+cmpccxadd"
 // NO-CMPCCXADD: "-target-feature" "-cmpccxadd"
 
+// RUN: %clang --target=i386 -march=i386 -mraoint %s -### 2>&1 | FileCheck -check-prefix=RAOINT %s
+// RUN: %clang --target=i386 -march=i386 -mno-raoint %s -### 2>&1 | FileCheck -check-prefix=NO-RAOINT %s
+// RAOINT: "-target-feature" "+raoint"
+// NO-RAOINT: "-target-feature" "-raoint"
+
 // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
 // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
 // CRC32: "-target-feature" "+crc32"
 // NO-CRC32: "-target-feature" "-crc32"
 
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-RET,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=none -mharden-sls=all %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,SLS-RET %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=all -mharden-sls=none %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return,indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefix=BAD-SLS %s
 // NO-SLS-NOT: "+harden-sls-
 // SLS-RET-DAG: "-target-feature" "+harden-sls-ret"
 // SLS-IJMP-DAG: "-target-feature" "+harden-sls-ijmp"
 // NO-SLS-NOT: "+harden-sls-
 // BAD-SLS: unsupported argument '{{[^']+}}' to option '-mharden-sls='

clang/test/Preprocessor/x86_target_features.c

 // RUN: %clang -target x86_64-unknown-linux-gnu -march=atom -mcmpccxadd -x c -E -dM -o - %s | FileCheck  -check-prefix=CMPCCXADD %s
 
 // CMPCCXADD: #define __CMPCCXADD__ 1
 
 // RUN: %clang -target x86_64-unknown-linux-gnu -march=atom -mno-cmpccxadd -x c -E -dM -o - %s | FileCheck  -check-prefix=NO-CMPCCXADD %s
 
 // NO-CMPCCXADD-NOT: #define __CMPCCXADD__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mraoint -x c -E -dM -o - %s | FileCheck  -check-prefix=RAOINT %s
+
+// RAOINT: #define __RAOINT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mno-raoint -x c -E -dM -o - %s | FileCheck  -check-prefix=NO-RAOINT %s
+
+// NO-RAOINT-NOT: #define __RAOINT__ 1
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
 
 // CRC32: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-crc32 -x c -E -dM -o - %s | FileCheck -check-prefix=NOCRC32 %s
 
 // NOCRC32-NOT: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpru -x c -E -dM -o - %s | FileCheck -check-prefix=RDPRU %s
 
 // RDPRU: #define __RDPRU__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpru -x c -E -dM -o - %s | FileCheck -check-prefix=NORDPRU %s
 
 // NORDPRU-NOT: #define __RDPRU__ 1

llvm/include/llvm/IR/IntrinsicsX86.td

 let TargetPrefix = "x86" in {
 // AMX_FP16 - Intel FP16 AMX extensions
   def int_x86_tdpfp16ps : ClangBuiltin<"__builtin_ia32_tdpfp16ps">,
                           Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
                                     [ImmArg<ArgIndex<0>>,
                                     ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
 }
 //===----------------------------------------------------------------------===//
+// RAO-INT intrinsics
+let TargetPrefix = "x86" in {
+  def int_x86_aadd32 : ClangBuiltin<"__builtin_ia32_aadd32">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
+  def int_x86_aadd64 : ClangBuiltin<"__builtin_ia32_aadd64">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
+  def int_x86_aand32 : ClangBuiltin<"__builtin_ia32_aand32">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
+  def int_x86_aand64 : ClangBuiltin<"__builtin_ia32_aand64">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
+  def int_x86_aor32 : ClangBuiltin<"__builtin_ia32_aor32">,
+                      Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
+  def int_x86_aor64 : ClangBuiltin<"__builtin_ia32_aor64">,
+                      Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
+  def int_x86_axor32 : ClangBuiltin<"__builtin_ia32_axor32">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
+  def int_x86_axor64 : ClangBuiltin<"__builtin_ia32_axor64">,
+                       Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
+}
+
+//===----------------------------------------------------------------------===//
 // UINTR - User Level Interrupt
 
 let TargetPrefix = "x86" in {
   def int_x86_clui : ClangBuiltin<"__builtin_ia32_clui">,
               Intrinsic<[], [], []>;
   def int_x86_stui : ClangBuiltin<"__builtin_ia32_stui">,
               Intrinsic<[], [], []>;
   def int_x86_testui : ClangBuiltin<"__builtin_ia32_testui">,

llvm/include/llvm/Support/X86TargetParser.def

 X86_FEATURE       (WAITPKG,         "waitpkg")
 X86_FEATURE       (WBNOINVD,        "wbnoinvd")
 X86_FEATURE       (X87,             "x87")
 X86_FEATURE       (XSAVE,           "xsave")
 X86_FEATURE       (XSAVEC,          "xsavec")
 X86_FEATURE       (XSAVEOPT,        "xsaveopt")
 X86_FEATURE       (XSAVES,          "xsaves")
 X86_FEATURE       (HRESET,          "hreset")
+X86_FEATURE       (RAOINT,          "raoint")
 X86_FEATURE       (AVX512FP16,      "avx512fp16")
 X86_FEATURE       (AMX_FP16,        "amx-fp16")
 X86_FEATURE       (CMPCCXADD,       "cmpccxadd")
 X86_FEATURE       (AVXVNNI,         "avxvnni")
 // These features aren't really CPU features, but the frontend can set them.
 X86_FEATURE       (RETPOLINE_EXTERNAL_THUNK,    "retpoline-external-thunk")
 X86_FEATURE       (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
 X86_FEATURE       (RETPOLINE_INDIRECT_CALLS,    "retpoline-indirect-calls")

llvm/lib/Support/Host.cpp

#endif
   // For more info, see X86 ISA docs.
   Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
   Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
   Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
   Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
   Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
   bool HasLeaf7Subleaf1 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
+  Features["raoint"]     = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
   Features["avxvnni"]    = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
   Features["amx-fp16"]   = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
   Features["cmpccxadd"]  = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
   Features["hreset"]     = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
   Features["prefetchi"]  = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
 
   bool HasLeafD = MaxLevel >= 0xd &&

llvm/lib/Support/X86TargetParser.cpp

 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
 
 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
+constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
     FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
 // Key Locker Features
 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
 
 // AVXVNNI Features
 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;

llvm/lib/Target/X86/X86.td

 def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
                                       "Support AMX-INT8 instructions",
                                       [FeatureAMXTILE]>;
 def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
                                       "Support AMX-BF16 instructions",
                                       [FeatureAMXTILE]>;
 def FeatureAMXFP16     : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true",
                                       "Support AMX amx-fp16 instructions",
                                       [FeatureAMXTILE]>;
 def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true",
                                         "Support CMPCCXADD instructions">;
+def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",
+                                     "Support RAO-INT instructions",
+                                     []>;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
                                       "Invalidate Process-Context Identifier">;
 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
                                       "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
                                       "Flush A Cache Line Optimized">;
 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
                                       "Cache Line Write Back">;

llvm/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
     LSUB,
     LOR,
     LXOR,
     LAND,
     LBTS,
     LBTC,
     LBTR,
 
+    /// RAO arithmetic instructions.
+    /// OUTCHAIN = AADD(INCHAIN, PTR, RHS)
+    AADD,
+    AOR,
+    AXOR,
+    AAND,
+
     // Load, scalar_to_vector, and zero extend.
     VZEXT_LOAD,
 
     // extract_vector_elt, store.
     VEXTRACT_STORE,
 
     // scalar broadcast from memory.
     VBROADCAST_LOAD,

llvm/lib/Target/X86/X86ISelLowering.cpp

case Intrinsic::x86_atomic_btr: {
       Info.ptrVal = I.getArgOperand(0);
       unsigned Size = I.getType()->getScalarSizeInBits();
       Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), Size);
       Info.align = Align(Size);
       Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
                     MachineMemOperand::MOVolatile;
       return true;
     }
+    case Intrinsic::x86_aadd32:
+    case Intrinsic::x86_aadd64:
+    case Intrinsic::x86_aand32:
+    case Intrinsic::x86_aand64:
+    case Intrinsic::x86_aor32:
+    case Intrinsic::x86_aor64:
+    case Intrinsic::x86_axor32:
+    case Intrinsic::x86_axor64: {
+      Info.opc = ISD::INTRINSIC_W_CHAIN;
+      Info.ptrVal = I.getArgOperand(0);
+      unsigned Size = I.getArgOperand(1)->getType()->getScalarSizeInBits();
+      Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), Size);
+      Info.align = Align(Size);
+      Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
+                    MachineMemOperand::MOVolatile;
+      return true;
+    }
     }
     return false;
   }
 
   switch (IntrData->Type) {
   case TRUNCATE_TO_MEM_VI8:
   case TRUNCATE_TO_MEM_VI16:
   case TRUNCATE_TO_MEM_VI32: {
case Intrinsic::x86_cmpccxadd64: {
       SDValue Src2 = Op.getOperand(4);
       SDValue CC = Op.getOperand(5);
       MachineMemOperand *MMO = cast<MemIntrinsicSDNode>(Op)->getMemOperand();
       SDValue Operation = DAG.getMemIntrinsicNode(
           X86ISD::CMPCCXADD, DL, Op->getVTList(), {Chain, Addr, Src1, Src2, CC},
           MVT::i32, MMO);
       return Operation;
     }
+    case Intrinsic::x86_aadd32:
+    case Intrinsic::x86_aadd64:
+    case Intrinsic::x86_aand32:
+    case Intrinsic::x86_aand64:
+    case Intrinsic::x86_aor32:
+    case Intrinsic::x86_aor64:
+    case Intrinsic::x86_axor32:
+    case Intrinsic::x86_axor64: {
+      SDLoc DL(Op);
+      SDValue Chain = Op.getOperand(0);
+      SDValue Op1 = Op.getOperand(2);
+      SDValue Op2 = Op.getOperand(3);
+      MVT VT = Op2.getSimpleValueType();
+      unsigned Opc = 0;
+      switch (IntNo) {
+      default:
+        llvm_unreachable("Unknown Intrinsic");
+      case Intrinsic::x86_aadd32:
+      case Intrinsic::x86_aadd64:
+        Opc = X86ISD::AADD;
+        break;
+      case Intrinsic::x86_aand32:
+      case Intrinsic::x86_aand64:
+        Opc = X86ISD::AAND;
+        break;
+      case Intrinsic::x86_aor32:
+      case Intrinsic::x86_aor64:
+        Opc = X86ISD::AOR;
+        break;
+      case Intrinsic::x86_axor32:
+      case Intrinsic::x86_axor64:
+        Opc = X86ISD::AXOR;
+        break;
+      }
+      MachineMemOperand *MMO = cast<MemSDNode>(Op)->getMemOperand();
+      return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(),
+                                     {Chain, Op1, Op2}, VT, MMO);
+    }
     }
     return SDValue();
   }
 
   SDLoc dl(Op);
   switch(IntrData->Type) {
   default: llvm_unreachable("Unknown Intrinsic Type");
   case RDSEED:
if (Opc == ISD::ATOMIC_LOAD_SUB) {
       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, VT, Chain, LHS,
                            RHS, AN->getMemOperand());
     }
     assert(Opc == ISD::ATOMIC_LOAD_ADD &&
            "Used AtomicRMW ops other than Add should have been expanded!");
     return N;
   }
 
   // Specialized lowering for the canonical form of an idemptotent atomicrmw.
   // The core idea here is that since the memory location isn't actually
   // changing, all we need is a lowering for the *ordering* impacts of the
   // atomicrmw.  As such, we can chose a different operation and memory
   // location to minimize impact on other code.
   if (Opc == ISD::ATOMIC_LOAD_OR && isNullConstant(RHS)) {
     // On X86, the only ordering which actually requires an instruction is
     // seq_cst which isn't SingleThread, everything just needs to be preserved
     // during codegen and then dropped. Note that we expect (but don't assume),
#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
   NODE_NAME_CASE(LADD)
   NODE_NAME_CASE(LSUB)
   NODE_NAME_CASE(LOR)
   NODE_NAME_CASE(LXOR)
   NODE_NAME_CASE(LAND)
   NODE_NAME_CASE(LBTS)
   NODE_NAME_CASE(LBTC)
   NODE_NAME_CASE(LBTR)
+  NODE_NAME_CASE(AADD)
+  NODE_NAME_CASE(AOR)
+  NODE_NAME_CASE(AXOR)
+  NODE_NAME_CASE(AAND)
   NODE_NAME_CASE(VZEXT_MOVL)
   NODE_NAME_CASE(VZEXT_LOAD)
   NODE_NAME_CASE(VEXTRACT_STORE)
   NODE_NAME_CASE(VTRUNC)
   NODE_NAME_CASE(VTRUNCS)
   NODE_NAME_CASE(VTRUNCUS)
   NODE_NAME_CASE(VMTRUNC)
   NODE_NAME_CASE(VMTRUNCS)

llvm/lib/Target/X86/X86InstrInfo.td

 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
 def HasCX8       : Predicate<"Subtarget->hasCX8()">;
 def HasCX16      : Predicate<"Subtarget->hasCX16()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def HasENQCMD    : Predicate<"Subtarget->hasENQCMD()">;
 def HasAMXFP16   : Predicate<"Subtarget->hasAMXFP16()">;
 def HasCMPCCXADD : Predicate<"Subtarget->hasCMPCCXADD()">;
 def HasKL        : Predicate<"Subtarget->hasKL()">;
+def HasRAOINT    : Predicate<"Subtarget->hasRAOINT()">;
 def HasWIDEKL    : Predicate<"Subtarget->hasWIDEKL()">;
 def HasHRESET    : Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
 def HasAMXBF16   : Predicate<"Subtarget->hasAMXBF16()">;
 def HasAMXINT8   : Predicate<"Subtarget->hasAMXINT8()">;
 def HasUINTR     : Predicate<"Subtarget->hasUINTR()">;

 include "X86InstrTDX.td"
 
 // Key Locker instructions
 include "X86InstrKL.td"
 
 // AMX instructions
 include "X86InstrAMX.td"
 
+// RAO-INT instructions
+include "X86InstrRAOINT.td"
+
 // System instructions.
 include "X86InstrSystem.td"
 
 // Compiler Pseudo Instructions and Pat Patterns
 include "X86InstrCompiler.td"
 include "X86InstrVecCompiler.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86InstrRAOINT.td

+//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the Intel RAO-INT
+// instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// RAO-INT instructions
+
+def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
+
+def X86rao_add  : SDNode<"X86ISD::AADD", SDTRAOBinaryArith,
+                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def X86rao_or   : SDNode<"X86ISD::AOR",  SDTRAOBinaryArith,
+                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def X86rao_xor  : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith,
+                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def X86rao_and  : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
+                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+
+multiclass RAOINT_BASE<string OpcodeStr> {
+  let Predicates = [HasRAOINT] in
+    def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                 !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
+                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>,
+               Sched<[WriteALURMW]>;
+
+  let Predicates = [HasRAOINT, In64BitMode] in
+    def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                 !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
+                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>,
+               Sched<[WriteALURMW]>, REX_W;
+}
+
+defm AADD : RAOINT_BASE<"add">, T8PS;
+defm AAND : RAOINT_BASE<"and">, T8PD;
+defm AOR  : RAOINT_BASE<"or" >, T8XD;
+defm AXOR : RAOINT_BASE<"xor">, T8XS;

llvm/test/CodeGen/X86/raoint-intrinsics-32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X86
+
+define void @test_int_x86_aadd32(i8* %A, i32 %B) {
+; X64-LABEL: test_int_x86_aadd32:
+; X64:       # %bb.0:
+; X64-NEXT:    aaddl %esi, (%rdi) # encoding: [0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_aadd32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT:    aaddl %eax, (%ecx) # encoding: [0x0f,0x38,0xfc,0x01]
+; X86-NEXT:    retl # encoding: [0xc3]
+  call void @llvm.x86.aadd32(i8* %A, i32 %B)
+  ret  void
+}
+declare void @llvm.x86.aadd32(i8* %A, i32 %B)
+
+define void @test_int_x86_aand32(i8* %A, i32 %B) {
+; X64-LABEL: test_int_x86_aand32:
+; X64:       # %bb.0:
+; X64-NEXT:    aandl %esi, (%rdi) # encoding: [0x66,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_aand32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT:    aandl %eax, (%ecx) # encoding: [0x66,0x0f,0x38,0xfc,0x01]
+; X86-NEXT:    retl # encoding: [0xc3]
+  call void @llvm.x86.aand32(i8* %A, i32 %B)
+  ret  void
+}
+declare void @llvm.x86.aand32(i8* %A, i32 %B)
+
+define void @test_int_x86_aor32(i8* %A, i32 %B) {
+; X64-LABEL: test_int_x86_aor32:
+; X64:       # %bb.0:
+; X64-NEXT:    aorl %esi, (%rdi) # encoding: [0xf2,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_aor32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT:    aorl %eax, (%ecx) # encoding: [0xf2,0x0f,0x38,0xfc,0x01]
+; X86-NEXT:    retl # encoding: [0xc3]
+  call void @llvm.x86.aor32(i8* %A, i32 %B)
+  ret  void
+}
+declare void @llvm.x86.aor32(i8* %A, i32 %B)
+
+define void @test_int_x86_axor32(i8* %A, i32 %B) {
+; X64-LABEL: test_int_x86_axor32:
+; X64:       # %bb.0:
+; X64-NEXT:    axorl %esi, (%rdi) # encoding: [0xf3,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_axor32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
+; X86-NEXT:    axorl %eax, (%ecx) # encoding: [0xf3,0x0f,0x38,0xfc,0x01]
+; X86-NEXT:    retl # encoding: [0xc3]
+  call void @llvm.x86.axor32(i8* %A, i32 %B)
+  ret  void
+}
+declare void @llvm.x86.axor32(i8* %A, i32 %B)

llvm/test/CodeGen/X86/raoint-intrinsics-64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64
+
+define void @test_int_x86_aadd64(i8* %A, i64 %B) {
+; X64-LABEL: test_int_x86_aadd64:
+; X64:       # %bb.0:
+; X64-NEXT:    aaddq %rsi, (%rdi) # encoding: [0x48,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+  call void @llvm.x86.aadd64(i8* %A, i64 %B)
+  ret  void
+}
+declare void @llvm.x86.aadd64(i8* %A, i64 %B)
+
+define void @test_int_x86_aand64(i8* %A, i64 %B) {
+; X64-LABEL: test_int_x86_aand64:
+; X64:       # %bb.0:
+; X64-NEXT:    aandq %rsi, (%rdi) # encoding: [0x66,0x48,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+  call void @llvm.x86.aand64(i8* %A, i64 %B)
+  ret  void
+}
+declare void @llvm.x86.aand64(i8* %A, i64 %B)
+
+define void @test_int_x86_aor64(i8* %A, i64 %B) {
+; X64-LABEL: test_int_x86_aor64:
+; X64:       # %bb.0:
+; X64-NEXT:    aorq %rsi, (%rdi) # encoding: [0xf2,0x48,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+  call void @llvm.x86.aor64(i8* %A, i64 %B)
+  ret  void
+}
+declare void @llvm.x86.aor64(i8* %A, i64 %B)
+
+define void @test_int_x86_axor64(i8* %A, i64 %B) {
+; X64-LABEL: test_int_x86_axor64:
+; X64:       # %bb.0:
+; X64-NEXT:    axorq %rsi, (%rdi) # encoding: [0xf3,0x48,0x0f,0x38,0xfc,0x37]
+; X64-NEXT:    retq # encoding: [0xc3]
+  call void @llvm.x86.axor64(i8* %A, i64 %B)
+  ret  void
+}
+declare void @llvm.x86.axor64(i8* %A, i64 %B)

llvm/test/MC/Disassembler/X86/rao-int.txt

+# RUN: llvm-mc --disassemble %s -triple=i686 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        aaddl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aaddl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aadd dword ptr [edi + 4*eax + 291], ebx
+0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aaddl  %ebx, (%eax)
+# INTEL:      aadd dword ptr [eax], ebx
+0x0f,0x38,0xfc,0x18
+
+# ATT:        aaddl  %ebx, -512(,%ebp,2)
+# INTEL:      aadd dword ptr [2*ebp - 512], ebx
+0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddl  %ebx, 2032(%ecx)
+# INTEL:      aadd dword ptr [ecx + 2032], ebx
+0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddl  %ebx, -2048(%edx)
+# INTEL:      aadd dword ptr [edx - 2048], ebx
+0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aand dword ptr [esp + 8*esi + 268435456], ebx
+0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aandl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aand dword ptr [edi + 4*eax + 291], ebx
+0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aandl  %ebx, (%eax)
+# INTEL:      aand dword ptr [eax], ebx
+0x66,0x0f,0x38,0xfc,0x18
+
+# ATT:        aandl  %ebx, -512(,%ebp,2)
+# INTEL:      aand dword ptr [2*ebp - 512], ebx
+0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandl  %ebx, 2032(%ecx)
+# INTEL:      aand dword ptr [ecx + 2032], ebx
+0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aandl  %ebx, -2048(%edx)
+# INTEL:      aand dword ptr [edx - 2048], ebx
+0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aor dword ptr [esp + 8*esi + 268435456], ebx
+0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aor dword ptr [edi + 4*eax + 291], ebx
+0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aorl  %ebx, (%eax)
+# INTEL:      aor dword ptr [eax], ebx
+0xf2,0x0f,0x38,0xfc,0x18
+
+# ATT:        aorl  %ebx, -512(,%ebp,2)
+# INTEL:      aor dword ptr [2*ebp - 512], ebx
+0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorl  %ebx, 2032(%ecx)
+# INTEL:      aor dword ptr [ecx + 2032], ebx
+0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aorl  %ebx, -2048(%edx)
+# INTEL:      aor dword ptr [edx - 2048], ebx
+0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      axor dword ptr [esp + 8*esi + 268435456], ebx
+0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        axorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      axor dword ptr [edi + 4*eax + 291], ebx
+0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        axorl  %ebx, (%eax)
+# INTEL:      axor dword ptr [eax], ebx
+0xf3,0x0f,0x38,0xfc,0x18
+
+# ATT:        axorl  %ebx, -512(,%ebp,2)
+# INTEL:      axor dword ptr [2*ebp - 512], ebx
+0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorl  %ebx, 2032(%ecx)
+# INTEL:      axor dword ptr [ecx + 2032], ebx
+0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        axorl  %ebx, -2048(%edx)
+# INTEL:      axor dword ptr [edx - 2048], ebx
+0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff

llvm/test/MC/Disassembler/X86/x86-64-rao-int.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        aaddq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aadd qword ptr [rbp + 8*r14 + 268435456], r9
+0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aaddq  %r9, 291(%r8,%rax,4)
+# INTEL:      aadd qword ptr [r8 + 4*rax + 291], r9
+0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aaddq  %r9, (%rip)
+# INTEL:      aadd qword ptr [rip], r9
+0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aaddq  %r9, -512(,%rbp,2)
+# INTEL:      aadd qword ptr [2*rbp - 512], r9
+0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddq  %r9, 2032(%rcx)
+# INTEL:      aadd qword ptr [rcx + 2032], r9
+0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddq  %r9, -2048(%rdx)
+# INTEL:      aadd qword ptr [rdx - 2048], r9
+0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aaddl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aaddl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aadd dword ptr [edi + 4*eax + 291], ebx
+0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aaddl  %ebx, (%eax)
+# INTEL:      aadd dword ptr [eax], ebx
+0x67,0x0f,0x38,0xfc,0x18
+
+# ATT:        aaddl  %ebx, -512(,%ebp,2)
+# INTEL:      aadd dword ptr [2*ebp - 512], ebx
+0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddl  %ebx, 2032(%ecx)
+# INTEL:      aadd dword ptr [ecx + 2032], ebx
+0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddl  %ebx, -2048(%edx)
+# INTEL:      aadd dword ptr [edx - 2048], ebx
+0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aand qword ptr [rbp + 8*r14 + 268435456], r9
+0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aandq  %r9, 291(%r8,%rax,4)
+# INTEL:      aand qword ptr [r8 + 4*rax + 291], r9
+0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aandq  %r9, (%rip)
+# INTEL:      aand qword ptr [rip], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aandq  %r9, -512(,%rbp,2)
+# INTEL:      aand qword ptr [2*rbp - 512], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandq  %r9, 2032(%rcx)
+# INTEL:      aand qword ptr [rcx + 2032], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aandq  %r9, -2048(%rdx)
+# INTEL:      aand qword ptr [rdx - 2048], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aand dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aandl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aand dword ptr [edi + 4*eax + 291], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aandl  %ebx, (%eax)
+# INTEL:      aand dword ptr [eax], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x18
+
+# ATT:        aandl  %ebx, -512(,%ebp,2)
+# INTEL:      aand dword ptr [2*ebp - 512], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandl  %ebx, 2032(%ecx)
+# INTEL:      aand dword ptr [ecx + 2032], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aandl  %ebx, -2048(%edx)
+# INTEL:      aand dword ptr [edx - 2048], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aor qword ptr [rbp + 8*r14 + 268435456], r9
+0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aorq  %r9, 291(%r8,%rax,4)
+# INTEL:      aor qword ptr [r8 + 4*rax + 291], r9
+0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aorq  %r9, (%rip)
+# INTEL:      aor qword ptr [rip], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aorq  %r9, -512(,%rbp,2)
+# INTEL:      aor qword ptr [2*rbp - 512], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorq  %r9, 2032(%rcx)
+# INTEL:      aor qword ptr [rcx + 2032], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aorq  %r9, -2048(%rdx)
+# INTEL:      aor qword ptr [rdx - 2048], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aor dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aor dword ptr [edi + 4*eax + 291], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aorl  %ebx, (%eax)
+# INTEL:      aor dword ptr [eax], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x18
+
+# ATT:        aorl  %ebx, -512(,%ebp,2)
+# INTEL:      aor dword ptr [2*ebp - 512], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorl  %ebx, 2032(%ecx)
+# INTEL:      aor dword ptr [ecx + 2032], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aorl  %ebx, -2048(%edx)
+# INTEL:      aor dword ptr [edx - 2048], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      axor qword ptr [rbp + 8*r14 + 268435456], r9
+0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        axorq  %r9, 291(%r8,%rax,4)
+# INTEL:      axor qword ptr [r8 + 4*rax + 291], r9
+0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        axorq  %r9, (%rip)
+# INTEL:      axor qword ptr [rip], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        axorq  %r9, -512(,%rbp,2)
+# INTEL:      axor qword ptr [2*rbp - 512], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorq  %r9, 2032(%rcx)
+# INTEL:      axor qword ptr [rcx + 2032], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        axorq  %r9, -2048(%rdx)
+# INTEL:      axor qword ptr [rdx - 2048], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      axor dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        axorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      axor dword ptr [edi + 4*eax + 291], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        axorl  %ebx, (%eax)
+# INTEL:      axor dword ptr [eax], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x18
+
+# ATT:        axorl  %ebx, -512(,%ebp,2)
+# INTEL:      axor dword ptr [2*ebp - 512], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorl  %ebx, 2032(%ecx)
+# INTEL:      axor dword ptr [ecx + 2032], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        axorl  %ebx, -2048(%edx)
+# INTEL:      axor dword ptr [edx - 2048], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff

llvm/test/MC/X86/rao-int-att.s

+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      aaddl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aaddl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aaddl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aaddl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aaddl  %ebx, (%eax)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x18]
+               aaddl  %ebx, (%eax)
+
+// CHECK:      aaddl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aaddl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aaddl  %ebx, 2032(%ecx)
+
+// CHECK:      aaddl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aaddl  %ebx, -2048(%edx)
+
+// CHECK:      aandl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aandl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aandl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aandl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aandl  %ebx, (%eax)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18]
+               aandl  %ebx, (%eax)
+
+// CHECK:      aandl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aandl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aandl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aandl  %ebx, 2032(%ecx)
+
+// CHECK:      aandl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aandl  %ebx, -2048(%edx)
+
+// CHECK:      aorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aorl  %ebx, (%eax)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18]
+               aorl  %ebx, (%eax)
+
+// CHECK:      aorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aorl  %ebx, 2032(%ecx)
+
+// CHECK:      aorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aorl  %ebx, -2048(%edx)
+
+// CHECK:      axorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      axorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      axorl  %ebx, (%eax)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18]
+               axorl  %ebx, (%eax)
+
+// CHECK:      axorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      axorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axorl  %ebx, 2032(%ecx)
+
+// CHECK:      axorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axorl  %ebx, -2048(%edx)

llvm/test/MC/X86/rao-int-intel.s

+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aadd dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aadd dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aadd dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aadd dword ptr [eax], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x18]
+               aadd dword ptr [eax], ebx
+
+// CHECK:      aadd dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aadd dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aadd dword ptr [ecx + 2032], ebx
+
+// CHECK:      aadd dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aadd dword ptr [edx - 2048], ebx
+
+// CHECK:      aand dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aand dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aand dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aand dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aand dword ptr [eax], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18]
+               aand dword ptr [eax], ebx
+
+// CHECK:      aand dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aand dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aand dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aand dword ptr [ecx + 2032], ebx
+
+// CHECK:      aand dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aand dword ptr [edx - 2048], ebx
+
+// CHECK:      aor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aor dword ptr [eax], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18]
+               aor dword ptr [eax], ebx
+
+// CHECK:      aor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aor dword ptr [ecx + 2032], ebx
+
+// CHECK:      aor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aor dword ptr [edx - 2048], ebx
+
+// CHECK:      axor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      axor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      axor dword ptr [eax], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18]
+               axor dword ptr [eax], ebx
+
+// CHECK:      axor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      axor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axor dword ptr [ecx + 2032], ebx
+
+// CHECK:      axor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axor dword ptr [edx - 2048], ebx

llvm/test/MC/X86/x86-64-rao-int-att.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      aaddq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aaddq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aaddq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aaddq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aaddq  %r9, (%rip)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aaddq  %r9, (%rip)
+
+// CHECK:      aaddq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddq  %r9, -512(,%rbp,2)
+
+// CHECK:      aaddq  %r9, 2032(%rcx)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aaddq  %r9, 2032(%rcx)
+
+// CHECK:      aaddq  %r9, -2048(%rdx)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aaddq  %r9, -2048(%rdx)
+
+// CHECK:      aaddl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aaddl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aaddl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aaddl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aaddl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18]
+               aaddl  %ebx, (%eax)
+
+// CHECK:      aaddl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aaddl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aaddl  %ebx, 2032(%ecx)
+
+// CHECK:      aaddl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aaddl  %ebx, -2048(%edx)
+
+// CHECK:      aandq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aandq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aandq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aandq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aandq  %r9, (%rip)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aandq  %r9, (%rip)
+
+// CHECK:      aandq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aandq  %r9, -512(,%rbp,2)
+
+// CHECK:      aandq  %r9, 2032(%rcx)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aandq  %r9, 2032(%rcx)
+
+// CHECK:      aandq  %r9, -2048(%rdx)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aandq  %r9, -2048(%rdx)
+
+// CHECK:      aandl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aandl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aandl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aandl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aandl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18]
+               aandl  %ebx, (%eax)
+
+// CHECK:      aandl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aandl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aandl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aandl  %ebx, 2032(%ecx)
+
+// CHECK:      aandl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aandl  %ebx, -2048(%edx)
+
+// CHECK:      aorq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aorq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aorq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aorq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aorq  %r9, (%rip)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aorq  %r9, (%rip)
+
+// CHECK:      aorq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aorq  %r9, -512(,%rbp,2)
+
+// CHECK:      aorq  %r9, 2032(%rcx)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aorq  %r9, 2032(%rcx)
+
+// CHECK:      aorq  %r9, -2048(%rdx)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aorq  %r9, -2048(%rdx)
+
+// CHECK:      aorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aorl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18]
+               aorl  %ebx, (%eax)
+
+// CHECK:      aorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aorl  %ebx, 2032(%ecx)
+
+// CHECK:      aorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aorl  %ebx, -2048(%edx)
+
+// CHECK:      axorq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               axorq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      axorq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               axorq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      axorq  %r9, (%rip)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               axorq  %r9, (%rip)
+
+// CHECK:      axorq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               axorq  %r9, -512(,%rbp,2)
+
+// CHECK:      axorq  %r9, 2032(%rcx)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               axorq  %r9, 2032(%rcx)
+
+// CHECK:      axorq  %r9, -2048(%rdx)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               axorq  %r9, -2048(%rdx)
+
+// CHECK:      axorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      axorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      axorl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18]
+               axorl  %ebx, (%eax)
+
+// CHECK:      axorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      axorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axorl  %ebx, 2032(%ecx)
+
+// CHECK:      axorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axorl  %ebx, -2048(%edx)

llvm/test/MC/X86/x86-64-rao-int-intel.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      aadd qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aadd qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aadd qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aadd qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aadd qword ptr [rip], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aadd qword ptr [rip], r9
+
+// CHECK:      aadd qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd qword ptr [2*rbp - 512], r9
+
+// CHECK:      aadd qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aadd qword ptr [rcx + 2032], r9
+
+// CHECK:      aadd qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aadd qword ptr [rdx - 2048], r9
+
+// CHECK:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aadd dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aadd dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aadd dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aadd dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18]
+               aadd dword ptr [eax], ebx
+
+// CHECK:      aadd dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aadd dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aadd dword ptr [ecx + 2032], ebx
+
+// CHECK:      aadd dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aadd dword ptr [edx - 2048], ebx
+
+// CHECK:      aand qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aand qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aand qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aand qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aand qword ptr [rip], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aand qword ptr [rip], r9
+
+// CHECK:      aand qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aand qword ptr [2*rbp - 512], r9
+
+// CHECK:      aand qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aand qword ptr [rcx + 2032], r9
+
+// CHECK:      aand qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aand qword ptr [rdx - 2048], r9
+
+// CHECK:      aand dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aand dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aand dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aand dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aand dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18]
+               aand dword ptr [eax], ebx
+
+// CHECK:      aand dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aand dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aand dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aand dword ptr [ecx + 2032], ebx
+
+// CHECK:      aand dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aand dword ptr [edx - 2048], ebx
+
+// CHECK:      aor qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aor qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aor qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aor qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aor qword ptr [rip], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aor qword ptr [rip], r9
+
+// CHECK:      aor qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aor qword ptr [2*rbp - 512], r9
+
+// CHECK:      aor qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aor qword ptr [rcx + 2032], r9
+
+// CHECK:      aor qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aor qword ptr [rdx - 2048], r9
+
+// CHECK:      aor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aor dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18]
+               aor dword ptr [eax], ebx
+
+// CHECK:      aor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aor dword ptr [ecx + 2032], ebx
+
+// CHECK:      aor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aor dword ptr [edx - 2048], ebx
+
+// CHECK:      axor qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               axor qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      axor qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               axor qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      axor qword ptr [rip], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               axor qword ptr [rip], r9
+
+// CHECK:      axor qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               axor qword ptr [2*rbp - 512], r9
+
+// CHECK:      axor qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               axor qword ptr [rcx + 2032], r9
+
+// CHECK:      axor qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               axor qword ptr [rdx - 2048], r9
+
+// CHECK:      axor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      axor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      axor dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18]
+               axor dword ptr [eax], ebx
+
+// CHECK:      axor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      axor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axor dword ptr [ecx + 2032], ebx
+
+// CHECK:      axor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axor dword ptr [edx - 2048], ebx