User Details
- User Since
- Sep 24 2018, 10:28 PM (121 w, 3 d)
Today
Yesterday
Tue, Jan 19
Rebase.
Address Pengfei's comments.
Mon, Jan 18
Address Pengfei's comments.
Address Pengfei's comments.
Sat, Jan 16
Address Xiang's comments.
Make the logic more clean.
Fri, Jan 15
Thu, Jan 14
Get tile register number from backend.
We also need check tile config register interference. Since we
don't model the config register we should check interference from the
ldtilecfg to each tile data register def.
ldtilecfg / \ BB1 BB2 / \ call BB3 / \ %1=tileload %2=tilezero
We can start from the instruction of each tile def, and backward to
ldtilecfg. If there is any call instruction, and tile data register is
not preserved, we should insert ldtilecfg after the call instruction.
Wed, Jan 13
Address Pengfei's comments.
Tue, Jan 12
Support tile_zero and fix bugs for tile_load and tile_store.
Mon, Jan 11
Address Pengfei's comments.
Thank David!
Sun, Jan 10
Address Pengfei's comments.
Sat, Jan 9
Fix typo in the comments.
Wed, Jan 6
Add test case for IPRA.
Tue, Jan 5
Remove dead code.
Sun, Jan 3
Address Wei's comments.
Rebase.
Wed, Dec 30
Rebase.
Add avx512f in test case.
Rebase.
Tue, Dec 29
Remove datalayout from test case.
Rebase
Thu, Dec 24
Refine comments.
Address Pengfei's comments.
Wed, Dec 23
Address Pengfei's comments.
Improve the comments.
Address Pengfei's comments.
Dec 22 2020
Scalarize tilestore.
Move comments.
Address Pengfei's comments.
Rebase and fix lit test case failure.