[X86][1/2] SUPPORT RAO-INT

[pengfei]

Summary

For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Initial authored by Liu Chen (@LiuChen3)

[pengfei]

Add atomic operations lowering for RAO-INT instructions.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.h

801 ↗

(On Diff #468020)

very pedantic, but are these likely to get confused with ROR / RAND instructions? Would it be better to use a RAO_ prefix?

llvm/test/CodeGen/X86/atomic-instructions-32.ll

5 ↗

(On Diff #468020)

Is the -O0 necessary?

[craig.topper]

llvm/lib/Target/X86/X86.td

259

Why do these require SSE2?

llvm/lib/Target/X86/X86ISelLowering.h

801 ↗

(On Diff #468020)

Why not AADD etc to match the instruction names?

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

31799 ↗

(On Diff #468020)

This should probably be in a separate patch.

[pengfei]

Split atomic operations lowering into D136032.

[pengfei]

llvm/lib/Target/X86/X86.td

259

We need mfence instructions for strong orders. The mfence feature relies on SSE2.
I see your concern, we may need split these features from SSE2. Filed an issue https://github.com/llvm/llvm-project/issues/58388

llvm/lib/Target/X86/X86ISelLowering.h

801 ↗

(On Diff #468020)

Good ideas, thanks!

llvm/test/CodeGen/X86/atomic-instructions-32.ll

5 ↗

(On Diff #468020)

I missed that, thanks!

[craig.topper]

llvm/lib/Target/X86/X86.td

259

The lowering code for atomics could check SSE2 in addition to the RAO-INT feature. My primary concern was that the RAO-INT feature itself shouldn't require it.

Are there going to be intrinsics for RAO-INT?

[pengfei]

llvm/lib/Target/X86/X86.td

259

I don't think there will be a target supports RAO-INT but no SSE2. All I can think out is for Kernel build that disable vector registers intentionally.

Are there going to be intrinsics for RAO-INT?

This is a good question. In fact we wander whether providing intrinsics or not. The current preference is not. We don't want to add new intrinsics arbitrarily, there're burdens to maintenance and it's always easy to adding per to actual requests than removing afterwards.

[pengfei]

Add intrinsic support first.

[FreddyYe]

clang/docs/ReleaseNotes.rst

540

Add bullets for supported intrinsics.

clang/test/CodeGen/X86/raoint-builtins.c

2 ↗

(On Diff #469642)

32 bit test coverage.

llvm/lib/Target/X86/X86InstrRAOINT.td

10

RAOINT

[pengfei]

Address review comments; Change intrinsics name from *_si* to *_i*.

[RKSimon]

LGTM

clang/docs/ReleaseNotes.rst

 -----------------------
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for ``-mcpu``.
   Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
 
 X86 Support in Clang
 --------------------
 - Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk.
 - Fix 32-bit ``__fastcall`` and ``__vectorcall`` ABI mismatch with MSVC.
+- Support ISA of ``RAO-INT``.
 
 DWARF Support in Clang
 ----------------------
 
 Arm and AArch64 Support in Clang
 --------------------------------
 
 - The target(..) function attributes for AArch64 now accept:

clang/include/clang/Driver/Options.td

 def mpopcnt : Flag<["-"], "mpopcnt">, Group<m_x86_Features_Group>;
 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group<m_x86_Features_Group>;
 def mprefetchwt1 : Flag<["-"], "mprefetchwt1">, Group<m_x86_Features_Group>;
 def mno_prefetchwt1 : Flag<["-"], "mno-prefetchwt1">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mptwrite : Flag<["-"], "mptwrite">, Group<m_x86_Features_Group>;
 def mno_ptwrite : Flag<["-"], "mno-ptwrite">, Group<m_x86_Features_Group>;
+def mraoint : Flag<["-"], "mraoint">, Group<m_x86_Features_Group>;
+def mno_raoint : Flag<["-"], "mno-raoint">, Group<m_x86_Features_Group>;
 def mrdpid : Flag<["-"], "mrdpid">, Group<m_x86_Features_Group>;
 def mno_rdpid : Flag<["-"], "mno-rdpid">, Group<m_x86_Features_Group>;
 def mrdpru : Flag<["-"], "mrdpru">, Group<m_x86_Features_Group>;
 def mno_rdpru : Flag<["-"], "mno-rdpru">, Group<m_x86_Features_Group>;
 def mrdrnd : Flag<["-"], "mrdrnd">, Group<m_x86_Features_Group>;
 def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasLAHFSAHF = false;
   bool HasWBNOINVD = false;
   bool HasWAITPKG = false;
   bool HasMOVDIRI = false;
   bool HasMOVDIR64B = false;
   bool HasPTWRITE = false;
   bool HasINVPCID = false;
   bool HasENQCMD = false;
+  bool HasRAOINT = false;
   bool HasKL = false;      // For key locker
   bool HasWIDEKL = false; // For wide key locker
   bool HasHRESET = false;
   bool HasAVXVNNI = false;
   bool HasAMXTILE = false;
   bool HasAMXINT8 = false;
   bool HasAMXBF16 = false;
   bool HasSERIALIZE = false;

clang/lib/Basic/Targets/X86.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+hreset") {
       HasHRESET = true;
     } else if (Feature == "+amx-bf16") {
       HasAMXBF16 = true;
     } else if (Feature == "+amx-int8") {
       HasAMXINT8 = true;
     } else if (Feature == "+amx-tile") {
       HasAMXTILE = true;
+    } else if (Feature == "+raoint") {
+      HasRAOINT = true;
     } else if (Feature == "+avxvnni") {
       HasAVXVNNI = true;
     } else if (Feature == "+serialize") {
       HasSERIALIZE = true;
     } else if (Feature == "+tsxldtrk") {
       HasTSXLDTRK = true;
     } else if (Feature == "+uintr") {
       HasUINTR = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasHRESET)
     Builder.defineMacro("__HRESET__");
   if (HasAMXTILE)
     Builder.defineMacro("__AMXTILE__");
   if (HasAMXINT8)
     Builder.defineMacro("__AMXINT8__");
   if (HasAMXBF16)
     Builder.defineMacro("__AMXBF16__");
+  if (HasRAOINT)
+    Builder.defineMacro("__RAOINT__");
   if (HasAVXVNNI)
     Builder.defineMacro("__AVXVNNI__");
   if (HasSERIALIZE)
     Builder.defineMacro("__SERIALIZE__");
   if (HasTSXLDTRK)
     Builder.defineMacro("__TSXLDTRK__");
   if (HasUINTR)
     Builder.defineMacro("__UINTR__");
return llvm::StringSwitch<bool>(Name)
       .Case("mwaitx", true)
       .Case("pclmul", true)
       .Case("pconfig", true)
       .Case("pku", true)
       .Case("popcnt", true)
       .Case("prefetchwt1", true)
       .Case("prfchw", true)
       .Case("ptwrite", true)
+      .Case("raoint", true)
       .Case("rdpid", true)
       .Case("rdpru", true)
       .Case("rdrnd", true)
       .Case("rdseed", true)
       .Case("rtm", true)
       .Case("sahf", true)
       .Case("serialize", true)
       .Case("sgx", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("mwaitx", HasMWAITX)
       .Case("pclmul", HasPCLMUL)
       .Case("pconfig", HasPCONFIG)
       .Case("pku", HasPKU)
       .Case("popcnt", HasPOPCNT)
       .Case("prefetchwt1", HasPREFETCHWT1)
       .Case("prfchw", HasPRFCHW)
       .Case("ptwrite", HasPTWRITE)
+      .Case("raoint", HasRAOINT)
       .Case("rdpid", HasRDPID)
       .Case("rdpru", HasRDPRU)
       .Case("rdrnd", HasRDRND)
       .Case("rdseed", HasRDSEED)
       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
       .Case("rtm", HasRTM)
       .Case("sahf", HasLAHFSAHF)
       .Case("serialize", HasSERIALIZE)

clang/lib/Headers/cpuid.h

 #define bit_PCONFIG       0x00040000
 #define bit_IBT           0x00100000
 #define bit_AMXBF16       0x00400000
 #define bit_AVX512FP16    0x00800000
 #define bit_AMXTILE       0x01000000
 #define bit_AMXINT8       0x02000000
 
 /* Features in %eax for leaf 7 sub-leaf 1 */
+#define bit_RAOINT        0x00000008
 #define bit_AVXVNNI       0x00000010
 #define bit_AVX512BF16    0x00000020
 #define bit_HRESET        0x00400000
 
 /* Features in %eax for leaf 13 sub-leaf 1 */
 #define bit_XSAVEOPT    0x00000001
 #define bit_XSAVEC      0x00000002
 #define bit_XSAVES      0x00000008

clang/test/Driver/x86-target-features.c

 // AVX-VNNI: "-target-feature" "+avxvnni"
 // NO-AVX-VNNI: "-target-feature" "-avxvnni"
 
 // RUN: %clang --target=i386 -march=i386 -mavx512fp16 %s -### 2>&1 | FileCheck -check-prefix=AVX512FP16 %s
 // RUN: %clang --target=i386 -march=i386 -mno-avx512fp16 %s -### 2>&1 | FileCheck -check-prefix=NO-AVX512FP16 %s
 // AVX512FP16: "-target-feature" "+avx512fp16"
 // NO-AVX512FP16: "-target-feature" "-avx512fp16"
 
+// RUN: %clang --target=i386 -march=i386 -mraoint %s -### 2>&1 | FileCheck -check-prefix=RAOINT %s
+// RUN: %clang --target=i386 -march=i386 -mno-raoint %s -### 2>&1 | FileCheck -check-prefix=NO-RAOINT %s
+// RAOINT: "-target-feature" "+raoint"
+// NO-RAOINT: "-target-feature" "-raoint"
+
 // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
 // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
 // CRC32: "-target-feature" "+crc32"
 // NO-CRC32: "-target-feature" "-crc32"
 
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-RET,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=none -mharden-sls=all %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,SLS-RET %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=all -mharden-sls=none %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return,indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefix=BAD-SLS %s
 // NO-SLS-NOT: "+harden-sls-
 // SLS-RET-DAG: "-target-feature" "+harden-sls-ret"
 // SLS-IJMP-DAG: "-target-feature" "+harden-sls-ijmp"
 // NO-SLS-NOT: "+harden-sls-
 // BAD-SLS: unsupported argument '{{[^']+}}' to option '-mharden-sls='

clang/test/Preprocessor/x86_target_features.c

 // AVX512FP16NOAVX512BW-NOT: #define __AVX512BW__ 1
 // AVX512FP16NOAVX512BW-NOT: #define __AVX512FP16__ 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512dq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512DQ %s
 
 // AVX512FP16NOAVX512DQ-NOT: #define __AVX512DQ__ 1
 // AVX512FP16NOAVX512DQ-NOT: #define __AVX512FP16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mraoint -x c -E -dM -o - %s | FileCheck  -check-prefix=RAOINT %s
+
+// RAOINT: #define __RAOINT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mno-raoint -x c -E -dM -o - %s | FileCheck  -check-prefix=NO-RAOINT %s
+
+// NO-RAOINT-NOT: #define __RAOINT__ 1
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
 
 // CRC32: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-crc32 -x c -E -dM -o - %s | FileCheck -check-prefix=NOCRC32 %s
 
 // NOCRC32-NOT: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpru -x c -E -dM -o - %s | FileCheck -check-prefix=RDPRU %s
 
 // RDPRU: #define __RDPRU__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpru -x c -E -dM -o - %s | FileCheck -check-prefix=NORDPRU %s
 
 // NORDPRU-NOT: #define __RDPRU__ 1

llvm/include/llvm/Support/X86TargetParser.def

 X86_FEATURE       (WAITPKG,         "waitpkg")
 X86_FEATURE       (WBNOINVD,        "wbnoinvd")
 X86_FEATURE       (X87,             "x87")
 X86_FEATURE       (XSAVE,           "xsave")
 X86_FEATURE       (XSAVEC,          "xsavec")
 X86_FEATURE       (XSAVEOPT,        "xsaveopt")
 X86_FEATURE       (XSAVES,          "xsaves")
 X86_FEATURE       (HRESET,          "hreset")
+X86_FEATURE       (RAOINT,          "raoint")
 X86_FEATURE       (AVX512FP16,      "avx512fp16")
 X86_FEATURE       (AVXVNNI,         "avxvnni")
 // These features aren't really CPU features, but the frontend can set them.
 X86_FEATURE       (RETPOLINE_EXTERNAL_THUNK,    "retpoline-external-thunk")
 X86_FEATURE       (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
 X86_FEATURE       (RETPOLINE_INDIRECT_CALLS,    "retpoline-indirect-calls")
 X86_FEATURE       (LVI_CFI,                     "lvi-cfi")
 X86_FEATURE       (LVI_LOAD_HARDENING,          "lvi-load-hardening")

llvm/lib/Support/Host.cpp

#endif
   // For more info, see X86 ISA docs.
   Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
   Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
   Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
   Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
   Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
   bool HasLeaf7Subleaf1 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
+  Features["raoint"]     = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
   Features["avxvnni"]    = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
   Features["hreset"]     = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
 
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.

llvm/lib/Support/X86TargetParser.cpp

 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
 
 // AMX Features
 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
 
+static constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
 static constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
     FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
 // Key Locker Features
 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
 
 // AVXVNNI Features
 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;

llvm/lib/Target/X86/X86.td

 def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
                                       "Support AMX-TILE instructions">;
 def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
                                       "Support AMX-INT8 instructions",
                                       [FeatureAMXTILE]>;
 def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
                                       "Support AMX-BF16 instructions",
                                       [FeatureAMXTILE]>;
+def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",
+                                     "Support RAO-INT instructions",
+                                     []>;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
                                       "Invalidate Process-Context Identifier">;
 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
                                       "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
                                       "Flush A Cache Line Optimized">;
 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
                                       "Cache Line Write Back">;

llvm/lib/Target/X86/X86InstrInfo.td

 def HasRDPRU     : Predicate<"Subtarget->hasRDPRU()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
 def HasCX8       : Predicate<"Subtarget->hasCX8()">;
 def HasCX16      : Predicate<"Subtarget->hasCX16()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def HasENQCMD    : Predicate<"Subtarget->hasENQCMD()">;
 def HasKL        : Predicate<"Subtarget->hasKL()">;
+def HasRAOINT    : Predicate<"Subtarget->hasRAOINT()">;
 def HasWIDEKL    : Predicate<"Subtarget->hasWIDEKL()">;
 def HasHRESET    : Predicate<"Subtarget->hasHRESET()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
 def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
 def HasAMXBF16   : Predicate<"Subtarget->hasAMXBF16()">;
 def HasAMXINT8   : Predicate<"Subtarget->hasAMXINT8()">;
 def HasUINTR     : Predicate<"Subtarget->hasUINTR()">;

 include "X86InstrTDX.td"
 
 // Key Locker instructions
 include "X86InstrKL.td"
 
 // AMX instructions
 include "X86InstrAMX.td"
 
+// RAOINT instructions
+include "X86InstrRAOINT.td"
+
 // System instructions.
 include "X86InstrSystem.td"
 
 // Compiler Pseudo Instructions and Pat Patterns
 include "X86InstrCompiler.td"
 include "X86InstrVecCompiler.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86InstrRAOINT.td

+//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the Intel AMX instruction
+// set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// RAOINT instructions
+multiclass RAOINT_BASE<string OpcodeStr> {
+  let Predicates = [HasRAOINT] in
+    def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                 !strconcat(OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
+                 []>, Sched<[WriteALURMW]>;
+
+  let Predicates = [HasRAOINT, In64BitMode] in
+    def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                 !strconcat(OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
+                 []>, Sched<[WriteALURMW]>, REX_W;
+}
+
+defm AADD : RAOINT_BASE<"aadd">, T8PS;
+defm AAND : RAOINT_BASE<"aand">, T8PD;
+defm AOR  : RAOINT_BASE<"aor" >, T8XD;
+defm AXOR : RAOINT_BASE<"axor">, T8XS;

llvm/test/MC/Disassembler/X86/rao-int.txt

+# RUN: llvm-mc --disassemble %s -triple=i686 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        aaddl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aaddl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aadd dword ptr [edi + 4*eax + 291], ebx
+0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aaddl  %ebx, (%eax)
+# INTEL:      aadd dword ptr [eax], ebx
+0x0f,0x38,0xfc,0x18
+
+# ATT:        aaddl  %ebx, -512(,%ebp,2)
+# INTEL:      aadd dword ptr [2*ebp - 512], ebx
+0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddl  %ebx, 2032(%ecx)
+# INTEL:      aadd dword ptr [ecx + 2032], ebx
+0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddl  %ebx, -2048(%edx)
+# INTEL:      aadd dword ptr [edx - 2048], ebx
+0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aand dword ptr [esp + 8*esi + 268435456], ebx
+0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aandl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aand dword ptr [edi + 4*eax + 291], ebx
+0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aandl  %ebx, (%eax)
+# INTEL:      aand dword ptr [eax], ebx
+0x66,0x0f,0x38,0xfc,0x18
+
+# ATT:        aandl  %ebx, -512(,%ebp,2)
+# INTEL:      aand dword ptr [2*ebp - 512], ebx
+0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandl  %ebx, 2032(%ecx)
+# INTEL:      aand dword ptr [ecx + 2032], ebx
+0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aandl  %ebx, -2048(%edx)
+# INTEL:      aand dword ptr [edx - 2048], ebx
+0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aor dword ptr [esp + 8*esi + 268435456], ebx
+0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aor dword ptr [edi + 4*eax + 291], ebx
+0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aorl  %ebx, (%eax)
+# INTEL:      aor dword ptr [eax], ebx
+0xf2,0x0f,0x38,0xfc,0x18
+
+# ATT:        aorl  %ebx, -512(,%ebp,2)
+# INTEL:      aor dword ptr [2*ebp - 512], ebx
+0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorl  %ebx, 2032(%ecx)
+# INTEL:      aor dword ptr [ecx + 2032], ebx
+0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aorl  %ebx, -2048(%edx)
+# INTEL:      aor dword ptr [edx - 2048], ebx
+0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      axor dword ptr [esp + 8*esi + 268435456], ebx
+0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        axorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      axor dword ptr [edi + 4*eax + 291], ebx
+0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        axorl  %ebx, (%eax)
+# INTEL:      axor dword ptr [eax], ebx
+0xf3,0x0f,0x38,0xfc,0x18
+
+# ATT:        axorl  %ebx, -512(,%ebp,2)
+# INTEL:      axor dword ptr [2*ebp - 512], ebx
+0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorl  %ebx, 2032(%ecx)
+# INTEL:      axor dword ptr [ecx + 2032], ebx
+0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        axorl  %ebx, -2048(%edx)
+# INTEL:      axor dword ptr [edx - 2048], ebx
+0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff

llvm/test/MC/Disassembler/X86/x86-64-rao-int.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        aaddq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aadd qword ptr [rbp + 8*r14 + 268435456], r9
+0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aaddq  %r9, 291(%r8,%rax,4)
+# INTEL:      aadd qword ptr [r8 + 4*rax + 291], r9
+0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aaddq  %r9, (%rip)
+# INTEL:      aadd qword ptr [rip], r9
+0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aaddq  %r9, -512(,%rbp,2)
+# INTEL:      aadd qword ptr [2*rbp - 512], r9
+0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddq  %r9, 2032(%rcx)
+# INTEL:      aadd qword ptr [rcx + 2032], r9
+0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddq  %r9, -2048(%rdx)
+# INTEL:      aadd qword ptr [rdx - 2048], r9
+0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aaddl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aaddl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aadd dword ptr [edi + 4*eax + 291], ebx
+0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aaddl  %ebx, (%eax)
+# INTEL:      aadd dword ptr [eax], ebx
+0x67,0x0f,0x38,0xfc,0x18
+
+# ATT:        aaddl  %ebx, -512(,%ebp,2)
+# INTEL:      aadd dword ptr [2*ebp - 512], ebx
+0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aaddl  %ebx, 2032(%ecx)
+# INTEL:      aadd dword ptr [ecx + 2032], ebx
+0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aaddl  %ebx, -2048(%edx)
+# INTEL:      aadd dword ptr [edx - 2048], ebx
+0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aand qword ptr [rbp + 8*r14 + 268435456], r9
+0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aandq  %r9, 291(%r8,%rax,4)
+# INTEL:      aand qword ptr [r8 + 4*rax + 291], r9
+0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aandq  %r9, (%rip)
+# INTEL:      aand qword ptr [rip], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aandq  %r9, -512(,%rbp,2)
+# INTEL:      aand qword ptr [2*rbp - 512], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandq  %r9, 2032(%rcx)
+# INTEL:      aand qword ptr [rcx + 2032], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aandq  %r9, -2048(%rdx)
+# INTEL:      aand qword ptr [rdx - 2048], r9
+0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aandl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aand dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aandl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aand dword ptr [edi + 4*eax + 291], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aandl  %ebx, (%eax)
+# INTEL:      aand dword ptr [eax], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x18
+
+# ATT:        aandl  %ebx, -512(,%ebp,2)
+# INTEL:      aand dword ptr [2*ebp - 512], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aandl  %ebx, 2032(%ecx)
+# INTEL:      aand dword ptr [ecx + 2032], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aandl  %ebx, -2048(%edx)
+# INTEL:      aand dword ptr [edx - 2048], ebx
+0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      aor qword ptr [rbp + 8*r14 + 268435456], r9
+0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        aorq  %r9, 291(%r8,%rax,4)
+# INTEL:      aor qword ptr [r8 + 4*rax + 291], r9
+0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        aorq  %r9, (%rip)
+# INTEL:      aor qword ptr [rip], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        aorq  %r9, -512(,%rbp,2)
+# INTEL:      aor qword ptr [2*rbp - 512], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorq  %r9, 2032(%rcx)
+# INTEL:      aor qword ptr [rcx + 2032], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        aorq  %r9, -2048(%rdx)
+# INTEL:      aor qword ptr [rdx - 2048], r9
+0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        aorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      aor dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        aorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      aor dword ptr [edi + 4*eax + 291], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        aorl  %ebx, (%eax)
+# INTEL:      aor dword ptr [eax], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x18
+
+# ATT:        aorl  %ebx, -512(,%ebp,2)
+# INTEL:      aor dword ptr [2*ebp - 512], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        aorl  %ebx, 2032(%ecx)
+# INTEL:      aor dword ptr [ecx + 2032], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        aorl  %ebx, -2048(%edx)
+# INTEL:      aor dword ptr [edx - 2048], ebx
+0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorq  %r9, 268435456(%rbp,%r14,8)
+# INTEL:      axor qword ptr [rbp + 8*r14 + 268435456], r9
+0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:        axorq  %r9, 291(%r8,%rax,4)
+# INTEL:      axor qword ptr [r8 + 4*rax + 291], r9
+0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT:        axorq  %r9, (%rip)
+# INTEL:      axor qword ptr [rip], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00
+
+# ATT:        axorq  %r9, -512(,%rbp,2)
+# INTEL:      axor qword ptr [2*rbp - 512], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorq  %r9, 2032(%rcx)
+# INTEL:      axor qword ptr [rcx + 2032], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00
+
+# ATT:        axorq  %r9, -2048(%rdx)
+# INTEL:      axor qword ptr [rdx - 2048], r9
+0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff
+
+# ATT:        axorl  %ebx, 268435456(%esp,%esi,8)
+# INTEL:      axor dword ptr [esp + 8*esi + 268435456], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        axorl  %ebx, 291(%edi,%eax,4)
+# INTEL:      axor dword ptr [edi + 4*eax + 291], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        axorl  %ebx, (%eax)
+# INTEL:      axor dword ptr [eax], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x18
+
+# ATT:        axorl  %ebx, -512(,%ebp,2)
+# INTEL:      axor dword ptr [2*ebp - 512], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        axorl  %ebx, 2032(%ecx)
+# INTEL:      axor dword ptr [ecx + 2032], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00
+
+# ATT:        axorl  %ebx, -2048(%edx)
+# INTEL:      axor dword ptr [edx - 2048], ebx
+0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff

llvm/test/MC/X86/rao-int-att.s

+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      aaddl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aaddl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aaddl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aaddl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aaddl  %ebx, (%eax)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x18]
+               aaddl  %ebx, (%eax)
+
+// CHECK:      aaddl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aaddl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aaddl  %ebx, 2032(%ecx)
+
+// CHECK:      aaddl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aaddl  %ebx, -2048(%edx)
+
+// CHECK:      aandl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aandl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aandl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aandl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aandl  %ebx, (%eax)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18]
+               aandl  %ebx, (%eax)
+
+// CHECK:      aandl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aandl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aandl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aandl  %ebx, 2032(%ecx)
+
+// CHECK:      aandl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aandl  %ebx, -2048(%edx)
+
+// CHECK:      aorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aorl  %ebx, (%eax)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18]
+               aorl  %ebx, (%eax)
+
+// CHECK:      aorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aorl  %ebx, 2032(%ecx)
+
+// CHECK:      aorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aorl  %ebx, -2048(%edx)
+
+// CHECK:      axorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      axorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      axorl  %ebx, (%eax)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18]
+               axorl  %ebx, (%eax)
+
+// CHECK:      axorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      axorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axorl  %ebx, 2032(%ecx)
+
+// CHECK:      axorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axorl  %ebx, -2048(%edx)

llvm/test/MC/X86/rao-int-intel.s

+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aadd dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aadd dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aadd dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aadd dword ptr [eax], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x18]
+               aadd dword ptr [eax], ebx
+
+// CHECK:      aadd dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aadd dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aadd dword ptr [ecx + 2032], ebx
+
+// CHECK:      aadd dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aadd dword ptr [edx - 2048], ebx
+
+// CHECK:      aand dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aand dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aand dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aand dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aand dword ptr [eax], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18]
+               aand dword ptr [eax], ebx
+
+// CHECK:      aand dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aand dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aand dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aand dword ptr [ecx + 2032], ebx
+
+// CHECK:      aand dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aand dword ptr [edx - 2048], ebx
+
+// CHECK:      aor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aor dword ptr [eax], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18]
+               aor dword ptr [eax], ebx
+
+// CHECK:      aor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aor dword ptr [ecx + 2032], ebx
+
+// CHECK:      aor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aor dword ptr [edx - 2048], ebx
+
+// CHECK:      axor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      axor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      axor dword ptr [eax], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18]
+               axor dword ptr [eax], ebx
+
+// CHECK:      axor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      axor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axor dword ptr [ecx + 2032], ebx
+
+// CHECK:      axor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axor dword ptr [edx - 2048], ebx

llvm/test/MC/X86/x86-64-rao-int-att.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      aaddq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aaddq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aaddq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aaddq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aaddq  %r9, (%rip)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aaddq  %r9, (%rip)
+
+// CHECK:      aaddq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddq  %r9, -512(,%rbp,2)
+
+// CHECK:      aaddq  %r9, 2032(%rcx)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aaddq  %r9, 2032(%rcx)
+
+// CHECK:      aaddq  %r9, -2048(%rdx)
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aaddq  %r9, -2048(%rdx)
+
+// CHECK:      aaddl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aaddl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aaddl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aaddl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aaddl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18]
+               aaddl  %ebx, (%eax)
+
+// CHECK:      aaddl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aaddl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aaddl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aaddl  %ebx, 2032(%ecx)
+
+// CHECK:      aaddl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aaddl  %ebx, -2048(%edx)
+
+// CHECK:      aandq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aandq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aandq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aandq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aandq  %r9, (%rip)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aandq  %r9, (%rip)
+
+// CHECK:      aandq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aandq  %r9, -512(,%rbp,2)
+
+// CHECK:      aandq  %r9, 2032(%rcx)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aandq  %r9, 2032(%rcx)
+
+// CHECK:      aandq  %r9, -2048(%rdx)
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aandq  %r9, -2048(%rdx)
+
+// CHECK:      aandl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aandl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aandl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aandl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aandl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18]
+               aandl  %ebx, (%eax)
+
+// CHECK:      aandl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aandl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aandl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aandl  %ebx, 2032(%ecx)
+
+// CHECK:      aandl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aandl  %ebx, -2048(%edx)
+
+// CHECK:      aorq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aorq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      aorq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aorq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      aorq  %r9, (%rip)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aorq  %r9, (%rip)
+
+// CHECK:      aorq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aorq  %r9, -512(,%rbp,2)
+
+// CHECK:      aorq  %r9, 2032(%rcx)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aorq  %r9, 2032(%rcx)
+
+// CHECK:      aorq  %r9, -2048(%rdx)
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aorq  %r9, -2048(%rdx)
+
+// CHECK:      aorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      aorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      aorl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18]
+               aorl  %ebx, (%eax)
+
+// CHECK:      aorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      aorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aorl  %ebx, 2032(%ecx)
+
+// CHECK:      aorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aorl  %ebx, -2048(%edx)
+
+// CHECK:      axorq  %r9, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               axorq  %r9, 268435456(%rbp,%r14,8)
+
+// CHECK:      axorq  %r9, 291(%r8,%rax,4)
+// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               axorq  %r9, 291(%r8,%rax,4)
+
+// CHECK:      axorq  %r9, (%rip)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               axorq  %r9, (%rip)
+
+// CHECK:      axorq  %r9, -512(,%rbp,2)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               axorq  %r9, -512(,%rbp,2)
+
+// CHECK:      axorq  %r9, 2032(%rcx)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               axorq  %r9, 2032(%rcx)
+
+// CHECK:      axorq  %r9, -2048(%rdx)
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               axorq  %r9, -2048(%rdx)
+
+// CHECK:      axorl  %ebx, 268435456(%esp,%esi,8)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axorl  %ebx, 268435456(%esp,%esi,8)
+
+// CHECK:      axorl  %ebx, 291(%edi,%eax,4)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axorl  %ebx, 291(%edi,%eax,4)
+
+// CHECK:      axorl  %ebx, (%eax)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18]
+               axorl  %ebx, (%eax)
+
+// CHECK:      axorl  %ebx, -512(,%ebp,2)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axorl  %ebx, -512(,%ebp,2)
+
+// CHECK:      axorl  %ebx, 2032(%ecx)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axorl  %ebx, 2032(%ecx)
+
+// CHECK:      axorl  %ebx, -2048(%edx)
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axorl  %ebx, -2048(%edx)

llvm/test/MC/X86/x86-64-rao-int-intel.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      aadd qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aadd qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aadd qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aadd qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aadd qword ptr [rip], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aadd qword ptr [rip], r9
+
+// CHECK:      aadd qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd qword ptr [2*rbp - 512], r9
+
+// CHECK:      aadd qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aadd qword ptr [rcx + 2032], r9
+
+// CHECK:      aadd qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aadd qword ptr [rdx - 2048], r9
+
+// CHECK:      aadd dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aadd dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aadd dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aadd dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aadd dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18]
+               aadd dword ptr [eax], ebx
+
+// CHECK:      aadd dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aadd dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aadd dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aadd dword ptr [ecx + 2032], ebx
+
+// CHECK:      aadd dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aadd dword ptr [edx - 2048], ebx
+
+// CHECK:      aand qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aand qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aand qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aand qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aand qword ptr [rip], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aand qword ptr [rip], r9
+
+// CHECK:      aand qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aand qword ptr [2*rbp - 512], r9
+
+// CHECK:      aand qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aand qword ptr [rcx + 2032], r9
+
+// CHECK:      aand qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aand qword ptr [rdx - 2048], r9
+
+// CHECK:      aand dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aand dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aand dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aand dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aand dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18]
+               aand dword ptr [eax], ebx
+
+// CHECK:      aand dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aand dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aand dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aand dword ptr [ecx + 2032], ebx
+
+// CHECK:      aand dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aand dword ptr [edx - 2048], ebx
+
+// CHECK:      aor qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               aor qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      aor qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               aor qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      aor qword ptr [rip], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               aor qword ptr [rip], r9
+
+// CHECK:      aor qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               aor qword ptr [2*rbp - 512], r9
+
+// CHECK:      aor qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               aor qword ptr [rcx + 2032], r9
+
+// CHECK:      aor qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               aor qword ptr [rdx - 2048], r9
+
+// CHECK:      aor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               aor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      aor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               aor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      aor dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18]
+               aor dword ptr [eax], ebx
+
+// CHECK:      aor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               aor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      aor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               aor dword ptr [ecx + 2032], ebx
+
+// CHECK:      aor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               aor dword ptr [edx - 2048], ebx
+
+// CHECK:      axor qword ptr [rbp + 8*r14 + 268435456], r9
+// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10]
+               axor qword ptr [rbp + 8*r14 + 268435456], r9
+
+// CHECK:      axor qword ptr [r8 + 4*rax + 291], r9
+// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00]
+               axor qword ptr [r8 + 4*rax + 291], r9
+
+// CHECK:      axor qword ptr [rip], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00]
+               axor qword ptr [rip], r9
+
+// CHECK:      axor qword ptr [2*rbp - 512], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff]
+               axor qword ptr [2*rbp - 512], r9
+
+// CHECK:      axor qword ptr [rcx + 2032], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00]
+               axor qword ptr [rcx + 2032], r9
+
+// CHECK:      axor qword ptr [rdx - 2048], r9
+// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff]
+               axor qword ptr [rdx - 2048], r9
+
+// CHECK:      axor dword ptr [esp + 8*esi + 268435456], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10]
+               axor dword ptr [esp + 8*esi + 268435456], ebx
+
+// CHECK:      axor dword ptr [edi + 4*eax + 291], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00]
+               axor dword ptr [edi + 4*eax + 291], ebx
+
+// CHECK:      axor dword ptr [eax], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18]
+               axor dword ptr [eax], ebx
+
+// CHECK:      axor dword ptr [2*ebp - 512], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff]
+               axor dword ptr [2*ebp - 512], ebx
+
+// CHECK:      axor dword ptr [ecx + 2032], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00]
+               axor dword ptr [ecx + 2032], ebx
+
+// CHECK:      axor dword ptr [edx - 2048], ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff]
+               axor dword ptr [edx - 2048], ebx