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Differential D127976

[IR] Move vector.insert/vector.extract out of experimental namespace
ClosedPublic

Authored by bsmith on Jun 16 2022, 8:18 AM.

Details

Reviewers
paulwalker-arm
peterwaller-arm
c-rhodes
sdesmalen
Commits
rGa83aa33d1bf9: [IR] Move vector.insert/vector.extract out of experimental namespace
Summary

These intrinsics are now fundemental for SVE code generation and have been
present for a year and a half, hence move them out of the experimental
namespace.

Diff Detail

Event Timeline

bsmith created this revision.Jun 16 2022, 8:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 16 2022, 8:18 AM
Herald added subscribers: ctetreau, frasercrmck, jdoerfert and 21 others. · View Herald Transcript
bsmith requested review of this revision.Jun 16 2022, 8:18 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJun 16 2022, 8:18 AM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
bsmith mentioned this in D127100: [mlir][llvm] Add vector insert/extract intrinsics.Jun 16 2022, 8:22 AM
tschuett added a subscriber: tschuett.Jun 16 2022, 8:30 AM

Maybe a line in the Release Notes of LLVM?

bsmith updated this revision to Diff 437557.Jun 16 2022, 8:47 AM
  • Add info to release notes
Harbormaster completed remote builds in B170277: Diff 437557.Jun 16 2022, 9:50 AM
Matt added a subscriber: Matt.Jun 16 2022, 4:41 PM
paulwalker-arm accepted this revision.Jun 17 2022, 5:06 AM
This revision is now accepted and ready to land.Jun 17 2022, 5:06 AM
dcaballe added subscribers: jsetoain, dcaballe.Jun 17 2022, 12:24 PM

Hey Bradley! Thanks for pinging us about this upcoming change! Something that my colleague @jsetoain mentioned is that these vector insert/extract intrinsics can also work on fixed-length only vectors. However, the documentation and slightly tend to suggest that they should specifically be used to insert/extract fixed-length vectors into/out of scalable one. Perhaps clarifying that they can be used on fixed-length only vectors and adding an example for that case would be very helpful. Thanks!

bsmith updated this revision to Diff 438718.Jun 21 2022, 8:32 AM
  • Clarify LangRef slightly to make it clearer that fixed types can be used
  • Rebase on top of recent test changes
Harbormaster completed remote builds in B171106: Diff 438718.Jun 21 2022, 8:33 AM
craig.topper added inline comments.Jun 21 2022, 8:37 AM
llvm/docs/LangRef.rst
17296–17299

Now this comment makes it seems like you can't use it on purely scalable vectors.

17342

Same here

jsetoain added inline comments.Jun 21 2022, 10:05 AM
llvm/docs/LangRef.rst
17299–17301

To answer Craig's point, I don't think it was clear before that you could use this intrinsic with purely scalable vectors before, either. I believe the confusion comes from these clarifications. If instead of explicitly stating valid options you exclude the invalid ones, there's no room for ambiguity. Something like:

"Scalable vectors can only be inserted/extracted into/out of other scalable vectors". Examples of all other possible combinations might help to nail down this point.

bsmith updated this revision to Diff 438975.Jun 22 2022, 4:32 AM
  • Further improve clarity on usable types in LangRef
Harbormaster completed remote builds in B171285: Diff 438975.Jun 22 2022, 4:33 AM
paulwalker-arm accepted this revision.Jun 23 2022, 7:33 AM
paulwalker-arm added inline comments.
llvm/docs/LangRef.rst
17282

For this and the other instances, please remove the % as idx must be a literal (as documented below) but using %idx makes it look like an arbitrary variable can be used.

This revision was landed with ongoing or failed builds.Jun 27 2022, 3:50 AM
Closed by commit rGa83aa33d1bf9: [IR] Move vector.insert/vector.extract out of experimental namespace (authored by bsmith). · Explain Why
This revision was automatically updated to reflect the committed changes.
bsmith added a commit: rGa83aa33d1bf9: [IR] Move vector.insert/vector.extract out of experimental namespace.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
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lib/
CodeGen/
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test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
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rvv-intrinsics/
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aarch64-sve-intrinsics/
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aarch64_neon_sve_bridge_intrinsics/
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llvm/
docs/
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include/
llvm/
CodeGen/
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IR/
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lib/
Analysis/
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CodeGen/
SelectionDAG/
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IR/
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Target/
AArch64/
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Transforms/
InstCombine/
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test/
Analysis/
CostModel/
AArch64/
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RISCV/
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Bitcode/
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CodeGen/
AArch64/
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RISCV/
rvv/
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Transforms/
InstCombine/
AArch64/
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InstSimplify/
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InterleavedAccess/
AArch64/
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Verifier/
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Diff 440156

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 2,190 Lines • ▼ Show 20 Lines let Name = "vundefined", HasUnMaskedOverloaded = false, MaskedPolicy = NonePolicy,
def vundefined : RVVBuiltin<"v", "v", "csilxfd">; def vundefined : RVVBuiltin<"v", "v", "csilxfd">;
def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">; def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">;
} }
// LMUL truncation // LMUL truncation
// C/C++ Operand: VecTy, IR Operand: VecTy, Index // C/C++ Operand: VecTy, IR Operand: VecTy, Index
let Name = "vlmul_trunc_v", OverloadedName = "vlmul_trunc", MaskedPolicy = NonePolicy, let Name = "vlmul_trunc_v", OverloadedName = "vlmul_trunc", MaskedPolicy = NonePolicy,
ManualCodegen = [{ { ManualCodegen = [{ {
ID = Intrinsic::experimental_vector_extract; ID = Intrinsic::vector_extract;
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
Ops.push_back(ConstantInt::get(Int64Ty, 0)); Ops.push_back(ConstantInt::get(Int64Ty, 0));
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
} }] in { } }] in {
foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)", foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)",
"(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { "(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">; dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
} }
} }
// LMUL extension // LMUL extension
// C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
let Name = "vlmul_ext_v", OverloadedName = "vlmul_ext", MaskedPolicy = NonePolicy, let Name = "vlmul_ext_v", OverloadedName = "vlmul_ext", MaskedPolicy = NonePolicy,
ManualCodegen = [{ ManualCodegen = [{
ID = Intrinsic::experimental_vector_insert; ID = Intrinsic::vector_insert;
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
Ops.push_back(llvm::UndefValue::get(ResultType)); Ops.push_back(llvm::UndefValue::get(ResultType));
std::swap(Ops[0], Ops[1]); std::swap(Ops[0], Ops[1]);
Ops.push_back(ConstantInt::get(Int64Ty, 0)); Ops.push_back(ConstantInt::get(Int64Ty, 0));
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
}] in { }] in {
foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)", foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)",
"(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { "(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">; dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
} }
} }
let Name = "vget_v", MaskedPolicy = NonePolicy, let Name = "vget_v", MaskedPolicy = NonePolicy,
ManualCodegen = [{ ManualCodegen = [{
{ {
ID = Intrinsic::experimental_vector_extract; ID = Intrinsic::vector_extract;
auto *VecTy = cast<ScalableVectorType>(ResultType); auto *VecTy = cast<ScalableVectorType>(ResultType);
auto *OpVecTy = cast<ScalableVectorType>(Ops[0]->getType()); auto *OpVecTy = cast<ScalableVectorType>(Ops[0]->getType());
// Mask to only valid indices. // Mask to only valid indices.
unsigned MaxIndex = OpVecTy->getMinNumElements() / VecTy->getMinNumElements(); unsigned MaxIndex = OpVecTy->getMinNumElements() / VecTy->getMinNumElements();
assert(isPowerOf2_32(MaxIndex)); assert(isPowerOf2_32(MaxIndex));
Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1); Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1);
Ops[1] = Builder.CreateMul(Ops[1], Ops[1] = Builder.CreateMul(Ops[1],
ConstantInt::get(Ops[1]->getType(), ConstantInt::get(Ops[1]->getType(),
VecTy->getMinNumElements())); VecTy->getMinNumElements()));
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
} }
}] in { }] in {
foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">; def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">;
} }
} }
let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicy = NonePolicy, let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicy = NonePolicy,
ManualCodegen = [{ ManualCodegen = [{
{ {
ID = Intrinsic::experimental_vector_insert; ID = Intrinsic::vector_insert;
IntrinsicTypes = {ResultType, Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType()};
auto *ResVecTy = cast<ScalableVectorType>(ResultType); auto *ResVecTy = cast<ScalableVectorType>(ResultType);
auto *VecTy = cast<ScalableVectorType>(Ops[2]->getType()); auto *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
// Mask to only valid indices. // Mask to only valid indices.
unsigned MaxIndex = ResVecTy->getMinNumElements() / VecTy->getMinNumElements(); unsigned MaxIndex = ResVecTy->getMinNumElements() / VecTy->getMinNumElements();
assert(isPowerOf2_32(MaxIndex)); assert(isPowerOf2_32(MaxIndex));
Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1); Ops[1] = Builder.CreateAnd(Ops[1], MaxIndex - 1);
Ops[1] = Builder.CreateMul(Ops[1], Ops[1] = Builder.CreateMul(Ops[1],
Show All 12 Lines

clang/lib/CodeGen/CGCall.cpp

Show First 20 Lines • Show All 1,279 Lines • ▼ Show 20 Lines if (!SrcSize.isScalable() && !DstSize.isScalable() &&
// //
// FIXME: Assert that we aren't truncating non-padding bits when have access // FIXME: Assert that we aren't truncating non-padding bits when have access
// to that information. // to that information.
Src = CGF.Builder.CreateElementBitCast(Src, Ty); Src = CGF.Builder.CreateElementBitCast(Src, Ty);
return CGF.Builder.CreateLoad(Src); return CGF.Builder.CreateLoad(Src);
} }
// If coercing a fixed vector to a scalable vector for ABI compatibility, and // If coercing a fixed vector to a scalable vector for ABI compatibility, and
// the types match, use the llvm.experimental.vector.insert intrinsic to // the types match, use the llvm.vector.insert intrinsic to perform the
// perform the conversion. // conversion.
if (auto *ScalableDst = dyn_cast<llvm::ScalableVectorType>(Ty)) { if (auto *ScalableDst = dyn_cast<llvm::ScalableVectorType>(Ty)) {
if (auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) { if (auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) {
// If we are casting a fixed i8 vector to a scalable 16 x i1 predicate // If we are casting a fixed i8 vector to a scalable 16 x i1 predicate
// vector, use a vector insert and bitcast the result. // vector, use a vector insert and bitcast the result.
bool NeedsBitcast = false; bool NeedsBitcast = false;
auto PredType = auto PredType =
llvm::ScalableVectorType::get(CGF.Builder.getInt1Ty(), 16); llvm::ScalableVectorType::get(CGF.Builder.getInt1Ty(), 16);
llvm::Type *OrigType = Ty; llvm::Type *OrigType = Ty;
▲ Show 20 Lines • Show All 1,627 Lines • ▼ Show 20 Lines case ABIArgInfo::Direct: {
ArgVals.push_back(ParamValue::forDirect(V)); ArgVals.push_back(ParamValue::forDirect(V));
break; break;
} }
// VLST arguments are coerced to VLATs at the function boundary for // VLST arguments are coerced to VLATs at the function boundary for
// ABI consistency. If this is a VLST that was coerced to // ABI consistency. If this is a VLST that was coerced to
// a VLAT at the function boundary and the types match up, use // a VLAT at the function boundary and the types match up, use
// llvm.experimental.vector.extract to convert back to the original // llvm.vector.extract to convert back to the original VLST.
// VLST.
if (auto *VecTyTo = dyn_cast<llvm::FixedVectorType>(ConvertType(Ty))) { if (auto *VecTyTo = dyn_cast<llvm::FixedVectorType>(ConvertType(Ty))) {
llvm::Value *Coerced = Fn->getArg(FirstIRArg); llvm::Value *Coerced = Fn->getArg(FirstIRArg);
if (auto *VecTyFrom = if (auto *VecTyFrom =
dyn_cast<llvm::ScalableVectorType>(Coerced->getType())) { dyn_cast<llvm::ScalableVectorType>(Coerced->getType())) {
// If we are casting a scalable 16 x i1 predicate vector to a fixed i8 // If we are casting a scalable 16 x i1 predicate vector to a fixed i8
// vector, bitcast the source and use a vector extract. // vector, bitcast the source and use a vector extract.
auto PredType = auto PredType =
llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16); llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
▲ Show 20 Lines • Show All 2,672 Lines • Show Last 20 Lines

clang/lib/CodeGen/CGExprScalar.cpp

Show First 20 Lines • Show All 2,078 Lines • ▼ Show 20 Lines if (auto *CI = dyn_cast<llvm::CallBase>(Src)) {
QualType PointeeType = DestTy->getPointeeType(); QualType PointeeType = DestTy->getPointeeType();
if (!PointeeType.isNull()) if (!PointeeType.isNull())
CGF.getDebugInfo()->addHeapAllocSiteMetadata(CI, PointeeType, CGF.getDebugInfo()->addHeapAllocSiteMetadata(CI, PointeeType,
CE->getExprLoc()); CE->getExprLoc());
} }
} }
// If Src is a fixed vector and Dst is a scalable vector, and both have the // If Src is a fixed vector and Dst is a scalable vector, and both have the
// same element type, use the llvm.experimental.vector.insert intrinsic to // same element type, use the llvm.vector.insert intrinsic to perform the
// perform the bitcast. // bitcast.
if (const auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) { if (const auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) {
if (const auto *ScalableDst = dyn_cast<llvm::ScalableVectorType>(DstTy)) { if (const auto *ScalableDst = dyn_cast<llvm::ScalableVectorType>(DstTy)) {
// If we are casting a fixed i8 vector to a scalable 16 x i1 predicate // If we are casting a fixed i8 vector to a scalable 16 x i1 predicate
// vector, use a vector insert and bitcast the result. // vector, use a vector insert and bitcast the result.
bool NeedsBitCast = false; bool NeedsBitCast = false;
auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16); auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
llvm::Type *OrigType = DstTy; llvm::Type *OrigType = DstTy;
if (ScalableDst == PredType && if (ScalableDst == PredType &&
Show All 10 Lines if (const auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) {
if (NeedsBitCast) if (NeedsBitCast)
Result = Builder.CreateBitCast(Result, OrigType); Result = Builder.CreateBitCast(Result, OrigType);
return Result; return Result;
} }
} }
} }
// If Src is a scalable vector and Dst is a fixed vector, and both have the // If Src is a scalable vector and Dst is a fixed vector, and both have the
// same element type, use the llvm.experimental.vector.extract intrinsic to // same element type, use the llvm.vector.extract intrinsic to perform the
// perform the bitcast. // bitcast.
if (const auto *ScalableSrc = dyn_cast<llvm::ScalableVectorType>(SrcTy)) { if (const auto *ScalableSrc = dyn_cast<llvm::ScalableVectorType>(SrcTy)) {
if (const auto *FixedDst = dyn_cast<llvm::FixedVectorType>(DstTy)) { if (const auto *FixedDst = dyn_cast<llvm::FixedVectorType>(DstTy)) {
// If we are casting a scalable 16 x i1 predicate vector to a fixed i8 // If we are casting a scalable 16 x i1 predicate vector to a fixed i8
// vector, bitcast the source and use a vector extract. // vector, bitcast the source and use a vector extract.
auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16); auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
if (ScalableSrc == PredType && if (ScalableSrc == PredType &&
FixedDst->getElementType() == Builder.getInt8Ty()) { FixedDst->getElementType() == Builder.getInt8Ty()) {
SrcTy = llvm::ScalableVectorType::get(Builder.getInt8Ty(), 2); SrcTy = llvm::ScalableVectorType::get(Builder.getInt8Ty(), 2);
▲ Show 20 Lines • Show All 3,073 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src, size_t index) { vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src, size_t index) {
return vget_i8m1(src, 0); return vget_i8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) { vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) {
return vget_i8m1(src, 0); return vget_i8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src, size_t index) { vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src, size_t index) {
return vget_i8m1(src, 0); return vget_i8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m2( // CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src, size_t index) { vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src, size_t index) {
return vget_i8m2(src, 0); return vget_i8m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m2( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src, size_t index) { vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src, size_t index) {
return vget_i8m2(src, 0); return vget_i8m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m4( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src, size_t index) { vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src, size_t index) {
return vget_i8m4(src, 0); return vget_i8m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m2_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src, size_t index) { vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src, size_t index) {
return vget_u8m1(src, 0); return vget_u8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src, size_t index) { vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src, size_t index) {
return vget_u8m1(src, 0); return vget_u8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src, size_t index) { vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src, size_t index) {
return vget_u8m1(src, 0); return vget_u8m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m2( // CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src, size_t index) { vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src, size_t index) {
return vget_u8m2(src, 0); return vget_u8m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m2( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src, size_t index) { vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src, size_t index) {
return vget_u8m2(src, 0); return vget_u8m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m4( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src, size_t index) { vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src, size_t index) {
return vget_u8m4(src, 0); return vget_u8m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m2_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) { vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) {
return vget_i16m1(src, 0); return vget_i16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src, size_t index) { vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src, size_t index) {
return vget_i16m1(src, 0); return vget_i16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src, size_t index) { vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src, size_t index) {
return vget_i16m1(src, 0); return vget_i16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m2( // CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src, size_t index) { vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src, size_t index) {
return vget_i16m2(src, 0); return vget_i16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m2( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src, size_t index) { vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src, size_t index) {
return vget_i16m2(src, 0); return vget_i16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m4( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src, size_t index) { vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src, size_t index) {
return vget_i16m4(src, 0); return vget_i16m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m2_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src, size_t index) { vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src, size_t index) {
return vget_u16m1(src, 0); return vget_u16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src, size_t index) { vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src, size_t index) {
return vget_u16m1(src, 0); return vget_u16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src, size_t index) { vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src, size_t index) {
return vget_u16m1(src, 0); return vget_u16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m2( // CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src, size_t index) { vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src, size_t index) {
return vget_u16m2(src, 0); return vget_u16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m2( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src, size_t index) { vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src, size_t index) {
return vget_u16m2(src, 0); return vget_u16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m4( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src, size_t index) { vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src, size_t index) {
return vget_u16m4(src, 0); return vget_u16m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m2_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src, size_t index) { vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src, size_t index) {
return vget_i32m1(src, 0); return vget_i32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) { vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) {
return vget_i32m1(src, 0); return vget_i32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src, size_t index) { vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src, size_t index) {
return vget_i32m1(src, 0); return vget_i32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m2( // CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src, size_t index) { vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src, size_t index) {
return vget_i32m2(src, 0); return vget_i32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m2( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src, size_t index) { vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src, size_t index) {
return vget_i32m2(src, 0); return vget_i32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m4( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src, size_t index) { vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src, size_t index) {
return vget_i32m4(src, 0); return vget_i32m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m2_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src, size_t index) { vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src, size_t index) {
return vget_u32m1(src, 0); return vget_u32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src, size_t index) { vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src, size_t index) {
return vget_u32m1(src, 0); return vget_u32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src, size_t index) { vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src, size_t index) {
return vget_u32m1(src, 0); return vget_u32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m2( // CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src, size_t index) { vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src, size_t index) {
return vget_u32m2(src, 0); return vget_u32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m2( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src, size_t index) { vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src, size_t index) {
return vget_u32m2(src, 0); return vget_u32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m4( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src, size_t index) { vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src, size_t index) {
return vget_u32m4(src, 0); return vget_u32m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m2_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src, size_t index) { vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src, size_t index) {
return vget_f32m1(src, 0); return vget_f32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) { vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) {
return vget_f32m1(src, 0); return vget_f32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src, size_t index) { vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src, size_t index) {
return vget_f32m1(src, 0); return vget_f32m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m2( // CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src, size_t index) { vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src, size_t index) {
return vget_f32m2(src, 0); return vget_f32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m2( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src, size_t index) { vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src, size_t index) {
return vget_f32m2(src, 0); return vget_f32m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m4( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src, size_t index) { vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src, size_t index) {
return vget_f32m4(src, 0); return vget_f32m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m2_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src, size_t index) { vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src, size_t index) {
return vget_i64m1(src, 0); return vget_i64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) { vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) {
return vget_i64m1(src, 0); return vget_i64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src, size_t index) { vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src, size_t index) {
return vget_i64m1(src, 0); return vget_i64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m2( // CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src, size_t index) { vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src, size_t index) {
return vget_i64m2(src, 0); return vget_i64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m2( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src, size_t index) { vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src, size_t index) {
return vget_i64m2(src, 0); return vget_i64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m4( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src, size_t index) { vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src, size_t index) {
return vget_i64m4(src, 0); return vget_i64m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m2_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src, size_t index) { vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src, size_t index) {
return vget_u64m1(src, 0); return vget_u64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src, size_t index) { vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src, size_t index) {
return vget_u64m1(src, 0); return vget_u64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src, size_t index) { vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src, size_t index) {
return vget_u64m1(src, 0); return vget_u64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m2( // CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src, size_t index) { vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src, size_t index) {
return vget_u64m2(src, 0); return vget_u64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m2( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src, size_t index) { vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src, size_t index) {
return vget_u64m2(src, 0); return vget_u64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m4( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src, size_t index) { vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src, size_t index) {
return vget_u64m4(src, 0); return vget_u64m4(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m2_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m2_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) { vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) {
return vget_f64m1(src, 0); return vget_f64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src, size_t index) { vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src, size_t index) {
return vget_f64m1(src, 0); return vget_f64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src, size_t index) { vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src, size_t index) {
return vget_f64m1(src, 0); return vget_f64m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m2( // CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src, size_t index) { vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src, size_t index) {
return vget_f64m2(src, 0); return vget_f64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m2( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src, size_t index) { vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src, size_t index) {
return vget_f64m2(src, 0); return vget_f64m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m4( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src, size_t index) { vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src, size_t index) {
return vget_f64m4(src, 0); return vget_f64m4(src, 0);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) { vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
return vlmul_ext_i8mf4(op1); return vlmul_ext_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) { vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) {
return vlmul_ext_i8mf2(op1); return vlmul_ext_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) { vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) {
return vlmul_ext_i8m1(op1); return vlmul_ext_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) { vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) {
return vlmul_ext_i8m2(op1); return vlmul_ext_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) { vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) {
return vlmul_ext_i8m4(op1); return vlmul_ext_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) { vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) { vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) {
return vlmul_ext_i8mf2(op1); return vlmul_ext_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) { vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) {
return vlmul_ext_i8m1(op1); return vlmul_ext_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) { vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) {
return vlmul_ext_i8m2(op1); return vlmul_ext_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) { vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) {
return vlmul_ext_i8m4(op1); return vlmul_ext_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) { vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) { vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) {
return vlmul_ext_i8m1(op1); return vlmul_ext_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) { vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) {
return vlmul_ext_i8m2(op1); return vlmul_ext_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) { vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) {
return vlmul_ext_i8m4(op1); return vlmul_ext_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) { vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) { vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) {
return vlmul_ext_i8m2(op1); return vlmul_ext_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) { vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) {
return vlmul_ext_i8m4(op1); return vlmul_ext_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) { vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) { vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) {
return vlmul_ext_i8m4(op1); return vlmul_ext_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) { vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m4_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) { vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) {
return vlmul_ext_i8m8(op1); return vlmul_ext_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) { vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) {
return vlmul_ext_i16mf2(op1); return vlmul_ext_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) { vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) {
return vlmul_ext_i16m1(op1); return vlmul_ext_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) { vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) {
return vlmul_ext_i16m2(op1); return vlmul_ext_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) { vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) {
return vlmul_ext_i16m4(op1); return vlmul_ext_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
return vlmul_ext_i16m8(op1); return vlmul_ext_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) { vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) {
return vlmul_ext_i16m1(op1); return vlmul_ext_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) { vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) {
return vlmul_ext_i16m2(op1); return vlmul_ext_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) { vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) {
return vlmul_ext_i16m4(op1); return vlmul_ext_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) { vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) {
return vlmul_ext_i16m8(op1); return vlmul_ext_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) { vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) {
return vlmul_ext_i16m2(op1); return vlmul_ext_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) { vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) {
return vlmul_ext_i16m4(op1); return vlmul_ext_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) { vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) {
return vlmul_ext_i16m8(op1); return vlmul_ext_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) { vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) {
return vlmul_ext_i16m4(op1); return vlmul_ext_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) { vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) {
return vlmul_ext_i16m8(op1); return vlmul_ext_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m4_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) { vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) {
return vlmul_ext_i16m8(op1); return vlmul_ext_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) { vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) {
return vlmul_ext_i32m1(op1); return vlmul_ext_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) { vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) {
return vlmul_ext_i32m2(op1); return vlmul_ext_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) { vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) {
return vlmul_ext_i32m4(op1); return vlmul_ext_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) { vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) {
return vlmul_ext_i32m8(op1); return vlmul_ext_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) { vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) {
return vlmul_ext_i32m2(op1); return vlmul_ext_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) { vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) {
return vlmul_ext_i32m4(op1); return vlmul_ext_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) { vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) {
return vlmul_ext_i32m8(op1); return vlmul_ext_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) { vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) {
return vlmul_ext_i32m4(op1); return vlmul_ext_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) { vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) {
return vlmul_ext_i32m8(op1); return vlmul_ext_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m4_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) { vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) {
return vlmul_ext_i32m8(op1); return vlmul_ext_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) { vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) {
return vlmul_ext_i64m2(op1); return vlmul_ext_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) { vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) {
return vlmul_ext_i64m4(op1); return vlmul_ext_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) { vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) {
return vlmul_ext_i64m8(op1); return vlmul_ext_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) { vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) {
return vlmul_ext_i64m4(op1); return vlmul_ext_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
return vlmul_ext_i64m8(op1); return vlmul_ext_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m4_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) { vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) {
return vlmul_ext_i64m8(op1); return vlmul_ext_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) { vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) {
return vlmul_ext_u8mf4(op1); return vlmul_ext_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) { vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) {
return vlmul_ext_u8mf2(op1); return vlmul_ext_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) {
return vlmul_ext_u8m1(op1); return vlmul_ext_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) {
return vlmul_ext_u8m2(op1); return vlmul_ext_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) {
return vlmul_ext_u8m4(op1); return vlmul_ext_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) { vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) {
return vlmul_ext_u8mf2(op1); return vlmul_ext_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) {
return vlmul_ext_u8m1(op1); return vlmul_ext_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) {
return vlmul_ext_u8m2(op1); return vlmul_ext_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) {
return vlmul_ext_u8m4(op1); return vlmul_ext_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) {
return vlmul_ext_u8m1(op1); return vlmul_ext_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) {
return vlmul_ext_u8m2(op1); return vlmul_ext_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) {
return vlmul_ext_u8m4(op1); return vlmul_ext_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) { vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) {
return vlmul_ext_u8m2(op1); return vlmul_ext_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) { vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) {
return vlmul_ext_u8m4(op1); return vlmul_ext_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) { vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) { vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) {
return vlmul_ext_u8m4(op1); return vlmul_ext_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) { vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m4_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) { vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) {
return vlmul_ext_u8m8(op1); return vlmul_ext_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) { vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) {
return vlmul_ext_u16mf2(op1); return vlmul_ext_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) { vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) {
return vlmul_ext_u16m1(op1); return vlmul_ext_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) { vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) {
return vlmul_ext_u16m2(op1); return vlmul_ext_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) { vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) {
return vlmul_ext_u16m4(op1); return vlmul_ext_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) { vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) {
return vlmul_ext_u16m8(op1); return vlmul_ext_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) { vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) {
return vlmul_ext_u16m1(op1); return vlmul_ext_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) { vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) {
return vlmul_ext_u16m2(op1); return vlmul_ext_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) { vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) {
return vlmul_ext_u16m4(op1); return vlmul_ext_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) { vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) {
return vlmul_ext_u16m8(op1); return vlmul_ext_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) { vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) {
return vlmul_ext_u16m2(op1); return vlmul_ext_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) { vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) {
return vlmul_ext_u16m4(op1); return vlmul_ext_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) { vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) {
return vlmul_ext_u16m8(op1); return vlmul_ext_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) { vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) {
return vlmul_ext_u16m4(op1); return vlmul_ext_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) { vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) {
return vlmul_ext_u16m8(op1); return vlmul_ext_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m4_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) { vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) {
return vlmul_ext_u16m8(op1); return vlmul_ext_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) { vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) {
return vlmul_ext_u32m1(op1); return vlmul_ext_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) { vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) {
return vlmul_ext_u32m2(op1); return vlmul_ext_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) { vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) {
return vlmul_ext_u32m4(op1); return vlmul_ext_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) { vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) {
return vlmul_ext_u32m8(op1); return vlmul_ext_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) { vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) {
return vlmul_ext_u32m2(op1); return vlmul_ext_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) { vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) {
return vlmul_ext_u32m4(op1); return vlmul_ext_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) { vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) {
return vlmul_ext_u32m8(op1); return vlmul_ext_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) { vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) {
return vlmul_ext_u32m4(op1); return vlmul_ext_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) { vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) {
return vlmul_ext_u32m8(op1); return vlmul_ext_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m4_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) { vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) {
return vlmul_ext_u32m8(op1); return vlmul_ext_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) { vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) {
return vlmul_ext_u64m2(op1); return vlmul_ext_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) { vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) {
return vlmul_ext_u64m4(op1); return vlmul_ext_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) { vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) {
return vlmul_ext_u64m8(op1); return vlmul_ext_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) { vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) {
return vlmul_ext_u64m4(op1); return vlmul_ext_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) { vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) {
return vlmul_ext_u64m8(op1); return vlmul_ext_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m4_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) { vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) {
return vlmul_ext_u64m8(op1); return vlmul_ext_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) { vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) {
return vlmul_ext_f32m1(op1); return vlmul_ext_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) { vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) {
return vlmul_ext_f32m2(op1); return vlmul_ext_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) { vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) {
return vlmul_ext_f32m4(op1); return vlmul_ext_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) { vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) {
return vlmul_ext_f32m8(op1); return vlmul_ext_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) { vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) {
return vlmul_ext_f32m2(op1); return vlmul_ext_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) { vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) {
return vlmul_ext_f32m4(op1); return vlmul_ext_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) {
return vlmul_ext_f32m8(op1); return vlmul_ext_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) { vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) {
return vlmul_ext_f32m4(op1); return vlmul_ext_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) {
return vlmul_ext_f32m8(op1); return vlmul_ext_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m4_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m4_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) {
return vlmul_ext_f32m8(op1); return vlmul_ext_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) { vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) {
return vlmul_ext_f64m2(op1); return vlmul_ext_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) { vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) {
return vlmul_ext_f64m4(op1); return vlmul_ext_f64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) {
return vlmul_ext_f64m8(op1); return vlmul_ext_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) { vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) {
return vlmul_ext_f64m4(op1); return vlmul_ext_f64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) {
return vlmul_ext_f64m8(op1); return vlmul_ext_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m4_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m4_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) {
return vlmul_ext_f64m8(op1); return vlmul_ext_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1) { vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1) { vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1) { vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1) {
return vlmul_trunc_i8mf4(op1); return vlmul_trunc_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1) {
return vlmul_trunc_i8mf4(op1); return vlmul_trunc_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1) {
return vlmul_trunc_i8mf2(op1); return vlmul_trunc_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1) {
return vlmul_trunc_i8mf4(op1); return vlmul_trunc_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1) {
return vlmul_trunc_i8mf2(op1); return vlmul_trunc_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1) { vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1) {
return vlmul_trunc_i8m1(op1); return vlmul_trunc_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1) {
return vlmul_trunc_i8mf4(op1); return vlmul_trunc_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1) {
return vlmul_trunc_i8mf2(op1); return vlmul_trunc_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1) { vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1) {
return vlmul_trunc_i8m1(op1); return vlmul_trunc_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1) { vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1) {
return vlmul_trunc_i8m2(op1); return vlmul_trunc_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1) {
return vlmul_trunc_i8mf8(op1); return vlmul_trunc_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1) {
return vlmul_trunc_i8mf4(op1); return vlmul_trunc_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1) {
return vlmul_trunc_i8mf2(op1); return vlmul_trunc_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1) { vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1) {
return vlmul_trunc_i8m1(op1); return vlmul_trunc_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1) { vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1) {
return vlmul_trunc_i8m2(op1); return vlmul_trunc_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1) { vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1) {
return vlmul_trunc_i8m4(op1); return vlmul_trunc_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1) { vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1) {
return vlmul_trunc_i16mf4(op1); return vlmul_trunc_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1) {
return vlmul_trunc_i16mf4(op1); return vlmul_trunc_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1) {
return vlmul_trunc_i16mf2(op1); return vlmul_trunc_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1) {
return vlmul_trunc_i16mf4(op1); return vlmul_trunc_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1) {
return vlmul_trunc_i16mf2(op1); return vlmul_trunc_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1) { vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1) {
return vlmul_trunc_i16m1(op1); return vlmul_trunc_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1) {
return vlmul_trunc_i16mf4(op1); return vlmul_trunc_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1) {
return vlmul_trunc_i16mf2(op1); return vlmul_trunc_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1) { vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1) {
return vlmul_trunc_i16m1(op1); return vlmul_trunc_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1) { vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1) {
return vlmul_trunc_i16m2(op1); return vlmul_trunc_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1) {
return vlmul_trunc_i16mf4(op1); return vlmul_trunc_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1) {
return vlmul_trunc_i16mf2(op1); return vlmul_trunc_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1) { vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1) {
return vlmul_trunc_i16m1(op1); return vlmul_trunc_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1) { vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1) {
return vlmul_trunc_i16m2(op1); return vlmul_trunc_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1) { vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1) {
return vlmul_trunc_i16m4(op1); return vlmul_trunc_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1) {
return vlmul_trunc_i32mf2(op1); return vlmul_trunc_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1) {
return vlmul_trunc_i32mf2(op1); return vlmul_trunc_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1) { vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1) {
return vlmul_trunc_i32m1(op1); return vlmul_trunc_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1) {
return vlmul_trunc_i32mf2(op1); return vlmul_trunc_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1) { vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1) {
return vlmul_trunc_i32m1(op1); return vlmul_trunc_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1) { vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1) {
return vlmul_trunc_i32m2(op1); return vlmul_trunc_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1) {
return vlmul_trunc_i32mf2(op1); return vlmul_trunc_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1) { vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1) {
return vlmul_trunc_i32m1(op1); return vlmul_trunc_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1) { vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1) {
return vlmul_trunc_i32m2(op1); return vlmul_trunc_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1) { vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1) {
return vlmul_trunc_i32m4(op1); return vlmul_trunc_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m2_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1) { vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1) {
return vlmul_trunc_i64m1(op1); return vlmul_trunc_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1) { vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1) {
return vlmul_trunc_i64m1(op1); return vlmul_trunc_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1) { vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1) {
return vlmul_trunc_i64m2(op1); return vlmul_trunc_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1) { vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1) {
return vlmul_trunc_i64m1(op1); return vlmul_trunc_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1) { vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1) {
return vlmul_trunc_i64m2(op1); return vlmul_trunc_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1) { vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1) {
return vlmul_trunc_i64m4(op1); return vlmul_trunc_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1) {
return vlmul_trunc_u8mf4(op1); return vlmul_trunc_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1) {
return vlmul_trunc_u8mf4(op1); return vlmul_trunc_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1) {
return vlmul_trunc_u8mf2(op1); return vlmul_trunc_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1) {
return vlmul_trunc_u8mf4(op1); return vlmul_trunc_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1) {
return vlmul_trunc_u8mf2(op1); return vlmul_trunc_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1) {
return vlmul_trunc_u8m1(op1); return vlmul_trunc_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1) {
return vlmul_trunc_u8mf4(op1); return vlmul_trunc_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1) {
return vlmul_trunc_u8mf2(op1); return vlmul_trunc_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1) {
return vlmul_trunc_u8m1(op1); return vlmul_trunc_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1) { vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1) {
return vlmul_trunc_u8m2(op1); return vlmul_trunc_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1) {
return vlmul_trunc_u8mf8(op1); return vlmul_trunc_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1) {
return vlmul_trunc_u8mf4(op1); return vlmul_trunc_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1) {
return vlmul_trunc_u8mf2(op1); return vlmul_trunc_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1) {
return vlmul_trunc_u8m1(op1); return vlmul_trunc_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1) { vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1) {
return vlmul_trunc_u8m2(op1); return vlmul_trunc_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1) { vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1) {
return vlmul_trunc_u8m4(op1); return vlmul_trunc_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1) {
return vlmul_trunc_u16mf4(op1); return vlmul_trunc_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1) {
return vlmul_trunc_u16mf4(op1); return vlmul_trunc_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1) {
return vlmul_trunc_u16mf2(op1); return vlmul_trunc_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1) {
return vlmul_trunc_u16mf4(op1); return vlmul_trunc_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1) {
return vlmul_trunc_u16mf2(op1); return vlmul_trunc_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1) {
return vlmul_trunc_u16m1(op1); return vlmul_trunc_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1) {
return vlmul_trunc_u16mf4(op1); return vlmul_trunc_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1) {
return vlmul_trunc_u16mf2(op1); return vlmul_trunc_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1) {
return vlmul_trunc_u16m1(op1); return vlmul_trunc_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1) { vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1) {
return vlmul_trunc_u16m2(op1); return vlmul_trunc_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1) {
return vlmul_trunc_u16mf4(op1); return vlmul_trunc_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1) {
return vlmul_trunc_u16mf2(op1); return vlmul_trunc_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1) {
return vlmul_trunc_u16m1(op1); return vlmul_trunc_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1) { vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1) {
return vlmul_trunc_u16m2(op1); return vlmul_trunc_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1) { vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1) {
return vlmul_trunc_u16m4(op1); return vlmul_trunc_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1) {
return vlmul_trunc_u32mf2(op1); return vlmul_trunc_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1) {
return vlmul_trunc_u32mf2(op1); return vlmul_trunc_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1) {
return vlmul_trunc_u32m1(op1); return vlmul_trunc_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1) {
return vlmul_trunc_u32mf2(op1); return vlmul_trunc_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1) {
return vlmul_trunc_u32m1(op1); return vlmul_trunc_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1) { vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1) {
return vlmul_trunc_u32m2(op1); return vlmul_trunc_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1) {
return vlmul_trunc_u32mf2(op1); return vlmul_trunc_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1) {
return vlmul_trunc_u32m1(op1); return vlmul_trunc_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1) { vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1) {
return vlmul_trunc_u32m2(op1); return vlmul_trunc_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1) { vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1) {
return vlmul_trunc_u32m4(op1); return vlmul_trunc_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m2_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1) {
return vlmul_trunc_u64m1(op1); return vlmul_trunc_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1) {
return vlmul_trunc_u64m1(op1); return vlmul_trunc_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1) { vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1) {
return vlmul_trunc_u64m2(op1); return vlmul_trunc_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1) {
return vlmul_trunc_u64m1(op1); return vlmul_trunc_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1) { vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1) {
return vlmul_trunc_u64m2(op1); return vlmul_trunc_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1) { vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1) {
return vlmul_trunc_u64m4(op1); return vlmul_trunc_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1) {
return vlmul_trunc_f32mf2(op1); return vlmul_trunc_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1) {
return vlmul_trunc_f32mf2(op1); return vlmul_trunc_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1) {
return vlmul_trunc_f32m1(op1); return vlmul_trunc_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1) {
return vlmul_trunc_f32mf2(op1); return vlmul_trunc_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1) {
return vlmul_trunc_f32m1(op1); return vlmul_trunc_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1) { vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1) {
return vlmul_trunc_f32m2(op1); return vlmul_trunc_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1) {
return vlmul_trunc_f32mf2(op1); return vlmul_trunc_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1) {
return vlmul_trunc_f32m1(op1); return vlmul_trunc_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1) { vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1) {
return vlmul_trunc_f32m2(op1); return vlmul_trunc_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1) { vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1) {
return vlmul_trunc_f32m4(op1); return vlmul_trunc_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m2_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m2_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1) {
return vlmul_trunc_f64m1(op1); return vlmul_trunc_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1) {
return vlmul_trunc_f64m1(op1); return vlmul_trunc_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1) { vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1) {
return vlmul_trunc_f64m2(op1); return vlmul_trunc_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1) {
return vlmul_trunc_f64m1(op1); return vlmul_trunc_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1) { vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1) {
return vlmul_trunc_f64m2(op1); return vlmul_trunc_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1) { vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1) {
return vlmul_trunc_f64m4(op1); return vlmul_trunc_f64m4(op1);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, size_t index, vint8m1_t val) { vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, size_t index, vint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, size_t index, vint8m1_t val) { vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, size_t index, vint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4( // CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, size_t index, vint8m2_t val) { vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, size_t index, vint8m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, size_t index, vint8m1_t val) { vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, size_t index, vint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, size_t index, vint8m2_t val) { vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, size_t index, vint8m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, size_t index, vint8m4_t val) { vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, size_t index, vint8m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m2( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vset_v_u8m1_u8m2(vuint8m2_t dest, size_t index, vuint8m1_t val) { vuint8m2_t test_vset_v_u8m1_u8m2(vuint8m2_t dest, size_t index, vuint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m4( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vset_v_u8m1_u8m4(vuint8m4_t dest, size_t index, vuint8m1_t val) { vuint8m4_t test_vset_v_u8m1_u8m4(vuint8m4_t dest, size_t index, vuint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m4( // CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vset_v_u8m2_u8m4(vuint8m4_t dest, size_t index, vuint8m2_t val) { vuint8m4_t test_vset_v_u8m2_u8m4(vuint8m4_t dest, size_t index, vuint8m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m1_u8m8(vuint8m8_t dest, size_t index, vuint8m1_t val) { vuint8m8_t test_vset_v_u8m1_u8m8(vuint8m8_t dest, size_t index, vuint8m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m2_u8m8(vuint8m8_t dest, size_t index, vuint8m2_t val) { vuint8m8_t test_vset_v_u8m2_u8m8(vuint8m8_t dest, size_t index, vuint8m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m4_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m4_u8m8(vuint8m8_t dest, size_t index, vuint8m4_t val) { vuint8m8_t test_vset_v_u8m4_u8m8(vuint8m8_t dest, size_t index, vuint8m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, size_t index, vint16m1_t val) { vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, size_t index, vint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, size_t index, vint16m1_t val) { vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, size_t index, vint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4( // CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, size_t index, vint16m2_t val) { vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, size_t index, vint16m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, size_t index, vint16m1_t val) { vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, size_t index, vint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, size_t index, vint16m2_t val) { vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, size_t index, vint16m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m4_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, size_t index, vint16m4_t val) { vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, size_t index, vint16m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m2( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vset_v_u16m1_u16m2(vuint16m2_t dest, size_t index, vuint16m1_t val) { vuint16m2_t test_vset_v_u16m1_u16m2(vuint16m2_t dest, size_t index, vuint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m4( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vset_v_u16m1_u16m4(vuint16m4_t dest, size_t index, vuint16m1_t val) { vuint16m4_t test_vset_v_u16m1_u16m4(vuint16m4_t dest, size_t index, vuint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m4( // CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vset_v_u16m2_u16m4(vuint16m4_t dest, size_t index, vuint16m2_t val) { vuint16m4_t test_vset_v_u16m2_u16m4(vuint16m4_t dest, size_t index, vuint16m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m1_u16m8(vuint16m8_t dest, size_t index, vuint16m1_t val) { vuint16m8_t test_vset_v_u16m1_u16m8(vuint16m8_t dest, size_t index, vuint16m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m2_u16m8(vuint16m8_t dest, size_t index, vuint16m2_t val) { vuint16m8_t test_vset_v_u16m2_u16m8(vuint16m8_t dest, size_t index, vuint16m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m4_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m4_u16m8(vuint16m8_t dest, size_t index, vuint16m4_t val) { vuint16m8_t test_vset_v_u16m4_u16m8(vuint16m8_t dest, size_t index, vuint16m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m2( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, size_t index, vint32m1_t val) { vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, size_t index, vint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m4( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, size_t index, vint32m1_t val) { vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, size_t index, vint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m4( // CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, size_t index, vint32m2_t val) { vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, size_t index, vint32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, size_t index, vint32m1_t val) { vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, size_t index, vint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, size_t index, vint32m2_t val) { vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, size_t index, vint32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m4_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, size_t index, vint32m4_t val) { vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, size_t index, vint32m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m2( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vset_v_u32m1_u32m2(vuint32m2_t dest, size_t index, vuint32m1_t val) { vuint32m2_t test_vset_v_u32m1_u32m2(vuint32m2_t dest, size_t index, vuint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m4( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vset_v_u32m1_u32m4(vuint32m4_t dest, size_t index, vuint32m1_t val) { vuint32m4_t test_vset_v_u32m1_u32m4(vuint32m4_t dest, size_t index, vuint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m4( // CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vset_v_u32m2_u32m4(vuint32m4_t dest, size_t index, vuint32m2_t val) { vuint32m4_t test_vset_v_u32m2_u32m4(vuint32m4_t dest, size_t index, vuint32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m1_u32m8(vuint32m8_t dest, size_t index, vuint32m1_t val) { vuint32m8_t test_vset_v_u32m1_u32m8(vuint32m8_t dest, size_t index, vuint32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m2_u32m8(vuint32m8_t dest, size_t index, vuint32m2_t val) { vuint32m8_t test_vset_v_u32m2_u32m8(vuint32m8_t dest, size_t index, vuint32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m4_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m4_u32m8(vuint32m8_t dest, size_t index, vuint32m4_t val) { vuint32m8_t test_vset_v_u32m4_u32m8(vuint32m8_t dest, size_t index, vuint32m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m2( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vset_v_f32m1_f32m2(vfloat32m2_t dest, size_t index, vfloat32m1_t val) { vfloat32m2_t test_vset_v_f32m1_f32m2(vfloat32m2_t dest, size_t index, vfloat32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m4( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vset_v_f32m1_f32m4(vfloat32m4_t dest, size_t index, vfloat32m1_t val) { vfloat32m4_t test_vset_v_f32m1_f32m4(vfloat32m4_t dest, size_t index, vfloat32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m4( // CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vset_v_f32m2_f32m4(vfloat32m4_t dest, size_t index, vfloat32m2_t val) { vfloat32m4_t test_vset_v_f32m2_f32m4(vfloat32m4_t dest, size_t index, vfloat32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m1_f32m8(vfloat32m8_t dest, size_t index, vfloat32m1_t val) { vfloat32m8_t test_vset_v_f32m1_f32m8(vfloat32m8_t dest, size_t index, vfloat32m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m2_f32m8(vfloat32m8_t dest, size_t index, vfloat32m2_t val) { vfloat32m8_t test_vset_v_f32m2_f32m8(vfloat32m8_t dest, size_t index, vfloat32m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m4_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m4_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 8 x float> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 8 x float> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m4_f32m8(vfloat32m8_t dest, size_t index, vfloat32m4_t val) { vfloat32m8_t test_vset_v_f32m4_f32m8(vfloat32m8_t dest, size_t index, vfloat32m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m2( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, size_t index, vint64m1_t val) { vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, size_t index, vint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m4( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vset_v_i64m1_i64m4(vint64m4_t dest, size_t index, vint64m1_t val) { vint64m4_t test_vset_v_i64m1_i64m4(vint64m4_t dest, size_t index, vint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m4( // CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vset_v_i64m2_i64m4(vint64m4_t dest, size_t index, vint64m2_t val) { vint64m4_t test_vset_v_i64m2_i64m4(vint64m4_t dest, size_t index, vint64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m1_i64m8(vint64m8_t dest, size_t index, vint64m1_t val) { vint64m8_t test_vset_v_i64m1_i64m8(vint64m8_t dest, size_t index, vint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m2_i64m8(vint64m8_t dest, size_t index, vint64m2_t val) { vint64m8_t test_vset_v_i64m2_i64m8(vint64m8_t dest, size_t index, vint64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m4_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m4_i64m8(vint64m8_t dest, size_t index, vint64m4_t val) { vint64m8_t test_vset_v_i64m4_i64m8(vint64m8_t dest, size_t index, vint64m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m2( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vset_v_u64m1_u64m2(vuint64m2_t dest, size_t index, vuint64m1_t val) { vuint64m2_t test_vset_v_u64m1_u64m2(vuint64m2_t dest, size_t index, vuint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m4( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vset_v_u64m1_u64m4(vuint64m4_t dest, size_t index, vuint64m1_t val) { vuint64m4_t test_vset_v_u64m1_u64m4(vuint64m4_t dest, size_t index, vuint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m4( // CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vset_v_u64m2_u64m4(vuint64m4_t dest, size_t index, vuint64m2_t val) { vuint64m4_t test_vset_v_u64m2_u64m4(vuint64m4_t dest, size_t index, vuint64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m1_u64m8(vuint64m8_t dest, size_t index, vuint64m1_t val) { vuint64m8_t test_vset_v_u64m1_u64m8(vuint64m8_t dest, size_t index, vuint64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m2_u64m8(vuint64m8_t dest, size_t index, vuint64m2_t val) { vuint64m8_t test_vset_v_u64m2_u64m8(vuint64m8_t dest, size_t index, vuint64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m4_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m4_u64m8(vuint64m8_t dest, size_t index, vuint64m4_t val) { vuint64m8_t test_vset_v_u64m4_u64m8(vuint64m8_t dest, size_t index, vuint64m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m2( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vset_v_f64m1_f64m2(vfloat64m2_t dest, size_t index, vfloat64m1_t val) { vfloat64m2_t test_vset_v_f64m1_f64m2(vfloat64m2_t dest, size_t index, vfloat64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m4( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vset_v_f64m1_f64m4(vfloat64m4_t dest, size_t index, vfloat64m1_t val) { vfloat64m4_t test_vset_v_f64m1_f64m4(vfloat64m4_t dest, size_t index, vfloat64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m4( // CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vset_v_f64m2_f64m4(vfloat64m4_t dest, size_t index, vfloat64m2_t val) { vfloat64m4_t test_vset_v_f64m2_f64m4(vfloat64m4_t dest, size_t index, vfloat64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m1_f64m8(vfloat64m8_t dest, size_t index, vfloat64m1_t val) { vfloat64m8_t test_vset_v_f64m1_f64m8(vfloat64m8_t dest, size_t index, vfloat64m1_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, size_t index, vfloat64m2_t val) { vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, size_t index, vfloat64m2_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m4_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m4_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 4 x double> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 4 x double> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, size_t index, vfloat64m4_t val) { vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, size_t index, vfloat64m4_t val) {
return vset(dest, 0, val); return vset(dest, 0, val);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vget-vset-ice.cpp

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// Use constexpr function to make sure we correctly evaluate it as a constant // Use constexpr function to make sure we correctly evaluate it as a constant
// when emitting IR for the vget/vset builtins. // when emitting IR for the vget/vset builtins.
constexpr int foo() { return 1; } constexpr int foo() { return 1; }
// CHECK-RV64-LABEL: @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t // CHECK-RV64-LABEL: @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) { vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) {
return vget_v_i8m2_i8m1(src, foo()); return vget_v_i8m2_i8m1(src, foo());
} }
// CHECK-RV64-LABEL: @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t // CHECK-RV64-LABEL: @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) { vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
return vset_v_i8m1_i8m2(dest, foo(), val); return vset_v_i8m1_i8m2(dest, foo(), val);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) { vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) {
return vget_v_i8m2_i8m1(src, 1); return vget_v_i8m2_i8m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src) { vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src) {
return vget_v_i8m4_i8m1(src, 2); return vget_v_i8m4_i8m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m2( // CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src) { vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src) {
return vget_v_i8m4_i8m2(src, 1); return vget_v_i8m4_i8m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m1( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src) { vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src) {
return vget_v_i8m8_i8m1(src, 6); return vget_v_i8m8_i8m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m2( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src) { vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src) {
return vget_v_i8m8_i8m2(src, 3); return vget_v_i8m8_i8m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m4( // CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src) { vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src) {
return vget_v_i8m8_i8m4(src, 1); return vget_v_i8m8_i8m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m2_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src) { vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src) {
return vget_v_i16m2_i16m1(src, 1); return vget_v_i16m2_i16m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src) { vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src) {
return vget_v_i16m4_i16m1(src, 2); return vget_v_i16m4_i16m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m2( // CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src) { vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src) {
return vget_v_i16m4_i16m2(src, 1); return vget_v_i16m4_i16m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m1( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src) { vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src) {
return vget_v_i16m8_i16m1(src, 6); return vget_v_i16m8_i16m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m2( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src) { vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src) {
return vget_v_i16m8_i16m2(src, 3); return vget_v_i16m8_i16m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m4( // CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src) { vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src) {
return vget_v_i16m8_i16m4(src, 1); return vget_v_i16m8_i16m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m2_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src) { vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src) {
return vget_v_i32m2_i32m1(src, 1); return vget_v_i32m2_i32m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src) { vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src) {
return vget_v_i32m4_i32m1(src, 2); return vget_v_i32m4_i32m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m2( // CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src) { vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src) {
return vget_v_i32m4_i32m2(src, 1); return vget_v_i32m4_i32m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m1( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src) { vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src) {
return vget_v_i32m8_i32m1(src, 6); return vget_v_i32m8_i32m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m2( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src) { vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src) {
return vget_v_i32m8_i32m2(src, 3); return vget_v_i32m8_i32m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m4( // CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src) { vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src) {
return vget_v_i32m8_i32m4(src, 1); return vget_v_i32m8_i32m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m2_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src) { vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src) {
return vget_v_i64m2_i64m1(src, 1); return vget_v_i64m2_i64m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src) { vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src) {
return vget_v_i64m4_i64m1(src, 2); return vget_v_i64m4_i64m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m2( // CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src) { vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src) {
return vget_v_i64m4_i64m2(src, 1); return vget_v_i64m4_i64m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m1( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src) { vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src) {
return vget_v_i64m8_i64m1(src, 6); return vget_v_i64m8_i64m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m2( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src) { vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src) {
return vget_v_i64m8_i64m2(src, 3); return vget_v_i64m8_i64m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m4( // CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src) { vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src) {
return vget_v_i64m8_i64m4(src, 1); return vget_v_i64m8_i64m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m2_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src) { vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src) {
return vget_v_u8m2_u8m1(src, 1); return vget_v_u8m2_u8m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src) { vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src) {
return vget_v_u8m4_u8m1(src, 2); return vget_v_u8m4_u8m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m2( // CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src) { vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src) {
return vget_v_u8m4_u8m2(src, 1); return vget_v_u8m4_u8m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m1( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src) { vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src) {
return vget_v_u8m8_u8m1(src, 6); return vget_v_u8m8_u8m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m2( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src) { vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src) {
return vget_v_u8m8_u8m2(src, 3); return vget_v_u8m8_u8m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m4( // CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src) { vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src) {
return vget_v_u8m8_u8m4(src, 1); return vget_v_u8m8_u8m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m2_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src) { vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src) {
return vget_v_u16m2_u16m1(src, 1); return vget_v_u16m2_u16m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src) { vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src) {
return vget_v_u16m4_u16m1(src, 2); return vget_v_u16m4_u16m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m2( // CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src) { vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src) {
return vget_v_u16m4_u16m2(src, 1); return vget_v_u16m4_u16m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m1( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src) { vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src) {
return vget_v_u16m8_u16m1(src, 6); return vget_v_u16m8_u16m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m2( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src) { vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src) {
return vget_v_u16m8_u16m2(src, 3); return vget_v_u16m8_u16m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m4( // CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src) { vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src) {
return vget_v_u16m8_u16m4(src, 1); return vget_v_u16m8_u16m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m2_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src) { vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src) {
return vget_v_u32m2_u32m1(src, 1); return vget_v_u32m2_u32m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src) { vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src) {
return vget_v_u32m4_u32m1(src, 2); return vget_v_u32m4_u32m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m2( // CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src) { vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src) {
return vget_v_u32m4_u32m2(src, 1); return vget_v_u32m4_u32m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m1( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src) { vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src) {
return vget_v_u32m8_u32m1(src, 6); return vget_v_u32m8_u32m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m2( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src) { vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src) {
return vget_v_u32m8_u32m2(src, 3); return vget_v_u32m8_u32m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m4( // CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src) { vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src) {
return vget_v_u32m8_u32m4(src, 1); return vget_v_u32m8_u32m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m2_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src) { vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src) {
return vget_v_u64m2_u64m1(src, 1); return vget_v_u64m2_u64m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src) { vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src) {
return vget_v_u64m4_u64m1(src, 2); return vget_v_u64m4_u64m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m2( // CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src) { vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src) {
return vget_v_u64m4_u64m2(src, 1); return vget_v_u64m4_u64m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m1( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src) { vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src) {
return vget_v_u64m8_u64m1(src, 6); return vget_v_u64m8_u64m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m2( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src) { vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src) {
return vget_v_u64m8_u64m2(src, 3); return vget_v_u64m8_u64m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m4( // CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src) { vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src) {
return vget_v_u64m8_u64m4(src, 1); return vget_v_u64m8_u64m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m2_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src) { vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src) {
return vget_v_f32m2_f32m1(src, 1); return vget_v_f32m2_f32m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src) { vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src) {
return vget_v_f32m4_f32m1(src, 2); return vget_v_f32m4_f32m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m2( // CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src) { vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src) {
return vget_v_f32m4_f32m2(src, 1); return vget_v_f32m4_f32m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m1( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src) { vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src) {
return vget_v_f32m8_f32m1(src, 6); return vget_v_f32m8_f32m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m2( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src) { vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src) {
return vget_v_f32m8_f32m2(src, 3); return vget_v_f32m8_f32m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m4( // CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src) { vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src) {
return vget_v_f32m8_f32m4(src, 1); return vget_v_f32m8_f32m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m2_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m2_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src) { vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src) {
return vget_v_f64m2_f64m1(src, 1); return vget_v_f64m2_f64m1(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src) { vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src) {
return vget_v_f64m4_f64m1(src, 2); return vget_v_f64m4_f64m1(src, 2);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m2( // CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src) { vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src) {
return vget_v_f64m4_f64m2(src, 1); return vget_v_f64m4_f64m2(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m1( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src) { vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src) {
return vget_v_f64m8_f64m1(src, 6); return vget_v_f64m8_f64m1(src, 6);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m2( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src) { vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src) {
return vget_v_f64m8_f64m2(src, 3); return vget_v_f64m8_f64m2(src, 3);
} }
// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m4( // CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src) { vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src) {
return vget_v_f64m8_f64m4(src, 1); return vget_v_f64m8_f64m4(src, 1);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m2_f16m1( // CHECK-RV64-LABEL: @test_vget_v_f16m2_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vget_v_f16m2_f16m1 (vfloat16m2_t src) { vfloat16m1_t test_vget_v_f16m2_f16m1 (vfloat16m2_t src) {
return vget_v_f16m2_f16m1(src, 0); return vget_v_f16m2_f16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m1( // CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vget_v_f16m4_f16m1 (vfloat16m4_t src) { vfloat16m1_t test_vget_v_f16m4_f16m1 (vfloat16m4_t src) {
return vget_v_f16m4_f16m1(src, 0); return vget_v_f16m4_f16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m1( // CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vget_v_f16m8_f16m1 (vfloat16m8_t src) { vfloat16m1_t test_vget_v_f16m8_f16m1 (vfloat16m8_t src) {
return vget_v_f16m8_f16m1(src, 0); return vget_v_f16m8_f16m1(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m2( // CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vget_v_f16m4_f16m2 (vfloat16m4_t src) { vfloat16m2_t test_vget_v_f16m4_f16m2 (vfloat16m4_t src) {
return vget_v_f16m4_f16m2(src, 0); return vget_v_f16m4_f16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m2( // CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vget_v_f16m8_f16m2 (vfloat16m8_t src) { vfloat16m2_t test_vget_v_f16m8_f16m2 (vfloat16m8_t src) {
return vget_v_f16m8_f16m2(src, 0); return vget_v_f16m8_f16m2(src, 0);
} }
// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m4( // CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vget_v_f16m8_f16m4 (vfloat16m8_t src) { vfloat16m4_t test_vget_v_f16m8_f16m4 (vfloat16m8_t src) {
return vget_v_f16m8_f16m4(src, 0); return vget_v_f16m8_f16m4(src, 0);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) { vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8mf4(op1); return vlmul_ext_v_i8mf8_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) { vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8mf2(op1); return vlmul_ext_v_i8mf8_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) { vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8m1(op1); return vlmul_ext_v_i8mf8_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) { vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8m2(op1); return vlmul_ext_v_i8mf8_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) { vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8m4(op1); return vlmul_ext_v_i8mf8_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) { vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) {
return vlmul_ext_v_i8mf8_i8m8(op1); return vlmul_ext_v_i8mf8_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) { vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) {
return vlmul_ext_v_i8mf4_i8mf2(op1); return vlmul_ext_v_i8mf4_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) { vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) {
return vlmul_ext_v_i8mf4_i8m1(op1); return vlmul_ext_v_i8mf4_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) { vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) {
return vlmul_ext_v_i8mf4_i8m2(op1); return vlmul_ext_v_i8mf4_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) { vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) {
return vlmul_ext_v_i8mf4_i8m4(op1); return vlmul_ext_v_i8mf4_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) { vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) {
return vlmul_ext_v_i8mf4_i8m8(op1); return vlmul_ext_v_i8mf4_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) { vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) {
return vlmul_ext_v_i8mf2_i8m1(op1); return vlmul_ext_v_i8mf2_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) { vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) {
return vlmul_ext_v_i8mf2_i8m2(op1); return vlmul_ext_v_i8mf2_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) { vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) {
return vlmul_ext_v_i8mf2_i8m4(op1); return vlmul_ext_v_i8mf2_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) { vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) {
return vlmul_ext_v_i8mf2_i8m8(op1); return vlmul_ext_v_i8mf2_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) { vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) {
return vlmul_ext_v_i8m1_i8m2(op1); return vlmul_ext_v_i8m1_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) { vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) {
return vlmul_ext_v_i8m1_i8m4(op1); return vlmul_ext_v_i8m1_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m1_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) { vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) {
return vlmul_ext_v_i8m1_i8m8(op1); return vlmul_ext_v_i8m1_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) { vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) {
return vlmul_ext_v_i8m2_i8m4(op1); return vlmul_ext_v_i8m2_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) { vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) {
return vlmul_ext_v_i8m2_i8m8(op1); return vlmul_ext_v_i8m2_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m4_i8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i8m4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) { vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) {
return vlmul_ext_v_i8m4_i8m8(op1); return vlmul_ext_v_i8m4_i8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) { vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) {
return vlmul_ext_v_i16mf4_i16mf2(op1); return vlmul_ext_v_i16mf4_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) { vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) {
return vlmul_ext_v_i16mf4_i16m1(op1); return vlmul_ext_v_i16mf4_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) { vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) {
return vlmul_ext_v_i16mf4_i16m2(op1); return vlmul_ext_v_i16mf4_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) { vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) {
return vlmul_ext_v_i16mf4_i16m4(op1); return vlmul_ext_v_i16mf4_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
return vlmul_ext_v_i16mf4_i16m8(op1); return vlmul_ext_v_i16mf4_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) { vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) {
return vlmul_ext_v_i16mf2_i16m1(op1); return vlmul_ext_v_i16mf2_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) { vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) {
return vlmul_ext_v_i16mf2_i16m2(op1); return vlmul_ext_v_i16mf2_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) { vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) {
return vlmul_ext_v_i16mf2_i16m4(op1); return vlmul_ext_v_i16mf2_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16mf2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) { vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) {
return vlmul_ext_v_i16mf2_i16m8(op1); return vlmul_ext_v_i16mf2_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) { vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) {
return vlmul_ext_v_i16m1_i16m2(op1); return vlmul_ext_v_i16m1_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) { vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) {
return vlmul_ext_v_i16m1_i16m4(op1); return vlmul_ext_v_i16m1_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m1_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) { vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) {
return vlmul_ext_v_i16m1_i16m8(op1); return vlmul_ext_v_i16m1_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) { vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) {
return vlmul_ext_v_i16m2_i16m4(op1); return vlmul_ext_v_i16m2_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) { vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) {
return vlmul_ext_v_i16m2_i16m8(op1); return vlmul_ext_v_i16m2_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m4_i16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i16m4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) { vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) {
return vlmul_ext_v_i16m4_i16m8(op1); return vlmul_ext_v_i16m4_i16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) { vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) {
return vlmul_ext_v_i32mf2_i32m1(op1); return vlmul_ext_v_i32mf2_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) { vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) {
return vlmul_ext_v_i32mf2_i32m2(op1); return vlmul_ext_v_i32mf2_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) { vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) {
return vlmul_ext_v_i32mf2_i32m4(op1); return vlmul_ext_v_i32mf2_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32mf2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) { vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) {
return vlmul_ext_v_i32mf2_i32m8(op1); return vlmul_ext_v_i32mf2_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) { vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) {
return vlmul_ext_v_i32m1_i32m2(op1); return vlmul_ext_v_i32m1_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) { vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) {
return vlmul_ext_v_i32m1_i32m4(op1); return vlmul_ext_v_i32m1_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m1_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) { vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) {
return vlmul_ext_v_i32m1_i32m8(op1); return vlmul_ext_v_i32m1_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) { vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) {
return vlmul_ext_v_i32m2_i32m4(op1); return vlmul_ext_v_i32m2_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) { vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) {
return vlmul_ext_v_i32m2_i32m8(op1); return vlmul_ext_v_i32m2_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m4_i32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i32m4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) { vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) {
return vlmul_ext_v_i32m4_i32m8(op1); return vlmul_ext_v_i32m4_i32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) { vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) {
return vlmul_ext_v_i64m1_i64m2(op1); return vlmul_ext_v_i64m1_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) { vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) {
return vlmul_ext_v_i64m1_i64m4(op1); return vlmul_ext_v_i64m1_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m1_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) { vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) {
return vlmul_ext_v_i64m1_i64m8(op1); return vlmul_ext_v_i64m1_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) { vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) {
return vlmul_ext_v_i64m2_i64m4(op1); return vlmul_ext_v_i64m2_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
return vlmul_ext_v_i64m2_i64m8(op1); return vlmul_ext_v_i64m2_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m4_i64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_i64m4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) { vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) {
return vlmul_ext_v_i64m4_i64m8(op1); return vlmul_ext_v_i64m4_i64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) { vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8mf4(op1); return vlmul_ext_v_u8mf8_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) { vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8mf2(op1); return vlmul_ext_v_u8mf8_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8m1(op1); return vlmul_ext_v_u8mf8_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8m2(op1); return vlmul_ext_v_u8mf8_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8m4(op1); return vlmul_ext_v_u8mf8_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf8_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) {
return vlmul_ext_v_u8mf8_u8m8(op1); return vlmul_ext_v_u8mf8_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) { vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) {
return vlmul_ext_v_u8mf4_u8mf2(op1); return vlmul_ext_v_u8mf4_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) {
return vlmul_ext_v_u8mf4_u8m1(op1); return vlmul_ext_v_u8mf4_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) {
return vlmul_ext_v_u8mf4_u8m2(op1); return vlmul_ext_v_u8mf4_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) {
return vlmul_ext_v_u8mf4_u8m4(op1); return vlmul_ext_v_u8mf4_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) {
return vlmul_ext_v_u8mf4_u8m8(op1); return vlmul_ext_v_u8mf4_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) { vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) {
return vlmul_ext_v_u8mf2_u8m1(op1); return vlmul_ext_v_u8mf2_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) { vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) {
return vlmul_ext_v_u8mf2_u8m2(op1); return vlmul_ext_v_u8mf2_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) { vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) {
return vlmul_ext_v_u8mf2_u8m4(op1); return vlmul_ext_v_u8mf2_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8mf2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) { vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) {
return vlmul_ext_v_u8mf2_u8m8(op1); return vlmul_ext_v_u8mf2_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) { vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) {
return vlmul_ext_v_u8m1_u8m2(op1); return vlmul_ext_v_u8m1_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) { vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) {
return vlmul_ext_v_u8m1_u8m4(op1); return vlmul_ext_v_u8m1_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m1_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) { vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) {
return vlmul_ext_v_u8m1_u8m8(op1); return vlmul_ext_v_u8m1_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) { vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) {
return vlmul_ext_v_u8m2_u8m4(op1); return vlmul_ext_v_u8m2_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) { vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) {
return vlmul_ext_v_u8m2_u8m8(op1); return vlmul_ext_v_u8m2_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m4_u8m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u8m4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) { vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) {
return vlmul_ext_v_u8m4_u8m8(op1); return vlmul_ext_v_u8m4_u8m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) { vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) {
return vlmul_ext_v_u16mf4_u16mf2(op1); return vlmul_ext_v_u16mf4_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) { vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) {
return vlmul_ext_v_u16mf4_u16m1(op1); return vlmul_ext_v_u16mf4_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) { vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) {
return vlmul_ext_v_u16mf4_u16m2(op1); return vlmul_ext_v_u16mf4_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) { vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) {
return vlmul_ext_v_u16mf4_u16m4(op1); return vlmul_ext_v_u16mf4_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) { vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) {
return vlmul_ext_v_u16mf4_u16m8(op1); return vlmul_ext_v_u16mf4_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) { vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) {
return vlmul_ext_v_u16mf2_u16m1(op1); return vlmul_ext_v_u16mf2_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) { vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) {
return vlmul_ext_v_u16mf2_u16m2(op1); return vlmul_ext_v_u16mf2_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) { vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) {
return vlmul_ext_v_u16mf2_u16m4(op1); return vlmul_ext_v_u16mf2_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16mf2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) { vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) {
return vlmul_ext_v_u16mf2_u16m8(op1); return vlmul_ext_v_u16mf2_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) { vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) {
return vlmul_ext_v_u16m1_u16m2(op1); return vlmul_ext_v_u16m1_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) { vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) {
return vlmul_ext_v_u16m1_u16m4(op1); return vlmul_ext_v_u16m1_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m1_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) { vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) {
return vlmul_ext_v_u16m1_u16m8(op1); return vlmul_ext_v_u16m1_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) { vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) {
return vlmul_ext_v_u16m2_u16m4(op1); return vlmul_ext_v_u16m2_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) { vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) {
return vlmul_ext_v_u16m2_u16m8(op1); return vlmul_ext_v_u16m2_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m4_u16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u16m4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) { vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) {
return vlmul_ext_v_u16m4_u16m8(op1); return vlmul_ext_v_u16m4_u16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) { vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) {
return vlmul_ext_v_u32mf2_u32m1(op1); return vlmul_ext_v_u32mf2_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) { vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) {
return vlmul_ext_v_u32mf2_u32m2(op1); return vlmul_ext_v_u32mf2_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) { vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) {
return vlmul_ext_v_u32mf2_u32m4(op1); return vlmul_ext_v_u32mf2_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32mf2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) { vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) {
return vlmul_ext_v_u32mf2_u32m8(op1); return vlmul_ext_v_u32mf2_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) { vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) {
return vlmul_ext_v_u32m1_u32m2(op1); return vlmul_ext_v_u32m1_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) { vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) {
return vlmul_ext_v_u32m1_u32m4(op1); return vlmul_ext_v_u32m1_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m1_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) { vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) {
return vlmul_ext_v_u32m1_u32m8(op1); return vlmul_ext_v_u32m1_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) { vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) {
return vlmul_ext_v_u32m2_u32m4(op1); return vlmul_ext_v_u32m2_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) { vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) {
return vlmul_ext_v_u32m2_u32m8(op1); return vlmul_ext_v_u32m2_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m4_u32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u32m4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) { vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) {
return vlmul_ext_v_u32m4_u32m8(op1); return vlmul_ext_v_u32m4_u32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) { vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) {
return vlmul_ext_v_u64m1_u64m2(op1); return vlmul_ext_v_u64m1_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) { vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) {
return vlmul_ext_v_u64m1_u64m4(op1); return vlmul_ext_v_u64m1_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m1_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> undef, <vscale x 1 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) { vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) {
return vlmul_ext_v_u64m1_u64m8(op1); return vlmul_ext_v_u64m1_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) { vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) {
return vlmul_ext_v_u64m2_u64m4(op1); return vlmul_ext_v_u64m2_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> undef, <vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) { vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) {
return vlmul_ext_v_u64m2_u64m8(op1); return vlmul_ext_v_u64m2_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m4_u64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_u64m4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> undef, <vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) { vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) {
return vlmul_ext_v_u64m4_u64m8(op1); return vlmul_ext_v_u64m4_u64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) { vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) {
return vlmul_ext_v_f32mf2_f32m1(op1); return vlmul_ext_v_f32mf2_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) { vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) {
return vlmul_ext_v_f32mf2_f32m2(op1); return vlmul_ext_v_f32mf2_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) { vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) {
return vlmul_ext_v_f32mf2_f32m4(op1); return vlmul_ext_v_f32mf2_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32mf2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) { vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) {
return vlmul_ext_v_f32mf2_f32m8(op1); return vlmul_ext_v_f32mf2_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) { vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) {
return vlmul_ext_v_f32m1_f32m2(op1); return vlmul_ext_v_f32m1_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) { vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) {
return vlmul_ext_v_f32m1_f32m4(op1); return vlmul_ext_v_f32m1_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m1_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) {
return vlmul_ext_v_f32m1_f32m8(op1); return vlmul_ext_v_f32m1_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) { vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) {
return vlmul_ext_v_f32m2_f32m4(op1); return vlmul_ext_v_f32m2_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) {
return vlmul_ext_v_f32m2_f32m8(op1); return vlmul_ext_v_f32m2_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m4_f32m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f32m4_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) { vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) {
return vlmul_ext_v_f32m4_f32m8(op1); return vlmul_ext_v_f32m4_f32m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) { vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) {
return vlmul_ext_v_f64m1_f64m2(op1); return vlmul_ext_v_f64m1_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) { vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) {
return vlmul_ext_v_f64m1_f64m4(op1); return vlmul_ext_v_f64m1_f64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m1_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) {
return vlmul_ext_v_f64m1_f64m8(op1); return vlmul_ext_v_f64m1_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) { vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) {
return vlmul_ext_v_f64m2_f64m4(op1); return vlmul_ext_v_f64m2_f64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m2_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) {
return vlmul_ext_v_f64m2_f64m8(op1); return vlmul_ext_v_f64m2_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m4_f64m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f64m4_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) { vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) {
return vlmul_ext_v_f64m4_f64m8(op1); return vlmul_ext_v_f64m4_f64m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf4_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1) { vint8mf8_t test_vlmul_trunc_v_i8mf4_i8mf8(vint8mf4_t op1) {
return vlmul_trunc_v_i8mf4_i8mf8(op1); return vlmul_trunc_v_i8mf4_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1) { vint8mf8_t test_vlmul_trunc_v_i8mf2_i8mf8(vint8mf2_t op1) {
return vlmul_trunc_v_i8mf2_i8mf8(op1); return vlmul_trunc_v_i8mf2_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8mf2_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1) { vint8mf4_t test_vlmul_trunc_v_i8mf2_i8mf4(vint8mf2_t op1) {
return vlmul_trunc_v_i8mf2_i8mf4(op1); return vlmul_trunc_v_i8mf2_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m1_i8mf8(vint8m1_t op1) {
return vlmul_trunc_v_i8m1_i8mf8(op1); return vlmul_trunc_v_i8m1_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m1_i8mf4(vint8m1_t op1) {
return vlmul_trunc_v_i8m1_i8mf4(op1); return vlmul_trunc_v_i8m1_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m1_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m1_i8mf2(vint8m1_t op1) {
return vlmul_trunc_v_i8m1_i8mf2(op1); return vlmul_trunc_v_i8m1_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m2_i8mf8(vint8m2_t op1) {
return vlmul_trunc_v_i8m2_i8mf8(op1); return vlmul_trunc_v_i8m2_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m2_i8mf4(vint8m2_t op1) {
return vlmul_trunc_v_i8m2_i8mf4(op1); return vlmul_trunc_v_i8m2_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m2_i8mf2(vint8m2_t op1) {
return vlmul_trunc_v_i8m2_i8mf2(op1); return vlmul_trunc_v_i8m2_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m2_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1) { vint8m1_t test_vlmul_trunc_v_i8m2_i8m1(vint8m2_t op1) {
return vlmul_trunc_v_i8m2_i8m1(op1); return vlmul_trunc_v_i8m2_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m4_i8mf8(vint8m4_t op1) {
return vlmul_trunc_v_i8m4_i8mf8(op1); return vlmul_trunc_v_i8m4_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m4_i8mf4(vint8m4_t op1) {
return vlmul_trunc_v_i8m4_i8mf4(op1); return vlmul_trunc_v_i8m4_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m4_i8mf2(vint8m4_t op1) {
return vlmul_trunc_v_i8m4_i8mf2(op1); return vlmul_trunc_v_i8m4_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1) { vint8m1_t test_vlmul_trunc_v_i8m4_i8m1(vint8m4_t op1) {
return vlmul_trunc_v_i8m4_i8m1(op1); return vlmul_trunc_v_i8m4_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m4_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1) { vint8m2_t test_vlmul_trunc_v_i8m4_i8m2(vint8m4_t op1) {
return vlmul_trunc_v_i8m4_i8m2(op1); return vlmul_trunc_v_i8m4_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1) { vint8mf8_t test_vlmul_trunc_v_i8m8_i8mf8(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8mf8(op1); return vlmul_trunc_v_i8m8_i8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1) { vint8mf4_t test_vlmul_trunc_v_i8m8_i8mf4(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8mf4(op1); return vlmul_trunc_v_i8m8_i8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1) { vint8mf2_t test_vlmul_trunc_v_i8m8_i8mf2(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8mf2(op1); return vlmul_trunc_v_i8m8_i8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1) { vint8m1_t test_vlmul_trunc_v_i8m8_i8m1(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8m1(op1); return vlmul_trunc_v_i8m8_i8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1) { vint8m2_t test_vlmul_trunc_v_i8m8_i8m2(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8m2(op1); return vlmul_trunc_v_i8m8_i8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i8m8_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1) { vint8m4_t test_vlmul_trunc_v_i8m8_i8m4(vint8m8_t op1) {
return vlmul_trunc_v_i8m8_i8m4(op1); return vlmul_trunc_v_i8m8_i8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16mf2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1) { vint16mf4_t test_vlmul_trunc_v_i16mf2_i16mf4(vint16mf2_t op1) {
return vlmul_trunc_v_i16mf2_i16mf4(op1); return vlmul_trunc_v_i16mf2_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m1_i16mf4(vint16m1_t op1) {
return vlmul_trunc_v_i16m1_i16mf4(op1); return vlmul_trunc_v_i16m1_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m1_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m1_i16mf2(vint16m1_t op1) {
return vlmul_trunc_v_i16m1_i16mf2(op1); return vlmul_trunc_v_i16m1_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m2_i16mf4(vint16m2_t op1) {
return vlmul_trunc_v_i16m2_i16mf4(op1); return vlmul_trunc_v_i16m2_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m2_i16mf2(vint16m2_t op1) {
return vlmul_trunc_v_i16m2_i16mf2(op1); return vlmul_trunc_v_i16m2_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1) { vint16m1_t test_vlmul_trunc_v_i16m2_i16m1(vint16m2_t op1) {
return vlmul_trunc_v_i16m2_i16m1(op1); return vlmul_trunc_v_i16m2_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m4_i16mf4(vint16m4_t op1) {
return vlmul_trunc_v_i16m4_i16mf4(op1); return vlmul_trunc_v_i16m4_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m4_i16mf2(vint16m4_t op1) {
return vlmul_trunc_v_i16m4_i16mf2(op1); return vlmul_trunc_v_i16m4_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1) { vint16m1_t test_vlmul_trunc_v_i16m4_i16m1(vint16m4_t op1) {
return vlmul_trunc_v_i16m4_i16m1(op1); return vlmul_trunc_v_i16m4_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m4_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1) { vint16m2_t test_vlmul_trunc_v_i16m4_i16m2(vint16m4_t op1) {
return vlmul_trunc_v_i16m4_i16m2(op1); return vlmul_trunc_v_i16m4_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1) { vint16mf4_t test_vlmul_trunc_v_i16m8_i16mf4(vint16m8_t op1) {
return vlmul_trunc_v_i16m8_i16mf4(op1); return vlmul_trunc_v_i16m8_i16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1) { vint16mf2_t test_vlmul_trunc_v_i16m8_i16mf2(vint16m8_t op1) {
return vlmul_trunc_v_i16m8_i16mf2(op1); return vlmul_trunc_v_i16m8_i16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1) { vint16m1_t test_vlmul_trunc_v_i16m8_i16m1(vint16m8_t op1) {
return vlmul_trunc_v_i16m8_i16m1(op1); return vlmul_trunc_v_i16m8_i16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1) { vint16m2_t test_vlmul_trunc_v_i16m8_i16m2(vint16m8_t op1) {
return vlmul_trunc_v_i16m8_i16m2(op1); return vlmul_trunc_v_i16m8_i16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i16m8_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1) { vint16m4_t test_vlmul_trunc_v_i16m8_i16m4(vint16m8_t op1) {
return vlmul_trunc_v_i16m8_i16m4(op1); return vlmul_trunc_v_i16m8_i16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m1_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m1_i32mf2(vint32m1_t op1) {
return vlmul_trunc_v_i32m1_i32mf2(op1); return vlmul_trunc_v_i32m1_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m2_i32mf2(vint32m2_t op1) {
return vlmul_trunc_v_i32m2_i32mf2(op1); return vlmul_trunc_v_i32m2_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1) { vint32m1_t test_vlmul_trunc_v_i32m2_i32m1(vint32m2_t op1) {
return vlmul_trunc_v_i32m2_i32m1(op1); return vlmul_trunc_v_i32m2_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m4_i32mf2(vint32m4_t op1) {
return vlmul_trunc_v_i32m4_i32mf2(op1); return vlmul_trunc_v_i32m4_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1) { vint32m1_t test_vlmul_trunc_v_i32m4_i32m1(vint32m4_t op1) {
return vlmul_trunc_v_i32m4_i32m1(op1); return vlmul_trunc_v_i32m4_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1) { vint32m2_t test_vlmul_trunc_v_i32m4_i32m2(vint32m4_t op1) {
return vlmul_trunc_v_i32m4_i32m2(op1); return vlmul_trunc_v_i32m4_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1) { vint32mf2_t test_vlmul_trunc_v_i32m8_i32mf2(vint32m8_t op1) {
return vlmul_trunc_v_i32m8_i32mf2(op1); return vlmul_trunc_v_i32m8_i32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1) { vint32m1_t test_vlmul_trunc_v_i32m8_i32m1(vint32m8_t op1) {
return vlmul_trunc_v_i32m8_i32m1(op1); return vlmul_trunc_v_i32m8_i32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1) { vint32m2_t test_vlmul_trunc_v_i32m8_i32m2(vint32m8_t op1) {
return vlmul_trunc_v_i32m8_i32m2(op1); return vlmul_trunc_v_i32m8_i32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i32m8_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1) { vint32m4_t test_vlmul_trunc_v_i32m8_i32m4(vint32m8_t op1) {
return vlmul_trunc_v_i32m8_i32m4(op1); return vlmul_trunc_v_i32m8_i32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m2_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1) { vint64m1_t test_vlmul_trunc_v_i64m2_i64m1(vint64m2_t op1) {
return vlmul_trunc_v_i64m2_i64m1(op1); return vlmul_trunc_v_i64m2_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1) { vint64m1_t test_vlmul_trunc_v_i64m4_i64m1(vint64m4_t op1) {
return vlmul_trunc_v_i64m4_i64m1(op1); return vlmul_trunc_v_i64m4_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1) { vint64m2_t test_vlmul_trunc_v_i64m4_i64m2(vint64m4_t op1) {
return vlmul_trunc_v_i64m4_i64m2(op1); return vlmul_trunc_v_i64m4_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1) { vint64m1_t test_vlmul_trunc_v_i64m8_i64m1(vint64m8_t op1) {
return vlmul_trunc_v_i64m8_i64m1(op1); return vlmul_trunc_v_i64m8_i64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1) { vint64m2_t test_vlmul_trunc_v_i64m8_i64m2(vint64m8_t op1) {
return vlmul_trunc_v_i64m8_i64m2(op1); return vlmul_trunc_v_i64m8_i64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_i64m8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1) { vint64m4_t test_vlmul_trunc_v_i64m8_i64m4(vint64m8_t op1) {
return vlmul_trunc_v_i64m8_i64m4(op1); return vlmul_trunc_v_i64m8_i64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf4_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv2i8(<vscale x 2 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8mf4_u8mf8(vuint8mf4_t op1) {
return vlmul_trunc_v_u8mf4_u8mf8(op1); return vlmul_trunc_v_u8mf4_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8mf2_u8mf8(vuint8mf2_t op1) {
return vlmul_trunc_v_u8mf2_u8mf8(op1); return vlmul_trunc_v_u8mf2_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8mf2_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv4i8(<vscale x 4 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8mf2_u8mf4(vuint8mf2_t op1) {
return vlmul_trunc_v_u8mf2_u8mf4(op1); return vlmul_trunc_v_u8mf2_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m1_u8mf8(vuint8m1_t op1) {
return vlmul_trunc_v_u8m1_u8mf8(op1); return vlmul_trunc_v_u8m1_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m1_u8mf4(vuint8m1_t op1) {
return vlmul_trunc_v_u8m1_u8mf4(op1); return vlmul_trunc_v_u8m1_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m1_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv8i8(<vscale x 8 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m1_u8mf2(vuint8m1_t op1) {
return vlmul_trunc_v_u8m1_u8mf2(op1); return vlmul_trunc_v_u8m1_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m2_u8mf8(vuint8m2_t op1) {
return vlmul_trunc_v_u8m2_u8mf8(op1); return vlmul_trunc_v_u8m2_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m2_u8mf4(vuint8m2_t op1) {
return vlmul_trunc_v_u8m2_u8mf4(op1); return vlmul_trunc_v_u8m2_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m2_u8mf2(vuint8m2_t op1) {
return vlmul_trunc_v_u8m2_u8mf2(op1); return vlmul_trunc_v_u8m2_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m2_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m2_u8m1(vuint8m2_t op1) {
return vlmul_trunc_v_u8m2_u8m1(op1); return vlmul_trunc_v_u8m2_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m4_u8mf8(vuint8m4_t op1) {
return vlmul_trunc_v_u8m4_u8mf8(op1); return vlmul_trunc_v_u8m4_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m4_u8mf4(vuint8m4_t op1) {
return vlmul_trunc_v_u8m4_u8mf4(op1); return vlmul_trunc_v_u8m4_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m4_u8mf2(vuint8m4_t op1) {
return vlmul_trunc_v_u8m4_u8mf2(op1); return vlmul_trunc_v_u8m4_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m4_u8m1(vuint8m4_t op1) {
return vlmul_trunc_v_u8m4_u8m1(op1); return vlmul_trunc_v_u8m4_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m4_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1) { vuint8m2_t test_vlmul_trunc_v_u8m4_u8m2(vuint8m4_t op1) {
return vlmul_trunc_v_u8m4_u8m2(op1); return vlmul_trunc_v_u8m4_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1) { vuint8mf8_t test_vlmul_trunc_v_u8m8_u8mf8(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8mf8(op1); return vlmul_trunc_v_u8m8_u8mf8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1) { vuint8mf4_t test_vlmul_trunc_v_u8m8_u8mf4(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8mf4(op1); return vlmul_trunc_v_u8m8_u8mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1) { vuint8mf2_t test_vlmul_trunc_v_u8m8_u8mf2(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8mf2(op1); return vlmul_trunc_v_u8m8_u8mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1) { vuint8m1_t test_vlmul_trunc_v_u8m8_u8m1(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8m1(op1); return vlmul_trunc_v_u8m8_u8m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1) { vuint8m2_t test_vlmul_trunc_v_u8m8_u8m2(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8m2(op1); return vlmul_trunc_v_u8m8_u8m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u8m8_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1) { vuint8m4_t test_vlmul_trunc_v_u8m8_u8m4(vuint8m8_t op1) {
return vlmul_trunc_v_u8m8_u8m4(op1); return vlmul_trunc_v_u8m8_u8m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16mf2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv2i16(<vscale x 2 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16mf2_u16mf4(vuint16mf2_t op1) {
return vlmul_trunc_v_u16mf2_u16mf4(op1); return vlmul_trunc_v_u16mf2_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m1_u16mf4(vuint16m1_t op1) {
return vlmul_trunc_v_u16m1_u16mf4(op1); return vlmul_trunc_v_u16m1_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m1_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m1_u16mf2(vuint16m1_t op1) {
return vlmul_trunc_v_u16m1_u16mf2(op1); return vlmul_trunc_v_u16m1_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m2_u16mf4(vuint16m2_t op1) {
return vlmul_trunc_v_u16m2_u16mf4(op1); return vlmul_trunc_v_u16m2_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m2_u16mf2(vuint16m2_t op1) {
return vlmul_trunc_v_u16m2_u16mf2(op1); return vlmul_trunc_v_u16m2_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m2_u16m1(vuint16m2_t op1) {
return vlmul_trunc_v_u16m2_u16m1(op1); return vlmul_trunc_v_u16m2_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m4_u16mf4(vuint16m4_t op1) {
return vlmul_trunc_v_u16m4_u16mf4(op1); return vlmul_trunc_v_u16m4_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m4_u16mf2(vuint16m4_t op1) {
return vlmul_trunc_v_u16m4_u16mf2(op1); return vlmul_trunc_v_u16m4_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m4_u16m1(vuint16m4_t op1) {
return vlmul_trunc_v_u16m4_u16m1(op1); return vlmul_trunc_v_u16m4_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m4_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1) { vuint16m2_t test_vlmul_trunc_v_u16m4_u16m2(vuint16m4_t op1) {
return vlmul_trunc_v_u16m4_u16m2(op1); return vlmul_trunc_v_u16m4_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1) { vuint16mf4_t test_vlmul_trunc_v_u16m8_u16mf4(vuint16m8_t op1) {
return vlmul_trunc_v_u16m8_u16mf4(op1); return vlmul_trunc_v_u16m8_u16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.experimental.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1) { vuint16mf2_t test_vlmul_trunc_v_u16m8_u16mf2(vuint16m8_t op1) {
return vlmul_trunc_v_u16m8_u16mf2(op1); return vlmul_trunc_v_u16m8_u16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1) { vuint16m1_t test_vlmul_trunc_v_u16m8_u16m1(vuint16m8_t op1) {
return vlmul_trunc_v_u16m8_u16m1(op1); return vlmul_trunc_v_u16m8_u16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1) { vuint16m2_t test_vlmul_trunc_v_u16m8_u16m2(vuint16m8_t op1) {
return vlmul_trunc_v_u16m8_u16m2(op1); return vlmul_trunc_v_u16m8_u16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u16m8_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1) { vuint16m4_t test_vlmul_trunc_v_u16m8_u16m4(vuint16m8_t op1) {
return vlmul_trunc_v_u16m8_u16m4(op1); return vlmul_trunc_v_u16m8_u16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m1_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m1_u32mf2(vuint32m1_t op1) {
return vlmul_trunc_v_u32m1_u32mf2(op1); return vlmul_trunc_v_u32m1_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m2_u32mf2(vuint32m2_t op1) {
return vlmul_trunc_v_u32m2_u32mf2(op1); return vlmul_trunc_v_u32m2_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m2_u32m1(vuint32m2_t op1) {
return vlmul_trunc_v_u32m2_u32m1(op1); return vlmul_trunc_v_u32m2_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m4_u32mf2(vuint32m4_t op1) {
return vlmul_trunc_v_u32m4_u32mf2(op1); return vlmul_trunc_v_u32m4_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m4_u32m1(vuint32m4_t op1) {
return vlmul_trunc_v_u32m4_u32m1(op1); return vlmul_trunc_v_u32m4_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1) { vuint32m2_t test_vlmul_trunc_v_u32m4_u32m2(vuint32m4_t op1) {
return vlmul_trunc_v_u32m4_u32m2(op1); return vlmul_trunc_v_u32m4_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1) { vuint32mf2_t test_vlmul_trunc_v_u32m8_u32mf2(vuint32m8_t op1) {
return vlmul_trunc_v_u32m8_u32mf2(op1); return vlmul_trunc_v_u32m8_u32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1) { vuint32m1_t test_vlmul_trunc_v_u32m8_u32m1(vuint32m8_t op1) {
return vlmul_trunc_v_u32m8_u32m1(op1); return vlmul_trunc_v_u32m8_u32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1) { vuint32m2_t test_vlmul_trunc_v_u32m8_u32m2(vuint32m8_t op1) {
return vlmul_trunc_v_u32m8_u32m2(op1); return vlmul_trunc_v_u32m8_u32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u32m8_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1) { vuint32m4_t test_vlmul_trunc_v_u32m8_u32m4(vuint32m8_t op1) {
return vlmul_trunc_v_u32m8_u32m4(op1); return vlmul_trunc_v_u32m8_u32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m2_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m2_u64m1(vuint64m2_t op1) {
return vlmul_trunc_v_u64m2_u64m1(op1); return vlmul_trunc_v_u64m2_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m4_u64m1(vuint64m4_t op1) {
return vlmul_trunc_v_u64m4_u64m1(op1); return vlmul_trunc_v_u64m4_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1) { vuint64m2_t test_vlmul_trunc_v_u64m4_u64m2(vuint64m4_t op1) {
return vlmul_trunc_v_u64m4_u64m2(op1); return vlmul_trunc_v_u64m4_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1) { vuint64m1_t test_vlmul_trunc_v_u64m8_u64m1(vuint64m8_t op1) {
return vlmul_trunc_v_u64m8_u64m1(op1); return vlmul_trunc_v_u64m8_u64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1) { vuint64m2_t test_vlmul_trunc_v_u64m8_u64m2(vuint64m8_t op1) {
return vlmul_trunc_v_u64m8_u64m2(op1); return vlmul_trunc_v_u64m8_u64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_u64m8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1) { vuint64m4_t test_vlmul_trunc_v_u64m8_u64m4(vuint64m8_t op1) {
return vlmul_trunc_v_u64m8_u64m4(op1); return vlmul_trunc_v_u64m8_u64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m1_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m1_f32mf2(vfloat32m1_t op1) {
return vlmul_trunc_v_f32m1_f32mf2(op1); return vlmul_trunc_v_f32m1_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m2_f32mf2(vfloat32m2_t op1) {
return vlmul_trunc_v_f32m2_f32mf2(op1); return vlmul_trunc_v_f32m2_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m2_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m2_f32m1(vfloat32m2_t op1) {
return vlmul_trunc_v_f32m2_f32m1(op1); return vlmul_trunc_v_f32m2_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m4_f32mf2(vfloat32m4_t op1) {
return vlmul_trunc_v_f32m4_f32mf2(op1); return vlmul_trunc_v_f32m4_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m4_f32m1(vfloat32m4_t op1) {
return vlmul_trunc_v_f32m4_f32m1(op1); return vlmul_trunc_v_f32m4_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m4_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1) { vfloat32m2_t test_vlmul_trunc_v_f32m4_f32m2(vfloat32m4_t op1) {
return vlmul_trunc_v_f32m4_f32m2(op1); return vlmul_trunc_v_f32m4_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.experimental.vector.extract.nxv1f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1) { vfloat32mf2_t test_vlmul_trunc_v_f32m8_f32mf2(vfloat32m8_t op1) {
return vlmul_trunc_v_f32m8_f32mf2(op1); return vlmul_trunc_v_f32m8_f32mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1) { vfloat32m1_t test_vlmul_trunc_v_f32m8_f32m1(vfloat32m8_t op1) {
return vlmul_trunc_v_f32m8_f32m1(op1); return vlmul_trunc_v_f32m8_f32m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1) { vfloat32m2_t test_vlmul_trunc_v_f32m8_f32m2(vfloat32m8_t op1) {
return vlmul_trunc_v_f32m8_f32m2(op1); return vlmul_trunc_v_f32m8_f32m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f32m8_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1) { vfloat32m4_t test_vlmul_trunc_v_f32m8_f32m4(vfloat32m8_t op1) {
return vlmul_trunc_v_f32m8_f32m4(op1); return vlmul_trunc_v_f32m8_f32m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m2_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m2_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m2_f64m1(vfloat64m2_t op1) {
return vlmul_trunc_v_f64m2_f64m1(op1); return vlmul_trunc_v_f64m2_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m4_f64m1(vfloat64m4_t op1) {
return vlmul_trunc_v_f64m4_f64m1(op1); return vlmul_trunc_v_f64m4_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m4_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1) { vfloat64m2_t test_vlmul_trunc_v_f64m4_f64m2(vfloat64m4_t op1) {
return vlmul_trunc_v_f64m4_f64m2(op1); return vlmul_trunc_v_f64m4_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1) { vfloat64m1_t test_vlmul_trunc_v_f64m8_f64m1(vfloat64m8_t op1) {
return vlmul_trunc_v_f64m8_f64m1(op1); return vlmul_trunc_v_f64m8_f64m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1) { vfloat64m2_t test_vlmul_trunc_v_f64m8_f64m2(vfloat64m8_t op1) {
return vlmul_trunc_v_f64m8_f64m2(op1); return vlmul_trunc_v_f64m8_f64m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f64m8_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1) { vfloat64m4_t test_vlmul_trunc_v_f64m8_f64m4(vfloat64m8_t op1) {
return vlmul_trunc_v_f64m8_f64m4(op1); return vlmul_trunc_v_f64m8_f64m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16mf2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.experimental.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2 (vfloat16mf4_t op1) { vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2 (vfloat16mf4_t op1) {
return vlmul_ext_v_f16mf4_f16mf2(op1); return vlmul_ext_v_f16mf4_f16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vlmul_ext_v_f16mf4_f16m1 (vfloat16mf4_t op1) { vfloat16m1_t test_vlmul_ext_v_f16mf4_f16m1 (vfloat16mf4_t op1) {
return vlmul_ext_v_f16mf4_f16m1(op1); return vlmul_ext_v_f16mf4_f16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vlmul_ext_v_f16mf4_f16m2 (vfloat16mf4_t op1) { vfloat16m2_t test_vlmul_ext_v_f16mf4_f16m2 (vfloat16mf4_t op1) {
return vlmul_ext_v_f16mf4_f16m2(op1); return vlmul_ext_v_f16mf4_f16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vlmul_ext_v_f16mf4_f16m4 (vfloat16mf4_t op1) { vfloat16m4_t test_vlmul_ext_v_f16mf4_f16m4 (vfloat16mf4_t op1) {
return vlmul_ext_v_f16mf4_f16m4(op1); return vlmul_ext_v_f16mf4_f16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf4_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8 (vfloat16mf4_t op1) { vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8 (vfloat16mf4_t op1) {
return vlmul_ext_v_f16mf4_f16m8(op1); return vlmul_ext_v_f16mf4_f16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m1( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vlmul_ext_v_f16mf2_f16m1 (vfloat16mf2_t op1) { vfloat16m1_t test_vlmul_ext_v_f16mf2_f16m1 (vfloat16mf2_t op1) {
return vlmul_ext_v_f16mf2_f16m1(op1); return vlmul_ext_v_f16mf2_f16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vlmul_ext_v_f16mf2_f16m2 (vfloat16mf2_t op1) { vfloat16m2_t test_vlmul_ext_v_f16mf2_f16m2 (vfloat16mf2_t op1) {
return vlmul_ext_v_f16mf2_f16m2(op1); return vlmul_ext_v_f16mf2_f16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vlmul_ext_v_f16mf2_f16m4 (vfloat16mf2_t op1) { vfloat16m4_t test_vlmul_ext_v_f16mf2_f16m4 (vfloat16mf2_t op1) {
return vlmul_ext_v_f16mf2_f16m4(op1); return vlmul_ext_v_f16mf2_f16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16mf2_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vlmul_ext_v_f16mf2_f16m8 (vfloat16mf2_t op1) { vfloat16m8_t test_vlmul_ext_v_f16mf2_f16m8 (vfloat16mf2_t op1) {
return vlmul_ext_v_f16mf2_f16m8(op1); return vlmul_ext_v_f16mf2_f16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m2( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vlmul_ext_v_f16m1_f16m2 (vfloat16m1_t op1) { vfloat16m2_t test_vlmul_ext_v_f16m1_f16m2 (vfloat16m1_t op1) {
return vlmul_ext_v_f16m1_f16m2(op1); return vlmul_ext_v_f16m1_f16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vlmul_ext_v_f16m1_f16m4 (vfloat16m1_t op1) { vfloat16m4_t test_vlmul_ext_v_f16m1_f16m4 (vfloat16m1_t op1) {
return vlmul_ext_v_f16m1_f16m4(op1); return vlmul_ext_v_f16m1_f16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m1_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vlmul_ext_v_f16m1_f16m8 (vfloat16m1_t op1) { vfloat16m8_t test_vlmul_ext_v_f16m1_f16m8 (vfloat16m1_t op1) {
return vlmul_ext_v_f16m1_f16m8(op1); return vlmul_ext_v_f16m1_f16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m2_f16m4( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m2_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vlmul_ext_v_f16m2_f16m4 (vfloat16m2_t op1) { vfloat16m4_t test_vlmul_ext_v_f16m2_f16m4 (vfloat16m2_t op1) {
return vlmul_ext_v_f16m2_f16m4(op1); return vlmul_ext_v_f16m2_f16m4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m2_f16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m2_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vlmul_ext_v_f16m2_f16m8 (vfloat16m2_t op1) { vfloat16m8_t test_vlmul_ext_v_f16m2_f16m8 (vfloat16m2_t op1) {
return vlmul_ext_v_f16m2_f16m8(op1); return vlmul_ext_v_f16m2_f16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m4_f16m8( // CHECK-RV64-LABEL: @test_vlmul_ext_v_f16m4_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> undef, <vscale x 16 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> undef, <vscale x 16 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vlmul_ext_v_f16m4_f16m8 (vfloat16m4_t op1) { vfloat16m8_t test_vlmul_ext_v_f16m4_f16m8 (vfloat16m4_t op1) {
return vlmul_ext_v_f16m4_f16m8(op1); return vlmul_ext_v_f16m4_f16m8(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16mf2_f16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16mf2_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.experimental.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4 (vfloat16mf2_t op1) { vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4 (vfloat16mf2_t op1) {
return vlmul_trunc_v_f16mf2_f16mf4(op1); return vlmul_trunc_v_f16mf2_f16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m1_f16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m1_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.experimental.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vlmul_trunc_v_f16m1_f16mf4 (vfloat16m1_t op1) { vfloat16mf4_t test_vlmul_trunc_v_f16m1_f16mf4 (vfloat16m1_t op1) {
return vlmul_trunc_v_f16m1_f16mf4(op1); return vlmul_trunc_v_f16m1_f16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m1_f16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m1_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vlmul_trunc_v_f16m1_f16mf2 (vfloat16m1_t op1) { vfloat16mf2_t test_vlmul_trunc_v_f16m1_f16mf2 (vfloat16m1_t op1) {
return vlmul_trunc_v_f16m1_f16mf2(op1); return vlmul_trunc_v_f16m1_f16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.experimental.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vlmul_trunc_v_f16m2_f16mf4 (vfloat16m2_t op1) { vfloat16mf4_t test_vlmul_trunc_v_f16m2_f16mf4 (vfloat16m2_t op1) {
return vlmul_trunc_v_f16m2_f16mf4(op1); return vlmul_trunc_v_f16m2_f16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vlmul_trunc_v_f16m2_f16mf2 (vfloat16m2_t op1) { vfloat16mf2_t test_vlmul_trunc_v_f16m2_f16mf2 (vfloat16m2_t op1) {
return vlmul_trunc_v_f16m2_f16mf2(op1); return vlmul_trunc_v_f16m2_f16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m2_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vlmul_trunc_v_f16m2_f16m1 (vfloat16m2_t op1) { vfloat16m1_t test_vlmul_trunc_v_f16m2_f16m1 (vfloat16m2_t op1) {
return vlmul_trunc_v_f16m2_f16m1(op1); return vlmul_trunc_v_f16m2_f16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.experimental.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vlmul_trunc_v_f16m4_f16mf4 (vfloat16m4_t op1) { vfloat16mf4_t test_vlmul_trunc_v_f16m4_f16mf4 (vfloat16m4_t op1) {
return vlmul_trunc_v_f16m4_f16mf4(op1); return vlmul_trunc_v_f16m4_f16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vlmul_trunc_v_f16m4_f16mf2 (vfloat16m4_t op1) { vfloat16mf2_t test_vlmul_trunc_v_f16m4_f16mf2 (vfloat16m4_t op1) {
return vlmul_trunc_v_f16m4_f16mf2(op1); return vlmul_trunc_v_f16m4_f16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vlmul_trunc_v_f16m4_f16m1 (vfloat16m4_t op1) { vfloat16m1_t test_vlmul_trunc_v_f16m4_f16m1 (vfloat16m4_t op1) {
return vlmul_trunc_v_f16m4_f16m1(op1); return vlmul_trunc_v_f16m4_f16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m4_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vlmul_trunc_v_f16m4_f16m2 (vfloat16m4_t op1) { vfloat16m2_t test_vlmul_trunc_v_f16m4_f16m2 (vfloat16m4_t op1) {
return vlmul_trunc_v_f16m4_f16m2(op1); return vlmul_trunc_v_f16m4_f16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16mf4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.experimental.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vlmul_trunc_v_f16m8_f16mf4 (vfloat16m8_t op1) { vfloat16mf4_t test_vlmul_trunc_v_f16m8_f16mf4 (vfloat16m8_t op1) {
return vlmul_trunc_v_f16m8_f16mf4(op1); return vlmul_trunc_v_f16m8_f16mf4(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16mf2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vlmul_trunc_v_f16m8_f16mf2 (vfloat16m8_t op1) { vfloat16mf2_t test_vlmul_trunc_v_f16m8_f16mf2 (vfloat16m8_t op1) {
return vlmul_trunc_v_f16m8_f16mf2(op1); return vlmul_trunc_v_f16m8_f16mf2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m1( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vlmul_trunc_v_f16m8_f16m1 (vfloat16m8_t op1) { vfloat16m1_t test_vlmul_trunc_v_f16m8_f16m1 (vfloat16m8_t op1) {
return vlmul_trunc_v_f16m8_f16m1(op1); return vlmul_trunc_v_f16m8_f16m1(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m2( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vlmul_trunc_v_f16m8_f16m2 (vfloat16m8_t op1) { vfloat16m2_t test_vlmul_trunc_v_f16m8_f16m2 (vfloat16m8_t op1) {
return vlmul_trunc_v_f16m8_f16m2(op1); return vlmul_trunc_v_f16m8_f16m2(op1);
} }
// CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m4( // CHECK-RV64-LABEL: @test_vlmul_trunc_v_f16m8_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[OP1:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4 (vfloat16m8_t op1) { vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4 (vfloat16m8_t op1) {
return vlmul_trunc_v_f16m8_f16m4(op1); return vlmul_trunc_v_f16m8_f16m4(op1);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) { vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
return vset_v_i8m1_i8m2(dest, 1, val); return vset_v_i8m1_i8m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) { vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
return vset_v_i8m1_i8m4(dest, 3, val); return vset_v_i8m1_i8m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4( // CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) { vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
return vset_v_i8m2_i8m4(dest, 1, val); return vset_v_i8m2_i8m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) { vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
return vset_v_i8m1_i8m8(dest, 7, val); return vset_v_i8m1_i8m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) { vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
return vset_v_i8m2_i8m8(dest, 2, val); return vset_v_i8m2_i8m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8( // CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) { vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
return vset_v_i8m4_i8m8(dest, 1, val); return vset_v_i8m4_i8m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) { vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
return vset_v_i16m1_i16m2(dest, 1, val); return vset_v_i16m1_i16m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) { vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
return vset_v_i16m1_i16m4(dest, 3, val); return vset_v_i16m1_i16m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4( // CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) { vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
return vset_v_i16m2_i16m4(dest, 1, val); return vset_v_i16m2_i16m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) { vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
return vset_v_i16m1_i16m8(dest, 7, val); return vset_v_i16m1_i16m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) { vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) {
return vset_v_i16m2_i16m8(dest, 2, val); return vset_v_i16m2_i16m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i16m4_i16m8( // CHECK-RV64-LABEL: @test_vset_v_i16m4_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, vint16m4_t val) { vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, vint16m4_t val) {
return vset_v_i16m4_i16m8(dest, 1, val); return vset_v_i16m4_i16m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m2( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, vint32m1_t val) { vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, vint32m1_t val) {
return vset_v_i32m1_i32m2(dest, 1, val); return vset_v_i32m1_i32m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m4( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, vint32m1_t val) { vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, vint32m1_t val) {
return vset_v_i32m1_i32m4(dest, 3, val); return vset_v_i32m1_i32m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m4( // CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, vint32m2_t val) { vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, vint32m2_t val) {
return vset_v_i32m2_i32m4(dest, 1, val); return vset_v_i32m2_i32m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, vint32m1_t val) { vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, vint32m1_t val) {
return vset_v_i32m1_i32m8(dest, 7, val); return vset_v_i32m1_i32m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, vint32m2_t val) { vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, vint32m2_t val) {
return vset_v_i32m2_i32m8(dest, 2, val); return vset_v_i32m2_i32m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i32m4_i32m8( // CHECK-RV64-LABEL: @test_vset_v_i32m4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, vint32m4_t val) { vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, vint32m4_t val) {
return vset_v_i32m4_i32m8(dest, 1, val); return vset_v_i32m4_i32m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m2( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, vint64m1_t val) { vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, vint64m1_t val) {
return vset_v_i64m1_i64m2(dest, 1, val); return vset_v_i64m1_i64m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m4( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vset_v_i64m1_i64m4(vint64m4_t dest, vint64m1_t val) { vint64m4_t test_vset_v_i64m1_i64m4(vint64m4_t dest, vint64m1_t val) {
return vset_v_i64m1_i64m4(dest, 3, val); return vset_v_i64m1_i64m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m4( // CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vset_v_i64m2_i64m4(vint64m4_t dest, vint64m2_t val) { vint64m4_t test_vset_v_i64m2_i64m4(vint64m4_t dest, vint64m2_t val) {
return vset_v_i64m2_i64m4(dest, 1, val); return vset_v_i64m2_i64m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m1_i64m8(vint64m8_t dest, vint64m1_t val) { vint64m8_t test_vset_v_i64m1_i64m8(vint64m8_t dest, vint64m1_t val) {
return vset_v_i64m1_i64m8(dest, 7, val); return vset_v_i64m1_i64m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m2_i64m8(vint64m8_t dest, vint64m2_t val) { vint64m8_t test_vset_v_i64m2_i64m8(vint64m8_t dest, vint64m2_t val) {
return vset_v_i64m2_i64m8(dest, 2, val); return vset_v_i64m2_i64m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_i64m4_i64m8( // CHECK-RV64-LABEL: @test_vset_v_i64m4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vset_v_i64m4_i64m8(vint64m8_t dest, vint64m4_t val) { vint64m8_t test_vset_v_i64m4_i64m8(vint64m8_t dest, vint64m4_t val) {
return vset_v_i64m4_i64m8(dest, 1, val); return vset_v_i64m4_i64m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m2( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vset_v_u8m1_u8m2(vuint8m2_t dest, vuint8m1_t val) { vuint8m2_t test_vset_v_u8m1_u8m2(vuint8m2_t dest, vuint8m1_t val) {
return vset_v_u8m1_u8m2(dest, 1, val); return vset_v_u8m1_u8m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m4( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vset_v_u8m1_u8m4(vuint8m4_t dest, vuint8m1_t val) { vuint8m4_t test_vset_v_u8m1_u8m4(vuint8m4_t dest, vuint8m1_t val) {
return vset_v_u8m1_u8m4(dest, 3, val); return vset_v_u8m1_u8m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m4( // CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vset_v_u8m2_u8m4(vuint8m4_t dest, vuint8m2_t val) { vuint8m4_t test_vset_v_u8m2_u8m4(vuint8m4_t dest, vuint8m2_t val) {
return vset_v_u8m2_u8m4(dest, 1, val); return vset_v_u8m2_u8m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m1_u8m8(vuint8m8_t dest, vuint8m1_t val) { vuint8m8_t test_vset_v_u8m1_u8m8(vuint8m8_t dest, vuint8m1_t val) {
return vset_v_u8m1_u8m8(dest, 7, val); return vset_v_u8m1_u8m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m2_u8m8(vuint8m8_t dest, vuint8m2_t val) { vuint8m8_t test_vset_v_u8m2_u8m8(vuint8m8_t dest, vuint8m2_t val) {
return vset_v_u8m2_u8m8(dest, 2, val); return vset_v_u8m2_u8m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u8m4_u8m8( // CHECK-RV64-LABEL: @test_vset_v_u8m4_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vset_v_u8m4_u8m8(vuint8m8_t dest, vuint8m4_t val) { vuint8m8_t test_vset_v_u8m4_u8m8(vuint8m8_t dest, vuint8m4_t val) {
return vset_v_u8m4_u8m8(dest, 1, val); return vset_v_u8m4_u8m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m2( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vset_v_u16m1_u16m2(vuint16m2_t dest, vuint16m1_t val) { vuint16m2_t test_vset_v_u16m1_u16m2(vuint16m2_t dest, vuint16m1_t val) {
return vset_v_u16m1_u16m2(dest, 1, val); return vset_v_u16m1_u16m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m4( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vset_v_u16m1_u16m4(vuint16m4_t dest, vuint16m1_t val) { vuint16m4_t test_vset_v_u16m1_u16m4(vuint16m4_t dest, vuint16m1_t val) {
return vset_v_u16m1_u16m4(dest, 3, val); return vset_v_u16m1_u16m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m4( // CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vset_v_u16m2_u16m4(vuint16m4_t dest, vuint16m2_t val) { vuint16m4_t test_vset_v_u16m2_u16m4(vuint16m4_t dest, vuint16m2_t val) {
return vset_v_u16m2_u16m4(dest, 1, val); return vset_v_u16m2_u16m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m1_u16m8(vuint16m8_t dest, vuint16m1_t val) { vuint16m8_t test_vset_v_u16m1_u16m8(vuint16m8_t dest, vuint16m1_t val) {
return vset_v_u16m1_u16m8(dest, 7, val); return vset_v_u16m1_u16m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m2_u16m8(vuint16m8_t dest, vuint16m2_t val) { vuint16m8_t test_vset_v_u16m2_u16m8(vuint16m8_t dest, vuint16m2_t val) {
return vset_v_u16m2_u16m8(dest, 2, val); return vset_v_u16m2_u16m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u16m4_u16m8( // CHECK-RV64-LABEL: @test_vset_v_u16m4_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vset_v_u16m4_u16m8(vuint16m8_t dest, vuint16m4_t val) { vuint16m8_t test_vset_v_u16m4_u16m8(vuint16m8_t dest, vuint16m4_t val) {
return vset_v_u16m4_u16m8(dest, 1, val); return vset_v_u16m4_u16m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m2( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vset_v_u32m1_u32m2(vuint32m2_t dest, vuint32m1_t val) { vuint32m2_t test_vset_v_u32m1_u32m2(vuint32m2_t dest, vuint32m1_t val) {
return vset_v_u32m1_u32m2(dest, 1, val); return vset_v_u32m1_u32m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m4( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vset_v_u32m1_u32m4(vuint32m4_t dest, vuint32m1_t val) { vuint32m4_t test_vset_v_u32m1_u32m4(vuint32m4_t dest, vuint32m1_t val) {
return vset_v_u32m1_u32m4(dest, 3, val); return vset_v_u32m1_u32m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m4( // CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vset_v_u32m2_u32m4(vuint32m4_t dest, vuint32m2_t val) { vuint32m4_t test_vset_v_u32m2_u32m4(vuint32m4_t dest, vuint32m2_t val) {
return vset_v_u32m2_u32m4(dest, 1, val); return vset_v_u32m2_u32m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m1_u32m8(vuint32m8_t dest, vuint32m1_t val) { vuint32m8_t test_vset_v_u32m1_u32m8(vuint32m8_t dest, vuint32m1_t val) {
return vset_v_u32m1_u32m8(dest, 7, val); return vset_v_u32m1_u32m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m2_u32m8(vuint32m8_t dest, vuint32m2_t val) { vuint32m8_t test_vset_v_u32m2_u32m8(vuint32m8_t dest, vuint32m2_t val) {
return vset_v_u32m2_u32m8(dest, 2, val); return vset_v_u32m2_u32m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u32m4_u32m8( // CHECK-RV64-LABEL: @test_vset_v_u32m4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vset_v_u32m4_u32m8(vuint32m8_t dest, vuint32m4_t val) { vuint32m8_t test_vset_v_u32m4_u32m8(vuint32m8_t dest, vuint32m4_t val) {
return vset_v_u32m4_u32m8(dest, 1, val); return vset_v_u32m4_u32m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m2( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vset_v_u64m1_u64m2(vuint64m2_t dest, vuint64m1_t val) { vuint64m2_t test_vset_v_u64m1_u64m2(vuint64m2_t dest, vuint64m1_t val) {
return vset_v_u64m1_u64m2(dest, 1, val); return vset_v_u64m1_u64m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m4( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vset_v_u64m1_u64m4(vuint64m4_t dest, vuint64m1_t val) { vuint64m4_t test_vset_v_u64m1_u64m4(vuint64m4_t dest, vuint64m1_t val) {
return vset_v_u64m1_u64m4(dest, 3, val); return vset_v_u64m1_u64m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m4( // CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vset_v_u64m2_u64m4(vuint64m4_t dest, vuint64m2_t val) { vuint64m4_t test_vset_v_u64m2_u64m4(vuint64m4_t dest, vuint64m2_t val) {
return vset_v_u64m2_u64m4(dest, 1, val); return vset_v_u64m2_u64m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m1_u64m8(vuint64m8_t dest, vuint64m1_t val) { vuint64m8_t test_vset_v_u64m1_u64m8(vuint64m8_t dest, vuint64m1_t val) {
return vset_v_u64m1_u64m8(dest, 7, val); return vset_v_u64m1_u64m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m2_u64m8(vuint64m8_t dest, vuint64m2_t val) { vuint64m8_t test_vset_v_u64m2_u64m8(vuint64m8_t dest, vuint64m2_t val) {
return vset_v_u64m2_u64m8(dest, 2, val); return vset_v_u64m2_u64m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_u64m4_u64m8( // CHECK-RV64-LABEL: @test_vset_v_u64m4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vset_v_u64m4_u64m8(vuint64m8_t dest, vuint64m4_t val) { vuint64m8_t test_vset_v_u64m4_u64m8(vuint64m8_t dest, vuint64m4_t val) {
return vset_v_u64m4_u64m8(dest, 1, val); return vset_v_u64m4_u64m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m2( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vset_v_f32m1_f32m2(vfloat32m2_t dest, vfloat32m1_t val) { vfloat32m2_t test_vset_v_f32m1_f32m2(vfloat32m2_t dest, vfloat32m1_t val) {
return vset_v_f32m1_f32m2(dest, 1, val); return vset_v_f32m1_f32m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m4( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 6) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 6)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vset_v_f32m1_f32m4(vfloat32m4_t dest, vfloat32m1_t val) { vfloat32m4_t test_vset_v_f32m1_f32m4(vfloat32m4_t dest, vfloat32m1_t val) {
return vset_v_f32m1_f32m4(dest, 3, val); return vset_v_f32m1_f32m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m4( // CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vset_v_f32m2_f32m4(vfloat32m4_t dest, vfloat32m2_t val) { vfloat32m4_t test_vset_v_f32m2_f32m4(vfloat32m4_t dest, vfloat32m2_t val) {
return vset_v_f32m2_f32m4(dest, 1, val); return vset_v_f32m2_f32m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 14) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 14)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m1_f32m8(vfloat32m8_t dest, vfloat32m1_t val) { vfloat32m8_t test_vset_v_f32m1_f32m8(vfloat32m8_t dest, vfloat32m1_t val) {
return vset_v_f32m1_f32m8(dest, 7, val); return vset_v_f32m1_f32m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m2_f32m8(vfloat32m8_t dest, vfloat32m2_t val) { vfloat32m8_t test_vset_v_f32m2_f32m8(vfloat32m8_t dest, vfloat32m2_t val) {
return vset_v_f32m2_f32m8(dest, 2, val); return vset_v_f32m2_f32m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f32m4_f32m8( // CHECK-RV64-LABEL: @test_vset_v_f32m4_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 8 x float> [[VAL:%.*]], i64 8) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 8 x float> [[VAL:%.*]], i64 8)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vset_v_f32m4_f32m8(vfloat32m8_t dest, vfloat32m4_t val) { vfloat32m8_t test_vset_v_f32m4_f32m8(vfloat32m8_t dest, vfloat32m4_t val) {
return vset_v_f32m4_f32m8(dest, 1, val); return vset_v_f32m4_f32m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m2( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vset_v_f64m1_f64m2(vfloat64m2_t dest, vfloat64m1_t val) { vfloat64m2_t test_vset_v_f64m1_f64m2(vfloat64m2_t dest, vfloat64m1_t val) {
return vset_v_f64m1_f64m2(dest, 1, val); return vset_v_f64m1_f64m2(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m4( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vset_v_f64m1_f64m4(vfloat64m4_t dest, vfloat64m1_t val) { vfloat64m4_t test_vset_v_f64m1_f64m4(vfloat64m4_t dest, vfloat64m1_t val) {
return vset_v_f64m1_f64m4(dest, 3, val); return vset_v_f64m1_f64m4(dest, 3, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m4( // CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vset_v_f64m2_f64m4(vfloat64m4_t dest, vfloat64m2_t val) { vfloat64m4_t test_vset_v_f64m2_f64m4(vfloat64m4_t dest, vfloat64m2_t val) {
return vset_v_f64m2_f64m4(dest, 1, val); return vset_v_f64m2_f64m4(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 7) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 7)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m1_f64m8(vfloat64m8_t dest, vfloat64m1_t val) { vfloat64m8_t test_vset_v_f64m1_f64m8(vfloat64m8_t dest, vfloat64m1_t val) {
return vset_v_f64m1_f64m8(dest, 7, val); return vset_v_f64m1_f64m8(dest, 7, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, vfloat64m2_t val) { vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, vfloat64m2_t val) {
return vset_v_f64m2_f64m8(dest, 2, val); return vset_v_f64m2_f64m8(dest, 2, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f64m4_f64m8( // CHECK-RV64-LABEL: @test_vset_v_f64m4_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 4 x double> [[VAL:%.*]], i64 4) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 4 x double> [[VAL:%.*]], i64 4)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, vfloat64m4_t val) { vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, vfloat64m4_t val) {
return vset_v_f64m4_f64m8(dest, 1, val); return vset_v_f64m4_f64m8(dest, 1, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m2( // CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vset_v_f16m1_f16m2 (vfloat16m2_t dest, vfloat16m1_t val) { vfloat16m2_t test_vset_v_f16m1_f16m2 (vfloat16m2_t dest, vfloat16m1_t val) {
return vset_v_f16m1_f16m2(dest, 0, val); return vset_v_f16m1_f16m2(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m4( // CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vset_v_f16m1_f16m4 (vfloat16m4_t dest, vfloat16m1_t val) { vfloat16m4_t test_vset_v_f16m1_f16m4 (vfloat16m4_t dest, vfloat16m1_t val) {
return vset_v_f16m1_f16m4(dest, 0, val); return vset_v_f16m1_f16m4(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m4( // CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vset_v_f16m2_f16m4 (vfloat16m4_t dest, vfloat16m2_t val) { vfloat16m4_t test_vset_v_f16m2_f16m4 (vfloat16m4_t dest, vfloat16m2_t val) {
return vset_v_f16m2_f16m4(dest, 0, val); return vset_v_f16m2_f16m4(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m8( // CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vset_v_f16m1_f16m8 (vfloat16m8_t dest, vfloat16m1_t val) { vfloat16m8_t test_vset_v_f16m1_f16m8 (vfloat16m8_t dest, vfloat16m1_t val) {
return vset_v_f16m1_f16m8(dest, 0, val); return vset_v_f16m1_f16m8(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m8( // CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vset_v_f16m2_f16m8 (vfloat16m8_t dest, vfloat16m2_t val) { vfloat16m8_t test_vset_v_f16m2_f16m8 (vfloat16m8_t dest, vfloat16m2_t val) {
return vset_v_f16m2_f16m8(dest, 0, val); return vset_v_f16m2_f16m8(dest, 0, val);
} }
// CHECK-RV64-LABEL: @test_vset_v_f16m4_f16m8( // CHECK-RV64-LABEL: @test_vset_v_f16m4_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 16 x half> [[VAL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 16 x half> [[VAL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vset_v_f16m4_f16m8 (vfloat16m8_t dest, vfloat16m4_t val) { vfloat16m8_t test_vset_v_f16m4_f16m8 (vfloat16m8_t dest, vfloat16m4_t val) {
return vset_v_f16m4_f16m8(dest, 0, val); return vset_v_f16m4_f16m8(dest, 0, val);
} }

clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// continues to be a normal GNU vector type, with base Armv8-A PCS // continues to be a normal GNU vector type, with base Armv8-A PCS
// rules. // rules.
#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
#define N __ARM_FEATURE_SVE_BITS #define N __ARM_FEATURE_SVE_BITS
typedef int8_t vec_int8 __attribute__((vector_size(N / 8))); typedef int8_t vec_int8 __attribute__((vector_size(N / 8)));
// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> noundef %x) // CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> noundef %x)
// CHECK128-NEXT: entry: // CHECK128-NEXT: entry:
// CHECK128-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) // CHECK128-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
// CHECK128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[X:%.*]], i64 0) // CHECK128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[X:%.*]], i64 0)
// CHECK128-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i8> [[CASTSCALABLESVE]], i32 1) // CHECK128-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i8> [[CASTSCALABLESVE]], i32 1)
// CHECK128-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[TMP1]], i64 0) // CHECK128-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[TMP1]], i64 0)
// CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]] // CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]]
// CHECK-LABEL: define{{.*}} void @f2( // CHECK-LABEL: define{{.*}} void @f2(
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture noundef readonly %0) // CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture noundef readonly %0)
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]] // CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v[[#div(VBITS,8)]]i8(<vscale x 16 x i8> undef, <[[#div(VBITS,8)]] x i8> [[X]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v[[#div(VBITS,8)]]i8(<vscale x 16 x i8> undef, <[[#div(VBITS,8)]] x i8> [[X]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[TMP1]], <vscale x 16 x i8> [[CASTSCALABLESVE]], i32 1) // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[TMP1]], <vscale x 16 x i8> [[CASTSCALABLESVE]], i32 1)
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8(<vscale x 16 x i8> [[TMP2]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8(<vscale x 16 x i8> [[TMP2]], i64 0)
// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[CASTFIXEDSVE]], <[[#div(VBITS,8)]] x i8>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]] // CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[CASTFIXEDSVE]], <[[#div(VBITS,8)]] x i8>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
vec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); } vec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); }
#endif #endif
// Page 27, item 3. // Page 27, item 3.
#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
#define N __ARM_FEATURE_SVE_BITS #define N __ARM_FEATURE_SVE_BITS
typedef int8_t vec1 __attribute__((vector_size(N / 8))); typedef int8_t vec1 __attribute__((vector_size(N / 8)));
void f3(vec1); void f3(vec1);
typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N))); typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N)));
// CHECK128-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce) // CHECK128-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce)
// CHECK128-NEXT: entry: // CHECK128-NEXT: entry:
// CHECK128-NEXT: [[X:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0) // CHECK128-NEXT: [[X:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0)
// CHECK128-NEXT: call void @f3(<16 x i8> noundef [[X]]) [[ATTR5:#.*]] // CHECK128-NEXT: call void @f3(<16 x i8> noundef [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: ret void // CHECK128-NEXT: ret void
// CHECK-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce) // CHECK-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce)
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS,8)]] x i8>, align 16 // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS,8)]] x i8>, align 16
// CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0) // CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0)
// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[X]], <[[#div(VBITS,8)]] x i8>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6]] // CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[X]], <[[#div(VBITS,8)]] x i8>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6]]
// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] // CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// CHECK128-LABEL: declare void @f3(<16 x i8> noundef) // CHECK128-LABEL: declare void @f3(<16 x i8> noundef)
// CHECK-LABEL: declare void @f3( // CHECK-LABEL: declare void @f3(
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noundef) // CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noundef)
void g(vec2 x) { f3(x); } // OK void g(vec2 x) { f3(x); } // OK
#endif #endif

clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
// Page 27, item 1. // Page 27, item 1.
#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
#define N __ARM_FEATURE_SVE_BITS #define N __ARM_FEATURE_SVE_BITS
// CHECK-LABEL: define{{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj // CHECK-LABEL: define{{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj
// CHECK-SAME: [[#VBITS]] // CHECK-SAME: [[#VBITS]]
// CHECK-SAME: EES_(<vscale x 4 x i32> noundef %x.coerce, <vscale x 4 x i32> noundef %y.coerce) // CHECK-SAME: EES_(<vscale x 4 x i32> noundef %x.coerce, <vscale x 4 x i32> noundef %y.coerce)
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE:%.*]], i64 0) // CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE1:%.*]], i64 0) // CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE1:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <[[#div(VBITS, 32)]] x i32> [[Y]], [[X]] // CHECK-NEXT: [[ADD:%.*]] = add <[[#div(VBITS, 32)]] x i32> [[Y]], [[X]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v[[#div(VBITS, 32)]]i32(<vscale x 4 x i32> undef, <[[#div(VBITS, 32)]] x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v[[#div(VBITS, 32)]]i32(<vscale x 4 x i32> undef, <[[#div(VBITS, 32)]] x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
typedef svint32_t vec __attribute__((arm_sve_vector_bits(N))); typedef svint32_t vec __attribute__((arm_sve_vector_bits(N)));
auto f(vec x, vec y) { return x + y; } // Returns a vec. auto f(vec x, vec y) { return x + y; } // Returns a vec.
#endif #endif
// Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS // Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS
#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
#define N __ARM_FEATURE_SVE_BITS #define N __ARM_FEATURE_SVE_BITS
typedef int16_t vec1 __attribute__((vector_size(N / 8))); typedef int16_t vec1 __attribute__((vector_size(N / 8)));
void f(vec1); void f(vec1);
typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N))); typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N)));
// CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj // CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj
// CHECK-SAME: [[#VBITS]] // CHECK-SAME: [[#VBITS]]
// CHECK-SAME: EE(<vscale x 8 x i16> noundef %x.coerce) // CHECK-SAME: EE(<vscale x 8 x i16> noundef %x.coerce)
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0) // CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> noundef [[X]]) [[ATTR5:#.*]] // CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> noundef [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: ret void // CHECK128-NEXT: ret void
// CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16 // CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16
// CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.experimental.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0) // CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
// CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]] // CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]]
// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] // CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECKWIDE-NEXT: ret void // CHECKWIDE-NEXT: ret void
void g(vec2 x) { f(x); } // OK void g(vec2 x) { f(x); } // OK
#endif #endif

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c

Show All 33 Lines
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> undef, bfloat [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> undef, bfloat [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x bfloat> [[TMP0]], bfloat [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x bfloat> [[TMP0]], bfloat [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x bfloat> [[TMP1]], bfloat [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x bfloat> [[TMP1]], bfloat [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x bfloat> [[TMP2]], bfloat [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x bfloat> [[TMP2]], bfloat [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x bfloat> [[TMP3]], bfloat [[X4:%.*]], i64 4 // CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x bfloat> [[TMP3]], bfloat [[X4:%.*]], i64 4
// CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x bfloat> [[TMP4]], bfloat [[X5:%.*]], i64 5 // CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x bfloat> [[TMP4]], bfloat [[X5:%.*]], i64 5
// CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x bfloat> [[TMP5]], bfloat [[X6:%.*]], i64 6 // CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x bfloat> [[TMP5]], bfloat [[X6:%.*]], i64 6
// CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x bfloat> [[TMP6]], bfloat [[X7:%.*]], i64 7 // CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x bfloat> [[TMP6]], bfloat [[X7:%.*]], i64 7
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP7]], i64 0) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP8]], i64 0) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP8]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP9]] // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP9]]
// //
// CPP-CHECK-LABEL: @_Z18test_svdupq_n_bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16( // CPP-CHECK-LABEL: @_Z18test_svdupq_n_bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16u6__bf16(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> undef, bfloat [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> undef, bfloat [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x bfloat> [[TMP0]], bfloat [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x bfloat> [[TMP0]], bfloat [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x bfloat> [[TMP1]], bfloat [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x bfloat> [[TMP1]], bfloat [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x bfloat> [[TMP2]], bfloat [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x bfloat> [[TMP2]], bfloat [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x bfloat> [[TMP3]], bfloat [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x bfloat> [[TMP3]], bfloat [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x bfloat> [[TMP4]], bfloat [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x bfloat> [[TMP4]], bfloat [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x bfloat> [[TMP5]], bfloat [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x bfloat> [[TMP5]], bfloat [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x bfloat> [[TMP6]], bfloat [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x bfloat> [[TMP6]], bfloat [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP7]], i64 0) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP7]], i64 0)
// CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP8]], i64 0) // CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP8]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP9]] // CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP9]]
// //
svbfloat16_t test_svdupq_n_bf16(bfloat16_t x0, bfloat16_t x1, bfloat16_t x2, bfloat16_t x3, svbfloat16_t test_svdupq_n_bf16(bfloat16_t x0, bfloat16_t x1, bfloat16_t x2, bfloat16_t x3,
bfloat16_t x4, bfloat16_t x5, bfloat16_t x6, bfloat16_t x7) { bfloat16_t x4, bfloat16_t x5, bfloat16_t x6, bfloat16_t x7) {
// <assume other insertelement> // <assume other insertelement>
// expected-warning@+1 {{implicit declaration of function 'svdupq_n_bf16'}} // expected-warning@+1 {{implicit declaration of function 'svdupq_n_bf16'}}
return SVE_ACLE_FUNC(svdupq, _n, _bf16, )(x0, x1, x2, x3, x4, x5, x6, x7); return SVE_ACLE_FUNC(svdupq, _n, _bf16, )(x0, x1, x2, x3, x4, x5, x6, x7);
} }

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
// CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8 // CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8
// CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9 // CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9
// CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10 // CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10
// CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11 // CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11
// CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12 // CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12
// CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13 // CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13
// CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14 // CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14
// CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15 // CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15
// CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0) // CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]]
// //
// CPP-CHECK-LABEL: @_Z16test_svdupq_n_s8aaaaaaaaaaaaaaaa( // CPP-CHECK-LABEL: @_Z16test_svdupq_n_s8aaaaaaaaaaaaaaaa(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> undef, i8 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> undef, i8 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8 // CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8
// CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9 // CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9
// CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10 // CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10
// CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11 // CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11
// CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12 // CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12
// CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13 // CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13
// CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14 // CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14
// CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15 // CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15
// CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0) // CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]]
// //
svint8_t test_svdupq_n_s8(int8_t x0, int8_t x1, int8_t x2, int8_t x3, svint8_t test_svdupq_n_s8(int8_t x0, int8_t x1, int8_t x2, int8_t x3,
int8_t x4, int8_t x5, int8_t x6, int8_t x7, int8_t x4, int8_t x5, int8_t x6, int8_t x7,
int8_t x8, int8_t x9, int8_t x10, int8_t x11, int8_t x8, int8_t x9, int8_t x10, int8_t x11,
int8_t x12, int8_t x13, int8_t x14, int8_t x15) int8_t x12, int8_t x13, int8_t x14, int8_t x15)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_s8,)(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15); return SVE_ACLE_FUNC(svdupq,_n,_s8,)(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15);
} }
// CHECK-LABEL: @test_svdupq_n_s16( // CHECK-LABEL: @test_svdupq_n_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4 // CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4
// CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5 // CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5
// CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6 // CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6
// CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7 // CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_s16ssssssss( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_s16ssssssss(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0)
// CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0) // CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]]
// //
svint16_t test_svdupq_n_s16(int16_t x0, int16_t x1, int16_t x2, int16_t x3, svint16_t test_svdupq_n_s16(int16_t x0, int16_t x1, int16_t x2, int16_t x3,
int16_t x4, int16_t x5, int16_t x6, int16_t x7) int16_t x4, int16_t x5, int16_t x6, int16_t x7)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_s16,)(x0, x1, x2, x3, x4, x5, x6, x7); return SVE_ACLE_FUNC(svdupq,_n,_s16,)(x0, x1, x2, x3, x4, x5, x6, x7);
} }
// CHECK-LABEL: @test_svdupq_n_s32( // CHECK-LABEL: @test_svdupq_n_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0) // CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0)
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0) // CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_s32iiii( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_s32iiii(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0) // CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0)
// CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0) // CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]]
// //
svint32_t test_svdupq_n_s32(int32_t x0, int32_t x1, int32_t x2, int32_t x3) svint32_t test_svdupq_n_s32(int32_t x0, int32_t x1, int32_t x2, int32_t x3)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_s32,)(x0, x1, x2, x3); return SVE_ACLE_FUNC(svdupq,_n,_s32,)(x0, x1, x2, x3);
} }
// CHECK-LABEL: @test_svdupq_n_s64( // CHECK-LABEL: @test_svdupq_n_s64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0) // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0)
// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_s64ll( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_s64ll(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0) // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0)
// CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]]
// //
svint64_t test_svdupq_n_s64(int64_t x0, int64_t x1) svint64_t test_svdupq_n_s64(int64_t x0, int64_t x1)
{ {
return SVE_ACLE_FUNC(svdupq,_n,_s64,)(x0, x1); return SVE_ACLE_FUNC(svdupq,_n,_s64,)(x0, x1);
} }
Show All 10 Lines
// CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8 // CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8
// CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9 // CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9
// CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10 // CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10
// CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11 // CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11
// CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12 // CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12
// CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13 // CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13
// CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14 // CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14
// CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15 // CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15
// CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0) // CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]]
// //
// CPP-CHECK-LABEL: @_Z16test_svdupq_n_u8hhhhhhhhhhhhhhhh( // CPP-CHECK-LABEL: @_Z16test_svdupq_n_u8hhhhhhhhhhhhhhhh(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> undef, i8 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> undef, i8 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8 // CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[X8:%.*]], i64 8
// CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9 // CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[X9:%.*]], i64 9
// CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10 // CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[X10:%.*]], i64 10
// CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11 // CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[X11:%.*]], i64 11
// CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12 // CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[X12:%.*]], i64 12
// CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13 // CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[X13:%.*]], i64 13
// CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14 // CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[X14:%.*]], i64 14
// CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15 // CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[X15:%.*]], i64 15
// CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0) // CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP16]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP17]]
// //
svuint8_t test_svdupq_n_u8(uint8_t x0, uint8_t x1, uint8_t x2, uint8_t x3, svuint8_t test_svdupq_n_u8(uint8_t x0, uint8_t x1, uint8_t x2, uint8_t x3,
uint8_t x4, uint8_t x5, uint8_t x6, uint8_t x7, uint8_t x4, uint8_t x5, uint8_t x6, uint8_t x7,
uint8_t x8, uint8_t x9, uint8_t x10, uint8_t x11, uint8_t x8, uint8_t x9, uint8_t x10, uint8_t x11,
uint8_t x12, uint8_t x13, uint8_t x14, uint8_t x15) uint8_t x12, uint8_t x13, uint8_t x14, uint8_t x15)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_u8,)(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15); return SVE_ACLE_FUNC(svdupq,_n,_u8,)(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15);
} }
// CHECK-LABEL: @test_svdupq_n_u16( // CHECK-LABEL: @test_svdupq_n_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4 // CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4
// CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5 // CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5
// CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6 // CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6
// CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7 // CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_u16tttttttt( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_u16tttttttt(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> undef, i16 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP7]], i64 0)
// CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0) // CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP8]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP9]]
// //
svuint16_t test_svdupq_n_u16(uint16_t x0, uint16_t x1, uint16_t x2, uint16_t x3, svuint16_t test_svdupq_n_u16(uint16_t x0, uint16_t x1, uint16_t x2, uint16_t x3,
uint16_t x4, uint16_t x5, uint16_t x6, uint16_t x7) uint16_t x4, uint16_t x5, uint16_t x6, uint16_t x7)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_u16,)(x0, x1, x2, x3, x4, x5, x6, x7); return SVE_ACLE_FUNC(svdupq,_n,_u16,)(x0, x1, x2, x3, x4, x5, x6, x7);
} }
// CHECK-LABEL: @test_svdupq_n_u32( // CHECK-LABEL: @test_svdupq_n_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0) // CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0)
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0) // CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_u32jjjj( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_u32jjjj(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0) // CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP3]], i64 0)
// CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0) // CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP5]]
// //
svuint32_t test_svdupq_n_u32(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3) svuint32_t test_svdupq_n_u32(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_u32,)(x0, x1, x2, x3); return SVE_ACLE_FUNC(svdupq,_n,_u32,)(x0, x1, x2, x3);
} }
// CHECK-LABEL: @test_svdupq_n_u64( // CHECK-LABEL: @test_svdupq_n_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0) // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0)
// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_u64mm( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_u64mm(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0) // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP1]], i64 0)
// CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP3]]
// //
svuint64_t test_svdupq_n_u64(uint64_t x0, uint64_t x1) svuint64_t test_svdupq_n_u64(uint64_t x0, uint64_t x1)
{ {
return SVE_ACLE_FUNC(svdupq,_n,_u64,)(x0, x1); return SVE_ACLE_FUNC(svdupq,_n,_u64,)(x0, x1);
} }
// CHECK-LABEL: @test_svdupq_n_f16( // CHECK-LABEL: @test_svdupq_n_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x half> undef, half [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x half> undef, half [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half [[X4:%.*]], i64 4 // CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half [[X4:%.*]], i64 4
// CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half [[X5:%.*]], i64 5 // CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half [[X5:%.*]], i64 5
// CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half [[X6:%.*]], i64 6 // CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half [[X6:%.*]], i64 6
// CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half [[X7:%.*]], i64 7 // CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half [[X7:%.*]], i64 7
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[TMP7]], i64 0) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP8]], i64 0) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP8]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP9]] // CHECK-NEXT: ret <vscale x 8 x half> [[TMP9]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_f16DhDhDhDhDhDhDhDh( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_f16DhDhDhDhDhDhDhDh(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x half> undef, half [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x half> undef, half [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half [[X4:%.*]], i64 4 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half [[X4:%.*]], i64 4
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half [[X5:%.*]], i64 5 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half [[X5:%.*]], i64 5
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half [[X6:%.*]], i64 6 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half [[X6:%.*]], i64 6
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half [[X7:%.*]], i64 7 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half [[X7:%.*]], i64 7
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[TMP7]], i64 0) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[TMP7]], i64 0)
// CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP8]], i64 0) // CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP8]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP9]] // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP9]]
// //
svfloat16_t test_svdupq_n_f16(float16_t x0, float16_t x1, float16_t x2, float16_t x3, svfloat16_t test_svdupq_n_f16(float16_t x0, float16_t x1, float16_t x2, float16_t x3,
float16_t x4, float16_t x5, float16_t x6, float16_t x7) float16_t x4, float16_t x5, float16_t x6, float16_t x7)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_f16,)(x0, x1, x2, x3, x4, x5, x6, x7); return SVE_ACLE_FUNC(svdupq,_n,_f16,)(x0, x1, x2, x3, x4, x5, x6, x7);
} }
// CHECK-LABEL: @test_svdupq_n_f32( // CHECK-LABEL: @test_svdupq_n_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> undef, float [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> undef, float [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[X2:%.*]], i64 2 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[X2:%.*]], i64 2
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[X3:%.*]], i64 3 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[X3:%.*]], i64 3
// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[TMP3]], i64 0) // CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[TMP3]], i64 0)
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP4]], i64 0) // CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP4]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP5]] // CHECK-NEXT: ret <vscale x 4 x float> [[TMP5]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_f32ffff( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_f32ffff(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> undef, float [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> undef, float [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[X2:%.*]], i64 2 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[X2:%.*]], i64 2
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[X3:%.*]], i64 3 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[X3:%.*]], i64 3
// CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[TMP3]], i64 0) // CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[TMP3]], i64 0)
// CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP4]], i64 0) // CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP4]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP5]] // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP5]]
// //
svfloat32_t test_svdupq_n_f32(float32_t x0, float32_t x1, float32_t x2, float32_t x3) svfloat32_t test_svdupq_n_f32(float32_t x0, float32_t x1, float32_t x2, float32_t x3)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_f32,)(x0, x1, x2, x3); return SVE_ACLE_FUNC(svdupq,_n,_f32,)(x0, x1, x2, x3);
} }
// CHECK-LABEL: @test_svdupq_n_f64( // CHECK-LABEL: @test_svdupq_n_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> undef, double [[X0:%.*]], i64 0 // CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> undef, double [[X0:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X1:%.*]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X1:%.*]], i64 1
// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP1]], i64 0) // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP1]], i64 0)
// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP2]], i64 0) // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP2]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP3]] // CHECK-NEXT: ret <vscale x 2 x double> [[TMP3]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_f64dd( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_f64dd(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> undef, double [[X0:%.*]], i64 0 // CPP-CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> undef, double [[X0:%.*]], i64 0
// CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X1:%.*]], i64 1 // CPP-CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X1:%.*]], i64 1
// CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP1]], i64 0) // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP1]], i64 0)
// CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP2]], i64 0) // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP2]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP3]] // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP3]]
// //
svfloat64_t test_svdupq_n_f64(float64_t x0, float64_t x1) svfloat64_t test_svdupq_n_f64(float64_t x0, float64_t x1)
{ {
return SVE_ACLE_FUNC(svdupq,_n,_f64,)(x0, x1); return SVE_ACLE_FUNC(svdupq,_n,_f64,)(x0, x1);
} }
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// CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[FROMBOOL9]], i64 9 // CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[FROMBOOL9]], i64 9
// CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[FROMBOOL10]], i64 10 // CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[FROMBOOL10]], i64 10
// CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[FROMBOOL11]], i64 11 // CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[FROMBOOL11]], i64 11
// CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[FROMBOOL12]], i64 12 // CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[FROMBOOL12]], i64 12
// CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[FROMBOOL13]], i64 13 // CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[FROMBOOL13]], i64 13
// CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[FROMBOOL14]], i64 14 // CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[FROMBOOL14]], i64 14
// CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[FROMBOOL15]], i64 15 // CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[FROMBOOL15]], i64 15
// CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) // CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
// CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP17]], i64 0) // CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP17]], i64 0)
// CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[TMP18]], <vscale x 2 x i64> zeroinitializer) // CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[TMP18]], <vscale x 2 x i64> zeroinitializer)
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP19]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP19]]
// //
// CPP-CHECK-LABEL: @_Z16test_svdupq_n_b8bbbbbbbbbbbbbbbb( // CPP-CHECK-LABEL: @_Z16test_svdupq_n_b8bbbbbbbbbbbbbbbb(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[X0:%.*]] to i8 // CPP-CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[X0:%.*]] to i8
// CPP-CHECK-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[X1:%.*]] to i8 // CPP-CHECK-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[X1:%.*]] to i8
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// CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[FROMBOOL9]], i64 9 // CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[FROMBOOL9]], i64 9
// CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[FROMBOOL10]], i64 10 // CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[FROMBOOL10]], i64 10
// CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[FROMBOOL11]], i64 11 // CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[FROMBOOL11]], i64 11
// CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[FROMBOOL12]], i64 12 // CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[FROMBOOL12]], i64 12
// CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[FROMBOOL13]], i64 13 // CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[FROMBOOL13]], i64 13
// CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[FROMBOOL14]], i64 14 // CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[FROMBOOL14]], i64 14
// CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[FROMBOOL15]], i64 15 // CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[FROMBOOL15]], i64 15
// CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) // CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
// CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0) // CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[TMP15]], i64 0)
// CPP-CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP17]], i64 0) // CPP-CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP17]], i64 0)
// CPP-CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[TMP18]], <vscale x 2 x i64> zeroinitializer) // CPP-CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[TMP18]], <vscale x 2 x i64> zeroinitializer)
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP19]] // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP19]]
// //
svbool_t test_svdupq_n_b8(bool x0, bool x1, bool x2, bool x3, svbool_t test_svdupq_n_b8(bool x0, bool x1, bool x2, bool x3,
bool x4, bool x5, bool x6, bool x7, bool x4, bool x5, bool x6, bool x7,
bool x8, bool x9, bool x10, bool x11, bool x8, bool x9, bool x10, bool x11,
bool x12, bool x13, bool x14, bool x15) bool x12, bool x13, bool x14, bool x15)
Show All 16 Lines
// CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[TMP1]], i64 1 // CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[TMP1]], i64 1
// CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP2]], i64 2 // CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP2]], i64 2
// CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP10]], i16 [[TMP3]], i64 3 // CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP10]], i16 [[TMP3]], i64 3
// CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[TMP4]], i64 4 // CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[TMP4]], i64 4
// CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[TMP5]], i64 5 // CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[TMP5]], i64 5
// CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[TMP6]], i64 6 // CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[TMP6]], i64 6
// CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[TMP7]], i64 7 // CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[TMP7]], i64 7
// CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) // CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
// CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP15]], i64 0) // CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP15]], i64 0)
// CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP17]], i64 0) // CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP17]], i64 0)
// CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> [[TMP16]], <vscale x 8 x i16> [[TMP18]], <vscale x 2 x i64> zeroinitializer) // CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> [[TMP16]], <vscale x 8 x i16> [[TMP18]], <vscale x 2 x i64> zeroinitializer)
// CHECK-NEXT: [[TMP20:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP19]]) // CHECK-NEXT: [[TMP20:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP19]])
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP20]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP20]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_b16bbbbbbbb( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_b16bbbbbbbb(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[X4:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[X4:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[X5:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[X5:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[X6:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[X6:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP7:%.*]] = zext i1 [[X7:%.*]] to i16 // CPP-CHECK-NEXT: [[TMP7:%.*]] = zext i1 [[X7:%.*]] to i16
// CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i16> undef, i16 [[TMP0]], i64 0 // CPP-CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i16> undef, i16 [[TMP0]], i64 0
// CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[TMP1]], i64 1 // CPP-CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[TMP1]], i64 1
// CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP2]], i64 2 // CPP-CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP2]], i64 2
// CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP10]], i16 [[TMP3]], i64 3 // CPP-CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP10]], i16 [[TMP3]], i64 3
// CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[TMP4]], i64 4 // CPP-CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[TMP4]], i64 4
// CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[TMP5]], i64 5 // CPP-CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[TMP5]], i64 5
// CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[TMP6]], i64 6 // CPP-CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[TMP6]], i64 6
// CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[TMP7]], i64 7 // CPP-CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[TMP7]], i64 7
// CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) // CPP-CHECK-NEXT: [[TMP16:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
// CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP15]], i64 0) // CPP-CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[TMP15]], i64 0)
// CPP-CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP17]], i64 0) // CPP-CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP17]], i64 0)
// CPP-CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> [[TMP16]], <vscale x 8 x i16> [[TMP18]], <vscale x 2 x i64> zeroinitializer) // CPP-CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> [[TMP16]], <vscale x 8 x i16> [[TMP18]], <vscale x 2 x i64> zeroinitializer)
// CPP-CHECK-NEXT: [[TMP20:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP19]]) // CPP-CHECK-NEXT: [[TMP20:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP19]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP20]] // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP20]]
// //
svbool_t test_svdupq_n_b16(bool x0, bool x1, bool x2, bool x3, svbool_t test_svdupq_n_b16(bool x0, bool x1, bool x2, bool x3,
bool x4, bool x5, bool x6, bool x7) bool x4, bool x5, bool x6, bool x7)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_b16,)(x0, x1, x2, x3, x4, x5, x6, x7); return SVE_ACLE_FUNC(svdupq,_n,_b16,)(x0, x1, x2, x3, x4, x5, x6, x7);
} }
// CHECK-LABEL: @test_svdupq_n_b32( // CHECK-LABEL: @test_svdupq_n_b32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i32 // CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i32
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i32
// CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> undef, i32 [[TMP0]], i64 0 // CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> undef, i32 [[TMP0]], i64 0
// CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i64 1 // CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i64 1
// CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP2]], i64 2 // CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP2]], i64 2
// CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP3]], i64 3 // CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP3]], i64 3
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP7]], i64 0) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP9]], i64 0) // CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP9]], i64 0)
// CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> [[TMP8]], <vscale x 4 x i32> [[TMP10]], <vscale x 2 x i64> zeroinitializer) // CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> [[TMP8]], <vscale x 4 x i32> [[TMP10]], <vscale x 2 x i64> zeroinitializer)
// CHECK-NEXT: [[TMP12:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP11]]) // CHECK-NEXT: [[TMP12:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP11]])
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP12]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP12]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_b32bbbb( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_b32bbbb(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i32 // CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i32
// CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i32 // CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i32
// CPP-CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i32 // CPP-CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[X2:%.*]] to i32
// CPP-CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i32 // CPP-CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[X3:%.*]] to i32
// CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> undef, i32 [[TMP0]], i64 0 // CPP-CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> undef, i32 [[TMP0]], i64 0
// CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i64 1 // CPP-CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i64 1
// CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP2]], i64 2 // CPP-CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP2]], i64 2
// CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP3]], i64 3 // CPP-CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP3]], i64 3
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
// CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP7]], i64 0) // CPP-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[TMP7]], i64 0)
// CPP-CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP9]], i64 0) // CPP-CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP9]], i64 0)
// CPP-CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> [[TMP8]], <vscale x 4 x i32> [[TMP10]], <vscale x 2 x i64> zeroinitializer) // CPP-CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> [[TMP8]], <vscale x 4 x i32> [[TMP10]], <vscale x 2 x i64> zeroinitializer)
// CPP-CHECK-NEXT: [[TMP12:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP11]]) // CPP-CHECK-NEXT: [[TMP12:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP11]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP12]] // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP12]]
// //
svbool_t test_svdupq_n_b32(bool x0, bool x1, bool x2, bool x3) svbool_t test_svdupq_n_b32(bool x0, bool x1, bool x2, bool x3)
{ {
// <assume other insertelement> // <assume other insertelement>
return SVE_ACLE_FUNC(svdupq,_n,_b32,)(x0, x1, x2, x3); return SVE_ACLE_FUNC(svdupq,_n,_b32,)(x0, x1, x2, x3);
} }
// CHECK-LABEL: @test_svdupq_n_b64( // CHECK-LABEL: @test_svdupq_n_b64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i64 // CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i64
// CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i64 // CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i64
// CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> undef, i64 [[TMP0]], i64 0 // CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> undef, i64 [[TMP0]], i64 0
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[TMP1]], i64 1 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[TMP1]], i64 1
// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) // CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP3]], i64 0) // CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP3]], i64 0)
// CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0) // CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0)
// CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> zeroinitializer) // CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> zeroinitializer)
// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP7]]) // CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP7]])
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP8]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP8]]
// //
// CPP-CHECK-LABEL: @_Z17test_svdupq_n_b64bb( // CPP-CHECK-LABEL: @_Z17test_svdupq_n_b64bb(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i64 // CPP-CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[X0:%.*]] to i64
// CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i64 // CPP-CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[X1:%.*]] to i64
// CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> undef, i64 [[TMP0]], i64 0 // CPP-CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> undef, i64 [[TMP0]], i64 0
// CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[TMP1]], i64 1 // CPP-CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[TMP1]], i64 1
// CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) // CPP-CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
// CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP3]], i64 0) // CPP-CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP3]], i64 0)
// CPP-CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0) // CPP-CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0)
// CPP-CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> zeroinitializer) // CPP-CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> [[TMP4]], <vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> zeroinitializer)
// CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP7]]) // CPP-CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP7]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP8]] // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP8]]
// //
svbool_t test_svdupq_n_b64(bool x0, bool x1) svbool_t test_svdupq_n_b64(bool x0, bool x1)
{ {
return SVE_ACLE_FUNC(svdupq,_n,_b64,)(x0, x1); return SVE_ACLE_FUNC(svdupq,_n,_b64,)(x0, x1);
} }

clang/test/CodeGen/aarch64-sve-vls-arith-ops.c

Show All 23 Lines
typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
// ADDITION // ADDITION
// CHECK-LABEL: @add_i8( // CHECK-LABEL: @add_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t add_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t add_i8(fixed_int8_t a, fixed_int8_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_i16( // CHECK-LABEL: @add_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t add_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t add_i16(fixed_int16_t a, fixed_int16_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_i32( // CHECK-LABEL: @add_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t add_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t add_i32(fixed_int32_t a, fixed_int32_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_i64( // CHECK-LABEL: @add_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t add_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t add_i64(fixed_int64_t a, fixed_int64_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_u8( // CHECK-LABEL: @add_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t add_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t add_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_u16( // CHECK-LABEL: @add_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t add_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t add_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_u32( // CHECK-LABEL: @add_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t add_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t add_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_u64( // CHECK-LABEL: @add_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t add_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t add_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_f16( // CHECK-LABEL: @add_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[ADD:%.*]] = fadd <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[ADD:%.*]] = fadd <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[ADD]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[ADD]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t add_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t add_f16(fixed_float16_t a, fixed_float16_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_f32( // CHECK-LABEL: @add_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t add_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t add_f32(fixed_float32_t a, fixed_float32_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_f64( // CHECK-LABEL: @add_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t add_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t add_f64(fixed_float64_t a, fixed_float64_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_inplace_i8( // CHECK-LABEL: @add_inplace_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t add_inplace_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t add_inplace_i8(fixed_int8_t a, fixed_int8_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_i16( // CHECK-LABEL: @add_inplace_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t add_inplace_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t add_inplace_i16(fixed_int16_t a, fixed_int16_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_i32( // CHECK-LABEL: @add_inplace_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t add_inplace_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t add_inplace_i32(fixed_int32_t a, fixed_int32_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_i64( // CHECK-LABEL: @add_inplace_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t add_inplace_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t add_inplace_i64(fixed_int64_t a, fixed_int64_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_u8( // CHECK-LABEL: @add_inplace_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t add_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t add_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_u16( // CHECK-LABEL: @add_inplace_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t add_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t add_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_u32( // CHECK-LABEL: @add_inplace_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t add_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t add_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_u64( // CHECK-LABEL: @add_inplace_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t add_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t add_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_f16( // CHECK-LABEL: @add_inplace_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[ADD:%.*]] = fadd <32 x float> [[CONV2]], [[CONV]] // CHECK-NEXT: [[ADD:%.*]] = fadd <32 x float> [[CONV2]], [[CONV]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[ADD]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[ADD]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t add_inplace_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t add_inplace_f16(fixed_float16_t a, fixed_float16_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_f32( // CHECK-LABEL: @add_inplace_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t add_inplace_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t add_inplace_f32(fixed_float32_t a, fixed_float32_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_inplace_f64( // CHECK-LABEL: @add_inplace_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[B]] // CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t add_inplace_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t add_inplace_f64(fixed_float64_t a, fixed_float64_t b) {
return a += b; return a += b;
} }
// CHECK-LABEL: @add_scalar_i8( // CHECK-LABEL: @add_scalar_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t add_scalar_i8(fixed_int8_t a, int8_t b) { fixed_int8_t add_scalar_i8(fixed_int8_t a, int8_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_i16( // CHECK-LABEL: @add_scalar_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t add_scalar_i16(fixed_int16_t a, int16_t b) { fixed_int16_t add_scalar_i16(fixed_int16_t a, int16_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_i32( // CHECK-LABEL: @add_scalar_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t add_scalar_i32(fixed_int32_t a, int32_t b) { fixed_int32_t add_scalar_i32(fixed_int32_t a, int32_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_i64( // CHECK-LABEL: @add_scalar_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t add_scalar_i64(fixed_int64_t a, int64_t b) { fixed_int64_t add_scalar_i64(fixed_int64_t a, int64_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_u8( // CHECK-LABEL: @add_scalar_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t add_scalar_u8(fixed_uint8_t a, uint8_t b) { fixed_uint8_t add_scalar_u8(fixed_uint8_t a, uint8_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_u16( // CHECK-LABEL: @add_scalar_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t add_scalar_u16(fixed_uint16_t a, uint16_t b) { fixed_uint16_t add_scalar_u16(fixed_uint16_t a, uint16_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_u32( // CHECK-LABEL: @add_scalar_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t add_scalar_u32(fixed_uint32_t a, uint32_t b) { fixed_uint32_t add_scalar_u32(fixed_uint32_t a, uint32_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_u64( // CHECK-LABEL: @add_scalar_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t add_scalar_u64(fixed_uint64_t a, uint64_t b) { fixed_uint64_t add_scalar_u64(fixed_uint64_t a, uint64_t b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_f16( // CHECK-LABEL: @add_scalar_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = fadd <32 x half> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = fadd <32 x half> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t add_scalar_f16(fixed_float16_t a, __fp16 b) { fixed_float16_t add_scalar_f16(fixed_float16_t a, __fp16 b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_f32( // CHECK-LABEL: @add_scalar_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t add_scalar_f32(fixed_float32_t a, float b) { fixed_float32_t add_scalar_f32(fixed_float32_t a, float b) {
return a + b; return a + b;
} }
// CHECK-LABEL: @add_scalar_f64( // CHECK-LABEL: @add_scalar_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[ADD:%.*]] = fadd <8 x double> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[ADD]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t add_scalar_f64(fixed_float64_t a, double b) { fixed_float64_t add_scalar_f64(fixed_float64_t a, double b) {
return a + b; return a + b;
} }
// SUBTRACTION // SUBTRACTION
// CHECK-LABEL: @sub_i8( // CHECK-LABEL: @sub_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t sub_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t sub_i8(fixed_int8_t a, fixed_int8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_i16( // CHECK-LABEL: @sub_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t sub_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t sub_i16(fixed_int16_t a, fixed_int16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_i32( // CHECK-LABEL: @sub_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t sub_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t sub_i32(fixed_int32_t a, fixed_int32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_i64( // CHECK-LABEL: @sub_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t sub_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t sub_i64(fixed_int64_t a, fixed_int64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_u8( // CHECK-LABEL: @sub_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t sub_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t sub_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_u16( // CHECK-LABEL: @sub_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t sub_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t sub_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_u32( // CHECK-LABEL: @sub_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t sub_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t sub_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_u64( // CHECK-LABEL: @sub_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t sub_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t sub_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_f16( // CHECK-LABEL: @sub_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[SUB:%.*]] = fsub <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[SUB:%.*]] = fsub <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[SUB]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[SUB]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t sub_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t sub_f16(fixed_float16_t a, fixed_float16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_f32( // CHECK-LABEL: @sub_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t sub_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t sub_f32(fixed_float32_t a, fixed_float32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_f64( // CHECK-LABEL: @sub_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t sub_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t sub_f64(fixed_float64_t a, fixed_float64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_i8( // CHECK-LABEL: @sub_inplace_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t sub_inplace_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t sub_inplace_i8(fixed_int8_t a, fixed_int8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_i16( // CHECK-LABEL: @sub_inplace_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t sub_inplace_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t sub_inplace_i16(fixed_int16_t a, fixed_int16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_i32( // CHECK-LABEL: @sub_inplace_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t sub_inplace_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t sub_inplace_i32(fixed_int32_t a, fixed_int32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_i64( // CHECK-LABEL: @sub_inplace_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t sub_inplace_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t sub_inplace_i64(fixed_int64_t a, fixed_int64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_u8( // CHECK-LABEL: @sub_inplace_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t sub_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t sub_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_u16( // CHECK-LABEL: @sub_inplace_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t sub_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t sub_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_u32( // CHECK-LABEL: @sub_inplace_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t sub_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t sub_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_u64( // CHECK-LABEL: @sub_inplace_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t sub_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t sub_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_f16( // CHECK-LABEL: @sub_inplace_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[SUB:%.*]] = fsub <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[SUB:%.*]] = fsub <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[SUB]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[SUB]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t sub_inplace_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t sub_inplace_f16(fixed_float16_t a, fixed_float16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_f32( // CHECK-LABEL: @sub_inplace_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t sub_inplace_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t sub_inplace_f32(fixed_float32_t a, fixed_float32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_inplace_f64( // CHECK-LABEL: @sub_inplace_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[B]] // CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t sub_inplace_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t sub_inplace_f64(fixed_float64_t a, fixed_float64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_i8( // CHECK-LABEL: @sub_scalar_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t sub_scalar_i8(fixed_int8_t a, int8_t b) { fixed_int8_t sub_scalar_i8(fixed_int8_t a, int8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_i16( // CHECK-LABEL: @sub_scalar_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t sub_scalar_i16(fixed_int16_t a, int16_t b) { fixed_int16_t sub_scalar_i16(fixed_int16_t a, int16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_i32( // CHECK-LABEL: @sub_scalar_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t sub_scalar_i32(fixed_int32_t a, int32_t b) { fixed_int32_t sub_scalar_i32(fixed_int32_t a, int32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_i64( // CHECK-LABEL: @sub_scalar_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t sub_scalar_i64(fixed_int64_t a, int64_t b) { fixed_int64_t sub_scalar_i64(fixed_int64_t a, int64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_u8( // CHECK-LABEL: @sub_scalar_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t sub_scalar_u8(fixed_uint8_t a, uint8_t b) { fixed_uint8_t sub_scalar_u8(fixed_uint8_t a, uint8_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_u16( // CHECK-LABEL: @sub_scalar_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t sub_scalar_u16(fixed_uint16_t a, uint16_t b) { fixed_uint16_t sub_scalar_u16(fixed_uint16_t a, uint16_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_u32( // CHECK-LABEL: @sub_scalar_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t sub_scalar_u32(fixed_uint32_t a, uint32_t b) { fixed_uint32_t sub_scalar_u32(fixed_uint32_t a, uint32_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_u64( // CHECK-LABEL: @sub_scalar_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = sub <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t sub_scalar_u64(fixed_uint64_t a, uint64_t b) { fixed_uint64_t sub_scalar_u64(fixed_uint64_t a, uint64_t b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_f16( // CHECK-LABEL: @sub_scalar_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = fsub <32 x half> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = fsub <32 x half> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t sub_scalar_f16(fixed_float16_t a, __fp16 b) { fixed_float16_t sub_scalar_f16(fixed_float16_t a, __fp16 b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_f32( // CHECK-LABEL: @sub_scalar_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = fsub <16 x float> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t sub_scalar_f32(fixed_float32_t a, float b) { fixed_float32_t sub_scalar_f32(fixed_float32_t a, float b) {
return a - b; return a - b;
} }
// CHECK-LABEL: @sub_scalar_f64( // CHECK-LABEL: @sub_scalar_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SUB:%.*]] = fsub <8 x double> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[SUB]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t sub_scalar_f64(fixed_float64_t a, double b) { fixed_float64_t sub_scalar_f64(fixed_float64_t a, double b) {
return a - b; return a - b;
} }
// MULTIPLICATION // MULTIPLICATION
// CHECK-LABEL: @mul_i8( // CHECK-LABEL: @mul_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t mul_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t mul_i8(fixed_int8_t a, fixed_int8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_i16( // CHECK-LABEL: @mul_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t mul_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t mul_i16(fixed_int16_t a, fixed_int16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_i32( // CHECK-LABEL: @mul_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t mul_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t mul_i32(fixed_int32_t a, fixed_int32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_i64( // CHECK-LABEL: @mul_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t mul_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t mul_i64(fixed_int64_t a, fixed_int64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_u8( // CHECK-LABEL: @mul_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t mul_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t mul_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_u16( // CHECK-LABEL: @mul_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t mul_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t mul_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_u32( // CHECK-LABEL: @mul_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t mul_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t mul_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_u64( // CHECK-LABEL: @mul_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t mul_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t mul_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_f16( // CHECK-LABEL: @mul_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[MUL:%.*]] = fmul <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[MUL:%.*]] = fmul <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[MUL]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[MUL]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t mul_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t mul_f16(fixed_float16_t a, fixed_float16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_f32( // CHECK-LABEL: @mul_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t mul_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t mul_f32(fixed_float32_t a, fixed_float32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_f64( // CHECK-LABEL: @mul_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t mul_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t mul_f64(fixed_float64_t a, fixed_float64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_i8( // CHECK-LABEL: @mul_inplace_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t mul_inplace_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t mul_inplace_i8(fixed_int8_t a, fixed_int8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_i16( // CHECK-LABEL: @mul_inplace_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t mul_inplace_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t mul_inplace_i16(fixed_int16_t a, fixed_int16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_i32( // CHECK-LABEL: @mul_inplace_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t mul_inplace_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t mul_inplace_i32(fixed_int32_t a, fixed_int32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_i64( // CHECK-LABEL: @mul_inplace_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t mul_inplace_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t mul_inplace_i64(fixed_int64_t a, fixed_int64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_u8( // CHECK-LABEL: @mul_inplace_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t mul_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t mul_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_u16( // CHECK-LABEL: @mul_inplace_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t mul_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t mul_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_u32( // CHECK-LABEL: @mul_inplace_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t mul_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t mul_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_u64( // CHECK-LABEL: @mul_inplace_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t mul_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t mul_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_f16( // CHECK-LABEL: @mul_inplace_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[MUL:%.*]] = fmul <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[MUL:%.*]] = fmul <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[MUL]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[MUL]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t mul_inplace_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t mul_inplace_f16(fixed_float16_t a, fixed_float16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_f32( // CHECK-LABEL: @mul_inplace_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t mul_inplace_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t mul_inplace_f32(fixed_float32_t a, fixed_float32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_inplace_f64( // CHECK-LABEL: @mul_inplace_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[B]] // CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t mul_inplace_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t mul_inplace_f64(fixed_float64_t a, fixed_float64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_i8( // CHECK-LABEL: @mul_scalar_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t mul_scalar_i8(fixed_int8_t a, int8_t b) { fixed_int8_t mul_scalar_i8(fixed_int8_t a, int8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_i16( // CHECK-LABEL: @mul_scalar_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t mul_scalar_i16(fixed_int16_t a, int16_t b) { fixed_int16_t mul_scalar_i16(fixed_int16_t a, int16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_i32( // CHECK-LABEL: @mul_scalar_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t mul_scalar_i32(fixed_int32_t a, int32_t b) { fixed_int32_t mul_scalar_i32(fixed_int32_t a, int32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_i64( // CHECK-LABEL: @mul_scalar_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t mul_scalar_i64(fixed_int64_t a, int64_t b) { fixed_int64_t mul_scalar_i64(fixed_int64_t a, int64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_u8( // CHECK-LABEL: @mul_scalar_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t mul_scalar_u8(fixed_uint8_t a, uint8_t b) { fixed_uint8_t mul_scalar_u8(fixed_uint8_t a, uint8_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_u16( // CHECK-LABEL: @mul_scalar_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t mul_scalar_u16(fixed_uint16_t a, uint16_t b) { fixed_uint16_t mul_scalar_u16(fixed_uint16_t a, uint16_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_u32( // CHECK-LABEL: @mul_scalar_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t mul_scalar_u32(fixed_uint32_t a, uint32_t b) { fixed_uint32_t mul_scalar_u32(fixed_uint32_t a, uint32_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_u64( // CHECK-LABEL: @mul_scalar_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = mul <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t mul_scalar_u64(fixed_uint64_t a, uint64_t b) { fixed_uint64_t mul_scalar_u64(fixed_uint64_t a, uint64_t b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_f16( // CHECK-LABEL: @mul_scalar_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = fmul <32 x half> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = fmul <32 x half> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t mul_scalar_f16(fixed_float16_t a, __fp16 b) { fixed_float16_t mul_scalar_f16(fixed_float16_t a, __fp16 b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_f32( // CHECK-LABEL: @mul_scalar_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = fmul <16 x float> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t mul_scalar_f32(fixed_float32_t a, float b) { fixed_float32_t mul_scalar_f32(fixed_float32_t a, float b) {
return a * b; return a * b;
} }
// CHECK-LABEL: @mul_scalar_f64( // CHECK-LABEL: @mul_scalar_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[MUL:%.*]] = fmul <8 x double> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[MUL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t mul_scalar_f64(fixed_float64_t a, double b) { fixed_float64_t mul_scalar_f64(fixed_float64_t a, double b) {
return a * b; return a * b;
} }
// DIVISION // DIVISION
// CHECK-LABEL: @div_i8( // CHECK-LABEL: @div_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t div_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t div_i8(fixed_int8_t a, fixed_int8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_i16( // CHECK-LABEL: @div_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t div_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t div_i16(fixed_int16_t a, fixed_int16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_i32( // CHECK-LABEL: @div_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t div_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t div_i32(fixed_int32_t a, fixed_int32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_i64( // CHECK-LABEL: @div_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t div_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t div_i64(fixed_int64_t a, fixed_int64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_u8( // CHECK-LABEL: @div_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t div_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t div_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_u16( // CHECK-LABEL: @div_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t div_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t div_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_u32( // CHECK-LABEL: @div_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t div_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t div_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_u64( // CHECK-LABEL: @div_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t div_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t div_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_f16( // CHECK-LABEL: @div_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[DIV]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[DIV]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t div_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t div_f16(fixed_float16_t a, fixed_float16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_f32( // CHECK-LABEL: @div_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t div_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t div_f32(fixed_float32_t a, fixed_float32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_f64( // CHECK-LABEL: @div_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t div_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t div_f64(fixed_float64_t a, fixed_float64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_i8( // CHECK-LABEL: @div_inplace_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t div_inplace_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t div_inplace_i8(fixed_int8_t a, fixed_int8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_i16( // CHECK-LABEL: @div_inplace_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t div_inplace_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t div_inplace_i16(fixed_int16_t a, fixed_int16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_i32( // CHECK-LABEL: @div_inplace_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t div_inplace_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t div_inplace_i32(fixed_int32_t a, fixed_int32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_i64( // CHECK-LABEL: @div_inplace_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t div_inplace_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t div_inplace_i64(fixed_int64_t a, fixed_int64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_u8( // CHECK-LABEL: @div_inplace_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t div_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t div_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_u16( // CHECK-LABEL: @div_inplace_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t div_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t div_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_u32( // CHECK-LABEL: @div_inplace_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t div_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t div_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_u64( // CHECK-LABEL: @div_inplace_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t div_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t div_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_f16( // CHECK-LABEL: @div_inplace_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[DIV]] to <32 x half> // CHECK-NEXT: [[CONV3:%.*]] = fptrunc <32 x float> [[DIV]] to <32 x half>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t div_inplace_f16(fixed_float16_t a, fixed_float16_t b) { fixed_float16_t div_inplace_f16(fixed_float16_t a, fixed_float16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_f32( // CHECK-LABEL: @div_inplace_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t div_inplace_f32(fixed_float32_t a, fixed_float32_t b) { fixed_float32_t div_inplace_f32(fixed_float32_t a, fixed_float32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_inplace_f64( // CHECK-LABEL: @div_inplace_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[B]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t div_inplace_f64(fixed_float64_t a, fixed_float64_t b) { fixed_float64_t div_inplace_f64(fixed_float64_t a, fixed_float64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_i8( // CHECK-LABEL: @div_scalar_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t div_scalar_i8(fixed_int8_t a, int8_t b) { fixed_int8_t div_scalar_i8(fixed_int8_t a, int8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_i16( // CHECK-LABEL: @div_scalar_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t div_scalar_i16(fixed_int16_t a, int16_t b) { fixed_int16_t div_scalar_i16(fixed_int16_t a, int16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_i32( // CHECK-LABEL: @div_scalar_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t div_scalar_i32(fixed_int32_t a, int32_t b) { fixed_int32_t div_scalar_i32(fixed_int32_t a, int32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_i64( // CHECK-LABEL: @div_scalar_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = sdiv <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t div_scalar_i64(fixed_int64_t a, int64_t b) { fixed_int64_t div_scalar_i64(fixed_int64_t a, int64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_u8( // CHECK-LABEL: @div_scalar_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = udiv <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t div_scalar_u8(fixed_uint8_t a, uint8_t b) { fixed_uint8_t div_scalar_u8(fixed_uint8_t a, uint8_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_u16( // CHECK-LABEL: @div_scalar_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = udiv <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t div_scalar_u16(fixed_uint16_t a, uint16_t b) { fixed_uint16_t div_scalar_u16(fixed_uint16_t a, uint16_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_u32( // CHECK-LABEL: @div_scalar_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = udiv <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t div_scalar_u32(fixed_uint32_t a, uint32_t b) { fixed_uint32_t div_scalar_u32(fixed_uint32_t a, uint32_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_u64( // CHECK-LABEL: @div_scalar_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = udiv <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t div_scalar_u64(fixed_uint64_t a, uint64_t b) { fixed_uint64_t div_scalar_u64(fixed_uint64_t a, uint64_t b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_f16( // CHECK-LABEL: @div_scalar_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x half> poison, half [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x half> [[SPLAT_SPLATINSERT]], <32 x half> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x half> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <32 x half> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v32f16(<vscale x 8 x half> undef, <32 x half> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x half> [[CASTSCALABLESVE]]
// //
fixed_float16_t div_scalar_f16(fixed_float16_t a, __fp16 b) { fixed_float16_t div_scalar_f16(fixed_float16_t a, __fp16 b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_f32( // CHECK-LABEL: @div_scalar_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x float> [[SPLAT_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <16 x float> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v16f32(<vscale x 4 x float> undef, <16 x float> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x float> [[CASTSCALABLESVE]]
// //
fixed_float32_t div_scalar_f32(fixed_float32_t a, float b) { fixed_float32_t div_scalar_f32(fixed_float32_t a, float b) {
return a / b; return a / b;
} }
// CHECK-LABEL: @div_scalar_f64( // CHECK-LABEL: @div_scalar_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x double> poison, double [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x double> [[SPLAT_SPLATINSERT]], <8 x double> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[DIV:%.*]] = fdiv <8 x double> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[DIV]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
fixed_float64_t div_scalar_f64(fixed_float64_t a, double b) { fixed_float64_t div_scalar_f64(fixed_float64_t a, double b) {
return a / b; return a / b;
} }
// REMAINDER // REMAINDER
// CHECK-LABEL: @rem_i8( // CHECK-LABEL: @rem_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rem_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t rem_i8(fixed_int8_t a, fixed_int8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_i16( // CHECK-LABEL: @rem_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rem_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t rem_i16(fixed_int16_t a, fixed_int16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_i32( // CHECK-LABEL: @rem_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rem_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t rem_i32(fixed_int32_t a, fixed_int32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_i64( // CHECK-LABEL: @rem_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rem_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t rem_i64(fixed_int64_t a, fixed_int64_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_u8( // CHECK-LABEL: @rem_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rem_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t rem_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_u16( // CHECK-LABEL: @rem_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rem_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t rem_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_u32( // CHECK-LABEL: @rem_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rem_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t rem_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_u64( // CHECK-LABEL: @rem_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rem_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t rem_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_i8( // CHECK-LABEL: @rem_inplace_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rem_inplace_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t rem_inplace_i8(fixed_int8_t a, fixed_int8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_i16( // CHECK-LABEL: @rem_inplace_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rem_inplace_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t rem_inplace_i16(fixed_int16_t a, fixed_int16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_i32( // CHECK-LABEL: @rem_inplace_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rem_inplace_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t rem_inplace_i32(fixed_int32_t a, fixed_int32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_i64( // CHECK-LABEL: @rem_inplace_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rem_inplace_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t rem_inplace_i64(fixed_int64_t a, fixed_int64_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_u8( // CHECK-LABEL: @rem_inplace_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rem_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t rem_inplace_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_u16( // CHECK-LABEL: @rem_inplace_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rem_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t rem_inplace_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_u32( // CHECK-LABEL: @rem_inplace_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rem_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t rem_inplace_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_inplace_u64( // CHECK-LABEL: @rem_inplace_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rem_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t rem_inplace_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_i8( // CHECK-LABEL: @rem_scalar_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = srem <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rem_scalar_i8(fixed_int8_t a, int8_t b) { fixed_int8_t rem_scalar_i8(fixed_int8_t a, int8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_i16( // CHECK-LABEL: @rem_scalar_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = srem <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rem_scalar_i16(fixed_int16_t a, int16_t b) { fixed_int16_t rem_scalar_i16(fixed_int16_t a, int16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_i32( // CHECK-LABEL: @rem_scalar_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = srem <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rem_scalar_i32(fixed_int32_t a, int32_t b) { fixed_int32_t rem_scalar_i32(fixed_int32_t a, int32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_i64( // CHECK-LABEL: @rem_scalar_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = srem <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rem_scalar_i64(fixed_int64_t a, int64_t b) { fixed_int64_t rem_scalar_i64(fixed_int64_t a, int64_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_u8( // CHECK-LABEL: @rem_scalar_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = urem <64 x i8> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rem_scalar_u8(fixed_uint8_t a, uint8_t b) { fixed_uint8_t rem_scalar_u8(fixed_uint8_t a, uint8_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_u16( // CHECK-LABEL: @rem_scalar_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = urem <32 x i16> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rem_scalar_u16(fixed_uint16_t a, uint16_t b) { fixed_uint16_t rem_scalar_u16(fixed_uint16_t a, uint16_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_u32( // CHECK-LABEL: @rem_scalar_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = urem <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rem_scalar_u32(fixed_uint32_t a, uint32_t b) { fixed_uint32_t rem_scalar_u32(fixed_uint32_t a, uint32_t b) {
return a % b; return a % b;
} }
// CHECK-LABEL: @rem_scalar_u64( // CHECK-LABEL: @rem_scalar_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[REM:%.*]] = urem <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[REM]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rem_scalar_u64(fixed_uint64_t a, uint64_t b) { fixed_uint64_t rem_scalar_u64(fixed_uint64_t a, uint64_t b) {
return a % b; return a % b;
} }

clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c

Show All 24 Lines
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
// AND // AND
// CHECK-LABEL: @and_bool( // CHECK-LABEL: @and_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[AND]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t and_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t and_bool(fixed_bool_t a, fixed_bool_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_i8( // CHECK-LABEL: @and_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t and_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t and_i8(fixed_int8_t a, fixed_int8_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_i16( // CHECK-LABEL: @and_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t and_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t and_i16(fixed_int16_t a, fixed_int16_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_i32( // CHECK-LABEL: @and_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t and_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t and_i32(fixed_int32_t a, fixed_int32_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_i64( // CHECK-LABEL: @and_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t and_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t and_i64(fixed_int64_t a, fixed_int64_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_u8( // CHECK-LABEL: @and_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t and_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t and_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_u16( // CHECK-LABEL: @and_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t and_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t and_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_u32( // CHECK-LABEL: @and_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t and_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t and_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a & b; return a & b;
} }
// CHECK-LABEL: @and_u64( // CHECK-LABEL: @and_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[AND:%.*]] = and <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[AND:%.*]] = and <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[AND]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[AND]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t and_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t and_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a & b; return a & b;
} }
// OR // OR
// CHECK-LABEL: @or_bool( // CHECK-LABEL: @or_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[OR]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t or_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t or_bool(fixed_bool_t a, fixed_bool_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_i8( // CHECK-LABEL: @or_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t or_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t or_i8(fixed_int8_t a, fixed_int8_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_i16( // CHECK-LABEL: @or_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t or_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t or_i16(fixed_int16_t a, fixed_int16_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_i32( // CHECK-LABEL: @or_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t or_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t or_i32(fixed_int32_t a, fixed_int32_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_i64( // CHECK-LABEL: @or_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t or_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t or_i64(fixed_int64_t a, fixed_int64_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_u8( // CHECK-LABEL: @or_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t or_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t or_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_u16( // CHECK-LABEL: @or_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t or_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t or_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_u32( // CHECK-LABEL: @or_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t or_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t or_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a | b; return a | b;
} }
// CHECK-LABEL: @or_u64( // CHECK-LABEL: @or_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[OR:%.*]] = or <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[OR:%.*]] = or <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[OR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[OR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t or_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t or_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a | b; return a | b;
} }
// XOR // XOR
// CHECK-LABEL: @xor_bool( // CHECK-LABEL: @xor_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[XOR]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t xor_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t xor_bool(fixed_bool_t a, fixed_bool_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_i8( // CHECK-LABEL: @xor_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t xor_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t xor_i8(fixed_int8_t a, fixed_int8_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_i16( // CHECK-LABEL: @xor_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t xor_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t xor_i16(fixed_int16_t a, fixed_int16_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_i32( // CHECK-LABEL: @xor_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t xor_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t xor_i32(fixed_int32_t a, fixed_int32_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_i64( // CHECK-LABEL: @xor_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t xor_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t xor_i64(fixed_int64_t a, fixed_int64_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_u8( // CHECK-LABEL: @xor_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t xor_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t xor_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_u16( // CHECK-LABEL: @xor_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t xor_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t xor_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_u32( // CHECK-LABEL: @xor_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t xor_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t xor_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a ^ b; return a ^ b;
} }
// CHECK-LABEL: @xor_u64( // CHECK-LABEL: @xor_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[XOR:%.*]] = xor <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[XOR:%.*]] = xor <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[XOR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[XOR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t xor_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t xor_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a ^ b; return a ^ b;
} }
// NEG // NEG
// CHECK-LABEL: @neg_bool( // CHECK-LABEL: @neg_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <8 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <8 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[NEG]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
fixed_bool_t neg_bool(fixed_bool_t a) { fixed_bool_t neg_bool(fixed_bool_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_i8( // CHECK-LABEL: @neg_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t neg_i8(fixed_int8_t a) { fixed_int8_t neg_i8(fixed_int8_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_i16( // CHECK-LABEL: @neg_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t neg_i16(fixed_int16_t a) { fixed_int16_t neg_i16(fixed_int16_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_i32( // CHECK-LABEL: @neg_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t neg_i32(fixed_int32_t a) { fixed_int32_t neg_i32(fixed_int32_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_i64( // CHECK-LABEL: @neg_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t neg_i64(fixed_int64_t a) { fixed_int64_t neg_i64(fixed_int64_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_u8( // CHECK-LABEL: @neg_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t neg_u8(fixed_uint8_t a) { fixed_uint8_t neg_u8(fixed_uint8_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_u16( // CHECK-LABEL: @neg_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t neg_u16(fixed_uint16_t a) { fixed_uint16_t neg_u16(fixed_uint16_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_u32( // CHECK-LABEL: @neg_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t neg_u32(fixed_uint32_t a) { fixed_uint32_t neg_u32(fixed_uint32_t a) {
return ~a; return ~a;
} }
// CHECK-LABEL: @neg_u64( // CHECK-LABEL: @neg_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NEG:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> // CHECK-NEXT: [[NEG:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NEG]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NEG]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t neg_u64(fixed_uint64_t a) { fixed_uint64_t neg_u64(fixed_uint64_t a) {
return ~a; return ~a;
} }

clang/test/CodeGen/aarch64-sve-vls-compare-ops.c

Show All 24 Lines
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
// EQ // EQ
// CHECK-LABEL: @eq_bool( // CHECK-LABEL: @eq_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t eq_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t eq_bool(fixed_bool_t a, fixed_bool_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_i8( // CHECK-LABEL: @eq_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t eq_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t eq_i8(fixed_int8_t a, fixed_int8_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_i16( // CHECK-LABEL: @eq_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t eq_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t eq_i16(fixed_int16_t a, fixed_int16_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_i32( // CHECK-LABEL: @eq_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t eq_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t eq_i32(fixed_int32_t a, fixed_int32_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_i64( // CHECK-LABEL: @eq_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t eq_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t eq_i64(fixed_int64_t a, fixed_int64_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_u8( // CHECK-LABEL: @eq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t eq_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t eq_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_u16( // CHECK-LABEL: @eq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t eq_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t eq_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_u32( // CHECK-LABEL: @eq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t eq_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t eq_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_u64( // CHECK-LABEL: @eq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t eq_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t eq_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_f16( // CHECK-LABEL: @eq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t eq_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t eq_f16(fixed_float16_t a, fixed_float16_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_f32( // CHECK-LABEL: @eq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t eq_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t eq_f32(fixed_float32_t a, fixed_float32_t b) {
return a == b; return a == b;
} }
// CHECK-LABEL: @eq_f64( // CHECK-LABEL: @eq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t eq_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t eq_f64(fixed_float64_t a, fixed_float64_t b) {
return a == b; return a == b;
} }
// NEQ // NEQ
// CHECK-LABEL: @neq_bool( // CHECK-LABEL: @neq_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t neq_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t neq_bool(fixed_bool_t a, fixed_bool_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_i8( // CHECK-LABEL: @neq_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t neq_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t neq_i8(fixed_int8_t a, fixed_int8_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_i16( // CHECK-LABEL: @neq_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t neq_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t neq_i16(fixed_int16_t a, fixed_int16_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_i32( // CHECK-LABEL: @neq_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t neq_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t neq_i32(fixed_int32_t a, fixed_int32_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_i64( // CHECK-LABEL: @neq_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t neq_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t neq_i64(fixed_int64_t a, fixed_int64_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_u8( // CHECK-LABEL: @neq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t neq_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t neq_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_u16( // CHECK-LABEL: @neq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t neq_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t neq_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_u32( // CHECK-LABEL: @neq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t neq_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t neq_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_u64( // CHECK-LABEL: @neq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t neq_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t neq_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_f16( // CHECK-LABEL: @neq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp une <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp une <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t neq_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t neq_f16(fixed_float16_t a, fixed_float16_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_f32( // CHECK-LABEL: @neq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp une <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp une <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t neq_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t neq_f32(fixed_float32_t a, fixed_float32_t b) {
return a != b; return a != b;
} }
// CHECK-LABEL: @neq_f64( // CHECK-LABEL: @neq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp une <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp une <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t neq_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t neq_f64(fixed_float64_t a, fixed_float64_t b) {
return a != b; return a != b;
} }
// LT // LT
// CHECK-LABEL: @lt_bool( // CHECK-LABEL: @lt_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t lt_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t lt_bool(fixed_bool_t a, fixed_bool_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_i8( // CHECK-LABEL: @lt_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp slt <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp slt <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t lt_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t lt_i8(fixed_int8_t a, fixed_int8_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_i16( // CHECK-LABEL: @lt_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp slt <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp slt <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lt_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t lt_i16(fixed_int16_t a, fixed_int16_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_i32( // CHECK-LABEL: @lt_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp slt <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp slt <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lt_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t lt_i32(fixed_int32_t a, fixed_int32_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_i64( // CHECK-LABEL: @lt_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lt_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t lt_i64(fixed_int64_t a, fixed_int64_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_u8( // CHECK-LABEL: @lt_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ult <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t lt_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t lt_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_u16( // CHECK-LABEL: @lt_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ult <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lt_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t lt_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_u32( // CHECK-LABEL: @lt_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ult <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lt_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t lt_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_u64( // CHECK-LABEL: @lt_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lt_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t lt_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_f16( // CHECK-LABEL: @lt_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lt_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t lt_f16(fixed_float16_t a, fixed_float16_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_f32( // CHECK-LABEL: @lt_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lt_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t lt_f32(fixed_float32_t a, fixed_float32_t b) {
return a < b; return a < b;
} }
// CHECK-LABEL: @lt_f64( // CHECK-LABEL: @lt_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lt_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t lt_f64(fixed_float64_t a, fixed_float64_t b) {
return a < b; return a < b;
} }
// LEQ // LEQ
// CHECK-LABEL: @leq_bool( // CHECK-LABEL: @leq_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t leq_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t leq_bool(fixed_bool_t a, fixed_bool_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_i8( // CHECK-LABEL: @leq_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sle <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sle <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t leq_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t leq_i8(fixed_int8_t a, fixed_int8_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_i16( // CHECK-LABEL: @leq_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sle <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sle <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t leq_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t leq_i16(fixed_int16_t a, fixed_int16_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_i32( // CHECK-LABEL: @leq_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sle <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sle <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t leq_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t leq_i32(fixed_int32_t a, fixed_int32_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_i64( // CHECK-LABEL: @leq_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sle <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sle <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t leq_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t leq_i64(fixed_int64_t a, fixed_int64_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_u8( // CHECK-LABEL: @leq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ule <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ule <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t leq_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t leq_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_u16( // CHECK-LABEL: @leq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ule <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ule <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t leq_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t leq_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_u32( // CHECK-LABEL: @leq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ule <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ule <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t leq_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t leq_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_u64( // CHECK-LABEL: @leq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t leq_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t leq_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_f16( // CHECK-LABEL: @leq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp ole <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t leq_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t leq_f16(fixed_float16_t a, fixed_float16_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_f32( // CHECK-LABEL: @leq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp ole <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t leq_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t leq_f32(fixed_float32_t a, fixed_float32_t b) {
return a <= b; return a <= b;
} }
// CHECK-LABEL: @leq_f64( // CHECK-LABEL: @leq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp ole <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t leq_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t leq_f64(fixed_float64_t a, fixed_float64_t b) {
return a <= b; return a <= b;
} }
// GT // GT
// CHECK-LABEL: @gt_bool( // CHECK-LABEL: @gt_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t gt_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t gt_bool(fixed_bool_t a, fixed_bool_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_i8( // CHECK-LABEL: @gt_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sgt <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t gt_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t gt_i8(fixed_int8_t a, fixed_int8_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_i16( // CHECK-LABEL: @gt_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sgt <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t gt_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t gt_i16(fixed_int16_t a, fixed_int16_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_i32( // CHECK-LABEL: @gt_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sgt <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t gt_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t gt_i32(fixed_int32_t a, fixed_int32_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_i64( // CHECK-LABEL: @gt_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t gt_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t gt_i64(fixed_int64_t a, fixed_int64_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_u8( // CHECK-LABEL: @gt_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ugt <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t gt_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t gt_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_u16( // CHECK-LABEL: @gt_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ugt <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t gt_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t gt_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_u32( // CHECK-LABEL: @gt_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ugt <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t gt_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t gt_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_u64( // CHECK-LABEL: @gt_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t gt_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t gt_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_f16( // CHECK-LABEL: @gt_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t gt_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t gt_f16(fixed_float16_t a, fixed_float16_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_f32( // CHECK-LABEL: @gt_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t gt_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t gt_f32(fixed_float32_t a, fixed_float32_t b) {
return a > b; return a > b;
} }
// CHECK-LABEL: @gt_f64( // CHECK-LABEL: @gt_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t gt_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t gt_f64(fixed_float64_t a, fixed_float64_t b) {
return a > b; return a > b;
} }
// GEQ // GEQ
// CHECK-LABEL: @geq_bool( // CHECK-LABEL: @geq_bool(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
// //
fixed_bool_t geq_bool(fixed_bool_t a, fixed_bool_t b) { fixed_bool_t geq_bool(fixed_bool_t a, fixed_bool_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_i8( // CHECK-LABEL: @geq_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sge <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sge <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t geq_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t geq_i8(fixed_int8_t a, fixed_int8_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_i16( // CHECK-LABEL: @geq_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sge <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sge <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t geq_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t geq_i16(fixed_int16_t a, fixed_int16_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_i32( // CHECK-LABEL: @geq_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sge <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sge <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t geq_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t geq_i32(fixed_int32_t a, fixed_int32_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_i64( // CHECK-LABEL: @geq_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp sge <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp sge <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t geq_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t geq_i64(fixed_int64_t a, fixed_int64_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_u8( // CHECK-LABEL: @geq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp uge <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp uge <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t geq_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_int8_t geq_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_u16( // CHECK-LABEL: @geq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp uge <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp uge <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t geq_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_int16_t geq_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_u32( // CHECK-LABEL: @geq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp uge <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp uge <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t geq_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_int32_t geq_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_u64( // CHECK-LABEL: @geq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t geq_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_int64_t geq_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_f16( // CHECK-LABEL: @geq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float>
// CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float>
// CHECK-NEXT: [[CMP:%.*]] = fcmp oge <32 x float> [[CONV]], [[CONV2]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <32 x float> [[CONV]], [[CONV2]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32>
// CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t geq_f16(fixed_float16_t a, fixed_float16_t b) { fixed_int16_t geq_f16(fixed_float16_t a, fixed_float16_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_f32( // CHECK-LABEL: @geq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp oge <16 x float> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <16 x float> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t geq_f32(fixed_float32_t a, fixed_float32_t b) { fixed_int32_t geq_f32(fixed_float32_t a, fixed_float32_t b) {
return a >= b; return a >= b;
} }
// CHECK-LABEL: @geq_f64( // CHECK-LABEL: @geq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CMP:%.*]] = fcmp oge <8 x double> [[A]], [[B]] // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <8 x double> [[A]], [[B]]
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64>
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t geq_f64(fixed_float64_t a, fixed_float64_t b) { fixed_int64_t geq_f64(fixed_float64_t a, fixed_float64_t b) {
return a >= b; return a >= b;
} }

clang/test/CodeGen/aarch64-sve-vls-shift-ops.c

Show All 21 Lines
typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
// CHECK-LABEL: @lshift_i8( // CHECK-LABEL: @lshift_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t lshift_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t lshift_i8(fixed_int8_t a, fixed_int8_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_i8( // CHECK-LABEL: @rshift_i8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rshift_i8(fixed_int8_t a, fixed_int8_t b) { fixed_int8_t rshift_i8(fixed_int8_t a, fixed_int8_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_u8( // CHECK-LABEL: @lshift_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t lshift_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t lshift_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_u8( // CHECK-LABEL: @rshift_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rshift_u8(fixed_uint8_t a, fixed_uint8_t b) { fixed_uint8_t rshift_u8(fixed_uint8_t a, fixed_uint8_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_i16( // CHECK-LABEL: @lshift_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lshift_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t lshift_i16(fixed_int16_t a, fixed_int16_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_i16( // CHECK-LABEL: @rshift_i16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rshift_i16(fixed_int16_t a, fixed_int16_t b) { fixed_int16_t rshift_i16(fixed_int16_t a, fixed_int16_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_u16( // CHECK-LABEL: @lshift_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t lshift_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t lshift_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_u16( // CHECK-LABEL: @rshift_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rshift_u16(fixed_uint16_t a, fixed_uint16_t b) { fixed_uint16_t rshift_u16(fixed_uint16_t a, fixed_uint16_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_i32( // CHECK-LABEL: @lshift_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lshift_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t lshift_i32(fixed_int32_t a, fixed_int32_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_i32( // CHECK-LABEL: @rshift_i32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rshift_i32(fixed_int32_t a, fixed_int32_t b) { fixed_int32_t rshift_i32(fixed_int32_t a, fixed_int32_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_u32( // CHECK-LABEL: @lshift_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t lshift_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t lshift_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_u32( // CHECK-LABEL: @rshift_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rshift_u32(fixed_uint32_t a, fixed_uint32_t b) { fixed_uint32_t rshift_u32(fixed_uint32_t a, fixed_uint32_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_i64( // CHECK-LABEL: @lshift_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lshift_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t lshift_i64(fixed_int64_t a, fixed_int64_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_i64( // CHECK-LABEL: @rshift_i64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rshift_i64(fixed_int64_t a, fixed_int64_t b) { fixed_int64_t rshift_i64(fixed_int64_t a, fixed_int64_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_u64( // CHECK-LABEL: @lshift_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t lshift_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t lshift_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @rshift_u64( // CHECK-LABEL: @rshift_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[A]], [[B]] // CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[A]], [[B]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rshift_u64(fixed_uint64_t a, fixed_uint64_t b) { fixed_uint64_t rshift_u64(fixed_uint64_t a, fixed_uint64_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @lshift_i8_rsplat( // CHECK-LABEL: @lshift_i8_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = sext i8 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8>
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t lshift_i8_rsplat(fixed_int8_t a, int8_t b) { fixed_int8_t lshift_i8_rsplat(fixed_int8_t a, int8_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_i8_lsplat( // CHECK-LABEL: @lshift_i8_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t lshift_i8_lsplat(fixed_int8_t a, int8_t b) { fixed_int8_t lshift_i8_lsplat(fixed_int8_t a, int8_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_i8_rsplat( // CHECK-LABEL: @rshift_i8_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = sext i8 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8>
// CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rshift_i8_rsplat(fixed_int8_t a, int8_t b) { fixed_int8_t rshift_i8_rsplat(fixed_int8_t a, int8_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_i8_lsplat( // CHECK-LABEL: @rshift_i8_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = ashr <64 x i8> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_int8_t rshift_i8_lsplat(fixed_int8_t a, int8_t b) { fixed_int8_t rshift_i8_lsplat(fixed_int8_t a, int8_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_u8_rsplat( // CHECK-LABEL: @lshift_u8_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = zext i8 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8>
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t lshift_u8_rsplat(fixed_uint8_t a, uint8_t b) { fixed_uint8_t lshift_u8_rsplat(fixed_uint8_t a, uint8_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_u8_lsplat( // CHECK-LABEL: @lshift_u8_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <64 x i8> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t lshift_u8_lsplat(fixed_uint8_t a, uint8_t b) { fixed_uint8_t lshift_u8_lsplat(fixed_uint8_t a, uint8_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_u8_rsplat( // CHECK-LABEL: @rshift_u8_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = zext i8 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i32> [[SPLAT_SPLATINSERT]], <64 x i32> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <64 x i32> [[SPLAT_SPLAT]] to <64 x i8>
// CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rshift_u8_rsplat(fixed_uint8_t a, uint8_t b) { fixed_uint8_t rshift_u8_rsplat(fixed_uint8_t a, uint8_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_u8_lsplat( // CHECK-LABEL: @rshift_u8_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.experimental.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <64 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <64 x i8> [[SPLAT_SPLATINSERT]], <64 x i8> poison, <64 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = lshr <64 x i8> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]]
// //
fixed_uint8_t rshift_u8_lsplat(fixed_uint8_t a, uint8_t b) { fixed_uint8_t rshift_u8_lsplat(fixed_uint8_t a, uint8_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_i16_rsplat( // CHECK-LABEL: @lshift_i16_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = sext i16 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = sext i16 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16>
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lshift_i16_rsplat(fixed_int16_t a, int16_t b) { fixed_int16_t lshift_i16_rsplat(fixed_int16_t a, int16_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_i16_lsplat( // CHECK-LABEL: @lshift_i16_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t lshift_i16_lsplat(fixed_int16_t a, int16_t b) { fixed_int16_t lshift_i16_lsplat(fixed_int16_t a, int16_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_i16_rsplat( // CHECK-LABEL: @rshift_i16_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = sext i16 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = sext i16 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16>
// CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rshift_i16_rsplat(fixed_int16_t a, int16_t b) { fixed_int16_t rshift_i16_rsplat(fixed_int16_t a, int16_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_i16_lsplat( // CHECK-LABEL: @rshift_i16_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = ashr <32 x i16> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_int16_t rshift_i16_lsplat(fixed_int16_t a, int16_t b) { fixed_int16_t rshift_i16_lsplat(fixed_int16_t a, int16_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_u16_rsplat( // CHECK-LABEL: @lshift_u16_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = zext i16 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16>
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t lshift_u16_rsplat(fixed_uint16_t a, uint16_t b) { fixed_uint16_t lshift_u16_rsplat(fixed_uint16_t a, uint16_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_u16_lsplat( // CHECK-LABEL: @lshift_u16_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <32 x i16> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t lshift_u16_lsplat(fixed_uint16_t a, uint16_t b) { fixed_uint16_t lshift_u16_lsplat(fixed_uint16_t a, uint16_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_u16_rsplat( // CHECK-LABEL: @rshift_u16_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[B:%.*]] to i32 // CHECK-NEXT: [[CONV:%.*]] = zext i16 [[B:%.*]] to i32
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i32> poison, i32 [[CONV]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i32> [[SPLAT_SPLATINSERT]], <32 x i32> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16> // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <32 x i32> [[SPLAT_SPLAT]] to <32 x i16>
// CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[A]], [[SH_PROM]] // CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[A]], [[SH_PROM]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rshift_u16_rsplat(fixed_uint16_t a, uint16_t b) { fixed_uint16_t rshift_u16_rsplat(fixed_uint16_t a, uint16_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_u16_lsplat( // CHECK-LABEL: @rshift_u16_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <32 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <32 x i16> [[SPLAT_SPLATINSERT]], <32 x i16> poison, <32 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = lshr <32 x i16> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]]
// //
fixed_uint16_t rshift_u16_lsplat(fixed_uint16_t a, uint16_t b) { fixed_uint16_t rshift_u16_lsplat(fixed_uint16_t a, uint16_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_i32_rsplat( // CHECK-LABEL: @lshift_i32_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lshift_i32_rsplat(fixed_int32_t a, int32_t b) { fixed_int32_t lshift_i32_rsplat(fixed_int32_t a, int32_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_i32_lsplat( // CHECK-LABEL: @lshift_i32_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t lshift_i32_lsplat(fixed_int32_t a, int32_t b) { fixed_int32_t lshift_i32_lsplat(fixed_int32_t a, int32_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_i32_rsplat( // CHECK-LABEL: @rshift_i32_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rshift_i32_rsplat(fixed_int32_t a, int32_t b) { fixed_int32_t rshift_i32_rsplat(fixed_int32_t a, int32_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_i32_lsplat( // CHECK-LABEL: @rshift_i32_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i32> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t rshift_i32_lsplat(fixed_int32_t a, int32_t b) { fixed_int32_t rshift_i32_lsplat(fixed_int32_t a, int32_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_u32_rsplat( // CHECK-LABEL: @lshift_u32_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t lshift_u32_rsplat(fixed_uint32_t a, uint32_t b) { fixed_uint32_t lshift_u32_rsplat(fixed_uint32_t a, uint32_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_u32_lsplat( // CHECK-LABEL: @lshift_u32_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i32> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t lshift_u32_lsplat(fixed_uint32_t a, uint32_t b) { fixed_uint32_t lshift_u32_lsplat(fixed_uint32_t a, uint32_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_u32_rsplat( // CHECK-LABEL: @rshift_u32_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rshift_u32_rsplat(fixed_uint32_t a, uint32_t b) { fixed_uint32_t rshift_u32_rsplat(fixed_uint32_t a, uint32_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_u32_lsplat( // CHECK-LABEL: @rshift_u32_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = lshr <16 x i32> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_uint32_t rshift_u32_lsplat(fixed_uint32_t a, uint32_t b) { fixed_uint32_t rshift_u32_lsplat(fixed_uint32_t a, uint32_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_i64_rsplat( // CHECK-LABEL: @lshift_i64_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lshift_i64_rsplat(fixed_int64_t a, int64_t b) { fixed_int64_t lshift_i64_rsplat(fixed_int64_t a, int64_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_i64_lsplat( // CHECK-LABEL: @lshift_i64_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t lshift_i64_lsplat(fixed_int64_t a, int64_t b) { fixed_int64_t lshift_i64_lsplat(fixed_int64_t a, int64_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_i64_rsplat( // CHECK-LABEL: @rshift_i64_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rshift_i64_rsplat(fixed_int64_t a, int64_t b) { fixed_int64_t rshift_i64_rsplat(fixed_int64_t a, int64_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_i64_lsplat( // CHECK-LABEL: @rshift_i64_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = ashr <8 x i64> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_int64_t rshift_i64_lsplat(fixed_int64_t a, int64_t b) { fixed_int64_t rshift_i64_lsplat(fixed_int64_t a, int64_t b) {
return b >> a; return b >> a;
} }
// CHECK-LABEL: @lshift_u64_rsplat( // CHECK-LABEL: @lshift_u64_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t lshift_u64_rsplat(fixed_uint64_t a, uint64_t b) { fixed_uint64_t lshift_u64_rsplat(fixed_uint64_t a, uint64_t b) {
return a << b; return a << b;
} }
// CHECK-LABEL: @lshift_u64_lsplat( // CHECK-LABEL: @lshift_u64_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHL:%.*]] = shl <8 x i64> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHL]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t lshift_u64_lsplat(fixed_uint64_t a, uint64_t b) { fixed_uint64_t lshift_u64_lsplat(fixed_uint64_t a, uint64_t b) {
return b << a; return b << a;
} }
// CHECK-LABEL: @rshift_u64_rsplat( // CHECK-LABEL: @rshift_u64_rsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[A]], [[SPLAT_SPLAT]] // CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[A]], [[SPLAT_SPLAT]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rshift_u64_rsplat(fixed_uint64_t a, uint64_t b) { fixed_uint64_t rshift_u64_rsplat(fixed_uint64_t a, uint64_t b) {
return a >> b; return a >> b;
} }
// CHECK-LABEL: @rshift_u64_lsplat( // CHECK-LABEL: @rshift_u64_lsplat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i32 0
// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <8 x i64> [[SPLAT_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[SPLAT_SPLAT]], [[A]] // CHECK-NEXT: [[SHR:%.*]] = lshr <8 x i64> [[SPLAT_SPLAT]], [[A]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SHR]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
fixed_uint64_t rshift_u64_lsplat(fixed_uint64_t a, uint64_t b) { fixed_uint64_t rshift_u64_lsplat(fixed_uint64_t a, uint64_t b) {
return b >> a; return b >> a;
} }

clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c

Show All 22 Lines
typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
// CHECK-LABEL: @subscript_int16( // CHECK-LABEL: @subscript_int16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i16> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i16> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i16 [[VECEXT]] // CHECK-NEXT: ret i16 [[VECEXT]]
// //
int16_t subscript_int16(fixed_int16_t a, size_t b) { int16_t subscript_int16(fixed_int16_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_uint16( // CHECK-LABEL: @subscript_uint16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.experimental.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i16> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x i16> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i16 [[VECEXT]] // CHECK-NEXT: ret i16 [[VECEXT]]
// //
uint16_t subscript_uint16(fixed_uint16_t a, size_t b) { uint16_t subscript_uint16(fixed_uint16_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_int32( // CHECK-LABEL: @subscript_int32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i32> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i32> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i32 [[VECEXT]] // CHECK-NEXT: ret i32 [[VECEXT]]
// //
int32_t subscript_int32(fixed_int32_t a, size_t b) { int32_t subscript_int32(fixed_int32_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_uint32( // CHECK-LABEL: @subscript_uint32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i32> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x i32> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i32 [[VECEXT]] // CHECK-NEXT: ret i32 [[VECEXT]]
// //
uint32_t subscript_uint32(fixed_uint32_t a, size_t b) { uint32_t subscript_uint32(fixed_uint32_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_int64( // CHECK-LABEL: @subscript_int64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i64> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i64> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i64 [[VECEXT]] // CHECK-NEXT: ret i64 [[VECEXT]]
// //
int64_t subscript_int64(fixed_int64_t a, size_t b) { int64_t subscript_int64(fixed_int64_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_uint64( // CHECK-LABEL: @subscript_uint64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i64> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i64> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret i64 [[VECEXT]] // CHECK-NEXT: ret i64 [[VECEXT]]
// //
uint64_t subscript_uint64(fixed_uint64_t a, size_t b) { uint64_t subscript_uint64(fixed_uint64_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_float16( // CHECK-LABEL: @subscript_float16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.experimental.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x half> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <32 x half> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret half [[VECEXT]] // CHECK-NEXT: ret half [[VECEXT]]
// //
__fp16 subscript_float16(fixed_float16_t a, size_t b) { __fp16 subscript_float16(fixed_float16_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_float32( // CHECK-LABEL: @subscript_float32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x float> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <16 x float> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret float [[VECEXT]] // CHECK-NEXT: ret float [[VECEXT]]
// //
float subscript_float32(fixed_float32_t a, size_t b) { float subscript_float32(fixed_float32_t a, size_t b) {
return a[b]; return a[b];
} }
// CHECK-LABEL: @subscript_float64( // CHECK-LABEL: @subscript_float64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x double> [[A]], i64 [[B:%.*]] // CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x double> [[A]], i64 [[B:%.*]]
// CHECK-NEXT: ret double [[VECEXT]] // CHECK-NEXT: ret double [[VECEXT]]
// //
double subscript_float64(fixed_float64_t a, size_t b) { double subscript_float64(fixed_float64_t a, size_t b) {
return a[b]; return a[b];
} }

clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c

Show All 10 Lines
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
#endif #endif
// CHECK-LABEL: @test_svdup_neonq_s8( // CHECK-LABEL: @test_svdup_neonq_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z19test_svdup_neonq_s811__Int8x16_t( // CPP-CHECK-LABEL: @_Z19test_svdup_neonq_s811__Int8x16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
svint8_t test_svdup_neonq_s8(int8x16_t n) { svint8_t test_svdup_neonq_s8(int8x16_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _s8, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _s8, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_s16( // CHECK-LABEL: @test_svdup_neonq_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s1611__Int16x8_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s1611__Int16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
svint16_t test_svdup_neonq_s16(int16x8_t n) { svint16_t test_svdup_neonq_s16(int16x8_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _s16, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _s16, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_s32( // CHECK-LABEL: @test_svdup_neonq_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s3211__Int32x4_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s3211__Int32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
svint32_t test_svdup_neonq_s32(int32x4_t n) { svint32_t test_svdup_neonq_s32(int32x4_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _s32, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _s32, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_s64( // CHECK-LABEL: @test_svdup_neonq_s64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s6411__Int64x2_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s6411__Int64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
svint64_t test_svdup_neonq_s64(int64x2_t n) { svint64_t test_svdup_neonq_s64(int64x2_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _s64, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _s64, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_u8( // CHECK-LABEL: @test_svdup_neonq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z19test_svdup_neonq_u812__Uint8x16_t( // CPP-CHECK-LABEL: @_Z19test_svdup_neonq_u812__Uint8x16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
svuint8_t test_svdup_neonq_u8(uint8x16_t n) { svuint8_t test_svdup_neonq_u8(uint8x16_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _u8, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _u8, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_u16( // CHECK-LABEL: @test_svdup_neonq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u1612__Uint16x8_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u1612__Uint16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
svuint16_t test_svdup_neonq_u16(uint16x8_t n) { svuint16_t test_svdup_neonq_u16(uint16x8_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _u16, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _u16, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_u32( // CHECK-LABEL: @test_svdup_neonq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u3212__Uint32x4_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u3212__Uint32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
svuint32_t test_svdup_neonq_u32(uint32x4_t n) { svuint32_t test_svdup_neonq_u32(uint32x4_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _u32, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _u32, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_u64( // CHECK-LABEL: @test_svdup_neonq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u6412__Uint64x2_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u6412__Uint64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
svuint64_t test_svdup_neonq_u64(uint64x2_t n) { svuint64_t test_svdup_neonq_u64(uint64x2_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _u64, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _u64, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_f16( // CHECK-LABEL: @test_svdup_neonq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f1613__Float16x8_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f1613__Float16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
svfloat16_t test_svdup_neonq_f16(float16x8_t n) { svfloat16_t test_svdup_neonq_f16(float16x8_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _f16, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _f16, , )(n);
} }
// CHECK-NEXT %0 = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %n, i64 0) // CHECK-NEXT %0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %n, i64 0)
// CHECK-NEXT %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 0) // CHECK-NEXT %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 0)
// CHECK-NEXT ret <vscale x 4 x float> %1 // CHECK-NEXT ret <vscale x 4 x float> %1
// CHECK-LABEL: @test_svdup_neonq_f32( // CHECK-LABEL: @test_svdup_neonq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f3213__Float32x4_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f3213__Float32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
svfloat32_t test_svdup_neonq_f32(float32x4_t n) { svfloat32_t test_svdup_neonq_f32(float32x4_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _f32, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _f32, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_f64( // CHECK-LABEL: @test_svdup_neonq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f6413__Float64x2_t( // CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f6413__Float64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
svfloat64_t test_svdup_neonq_f64(float64x2_t n) { svfloat64_t test_svdup_neonq_f64(float64x2_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _f64, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _f64, , )(n);
} }
// CHECK-LABEL: @test_svdup_neonq_bf16( // CHECK-LABEL: @test_svdup_neonq_bf16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0) // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
// //
// CPP-CHECK-LABEL: @_Z21test_svdup_neonq_bf1614__Bfloat16x8_t( // CPP-CHECK-LABEL: @_Z21test_svdup_neonq_bf1614__Bfloat16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0) // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> [[TMP0]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] // CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
// //
svbfloat16_t test_svdup_neonq_bf16(bfloat16x8_t n) { svbfloat16_t test_svdup_neonq_bf16(bfloat16x8_t n) {
return SVE_ACLE_FUNC(svdup_neonq, _bf16, , )(n); return SVE_ACLE_FUNC(svdup_neonq, _bf16, , )(n);
} }

clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c

Show All 10 Lines
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
#endif #endif
// CHECK-LABEL: @test_svget_neonq_s8( // CHECK-LABEL: @test_svget_neonq_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <16 x i8> [[TMP0]] // CHECK-NEXT: ret <16 x i8> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z19test_svget_neonq_s8u10__SVInt8_t( // CPP-CHECK-LABEL: @_Z19test_svget_neonq_s8u10__SVInt8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] // CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]]
// //
int8x16_t test_svget_neonq_s8(svint8_t n) { int8x16_t test_svget_neonq_s8(svint8_t n) {
return SVE_ACLE_FUNC(svget_neonq, _s8, , )(n); return SVE_ACLE_FUNC(svget_neonq, _s8, , )(n);
} }
// //
// CHECK-LABEL: @test_svget_neonq_s16( // CHECK-LABEL: @test_svget_neonq_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <8 x i16> [[TMP0]] // CHECK-NEXT: ret <8 x i16> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_s16u11__SVInt16_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_s16u11__SVInt16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <8 x i16> [[TMP0]] // CPP-CHECK-NEXT: ret <8 x i16> [[TMP0]]
// //
int16x8_t test_svget_neonq_s16(svint16_t n) { int16x8_t test_svget_neonq_s16(svint16_t n) {
return SVE_ACLE_FUNC(svget_neonq, _s16, , )(n); return SVE_ACLE_FUNC(svget_neonq, _s16, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_s32( // CHECK-LABEL: @test_svget_neonq_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_s32u11__SVInt32_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_s32u11__SVInt32_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <4 x i32> [[TMP0]] // CPP-CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
int32x4_t test_svget_neonq_s32(svint32_t n) { int32x4_t test_svget_neonq_s32(svint32_t n) {
return SVE_ACLE_FUNC(svget_neonq, _s32, , )(n); return SVE_ACLE_FUNC(svget_neonq, _s32, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_s64( // CHECK-LABEL: @test_svget_neonq_s64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <2 x i64> [[TMP0]] // CHECK-NEXT: ret <2 x i64> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_s64u11__SVInt64_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_s64u11__SVInt64_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <2 x i64> [[TMP0]] // CPP-CHECK-NEXT: ret <2 x i64> [[TMP0]]
// //
int64x2_t test_svget_neonq_s64(svint64_t n) { int64x2_t test_svget_neonq_s64(svint64_t n) {
return SVE_ACLE_FUNC(svget_neonq, _s64, , )(n); return SVE_ACLE_FUNC(svget_neonq, _s64, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_u8( // CHECK-LABEL: @test_svget_neonq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <16 x i8> [[TMP0]] // CHECK-NEXT: ret <16 x i8> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z19test_svget_neonq_u8u11__SVUint8_t( // CPP-CHECK-LABEL: @_Z19test_svget_neonq_u8u11__SVUint8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] // CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]]
// //
uint8x16_t test_svget_neonq_u8(svuint8_t n) { uint8x16_t test_svget_neonq_u8(svuint8_t n) {
return SVE_ACLE_FUNC(svget_neonq, _u8, , )(n); return SVE_ACLE_FUNC(svget_neonq, _u8, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_u16( // CHECK-LABEL: @test_svget_neonq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <8 x i16> [[TMP0]] // CHECK-NEXT: ret <8 x i16> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_u16u12__SVUint16_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_u16u12__SVUint16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <8 x i16> [[TMP0]] // CPP-CHECK-NEXT: ret <8 x i16> [[TMP0]]
// //
uint16x8_t test_svget_neonq_u16(svuint16_t n) { uint16x8_t test_svget_neonq_u16(svuint16_t n) {
return SVE_ACLE_FUNC(svget_neonq, _u16, , )(n); return SVE_ACLE_FUNC(svget_neonq, _u16, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_u32( // CHECK-LABEL: @test_svget_neonq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_u32u12__SVUint32_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_u32u12__SVUint32_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <4 x i32> [[TMP0]] // CPP-CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
uint32x4_t test_svget_neonq_u32(svuint32_t n) { uint32x4_t test_svget_neonq_u32(svuint32_t n) {
return SVE_ACLE_FUNC(svget_neonq, _u32, , )(n); return SVE_ACLE_FUNC(svget_neonq, _u32, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_u64( // CHECK-LABEL: @test_svget_neonq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <2 x i64> [[TMP0]] // CHECK-NEXT: ret <2 x i64> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_u64u12__SVUint64_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_u64u12__SVUint64_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <2 x i64> [[TMP0]] // CPP-CHECK-NEXT: ret <2 x i64> [[TMP0]]
// //
uint64x2_t test_svget_neonq_u64(svuint64_t n) { uint64x2_t test_svget_neonq_u64(svuint64_t n) {
return SVE_ACLE_FUNC(svget_neonq, _u64, , )(n); return SVE_ACLE_FUNC(svget_neonq, _u64, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_f16( // CHECK-LABEL: @test_svget_neonq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.experimental.vector.extract.v8f16.nxv8f16(<vscale x 8 x half> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.vector.extract.v8f16.nxv8f16(<vscale x 8 x half> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <8 x half> [[TMP0]] // CHECK-NEXT: ret <8 x half> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_f16u13__SVFloat16_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_f16u13__SVFloat16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.experimental.vector.extract.v8f16.nxv8f16(<vscale x 8 x half> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.vector.extract.v8f16.nxv8f16(<vscale x 8 x half> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <8 x half> [[TMP0]] // CPP-CHECK-NEXT: ret <8 x half> [[TMP0]]
// //
float16x8_t test_svget_neonq_f16(svfloat16_t n) { float16x8_t test_svget_neonq_f16(svfloat16_t n) {
return SVE_ACLE_FUNC(svget_neonq, _f16, , )(n); return SVE_ACLE_FUNC(svget_neonq, _f16, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_f32( // CHECK-LABEL: @test_svget_neonq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.experimental.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <4 x float> [[TMP0]] // CHECK-NEXT: ret <4 x float> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_f32u13__SVFloat32_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_f32u13__SVFloat32_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.experimental.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <4 x float> [[TMP0]] // CPP-CHECK-NEXT: ret <4 x float> [[TMP0]]
// //
float32x4_t test_svget_neonq_f32(svfloat32_t n) { float32x4_t test_svget_neonq_f32(svfloat32_t n) {
return SVE_ACLE_FUNC(svget_neonq, _f32, , )(n); return SVE_ACLE_FUNC(svget_neonq, _f32, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_f64( // CHECK-LABEL: @test_svget_neonq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <2 x double> @llvm.experimental.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <2 x double> @llvm.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <2 x double> [[TMP0]] // CHECK-NEXT: ret <2 x double> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svget_neonq_f64u13__SVFloat64_t( // CPP-CHECK-LABEL: @_Z20test_svget_neonq_f64u13__SVFloat64_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x double> @llvm.experimental.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <2 x double> @llvm.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <2 x double> [[TMP0]] // CPP-CHECK-NEXT: ret <2 x double> [[TMP0]]
// //
float64x2_t test_svget_neonq_f64(svfloat64_t n) { float64x2_t test_svget_neonq_f64(svfloat64_t n) {
return SVE_ACLE_FUNC(svget_neonq, _f64, , )(n); return SVE_ACLE_FUNC(svget_neonq, _f64, , )(n);
} }
// CHECK-LABEL: @test_svget_neonq_bf16( // CHECK-LABEL: @test_svget_neonq_bf16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <8 x bfloat> [[TMP0]] // CHECK-NEXT: ret <8 x bfloat> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z21test_svget_neonq_bf16u14__SVBFloat16_t( // CPP-CHECK-LABEL: @_Z21test_svget_neonq_bf16u14__SVBFloat16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <8 x bfloat> [[TMP0]] // CPP-CHECK-NEXT: ret <8 x bfloat> [[TMP0]]
// //
bfloat16x8_t test_svget_neonq_bf16(svbfloat16_t n) { bfloat16x8_t test_svget_neonq_bf16(svbfloat16_t n) {
return SVE_ACLE_FUNC(svget_neonq, _bf16, , )(n); return SVE_ACLE_FUNC(svget_neonq, _bf16, , )(n);
} }

clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c

Show All 10 Lines
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
#endif #endif
// CHECK-LABEL: @test_svset_neonq_s8( // CHECK-LABEL: @test_svset_neonq_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t( // CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) { svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) {
return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_s16( // CHECK-LABEL: @test_svset_neonq_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) { svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) {
return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_s32( // CHECK-LABEL: @test_svset_neonq_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) { svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) {
return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_s64( // CHECK-LABEL: @test_svset_neonq_s64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
svint64_t test_svset_neonq_s64(svint64_t s, int64x2_t n) { svint64_t test_svset_neonq_s64(svint64_t s, int64x2_t n) {
return SVE_ACLE_FUNC(svset_neonq, _s64, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _s64, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_u8( // CHECK-LABEL: @test_svset_neonq_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z19test_svset_neonq_u8u11__SVUint8_t12__Uint8x16_t( // CPP-CHECK-LABEL: @_Z19test_svset_neonq_u8u11__SVUint8_t12__Uint8x16_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
svuint8_t test_svset_neonq_u8(svuint8_t s, uint8x16_t n) { svuint8_t test_svset_neonq_u8(svuint8_t s, uint8x16_t n) {
return SVE_ACLE_FUNC(svset_neonq, _u8, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _u8, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_u16( // CHECK-LABEL: @test_svset_neonq_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_u16u12__SVUint16_t12__Uint16x8_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_u16u12__SVUint16_t12__Uint16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
svuint16_t test_svset_neonq_u16(svuint16_t s, uint16x8_t n) { svuint16_t test_svset_neonq_u16(svuint16_t s, uint16x8_t n) {
return SVE_ACLE_FUNC(svset_neonq, _u16, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _u16, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_u32( // CHECK-LABEL: @test_svset_neonq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_u32u12__SVUint32_t12__Uint32x4_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_u32u12__SVUint32_t12__Uint32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
svuint32_t test_svset_neonq_u32(svuint32_t s, uint32x4_t n) { svuint32_t test_svset_neonq_u32(svuint32_t s, uint32x4_t n) {
return SVE_ACLE_FUNC(svset_neonq, _u32, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _u32, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_u64( // CHECK-LABEL: @test_svset_neonq_u64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_u64u12__SVUint64_t12__Uint64x2_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_u64u12__SVUint64_t12__Uint64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
svuint64_t test_svset_neonq_u64(svuint64_t s, uint64x2_t n) { svuint64_t test_svset_neonq_u64(svuint64_t s, uint64x2_t n) {
return SVE_ACLE_FUNC(svset_neonq, _u64, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _u64, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_f16( // CHECK-LABEL: @test_svset_neonq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> [[S:%.*]], <8 x half> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> [[S:%.*]], <8 x half> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_f16u13__SVFloat16_t13__Float16x8_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_f16u13__SVFloat16_t13__Float16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> [[S:%.*]], <8 x half> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> [[S:%.*]], <8 x half> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
svfloat16_t test_svset_neonq_f16(svfloat16_t s, float16x8_t n) { svfloat16_t test_svset_neonq_f16(svfloat16_t s, float16x8_t n) {
return SVE_ACLE_FUNC(svset_neonq, _f16, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _f16, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_f32( // CHECK-LABEL: @test_svset_neonq_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> [[S:%.*]], <4 x float> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> [[S:%.*]], <4 x float> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_f32u13__SVFloat32_t13__Float32x4_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_f32u13__SVFloat32_t13__Float32x4_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> [[S:%.*]], <4 x float> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> [[S:%.*]], <4 x float> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
svfloat32_t test_svset_neonq_f32(svfloat32_t s, float32x4_t n) { svfloat32_t test_svset_neonq_f32(svfloat32_t s, float32x4_t n) {
return SVE_ACLE_FUNC(svset_neonq, _f32, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _f32, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_f64( // CHECK-LABEL: @test_svset_neonq_f64(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> [[S:%.*]], <2 x double> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> [[S:%.*]], <2 x double> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z20test_svset_neonq_f64u13__SVFloat64_t13__Float64x2_t( // CPP-CHECK-LABEL: @_Z20test_svset_neonq_f64u13__SVFloat64_t13__Float64x2_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> [[S:%.*]], <2 x double> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> [[S:%.*]], <2 x double> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
svfloat64_t test_svset_neonq_f64(svfloat64_t s, float64x2_t n) { svfloat64_t test_svset_neonq_f64(svfloat64_t s, float64x2_t n) {
return SVE_ACLE_FUNC(svset_neonq, _f64, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _f64, , )(s, n);
} }
// CHECK-LABEL: @test_svset_neonq_bf16( // CHECK-LABEL: @test_svset_neonq_bf16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0) // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
// //
// CPP-CHECK-LABEL: @_Z21test_svset_neonq_bf16u14__SVBFloat16_t14__Bfloat16x8_t( // CPP-CHECK-LABEL: @_Z21test_svset_neonq_bf16u14__SVBFloat16_t14__Bfloat16x8_t(
// CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0) // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> [[S:%.*]], <8 x bfloat> [[N:%.*]], i64 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] // CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
// //
svbfloat16_t test_svset_neonq_bf16(svbfloat16_t s, bfloat16x8_t n) { svbfloat16_t test_svset_neonq_bf16(svbfloat16_t s, bfloat16x8_t n) {
return SVE_ACLE_FUNC(svset_neonq, _bf16, , )(s, n); return SVE_ACLE_FUNC(svset_neonq, _bf16, , )(s, n);
} }

clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c

Show All 26 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// int64 // int64
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @read_int64( // CHECK-128-LABEL: @read_int64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP0]], i64 0)
// CHECK-128-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-128-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
// CHECK-256-LABEL: @read_int64( // CHECK-256-LABEL: @read_int64(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP0]], i64 0) // CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP0]], i64 0)
// CHECK-256-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-256-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
// CHECK-512-LABEL: @read_int64( // CHECK-512-LABEL: @read_int64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[TMP0]], i64 0)
// CHECK-512-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-512-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
svint64_t read_int64(struct struct_int64 *s) { svint64_t read_int64(struct struct_int64 *s) {
return s->y[0]; return s->y[0];
} }
// CHECK-128-LABEL: @write_int64( // CHECK-128-LABEL: @write_int64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0)
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-256-LABEL: @write_int64( // CHECK-256-LABEL: @write_int64(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0) // CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0)
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: store <4 x i64> [[CASTFIXEDSVE]], <4 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-256-NEXT: store <4 x i64> [[CASTFIXEDSVE]], <4 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-256-NEXT: ret void // CHECK-256-NEXT: ret void
// //
// CHECK-512-LABEL: @write_int64( // CHECK-512-LABEL: @write_int64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[X:%.*]], i64 0)
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_INT64:%.*]], %struct.struct_int64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_int64(struct struct_int64 *s, svint64_t x) { void write_int64(struct struct_int64 *s, svint64_t x) {
s->y[0] = x; s->y[0] = x;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// float64 // float64
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @read_float64( // CHECK-128-LABEL: @read_float64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> [[TMP0]], i64 0)
// CHECK-128-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-128-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
// CHECK-256-LABEL: @read_float64( // CHECK-256-LABEL: @read_float64(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x double>, <4 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x double>, <4 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP0]], i64 0) // CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP0]], i64 0)
// CHECK-256-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-256-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
// CHECK-512-LABEL: @read_float64( // CHECK-512-LABEL: @read_float64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x double>, <8 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x double>, <8 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> [[TMP0]], i64 0)
// CHECK-512-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]] // CHECK-512-NEXT: ret <vscale x 2 x double> [[CASTSCALABLESVE]]
// //
svfloat64_t read_float64(struct struct_float64 *s) { svfloat64_t read_float64(struct struct_float64 *s) {
return s->y[0]; return s->y[0];
} }
// CHECK-128-LABEL: @write_float64( // CHECK-128-LABEL: @write_float64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x double> @llvm.experimental.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x double> @llvm.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0)
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: store <2 x double> [[CASTFIXEDSVE]], <2 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: store <2 x double> [[CASTFIXEDSVE]], <2 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-256-LABEL: @write_float64( // CHECK-256-LABEL: @write_float64(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x double> @llvm.experimental.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0) // CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0)
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: store <4 x double> [[CASTFIXEDSVE]], <4 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-256-NEXT: store <4 x double> [[CASTFIXEDSVE]], <4 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-256-NEXT: ret void // CHECK-256-NEXT: ret void
// //
// CHECK-512-LABEL: @write_float64( // CHECK-512-LABEL: @write_float64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[X:%.*]], i64 0)
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_FLOAT64:%.*]], %struct.struct_float64* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: store <8 x double> [[CASTFIXEDSVE]], <8 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <8 x double> [[CASTFIXEDSVE]], <8 x double>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_float64(struct struct_float64 *s, svfloat64_t x) { void write_float64(struct struct_float64 *s, svfloat64_t x) {
s->y[0] = x; s->y[0] = x;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// bfloat16 // bfloat16
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @read_bfloat16( // CHECK-128-LABEL: @read_bfloat16(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP0]], i64 0)
// CHECK-128-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]] // CHECK-128-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]]
// //
// CHECK-256-LABEL: @read_bfloat16( // CHECK-256-LABEL: @read_bfloat16(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: [[TMP0:%.*]] = load <16 x bfloat>, <16 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-256-NEXT: [[TMP0:%.*]] = load <16 x bfloat>, <16 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP0]], i64 0) // CHECK-256-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP0]], i64 0)
// CHECK-256-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]] // CHECK-256-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]]
// //
// CHECK-512-LABEL: @read_bfloat16( // CHECK-512-LABEL: @read_bfloat16(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: [[TMP0:%.*]] = load <32 x bfloat>, <32 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <32 x bfloat>, <32 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v32bf16(<vscale x 8 x bfloat> undef, <32 x bfloat> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v32bf16(<vscale x 8 x bfloat> undef, <32 x bfloat> [[TMP0]], i64 0)
// CHECK-512-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]] // CHECK-512-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]]
// //
svbfloat16_t read_bfloat16(struct struct_bfloat16 *s) { svbfloat16_t read_bfloat16(struct struct_bfloat16 *s) {
return s->y[0]; return s->y[0];
} }
// CHECK-128-LABEL: @write_bfloat16( // CHECK-128-LABEL: @write_bfloat16(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0)
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-256-LABEL: @write_bfloat16( // CHECK-256-LABEL: @write_bfloat16(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x bfloat> @llvm.experimental.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0) // CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x bfloat> @llvm.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0)
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: store <16 x bfloat> [[CASTFIXEDSVE]], <16 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-256-NEXT: store <16 x bfloat> [[CASTFIXEDSVE]], <16 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-256-NEXT: ret void // CHECK-256-NEXT: ret void
// //
// CHECK-512-LABEL: @write_bfloat16( // CHECK-512-LABEL: @write_bfloat16(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <32 x bfloat> @llvm.experimental.vector.extract.v32bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <32 x bfloat> @llvm.vector.extract.v32bf16.nxv8bf16(<vscale x 8 x bfloat> [[X:%.*]], i64 0)
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BFLOAT16:%.*]], %struct.struct_bfloat16* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: store <32 x bfloat> [[CASTFIXEDSVE]], <32 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <32 x bfloat> [[CASTFIXEDSVE]], <32 x bfloat>* [[ARRAYIDX]], align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_bfloat16(struct struct_bfloat16 *s, svbfloat16_t x) { void write_bfloat16(struct struct_bfloat16 *s, svbfloat16_t x) {
s->y[0] = x; s->y[0] = x;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// bool // bool
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @read_bool( // CHECK-128-LABEL: @read_bool(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i8>, <2 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i8>, <2 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> [[TMP0]], i64 0)
// CHECK-128-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-128-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-128-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-128-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
// CHECK-256-LABEL: @read_bool( // CHECK-256-LABEL: @read_bool(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x i8>, <4 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-256-NEXT: [[TMP0:%.*]] = load <4 x i8>, <4 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> [[TMP0]], i64 0) // CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> [[TMP0]], i64 0)
// CHECK-256-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-256-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-256-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-256-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
// CHECK-512-LABEL: @read_bool( // CHECK-512-LABEL: @read_bool(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i8>, <8 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i8>, <8 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP0]], i64 0)
// CHECK-512-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-512-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-512-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-512-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
svbool_t read_bool(struct struct_bool *s) { svbool_t read_bool(struct struct_bool *s) {
return s->y[0]; return s->y[0];
} }
// CHECK-128-LABEL: @write_bool( // CHECK-128-LABEL: @write_bool(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8> // CHECK-128-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8>
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0)
// CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-128-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-128-NEXT: store <2 x i8> [[CASTFIXEDSVE]], <2 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-128-NEXT: store <2 x i8> [[CASTFIXEDSVE]], <2 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-256-LABEL: @write_bool( // CHECK-256-LABEL: @write_bool(
// CHECK-256-NEXT: entry: // CHECK-256-NEXT: entry:
// CHECK-256-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8> // CHECK-256-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8>
// CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0) // CHECK-256-NEXT: [[CASTFIXEDSVE:%.*]] = call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0)
// CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-256-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-256-NEXT: store <4 x i8> [[CASTFIXEDSVE]], <4 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-256-NEXT: store <4 x i8> [[CASTFIXEDSVE]], <4 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-256-NEXT: ret void // CHECK-256-NEXT: ret void
// //
// CHECK-512-LABEL: @write_bool( // CHECK-512-LABEL: @write_bool(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8> // CHECK-512-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> %x to <vscale x 2 x i8>
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0)
// CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0 // CHECK-512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_STRUCT_BOOL:%.*]], %struct.struct_bool* [[S:%.*]], i64 0, i32 1, i64 0
// CHECK-512-NEXT: store <8 x i8> [[CASTFIXEDSVE]], <8 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <8 x i8> [[CASTFIXEDSVE]], <8 x i8>* [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_bool(struct struct_bool *s, svbool_t x) { void write_bool(struct struct_bool *s, svbool_t x) {
s->y[0] = x; s->y[0] = x;
} }

clang/test/CodeGen/attr-arm-sve-vector-bits-call.c

Show All 39 Lines
} }
// CHECK-LABEL: @sizeless_caller( // CHECK-LABEL: @sizeless_caller(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[COERCE1:%.*]] = alloca <16 x i32>, align 16 // CHECK-NEXT: [[COERCE1:%.*]] = alloca <16 x i32>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i32>* [[COERCE1]] to <vscale x 4 x i32>* // CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i32>* [[COERCE1]] to <vscale x 4 x i32>*
// CHECK-NEXT: store <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32>* [[TMP0]], align 16 // CHECK-NEXT: store <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32>* [[TMP0]], align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-NEXT: [[CASTSCALABLESVE2:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP1]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE2:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP1]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE2]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE2]]
// //
svint32_t sizeless_caller(svint32_t x) { svint32_t sizeless_caller(svint32_t x) {
return fixed_callee(x); return fixed_callee(x);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// fixed, fixed // fixed, fixed
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clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

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// //
fixed_bool_t from_svbool_t(svbool_t type) { fixed_bool_t from_svbool_t(svbool_t type) {
return type; return type;
} }
// CHECK-LABEL: @lax_cast( // CHECK-LABEL: @lax_cast(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = alloca <16 x i32>, align 64 // CHECK-NEXT: [[TMP0:%.*]] = alloca <16 x i32>, align 64
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0)
// CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[TMP0:%.*]], align 64, !tbaa [[TBAA6:![0-9]+]] // CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[TMP0:%.*]], align 64, !tbaa [[TBAA6:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* [[TMP0]] to <vscale x 2 x i64>* // CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i32>* [[TMP0]] to <vscale x 2 x i64>*
// CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 2 x i64>, <vscale x 2 x i64>* [[TMP1]], align 64, !tbaa [[TBAA6]] // CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 2 x i64>, <vscale x 2 x i64>* [[TMP1]], align 64, !tbaa [[TBAA6]]
// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP2]] // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP2]]
// //
svint64_t lax_cast(fixed_int32_t type) { svint64_t lax_cast(fixed_int32_t type) {
return type; return type;
} }
// CHECK-LABEL: @to_svint32_t__from_gnu_int32_t( // CHECK-LABEL: @to_svint32_t__from_gnu_int32_t(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0:%.*]], align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0:%.*]], align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TYPE]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
svint32_t to_svint32_t__from_gnu_int32_t(gnu_int32_t type) { svint32_t to_svint32_t__from_gnu_int32_t(gnu_int32_t type) {
return type; return type;
} }
// CHECK-LABEL: @from_svint32_t__to_gnu_int32_t( // CHECK-LABEL: @from_svint32_t__to_gnu_int32_t(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE:%.*]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE:%.*]], i64 0)
// CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA6]] // CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
gnu_int32_t from_svint32_t__to_gnu_int32_t(svint32_t type) { gnu_int32_t from_svint32_t__to_gnu_int32_t(svint32_t type) {
return type; return type;
} }
// CHECK-LABEL: @to_fixed_int32_t__from_gnu_int32_t( // CHECK-LABEL: @to_fixed_int32_t__from_gnu_int32_t(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0:%.*]], align 16, !tbaa [[TBAA6]] // CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0:%.*]], align 16, !tbaa [[TBAA6]]
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TYPE]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TYPE]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t to_fixed_int32_t__from_gnu_int32_t(gnu_int32_t type) { fixed_int32_t to_fixed_int32_t__from_gnu_int32_t(gnu_int32_t type) {
return type; return type;
} }
// CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t( // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0) // CHECK-NEXT: [[TYPE:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0)
// CHECK-NEXT: store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA6]] // CHECK-NEXT: store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) { gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
return type; return type;
} }

clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

Show All 18 Lines
// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16 // CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16
// CHECK-NEXT: [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2 // CHECK-NEXT: [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2
// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16 // CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
// CHECK-NEXT: [[PG:%.*]] = alloca <vscale x 16 x i1>, align 2 // CHECK-NEXT: [[PG:%.*]] = alloca <vscale x 16 x i1>, align 2
// CHECK-NEXT: store <vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1>* [[PRED_ADDR]], align 2 // CHECK-NEXT: store <vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1>* [[PRED_ADDR]], align 2
// CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[VEC_ADDR]], align 16 // CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[VEC_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PRED_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PRED_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP1]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP1]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2 // CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2
// CHECK-NEXT: [[CASTFIXEDSVE2:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP3]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE2:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP3]], i64 0)
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE2]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE2]] to <vscale x 16 x i1>
// CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP4]])
// CHECK-NEXT: store <vscale x 16 x i1> [[TMP5]], <vscale x 16 x i1>* [[PG]], align 2 // CHECK-NEXT: store <vscale x 16 x i1> [[TMP5]], <vscale x 16 x i1>* [[PG]], align 2
// CHECK-NEXT: [[TMP6:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PG]], align 2 // CHECK-NEXT: [[TMP6:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PG]], align 2
// CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, <16 x i32>* @global_vec, align 16 // CHECK-NEXT: [[TMP7:%.*]] = load <16 x i32>, <16 x i32>* @global_vec, align 16
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP7]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP7]], i64 0)
// CHECK-NEXT: [[TMP8:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[VEC_ADDR]], align 16 // CHECK-NEXT: [[TMP8:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[VEC_ADDR]], align 16
// CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP6]]) // CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP6]])
// CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP8]]) // CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[TMP9]], <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP8]])
// CHECK-NEXT: [[CASTFIXEDSVE3:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP10]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE3:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP10]], i64 0)
// CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE3]], <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE3]], <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[TMP11:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: [[TMP11:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[CASTSCALABLESVE4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP11]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP11]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE4]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE4]]
// //
fixed_int32_t foo(svbool_t pred, svint32_t vec) { fixed_int32_t foo(svbool_t pred, svint32_t vec) {
svbool_t pg = svand_z(pred, global_pred, global_pred); svbool_t pg = svand_z(pred, global_pred, global_pred);
return svadd_m(pg, global_vec, vec); return svadd_m(pg, global_vec, vec);
} }
// CHECK-LABEL: @test_ptr_to_global( // CHECK-LABEL: @test_ptr_to_global(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16 // CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16
// CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca <16 x i32>*, align 8 // CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca <16 x i32>*, align 8
// CHECK-NEXT: store <16 x i32>* @global_vec, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8 // CHECK-NEXT: store <16 x i32>* @global_vec, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0]], align 16 // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0]], align 16
// CHECK-NEXT: store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t test_ptr_to_global() { fixed_int32_t test_ptr_to_global() {
fixed_int32_t *global_vec_ptr; fixed_int32_t *global_vec_ptr;
global_vec_ptr = &global_vec; global_vec_ptr = &global_vec;
return *global_vec_ptr; return *global_vec_ptr;
} }
// //
// Test casting pointer from fixed-length array to scalable vector. // Test casting pointer from fixed-length array to scalable vector.
// CHECK-LABEL: @array_arg( // CHECK-LABEL: @array_arg(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16 // CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16
// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca <16 x i32>*, align 8 // CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca <16 x i32>*, align 8
// CHECK-NEXT: store <16 x i32>* [[ARR:%.*]], <16 x i32>** [[ARR_ADDR]], align 8 // CHECK-NEXT: store <16 x i32>* [[ARR:%.*]], <16 x i32>** [[ARR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[ARR_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[ARR_ADDR]], align 8
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[TMP0]], i64 0 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[TMP0]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[ARRAYIDX]], align 16 // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[ARRAYIDX]], align 16
// CHECK-NEXT: store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP2]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]]
// //
fixed_int32_t array_arg(fixed_int32_t arr[]) { fixed_int32_t array_arg(fixed_int32_t arr[]) {
return arr[0]; return arr[0];
} }
// CHECK-LABEL: @address_of_array_idx( // CHECK-LABEL: @address_of_array_idx(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i8>, align 2 // CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i8>, align 2
// CHECK-NEXT: [[ARR:%.*]] = alloca [3 x <8 x i8>], align 2 // CHECK-NEXT: [[ARR:%.*]] = alloca [3 x <8 x i8>], align 2
// CHECK-NEXT: [[PARR:%.*]] = alloca <8 x i8>*, align 8 // CHECK-NEXT: [[PARR:%.*]] = alloca <8 x i8>*, align 8
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <8 x i8>], [3 x <8 x i8>]* [[ARR]], i64 0, i64 0 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <8 x i8>], [3 x <8 x i8>]* [[ARR]], i64 0, i64 0
// CHECK-NEXT: store <8 x i8>* [[ARRAYIDX]], <8 x i8>** [[PARR]], align 8 // CHECK-NEXT: store <8 x i8>* [[ARRAYIDX]], <8 x i8>** [[PARR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>*, <8 x i8>** [[PARR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>*, <8 x i8>** [[PARR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* [[TMP0]], align 2 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* [[TMP0]], align 2
// CHECK-NEXT: store <8 x i8> [[TMP1]], <8 x i8>* [[RETVAL]], align 2 // CHECK-NEXT: store <8 x i8> [[TMP1]], <8 x i8>* [[RETVAL]], align 2
// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[RETVAL]], align 2 // CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[RETVAL]], align 2
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP2]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP2]], i64 0)
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP3:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]]
// //
fixed_bool_t address_of_array_idx() { fixed_bool_t address_of_array_idx() {
fixed_bool_t arr[3]; fixed_bool_t arr[3];
fixed_bool_t *parr; fixed_bool_t *parr;
parr = &arr[0]; parr = &arr[0];
return *parr; return *parr;
} }
// CHECK-LABEL: @test_cast( // CHECK-LABEL: @test_cast(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16 // CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 16
// CHECK-NEXT: [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2 // CHECK-NEXT: [[PRED_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 2
// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16 // CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
// CHECK-NEXT: [[XX:%.*]] = alloca <8 x i8>, align 8 // CHECK-NEXT: [[XX:%.*]] = alloca <8 x i8>, align 8
// CHECK-NEXT: [[YY:%.*]] = alloca <8 x i8>, align 8 // CHECK-NEXT: [[YY:%.*]] = alloca <8 x i8>, align 8
// CHECK-NEXT: [[PG:%.*]] = alloca <vscale x 16 x i1>, align 2 // CHECK-NEXT: [[PG:%.*]] = alloca <vscale x 16 x i1>, align 2
// CHECK-NEXT: store <vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1>* [[PRED_ADDR]], align 2 // CHECK-NEXT: store <vscale x 16 x i1> [[PRED:%.*]], <vscale x 16 x i1>* [[PRED_ADDR]], align 2
// CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[VEC_ADDR]], align 16 // CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], <vscale x 4 x i32>* [[VEC_ADDR]], align 16
// CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[XX]], align 8 // CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[XX]], align 8
// CHECK-NEXT: store <8 x i8> <i8 2, i8 5, i8 4, i8 6, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[YY]], align 8 // CHECK-NEXT: store <8 x i8> <i8 2, i8 5, i8 4, i8 6, i8 0, i8 0, i8 0, i8 0>, <8 x i8>* [[YY]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PRED_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PRED_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2 // CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* @global_pred, align 2
// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP1]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP1]], i64 0)
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, <8 x i8>* [[XX]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, <8 x i8>* [[XX]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, <8 x i8>* [[YY]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, <8 x i8>* [[YY]], align 8
// CHECK-NEXT: [[ADD:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]] // CHECK-NEXT: [[ADD:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]
// CHECK-NEXT: [[CASTFIXEDSVE2:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[ADD]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE2:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[ADD]], i64 0)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE2]] to <vscale x 16 x i1> // CHECK-NEXT: [[TMP5:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE2]] to <vscale x 16 x i1>
// CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP5]]) // CHECK-NEXT: [[TMP6:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP5]])
// CHECK-NEXT: store <vscale x 16 x i1> [[TMP6]], <vscale x 16 x i1>* [[PG]], align 2 // CHECK-NEXT: store <vscale x 16 x i1> [[TMP6]], <vscale x 16 x i1>* [[PG]], align 2
// CHECK-NEXT: [[TMP7:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PG]], align 2 // CHECK-NEXT: [[TMP7:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[PG]], align 2
// CHECK-NEXT: [[TMP8:%.*]] = load <16 x i32>, <16 x i32>* @global_vec, align 16 // CHECK-NEXT: [[TMP8:%.*]] = load <16 x i32>, <16 x i32>* @global_vec, align 16
// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP8]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP8]], i64 0)
// CHECK-NEXT: [[TMP9:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[VEC_ADDR]], align 16 // CHECK-NEXT: [[TMP9:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[VEC_ADDR]], align 16
// CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP7]]) // CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[TMP7]])
// CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[TMP10]], <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP9]]) // CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[TMP10]], <vscale x 4 x i32> [[CASTSCALABLESVE]], <vscale x 4 x i32> [[TMP9]])
// CHECK-NEXT: [[CASTFIXEDSVE3:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP11]], i64 0) // CHECK-NEXT: [[CASTFIXEDSVE3:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP11]], i64 0)
// CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE3]], <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: store <16 x i32> [[CASTFIXEDSVE3]], <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[TMP12:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16 // CHECK-NEXT: [[TMP12:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
// CHECK-NEXT: [[CASTSCALABLESVE4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP12]], i64 0) // CHECK-NEXT: [[CASTSCALABLESVE4:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP12]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE4]] // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE4]]
// //
fixed_int32_t test_cast(svbool_t pred, svint32_t vec) { fixed_int32_t test_cast(svbool_t pred, svint32_t vec) {
uint8_vec_t xx = {1, 2, 3, 4}; uint8_vec_t xx = {1, 2, 3, 4};
uint8_vec_t yy = {2, 5, 4, 6}; uint8_vec_t yy = {2, 5, 4, 6};
svbool_t pg = svand_z(pred, global_pred, xx + yy); svbool_t pg = svand_z(pred, global_pred, xx + yy);
return svadd_m(pg, global_vec, vec); return svadd_m(pg, global_vec, vec);
} }

clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c

Show All 16 Lines
fixed_bool_t global_bool; fixed_bool_t global_bool;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// WRITES // WRITES
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @write_global_i64( // CHECK-128-LABEL: @write_global_i64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[V:%.*]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[V:%.*]], i64 0)
// CHECK-128-NEXT: store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-128-NEXT: store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-512-LABEL: @write_global_i64( // CHECK-512-LABEL: @write_global_i64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[V:%.*]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[V:%.*]], i64 0)
// CHECK-512-NEXT: store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, !tbaa [[TBAA6:![0-9]+]] // CHECK-512-NEXT: store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, !tbaa [[TBAA6:![0-9]+]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_global_i64(svint64_t v) { global_i64 = v; } void write_global_i64(svint64_t v) { global_i64 = v; }
// CHECK-128-LABEL: @write_global_bf16( // CHECK-128-LABEL: @write_global_bf16(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[V:%.*]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.vector.extract.v8bf16.nxv8bf16(<vscale x 8 x bfloat> [[V:%.*]], i64 0)
// CHECK-128-NEXT: store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-512-LABEL: @write_global_bf16( // CHECK-512-LABEL: @write_global_bf16(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <32 x bfloat> @llvm.experimental.vector.extract.v32bf16.nxv8bf16(<vscale x 8 x bfloat> [[V:%.*]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <32 x bfloat> @llvm.vector.extract.v32bf16.nxv8bf16(<vscale x 8 x bfloat> [[V:%.*]], i64 0)
// CHECK-512-NEXT: store <32 x bfloat> [[CASTFIXEDSVE]], <32 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <32 x bfloat> [[CASTFIXEDSVE]], <32 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_global_bf16(svbfloat16_t v) { global_bf16 = v; } void write_global_bf16(svbfloat16_t v) { global_bf16 = v; }
// CHECK-128-LABEL: @write_global_bool( // CHECK-128-LABEL: @write_global_bool(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> [[V:%.*]] to <vscale x 2 x i8> // CHECK-128-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> [[V:%.*]] to <vscale x 2 x i8>
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0)
// CHECK-128-NEXT: store <2 x i8> [[CASTFIXEDSVE]], <2 x i8>* @global_bool, align 2, !tbaa [[TBAA6:![0-9]+]] // CHECK-128-NEXT: store <2 x i8> [[CASTFIXEDSVE]], <2 x i8>* @global_bool, align 2, !tbaa [[TBAA6:![0-9]+]]
// CHECK-128-NEXT: ret void // CHECK-128-NEXT: ret void
// //
// CHECK-512-LABEL: @write_global_bool( // CHECK-512-LABEL: @write_global_bool(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> [[V:%.*]] to <vscale x 2 x i8> // CHECK-512-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i1> [[V:%.*]] to <vscale x 2 x i8>
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[TMP0]], i64 0)
// CHECK-512-NEXT: store <8 x i8> [[CASTFIXEDSVE]], <8 x i8>* @global_bool, align 2, !tbaa [[TBAA6]] // CHECK-512-NEXT: store <8 x i8> [[CASTFIXEDSVE]], <8 x i8>* @global_bool, align 2, !tbaa [[TBAA6]]
// CHECK-512-NEXT: ret void // CHECK-512-NEXT: ret void
// //
void write_global_bool(svbool_t v) { global_bool = v; } void write_global_bool(svbool_t v) { global_bool = v; }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// READS // READS
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK-128-LABEL: @read_global_i64( // CHECK-128-LABEL: @read_global_i64(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @global_i64, align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @global_i64, align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> [[TMP0]], i64 0)
// CHECK-128-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-128-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
// CHECK-512-LABEL: @read_global_i64( // CHECK-512-LABEL: @read_global_i64(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* @global_i64, align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* @global_i64, align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[TMP0]], i64 0)
// CHECK-512-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] // CHECK-512-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]]
// //
svint64_t read_global_i64() { return global_i64; } svint64_t read_global_i64() { return global_i64; }
// CHECK-128-LABEL: @read_global_bf16( // CHECK-128-LABEL: @read_global_bf16(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, <8 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <8 x bfloat>, <8 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> [[TMP0]], i64 0)
// CHECK-128-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]] // CHECK-128-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]]
// //
// CHECK-512-LABEL: @read_global_bf16( // CHECK-512-LABEL: @read_global_bf16(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[TMP0:%.*]] = load <32 x bfloat>, <32 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <32 x bfloat>, <32 x bfloat>* @global_bf16, align 16, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v32bf16(<vscale x 8 x bfloat> undef, <32 x bfloat> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v32bf16(<vscale x 8 x bfloat> undef, <32 x bfloat> [[TMP0]], i64 0)
// CHECK-512-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]] // CHECK-512-NEXT: ret <vscale x 8 x bfloat> [[CASTSCALABLESVE]]
// //
svbfloat16_t read_global_bf16() { return global_bf16; } svbfloat16_t read_global_bf16() { return global_bf16; }
// CHECK-128-LABEL: @read_global_bool( // CHECK-128-LABEL: @read_global_bool(
// CHECK-128-NEXT: entry: // CHECK-128-NEXT: entry:
// CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i8>, <2 x i8>* @global_bool, align 2, !tbaa [[TBAA6]] // CHECK-128-NEXT: [[TMP0:%.*]] = load <2 x i8>, <2 x i8>* @global_bool, align 2, !tbaa [[TBAA6]]
// CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> [[TMP0]], i64 0) // CHECK-128-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> [[TMP0]], i64 0)
// CHECK-128-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-128-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-128-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-128-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
// CHECK-512-LABEL: @read_global_bool( // CHECK-512-LABEL: @read_global_bool(
// CHECK-512-NEXT: entry: // CHECK-512-NEXT: entry:
// CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i8>, <8 x i8>* @global_bool, align 2, !tbaa [[TBAA6]] // CHECK-512-NEXT: [[TMP0:%.*]] = load <8 x i8>, <8 x i8>* @global_bool, align 2, !tbaa [[TBAA6]]
// CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP0]], i64 0) // CHECK-512-NEXT: [[CASTFIXEDSVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[TMP0]], i64 0)
// CHECK-512-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1> // CHECK-512-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CASTFIXEDSVE]] to <vscale x 16 x i1>
// CHECK-512-NEXT: ret <vscale x 16 x i1> [[TMP1]] // CHECK-512-NEXT: ret <vscale x 16 x i1> [[TMP1]]
// //
svbool_t read_global_bool() { return global_bool; } svbool_t read_global_bool() { return global_bool; }

llvm/docs/LangRef.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 17,262 Lines • ▼ Show 20 Lines
If the intrinsic call has the ``nnan`` fast-math flag, then the operation can If the intrinsic call has the ``nnan`` fast-math flag, then the operation can
assume that NaNs are not present in the input vector. assume that NaNs are not present in the input vector.
Arguments: Arguments:
"""""""""" """"""""""
The argument to this intrinsic must be a vector of floating-point values. The argument to this intrinsic must be a vector of floating-point values.
'``llvm.experimental.vector.insert``' Intrinsic '``llvm.vector.insert``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax: Syntax:
""""""" """""""
This is an overloaded intrinsic. You can use ``llvm.experimental.vector.insert`` This is an overloaded intrinsic.
to insert a fixed-width vector into a scalable vector, but not the other way
around.
:: ::
declare <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> %vec, <4 x float> %subvec, i64 %idx) ; Insert fixed type into scalable type
declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> %vec, <2 x double> %subvec, i64 %idx) declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> %vec, <4 x float> %subvec, i64 <idx>)
declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> %vec, <2 x double> %subvec, i64 <idx>)
paulwalker-armUnsubmitted
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For this and the other instances, please remove the % as idx must be a literal (as documented below) but using %idx makes it look like an arbitrary variable can be used.

paulwalker-arm: For this and the other instances, please remove the `%` as idx must be a literal (as documented…
; Insert scalable type into scalable type
declare <vscale x 4 x float> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x float> %vec, <vscale x 2 x float> %subvec, i64 <idx>)
; Insert fixed type into fixed type
declare <4 x double> @llvm.vector.insert.v4f64.v2f64(<4 x double> %vec, <2 x double> %subvec, i64 <idx>)
Overview: Overview:
""""""""" """""""""
The '``llvm.experimental.vector.insert.*``' intrinsics insert a vector into another vector The '``llvm.vector.insert.*``' intrinsics insert a vector into another vector
starting from a given index. The return type matches the type of the vector we starting from a given index. The return type matches the type of the vector we
insert into. Conceptually, this can be used to build a scalable vector out of insert into. Conceptually, this can be used to build a scalable vector out of
non-scalable vectors. non-scalable vectors, however this intrinsic can also be used on purely fixed
types.
Scalable vectors can only be inserted into other scalable vectors.
craig.topperUnsubmitted
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Now this comment makes it seems like you can't use it on purely scalable vectors.

craig.topper: Now this comment makes it seems like you can't use it on purely scalable vectors.
Arguments: Arguments:
jsetoainUnsubmitted
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To answer Craig's point, I don't think it was clear before that you could use this intrinsic with purely scalable vectors before, either. I believe the confusion comes from these clarifications. If instead of explicitly stating valid options you exclude the invalid ones, there's no room for ambiguity. Something like:

"Scalable vectors can only be inserted/extracted into/out of other scalable vectors". Examples of all other possible combinations might help to nail down this point.

jsetoain: To answer Craig's point, I don't think it was clear before that you could use this intrinsic…
"""""""""" """"""""""
The ``vec`` is the vector which ``subvec`` will be inserted into. The ``vec`` is the vector which ``subvec`` will be inserted into.
The ``subvec`` is the vector that will be inserted. The ``subvec`` is the vector that will be inserted.
``idx`` represents the starting element number at which ``subvec`` will be ``idx`` represents the starting element number at which ``subvec`` will be
inserted. ``idx`` must be a constant multiple of ``subvec``'s known minimum inserted. ``idx`` must be a constant multiple of ``subvec``'s known minimum
vector length. If ``subvec`` is a scalable vector, ``idx`` is first scaled by vector length. If ``subvec`` is a scalable vector, ``idx`` is first scaled by
the runtime scaling factor of ``subvec``. The elements of ``vec`` starting at the runtime scaling factor of ``subvec``. The elements of ``vec`` starting at
``idx`` are overwritten with ``subvec``. Elements ``idx`` through (``idx`` + ``idx`` are overwritten with ``subvec``. Elements ``idx`` through (``idx`` +
num_elements(``subvec``) - 1) must be valid ``vec`` indices. If this condition num_elements(``subvec``) - 1) must be valid ``vec`` indices. If this condition
cannot be determined statically but is false at runtime, then the result vector cannot be determined statically but is false at runtime, then the result vector
is undefined. is undefined.
'``llvm.experimental.vector.extract``' Intrinsic '``llvm.vector.extract``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax: Syntax:
""""""" """""""
This is an overloaded intrinsic. You can use This is an overloaded intrinsic.
``llvm.experimental.vector.extract`` to extract a fixed-width vector from a
scalable vector, but not the other way around.
:: ::
declare <4 x float> @llvm.experimental.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> %vec, i64 %idx) ; Extract fixed type from scalable type
declare <2 x double> @llvm.experimental.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> %vec, i64 %idx) declare <4 x float> @llvm.vector.extract.v4f32.nxv4f32(<vscale x 4 x float> %vec, i64 <idx>)
declare <2 x double> @llvm.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> %vec, i64 <idx>)
; Extract scalable type from scalable type
declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %vec, i64 <idx>)
; Extract fixed type from fixed type
declare <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %vec, i64 <idx>)
Overview: Overview:
""""""""" """""""""
The '``llvm.experimental.vector.extract.*``' intrinsics extract a vector from The '``llvm.vector.extract.*``' intrinsics extract a vector from within another
within another vector starting from a given index. The return type must be vector starting from a given index. The return type must be explicitly
explicitly specified. Conceptually, this can be used to decompose a scalable specified. Conceptually, this can be used to decompose a scalable vector into
vector into non-scalable parts. non-scalable parts, however this intrinsic can also be used on purely fixed
craig.topperUnsubmitted
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Same here

craig.topper: Same here
types.
Scalable vectors can only be extracted from other scalable vectors.
Arguments: Arguments:
"""""""""" """"""""""
The ``vec`` is the vector from which we will extract a subvector. The ``vec`` is the vector from which we will extract a subvector.
The ``idx`` specifies the starting element number within ``vec`` from which a The ``idx`` specifies the starting element number within ``vec`` from which a
subvector is extracted. ``idx`` must be a constant multiple of the known-minimum subvector is extracted. ``idx`` must be a constant multiple of the known-minimum
▲ Show 20 Lines • Show All 7,841 Lines • Show Last 20 Lines

llvm/docs/ReleaseNotes.rst

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
With the release of LLVM 16.x these requirements will be hard and LLVM developers With the release of LLVM 16.x these requirements will be hard and LLVM developers
can start using C++17 features, making it impossible to build with older can start using C++17 features, making it impossible to build with older
versions of these toolchains. versions of these toolchains.
Changes to the LLVM IR Changes to the LLVM IR
---------------------- ----------------------
* Renamed ``llvm.experimental.vector.extract`` intrinsic to ``llvm.vector.extract``.
* Renamed ``llvm.experimental.vector.insert`` intrinsic to ``llvm.vector.insert``.
Changes to building LLVM Changes to building LLVM
------------------------ ------------------------
* Omitting ``CMAKE_BUILD_TYPE`` when using a single configuration generator is now * Omitting ``CMAKE_BUILD_TYPE`` when using a single configuration generator is now
an error. You now have to pass ``-DCMAKE_BUILD_TYPE=<type>`` in order to configure an error. You now have to pass ``-DCMAKE_BUILD_TYPE=<type>`` in order to configure
LLVM. This is done to help new users of LLVM select the correct type: since building LLVM. This is done to help new users of LLVM select the correct type: since building
LLVM in Debug mode is very resource intensive, we want to make sure that new users LLVM in Debug mode is very resource intensive, we want to make sure that new users
make the choice that lines up with their usage. We have also improved documentation make the choice that lines up with their usage. We have also improved documentation
▲ Show 20 Lines • Show All 156 Lines • Show Last 20 Lines

llvm/include/llvm/CodeGen/BasicTTIImpl.h

Show First 20 Lines • Show All 1,468 Lines • ▼ Show 20 Lines case Intrinsic::masked_gather: {
VarMask, Alignment, CostKind, I); VarMask, Alignment, CostKind, I);
} }
case Intrinsic::experimental_stepvector: { case Intrinsic::experimental_stepvector: {
if (isa<ScalableVectorType>(RetTy)) if (isa<ScalableVectorType>(RetTy))
return BaseT::getIntrinsicInstrCost(ICA, CostKind); return BaseT::getIntrinsicInstrCost(ICA, CostKind);
// The cost of materialising a constant integer vector. // The cost of materialising a constant integer vector.
return TargetTransformInfo::TCC_Basic; return TargetTransformInfo::TCC_Basic;
} }
case Intrinsic::experimental_vector_extract: { case Intrinsic::vector_extract: {
// FIXME: Handle case where a scalable vector is extracted from a scalable // FIXME: Handle case where a scalable vector is extracted from a scalable
// vector // vector
if (isa<ScalableVectorType>(RetTy)) if (isa<ScalableVectorType>(RetTy))
return BaseT::getIntrinsicInstrCost(ICA, CostKind); return BaseT::getIntrinsicInstrCost(ICA, CostKind);
unsigned Index = cast<ConstantInt>(Args[1])->getZExtValue(); unsigned Index = cast<ConstantInt>(Args[1])->getZExtValue();
return thisT()->getShuffleCost(TTI::SK_ExtractSubvector, return thisT()->getShuffleCost(TTI::SK_ExtractSubvector,
cast<VectorType>(Args[0]->getType()), None, cast<VectorType>(Args[0]->getType()), None,
Index, cast<VectorType>(RetTy)); Index, cast<VectorType>(RetTy));
} }
case Intrinsic::experimental_vector_insert: { case Intrinsic::vector_insert: {
// FIXME: Handle case where a scalable vector is inserted into a scalable // FIXME: Handle case where a scalable vector is inserted into a scalable
// vector // vector
if (isa<ScalableVectorType>(Args[1]->getType())) if (isa<ScalableVectorType>(Args[1]->getType()))
return BaseT::getIntrinsicInstrCost(ICA, CostKind); return BaseT::getIntrinsicInstrCost(ICA, CostKind);
unsigned Index = cast<ConstantInt>(Args[2])->getZExtValue(); unsigned Index = cast<ConstantInt>(Args[2])->getZExtValue();
return thisT()->getShuffleCost( return thisT()->getShuffleCost(
TTI::SK_InsertSubvector, cast<VectorType>(Args[0]->getType()), None, TTI::SK_InsertSubvector, cast<VectorType>(Args[0]->getType()), None,
Index, cast<VectorType>(Args[1]->getType())); Index, cast<VectorType>(Args[1]->getType()));
▲ Show 20 Lines • Show All 867 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IRBuilder.h

Show First 20 Lines • Show All 908 Lines • ▼ Show 20 Lines#endif
/// Create a call to the arithmetic_fence intrinsic. /// Create a call to the arithmetic_fence intrinsic.
CallInst *CreateArithmeticFence(Value *Val, Type *DstType, CallInst *CreateArithmeticFence(Value *Val, Type *DstType,
const Twine &Name = "") { const Twine &Name = "") {
return CreateIntrinsic(Intrinsic::arithmetic_fence, DstType, Val, nullptr, return CreateIntrinsic(Intrinsic::arithmetic_fence, DstType, Val, nullptr,
Name); Name);
} }
/// Create a call to the experimental.vector.extract intrinsic. /// Create a call to the vector.extract intrinsic.
CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx, CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
const Twine &Name = "") { const Twine &Name = "") {
return CreateIntrinsic(Intrinsic::experimental_vector_extract, return CreateIntrinsic(Intrinsic::vector_extract,
{DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr, {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
Name); Name);
} }
/// Create a call to the experimental.vector.insert intrinsic. /// Create a call to the vector.insert intrinsic.
CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec, CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
Value *Idx, const Twine &Name = "") { Value *Idx, const Twine &Name = "") {
return CreateIntrinsic(Intrinsic::experimental_vector_insert, return CreateIntrinsic(Intrinsic::vector_insert,
{DstType, SubVec->getType()}, {SrcVec, SubVec, Idx}, {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
nullptr, Name); nullptr, Name);
} }
private: private:
/// Create a call to a masked intrinsic with given Id. /// Create a call to a masked intrinsic with given Id.
CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops, CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops,
ArrayRef<Type *> OverloadedTypes, ArrayRef<Type *> OverloadedTypes,
▲ Show 20 Lines • Show All 1,625 Lines • Show Last 20 Lines

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,955 Lines • ▼ Show 20 Linesdef int_experimental_vector_splice : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty], llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>; [IntrNoMem, ImmArg<ArgIndex<2>>]>;
//===---------- Intrinsics to query properties of scalable vectors --------===// //===---------- Intrinsics to query properties of scalable vectors --------===//
def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>; def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
//===---------- Intrinsics to perform subvector insertion/extraction ------===// //===---------- Intrinsics to perform subvector insertion/extraction ------===//
def int_experimental_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty], def int_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty], [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>; [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_experimental_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty], def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_i64_ty], [llvm_anyvector_ty, llvm_i64_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>; [IntrNoMem, ImmArg<ArgIndex<1>>]>;
//===----------------- Pointer Authentication Intrinsics ------------------===// //===----------------- Pointer Authentication Intrinsics ------------------===//
// //
// Sign an unauthenticated pointer using the specified key and discriminator, // Sign an unauthenticated pointer using the specified key and discriminator,
// passed in that order. // passed in that order.
// Returns the first argument, with some known bits replaced with a signature. // Returns the first argument, with some known bits replaced with a signature.
def int_ptrauth_sign : Intrinsic<[llvm_i64_ty], def int_ptrauth_sign : Intrinsic<[llvm_i64_ty],
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llvm/lib/Analysis/InstructionSimplify.cpp

Show First 20 Lines • Show All 6,015 Lines • ▼ Show 20 Lines if (auto *M0 = dyn_cast<IntrinsicInst>(Op0))
return Op0; return Op0;
if (auto *M1 = dyn_cast<IntrinsicInst>(Op1)) if (auto *M1 = dyn_cast<IntrinsicInst>(Op1))
if (M1->getIntrinsicID() == IID && if (M1->getIntrinsicID() == IID &&
(M1->getOperand(0) == Op0 || M1->getOperand(1) == Op0)) (M1->getOperand(0) == Op0 || M1->getOperand(1) == Op0))
return Op1; return Op1;
break; break;
} }
case Intrinsic::experimental_vector_extract: { case Intrinsic::vector_extract: {
Type *ReturnType = F->getReturnType(); Type *ReturnType = F->getReturnType();
// (extract_vector (insert_vector _, X, 0), 0) -> X // (extract_vector (insert_vector _, X, 0), 0) -> X
unsigned IdxN = cast<ConstantInt>(Op1)->getZExtValue(); unsigned IdxN = cast<ConstantInt>(Op1)->getZExtValue();
Value *X = nullptr; Value *X = nullptr;
if (match(Op0, m_Intrinsic<Intrinsic::experimental_vector_insert>( if (match(Op0, m_Intrinsic<Intrinsic::vector_insert>(m_Value(), m_Value(X),
m_Value(), m_Value(X), m_Zero())) && m_Zero())) &&
IdxN == 0 && X->getType() == ReturnType) IdxN == 0 && X->getType() == ReturnType)
return X; return X;
break; break;
} }
default: default:
break; break;
} }
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines case Intrinsic::smul_fix_sat: {
APInt ScaledOne = APInt ScaledOne =
APInt::getOneBitSet(ReturnType->getScalarSizeInBits(), APInt::getOneBitSet(ReturnType->getScalarSizeInBits(),
cast<ConstantInt>(Op2)->getZExtValue()); cast<ConstantInt>(Op2)->getZExtValue());
if (ScaledOne.isNonNegative() && match(Op1, m_SpecificInt(ScaledOne))) if (ScaledOne.isNonNegative() && match(Op1, m_SpecificInt(ScaledOne)))
return Op0; return Op0;
return nullptr; return nullptr;
} }
case Intrinsic::experimental_vector_insert: { case Intrinsic::vector_insert: {
Value *Vec = Call->getArgOperand(0); Value *Vec = Call->getArgOperand(0);
Value *SubVec = Call->getArgOperand(1); Value *SubVec = Call->getArgOperand(1);
Value *Idx = Call->getArgOperand(2); Value *Idx = Call->getArgOperand(2);
Type *ReturnType = F->getReturnType(); Type *ReturnType = F->getReturnType();
// (insert_vector Y, (extract_vector X, 0), 0) -> X // (insert_vector Y, (extract_vector X, 0), 0) -> X
// where: Y is X, or Y is undef // where: Y is X, or Y is undef
unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue(); unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
Value *X = nullptr; Value *X = nullptr;
if (match(SubVec, m_Intrinsic<Intrinsic::experimental_vector_extract>( if (match(SubVec,
m_Value(X), m_Zero())) && m_Intrinsic<Intrinsic::vector_extract>(m_Value(X), m_Zero())) &&
(Q.isUndefValue(Vec) || Vec == X) && IdxN == 0 && (Q.isUndefValue(Vec) || Vec == X) && IdxN == 0 &&
X->getType() == ReturnType) X->getType() == ReturnType)
return X; return X;
return nullptr; return nullptr;
} }
case Intrinsic::experimental_constrained_fadd: { case Intrinsic::experimental_constrained_fadd: {
auto *FPI = cast<ConstrainedFPIntrinsic>(Call); auto *FPI = cast<ConstrainedFPIntrinsic>(Call);
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llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,200 Lines • ▼ Show 20 Lines case Intrinsic::get_active_lane_mask: {
SDValue VectorStep = DAG.getStepVector(sdl, VecTy); SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
SDValue VectorInduction = DAG.getNode( SDValue VectorInduction = DAG.getNode(
ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep);
SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction,
VectorTripCount, ISD::CondCode::SETULT); VectorTripCount, ISD::CondCode::SETULT);
setValue(&I, SetCC); setValue(&I, SetCC);
return; return;
} }
case Intrinsic::experimental_vector_insert: { case Intrinsic::vector_insert: {
SDValue Vec = getValue(I.getOperand(0)); SDValue Vec = getValue(I.getOperand(0));
SDValue SubVec = getValue(I.getOperand(1)); SDValue SubVec = getValue(I.getOperand(1));
SDValue Index = getValue(I.getOperand(2)); SDValue Index = getValue(I.getOperand(2));
// The intrinsic's index type is i64, but the SDNode requires an index type // The intrinsic's index type is i64, but the SDNode requires an index type
// suitable for the target. Convert the index as required. // suitable for the target. Convert the index as required.
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
if (Index.getValueType() != VectorIdxTy) if (Index.getValueType() != VectorIdxTy)
Index = DAG.getVectorIdxConstant( Index = DAG.getVectorIdxConstant(
cast<ConstantSDNode>(Index)->getZExtValue(), sdl); cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec,
Index)); Index));
return; return;
} }
case Intrinsic::experimental_vector_extract: { case Intrinsic::vector_extract: {
SDValue Vec = getValue(I.getOperand(0)); SDValue Vec = getValue(I.getOperand(0));
SDValue Index = getValue(I.getOperand(1)); SDValue Index = getValue(I.getOperand(1));
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
// The intrinsic's index type is i64, but the SDNode requires an index type // The intrinsic's index type is i64, but the SDNode requires an index type
// suitable for the target. Convert the index as required. // suitable for the target. Convert the index as required.
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
if (Index.getValueType() != VectorIdxTy) if (Index.getValueType() != VectorIdxTy)
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llvm/lib/IR/AutoUpgrade.cpp

Show First 20 Lines • Show All 742 Lines • ▼ Show 20 Lines case 'd': {
if (Name == "dbg.value" && F->arg_size() == 4) { if (Name == "dbg.value" && F->arg_size() == 4) {
rename(F); rename(F);
NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value);
return true; return true;
} }
break; break;
} }
case 'e': { case 'e': {
if (Name.startswith("experimental.vector.extract.")) {
rename(F);
Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()};
NewFn = Intrinsic::getDeclaration(F->getParent(),
Intrinsic::vector_extract, Tys);
return true;
}
if (Name.startswith("experimental.vector.insert.")) {
rename(F);
auto Args = F->getFunctionType()->params();
Type *Tys[] = {Args[0], Args[1]};
NewFn = Intrinsic::getDeclaration(F->getParent(),
Intrinsic::vector_insert, Tys);
return true;
}
SmallVector<StringRef, 2> Groups; SmallVector<StringRef, 2> Groups;
static const Regex R("^experimental.vector.reduce.([a-z]+)\\.[a-z][0-9]+"); static const Regex R("^experimental.vector.reduce.([a-z]+)\\.[a-z][0-9]+");
if (R.match(Name, &Groups)) { if (R.match(Name, &Groups)) {
Intrinsic::ID ID; Intrinsic::ID ID;
ID = StringSwitch<Intrinsic::ID>(Groups[1]) ID = StringSwitch<Intrinsic::ID>(Groups[1])
.Case("add", Intrinsic::vector_reduce_add) .Case("add", Intrinsic::vector_reduce_add)
.Case("mul", Intrinsic::vector_reduce_mul) .Case("mul", Intrinsic::vector_reduce_mul)
.Case("and", Intrinsic::vector_reduce_and) .Case("and", Intrinsic::vector_reduce_and)
▲ Show 20 Lines • Show All 3,931 Lines • Show Last 20 Lines

llvm/lib/IR/Verifier.cpp

Show First 20 Lines • Show All 5,506 Lines • ▼ Show 20 Lines case Intrinsic::experimental_stepvector: {
VectorType *VecTy = dyn_cast<VectorType>(Call.getType()); VectorType *VecTy = dyn_cast<VectorType>(Call.getType());
Check(VecTy && VecTy->getScalarType()->isIntegerTy() && Check(VecTy && VecTy->getScalarType()->isIntegerTy() &&
VecTy->getScalarSizeInBits() >= 8, VecTy->getScalarSizeInBits() >= 8,
"experimental_stepvector only supported for vectors of integers " "experimental_stepvector only supported for vectors of integers "
"with a bitwidth of at least 8.", "with a bitwidth of at least 8.",
&Call); &Call);
break; break;
} }
case Intrinsic::experimental_vector_insert: { case Intrinsic::vector_insert: {
Value *Vec = Call.getArgOperand(0); Value *Vec = Call.getArgOperand(0);
Value *SubVec = Call.getArgOperand(1); Value *SubVec = Call.getArgOperand(1);
Value *Idx = Call.getArgOperand(2); Value *Idx = Call.getArgOperand(2);
unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue(); unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
VectorType *VecTy = cast<VectorType>(Vec->getType()); VectorType *VecTy = cast<VectorType>(Vec->getType());
VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); VectorType *SubVecTy = cast<VectorType>(SubVec->getType());
ElementCount VecEC = VecTy->getElementCount(); ElementCount VecEC = VecTy->getElementCount();
ElementCount SubVecEC = SubVecTy->getElementCount(); ElementCount SubVecEC = SubVecTy->getElementCount();
Check(VecTy->getElementType() == SubVecTy->getElementType(), Check(VecTy->getElementType() == SubVecTy->getElementType(),
"experimental_vector_insert parameters must have the same element " "vector_insert parameters must have the same element "
"type.", "type.",
&Call); &Call);
Check(IdxN % SubVecEC.getKnownMinValue() == 0, Check(IdxN % SubVecEC.getKnownMinValue() == 0,
"experimental_vector_insert index must be a constant multiple of " "vector_insert index must be a constant multiple of "
"the subvector's known minimum vector length."); "the subvector's known minimum vector length.");
// If this insertion is not the 'mixed' case where a fixed vector is // If this insertion is not the 'mixed' case where a fixed vector is
// inserted into a scalable vector, ensure that the insertion of the // inserted into a scalable vector, ensure that the insertion of the
// subvector does not overrun the parent vector. // subvector does not overrun the parent vector.
if (VecEC.isScalable() == SubVecEC.isScalable()) { if (VecEC.isScalable() == SubVecEC.isScalable()) {
Check(IdxN < VecEC.getKnownMinValue() && Check(IdxN < VecEC.getKnownMinValue() &&
IdxN + SubVecEC.getKnownMinValue() <= VecEC.getKnownMinValue(), IdxN + SubVecEC.getKnownMinValue() <= VecEC.getKnownMinValue(),
"subvector operand of experimental_vector_insert would overrun the " "subvector operand of vector_insert would overrun the "
"vector being inserted into."); "vector being inserted into.");
} }
break; break;
} }
case Intrinsic::experimental_vector_extract: { case Intrinsic::vector_extract: {
Value *Vec = Call.getArgOperand(0); Value *Vec = Call.getArgOperand(0);
Value *Idx = Call.getArgOperand(1); Value *Idx = Call.getArgOperand(1);
unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue(); unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
VectorType *ResultTy = cast<VectorType>(Call.getType()); VectorType *ResultTy = cast<VectorType>(Call.getType());
VectorType *VecTy = cast<VectorType>(Vec->getType()); VectorType *VecTy = cast<VectorType>(Vec->getType());
ElementCount VecEC = VecTy->getElementCount(); ElementCount VecEC = VecTy->getElementCount();
ElementCount ResultEC = ResultTy->getElementCount(); ElementCount ResultEC = ResultTy->getElementCount();
Check(ResultTy->getElementType() == VecTy->getElementType(), Check(ResultTy->getElementType() == VecTy->getElementType(),
"experimental_vector_extract result must have the same element " "vector_extract result must have the same element "
"type as the input vector.", "type as the input vector.",
&Call); &Call);
Check(IdxN % ResultEC.getKnownMinValue() == 0, Check(IdxN % ResultEC.getKnownMinValue() == 0,
"experimental_vector_extract index must be a constant multiple of " "vector_extract index must be a constant multiple of "
"the result type's known minimum vector length."); "the result type's known minimum vector length.");
// If this extraction is not the 'mixed' case where a fixed vector is is // If this extraction is not the 'mixed' case where a fixed vector is is
// extracted from a scalable vector, ensure that the extraction does not // extracted from a scalable vector, ensure that the extraction does not
// overrun the parent vector. // overrun the parent vector.
if (VecEC.isScalable() == ResultEC.isScalable()) { if (VecEC.isScalable() == ResultEC.isScalable()) {
Check(IdxN < VecEC.getKnownMinValue() && Check(IdxN < VecEC.getKnownMinValue() &&
IdxN + ResultEC.getKnownMinValue() <= VecEC.getKnownMinValue(), IdxN + ResultEC.getKnownMinValue() <= VecEC.getKnownMinValue(),
"experimental_vector_extract would overrun."); "vector_extract would overrun.");
} }
break; break;
} }
case Intrinsic::experimental_noalias_scope_decl: { case Intrinsic::experimental_noalias_scope_decl: {
NoAliasScopeDecls.push_back(cast<IntrinsicInst>(&Call)); NoAliasScopeDecls.push_back(cast<IntrinsicInst>(&Call));
break; break;
} }
case Intrinsic::preserve_array_access_index: case Intrinsic::preserve_array_access_index:
▲ Show 20 Lines • Show All 1,026 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Show First 20 Lines • Show All 646 Lines • ▼ Show 20 Lines if (!DupQLane ||
DupQLane->getIntrinsicID() != Intrinsic::aarch64_sve_dupq_lane) DupQLane->getIntrinsicID() != Intrinsic::aarch64_sve_dupq_lane)
return None; return None;
// Where the dupq is a lane 0 replicate of a vector insert // Where the dupq is a lane 0 replicate of a vector insert
if (!cast<ConstantInt>(DupQLane->getArgOperand(1))->isZero()) if (!cast<ConstantInt>(DupQLane->getArgOperand(1))->isZero())
return None; return None;
auto *VecIns = dyn_cast<IntrinsicInst>(DupQLane->getArgOperand(0)); auto *VecIns = dyn_cast<IntrinsicInst>(DupQLane->getArgOperand(0));
if (!VecIns || if (!VecIns || VecIns->getIntrinsicID() != Intrinsic::vector_insert)
VecIns->getIntrinsicID() != Intrinsic::experimental_vector_insert)
return None; return None;
// Where the vector insert is a fixed constant vector insert into undef at // Where the vector insert is a fixed constant vector insert into undef at
// index zero // index zero
if (!isa<UndefValue>(VecIns->getArgOperand(0))) if (!isa<UndefValue>(VecIns->getArgOperand(0)))
return None; return None;
if (!cast<ConstantInt>(VecIns->getArgOperand(2))->isZero()) if (!cast<ConstantInt>(VecIns->getArgOperand(2))->isZero())
▲ Show 20 Lines • Show All 2,247 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines if (!Store || !Store->isSimple())
return false; return false;
// ..that is storing a predicate vector sized worth of bits.. // ..that is storing a predicate vector sized worth of bits..
if (Store->getOperand(0)->getType() != FixedPredType) if (Store->getOperand(0)->getType() != FixedPredType)
return false; return false;
// ..where the value stored comes from a vector extract.. // ..where the value stored comes from a vector extract..
auto *IntrI = dyn_cast<IntrinsicInst>(Store->getOperand(0)); auto *IntrI = dyn_cast<IntrinsicInst>(Store->getOperand(0));
if (!IntrI || if (!IntrI || IntrI->getIntrinsicID() != Intrinsic::vector_extract)
IntrI->getIntrinsicID() != Intrinsic::experimental_vector_extract)
return false; return false;
// ..that is extracting from index 0.. // ..that is extracting from index 0..
if (!cast<ConstantInt>(IntrI->getOperand(1))->isZero()) if (!cast<ConstantInt>(IntrI->getOperand(1))->isZero())
return false; return false;
// ..where the value being extract from comes from a bitcast // ..where the value being extract from comes from a bitcast
auto *BitCast = dyn_cast<BitCastInst>(IntrI->getOperand(0)); auto *BitCast = dyn_cast<BitCastInst>(IntrI->getOperand(0));
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesbool SVEIntrinsicOpts::optimizePredicateLoad(Instruction *I) {
// If we have a bitcast.. // If we have a bitcast..
auto *BitCast = dyn_cast<BitCastInst>(I); auto *BitCast = dyn_cast<BitCastInst>(I);
if (!BitCast || BitCast->getType() != PredType) if (!BitCast || BitCast->getType() != PredType)
return false; return false;
// ..whose operand is a vector_insert.. // ..whose operand is a vector_insert..
auto *IntrI = dyn_cast<IntrinsicInst>(BitCast->getOperand(0)); auto *IntrI = dyn_cast<IntrinsicInst>(BitCast->getOperand(0));
if (!IntrI || if (!IntrI || IntrI->getIntrinsicID() != Intrinsic::vector_insert)
IntrI->getIntrinsicID() != Intrinsic::experimental_vector_insert)
return false; return false;
// ..that is inserting into index zero of an undef vector.. // ..that is inserting into index zero of an undef vector..
if (!isa<UndefValue>(IntrI->getOperand(0)) || if (!isa<UndefValue>(IntrI->getOperand(0)) ||
!cast<ConstantInt>(IntrI->getOperand(2))->isZero()) !cast<ConstantInt>(IntrI->getOperand(2))->isZero())
return false; return false;
// ..where the value inserted comes from a load.. // ..where the value inserted comes from a load..
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesbool SVEIntrinsicOpts::runOnModule(Module &M) {
// Check for SVE intrinsic declarations first so that we only iterate over // Check for SVE intrinsic declarations first so that we only iterate over
// relevant functions. Where an appropriate declaration is found, store the // relevant functions. Where an appropriate declaration is found, store the
// function(s) where it is used so we can target these only. // function(s) where it is used so we can target these only.
for (auto &F : M.getFunctionList()) { for (auto &F : M.getFunctionList()) {
if (!F.isDeclaration()) if (!F.isDeclaration())
continue; continue;
switch (F.getIntrinsicID()) { switch (F.getIntrinsicID()) {
case Intrinsic::experimental_vector_extract: case Intrinsic::vector_extract:
case Intrinsic::experimental_vector_insert: case Intrinsic::vector_insert:
case Intrinsic::aarch64_sve_ptrue: case Intrinsic::aarch64_sve_ptrue:
for (User *U : F.users()) for (User *U : F.users())
Functions.insert(cast<Instruction>(U)->getFunction()); Functions.insert(cast<Instruction>(U)->getFunction());
break; break;
default: default:
break; break;
} }
} }
if (!Functions.empty()) if (!Functions.empty())
Changed |= optimizeFunctions(Functions); Changed |= optimizeFunctions(Functions);
return Changed; return Changed;
} }

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Show First 20 Lines • Show All 2,351 Lines • ▼ Show 20 Lines if (match(NextInst,
} }
replaceOperand(*II, 0, Builder.CreateAnd(CurrCond, NextCond)); replaceOperand(*II, 0, Builder.CreateAnd(CurrCond, NextCond));
} }
eraseInstFromFunction(*NextInst); eraseInstFromFunction(*NextInst);
return II; return II;
} }
break; break;
} }
case Intrinsic::experimental_vector_insert: { case Intrinsic::vector_insert: {
Value *Vec = II->getArgOperand(0); Value *Vec = II->getArgOperand(0);
Value *SubVec = II->getArgOperand(1); Value *SubVec = II->getArgOperand(1);
Value *Idx = II->getArgOperand(2); Value *Idx = II->getArgOperand(2);
auto *DstTy = dyn_cast<FixedVectorType>(II->getType()); auto *DstTy = dyn_cast<FixedVectorType>(II->getType());
auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType()); auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType());
// Only canonicalize if the destination vector, Vec, and SubVec are all // Only canonicalize if the destination vector, Vec, and SubVec are all
Show All 29 Lines if (DstTy && VecTy && SubVecTy) {
for (unsigned i = IdxN + SubVecNumElts; i != DstNumElts; ++i) for (unsigned i = IdxN + SubVecNumElts; i != DstNumElts; ++i)
Mask.push_back(i); Mask.push_back(i);
Value *Shuffle = Builder.CreateShuffleVector(Vec, WidenShuffle, Mask); Value *Shuffle = Builder.CreateShuffleVector(Vec, WidenShuffle, Mask);
return replaceInstUsesWith(CI, Shuffle); return replaceInstUsesWith(CI, Shuffle);
} }
break; break;
} }
case Intrinsic::experimental_vector_extract: { case Intrinsic::vector_extract: {
Value *Vec = II->getArgOperand(0); Value *Vec = II->getArgOperand(0);
Value *Idx = II->getArgOperand(1); Value *Idx = II->getArgOperand(1);
auto *DstTy = dyn_cast<FixedVectorType>(II->getType()); auto *DstTy = dyn_cast<FixedVectorType>(II->getType());
auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType()); auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
// Only canonicalize if the the destination vector and Vec are fixed // Only canonicalize if the the destination vector and Vec are fixed
// vectors. // vectors.
▲ Show 20 Lines • Show All 1,216 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes='print<cost-model>' 2>&1 -disable-output -S -mtriple=aarch64--linux-gnu -mattr=+sve | FileCheck %s ; RUN: opt < %s -passes='print<cost-model>' 2>&1 -disable-output -S -mtriple=aarch64--linux-gnu -mattr=+sve | FileCheck %s
define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) { define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) {
; CHECK-LABEL: 'vector_insert_extract' ; CHECK-LABEL: 'vector_insert_extract'
; CHECK-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
; ;
%extract_fixed_from_scalable = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0) %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
%insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0) %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
%extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0) %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
%insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0) %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
ret void ret void
} }
declare <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64) declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32>, i64)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64) declare <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64)
define void @reductions(<vscale x 4 x i32> %v0, <vscale x 4 x i64> %v1, <vscale x 4 x float> %v2, <vscale x 4 x double> %v3) { define void @reductions(<vscale x 4 x i32> %v0, <vscale x 4 x i64> %v1, <vscale x 4 x float> %v2, <vscale x 4 x double> %v3) {
; CHECK-LABEL: 'reductions' ; CHECK-LABEL: 'reductions'
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %add_nxv4i32 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %add_nxv4i32 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %add_nxv4i64 = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %add_nxv4i64 = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v1)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i32 = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v0) ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i32 = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v0)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i64 = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v1) ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %mul_nxv4i64 = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v1)
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llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll

Show All 30 Lines;
%9 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer %9 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
%10 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer %10 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
%11 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer %11 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
ret void ret void
} }
define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) { define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) {
; CHECK-LABEL: 'vector_insert_extract' ; CHECK-LABEL: 'vector_insert_extract'
; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
%extract_fixed_from_scalable = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0) %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
%insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0) %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
%extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0) %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
%insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0) %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
ret void ret void
} }
declare <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64) declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32>, i64)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64) declare <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64)
define void @vector_reverse() { define void @vector_reverse() {
; CHECK-LABEL: 'vector_reverse' ; CHECK-LABEL: 'vector_reverse'
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i8 = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i8 = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv32i8 = call <vscale x 32 x i8> @llvm.experimental.vector.reverse.nxv32i8(<vscale x 32 x i8> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv32i8 = call <vscale x 32 x i8> @llvm.experimental.vector.reverse.nxv32i8(<vscale x 32 x i8> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call <vscale x 2 x i16> @llvm.experimental.vector.reverse.nxv2i16(<vscale x 2 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call <vscale x 2 x i16> @llvm.experimental.vector.reverse.nxv2i16(<vscale x 2 x i16> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call <vscale x 4 x i16> @llvm.experimental.vector.reverse.nxv4i16(<vscale x 4 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call <vscale x 4 x i16> @llvm.experimental.vector.reverse.nxv4i16(<vscale x 4 x i16> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i16 = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i16 = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> undef)
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/Bitcode/upgrade-vector-insert-extract-intrinsics.ll

  • This file was added.
; RUN: opt -S < %s | FileCheck %s
; RUN: llvm-dis < %s.bc | FileCheck %s
define <vscale x 16 x i8> @insert(<vscale x 16 x i8> %a, <4 x i8> %b) {
; CHECK-LABEL: @insert
; CHECK: %res = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v4i8(<vscale x 16 x i8> %a, <4 x i8> %b, i64 0)
%res = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i8(<vscale x 16 x i8> %a, <4 x i8> %b, i64 0)
ret <vscale x 16 x i8> %res
}
define <4 x i8> @extract(<vscale x 16 x i8> %a) {
; CHECK-LABEL: @extract
; CHECK: %res = call <4 x i8> @llvm.vector.extract.v4i8.nxv16i8(<vscale x 16 x i8> %a, i64 0)
%res = call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv16i8(<vscale x 16 x i8> %a, i64 0)
ret <4 x i8> %res
}
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i8(<vscale x 16 x i8>, <4 x i8>, i64 immarg)
; CHECK: declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v4i8(<vscale x 16 x i8>, <4 x i8>, i64 immarg)
declare <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv16i8(<vscale x 16 x i8>, i64 immarg)
; CHECK: declare <4 x i8> @llvm.vector.extract.v4i8.nxv16i8(<vscale x 16 x i8>, i64 immarg)

llvm/test/Bitcode/upgrade-vector-insert-extract-intrinsics.ll.bc

  • This binary file was added.

llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll

; RUN: llc < %s -o /dev/null ; RUN: llc < %s -o /dev/null
; This regression test is defending against a use of the wrong interface ; This regression test is defending against a use of the wrong interface
; (EVT::getVectorNumElements()) for a scalable vector. This issue ; (EVT::getVectorNumElements()) for a scalable vector. This issue
; appeared in DAGCombiner::visitINSERT_SUBVECTOR because of the use of ; appeared in DAGCombiner::visitINSERT_SUBVECTOR because of the use of
; getVectorNumElements() on scalable types. ; getVectorNumElements() on scalable types.
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
attributes #0 = {"target-features"="+sve"} attributes #0 = {"target-features"="+sve"}
declare <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64) declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64)
declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64) declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64)
define <vscale x 2 x double> @reproducer_one(<vscale x 4 x float> %vec_a) #0 { define <vscale x 2 x double> @reproducer_one(<vscale x 4 x float> %vec_a) #0 {
%a = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %vec_a, i64 0) %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %vec_a, i64 0)
%b = bitcast <16 x float> %a to <8 x double> %b = bitcast <16 x float> %a to <8 x double>
%retval = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> %b, i64 0) %retval = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> %b, i64 0)
ret <vscale x 2 x double> %retval ret <vscale x 2 x double> %retval
} }
define <vscale x 2 x double> @reproducer_two(<4 x double> %a, <4 x double> %b) #0 { define <vscale x 2 x double> @reproducer_two(<4 x double> %a, <4 x double> %b) #0 {
%concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%retval = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> %concat, i64 0) %retval = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> %concat, i64 0)
ret <vscale x 2 x double> %retval ret <vscale x 2 x double> %retval
} }

llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll

Show All 11 Lines
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1] ; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b %subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 0) %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 0)
ret <vscale x 8 x i8> %ins ret <vscale x 8 x i8> %ins
} }
define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 { define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8: ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1] ; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b %subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 4) %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 4)
ret <vscale x 8 x i8> %ins ret <vscale x 8 x i8> %ins
} }
define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 { define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16: ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1] ; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a %vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b %subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 0) %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 0)
ret <vscale x 4 x i16> %ins ret <vscale x 4 x i16> %ins
} }
define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 { define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16: ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1] ; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a %vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b %subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2) %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2)
ret <vscale x 4 x i16> %ins ret <vscale x 4 x i16> %ins
} }
; FIXED INSERTED INTO SCALABLE TESTS ; FIXED INSERTED INTO SCALABLE TESTS
define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 { define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: mov z0.h, p0/m, z1.h ; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <8 x i8>, <8 x i8>* %b %subvec = load <8 x i8>, <8 x i8>* %b
%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 0) %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 0)
ret <vscale x 8 x i8> %ins ret <vscale x 8 x i8> %ins
} }
define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 { define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a %vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <8 x i8>, <8 x i8>* %b %subvec = load <8 x i8>, <8 x i8>* %b
%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 8) %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 8)
ret <vscale x 8 x i8> %ins ret <vscale x 8 x i8> %ins
} }
define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 { define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: mov z0.s, p0/m, z1.s ; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a %vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <4 x i16>, <4 x i16>* %b %subvec = load <4 x i16>, <4 x i16>* %b
%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 0) %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 0)
ret <vscale x 4 x i16> %ins ret <vscale x 4 x i16> %ins
} }
define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 { define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a %vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <4 x i16>, <4 x i16>* %b %subvec = load <4 x i16>, <4 x i16>* %b
%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 4) %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 4)
ret <vscale x 4 x i16> %ins ret <vscale x 4 x i16> %ins
} }
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 { define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-NEXT: mov z0.d, p0/m, z1.d ; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a %vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <2 x i32>, <2 x i32>* %b %subvec = load <2 x i32>, <2 x i32>* %b
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 0) %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 0)
ret <vscale x 2 x i32> %ins ret <vscale x 2 x i32> %ins
} }
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 { define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a %vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <2 x i32>, <2 x i32>* %b %subvec = load <2 x i32>, <2 x i32>* %b
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 2) %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 2)
ret <vscale x 2 x i32> %ins ret <vscale x 2 x i32> %ins
} }
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vscale x 2 x i32>* %a, <8 x i32>* %b) #1 { define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vscale x 2 x i32>* %a, <8 x i32>* %b) #1 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3] ; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a %vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <8 x i32>, <8 x i32>* %b %subvec = load <8 x i32>, <8 x i32>* %b
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> %vec, <8 x i32> %subvec, i64 8) %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> %vec, <8 x i32> %subvec, i64 8)
ret <vscale x 2 x i32> %ins ret <vscale x 2 x i32> %ins
} }
declare <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8>, <vscale x 4 x i8>, i64) declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8>, <vscale x 4 x i8>, i64)
declare <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16>, <vscale x 2 x i16>, i64) declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16>, <vscale x 2 x i16>, i64)
declare <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8>, <8 x i8>, i64) declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8>, <8 x i8>, i64)
declare <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16>, <4 x i16>, i64) declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16>, <4 x i16>, i64)
declare <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32>, <2 x i32>, i64) declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32>, <2 x i32>, i64)
declare <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64) declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64)
attributes #0 = { nounwind "target-features"="+sve" } attributes #0 = { nounwind "target-features"="+sve" }
attributes #1 = { nounwind "target-features"="+sve" vscale_range(4,4) } attributes #1 = { nounwind "target-features"="+sve" vscale_range(4,4) }

llvm/test/CodeGen/AArch64/split-vector-insert.ll

; RUN: llc < %s -debug-only=legalize-types 2>&1 | FileCheck %s --check-prefix=CHECK-LEGALIZATION ; RUN: llc < %s -debug-only=legalize-types 2>&1 | FileCheck %s --check-prefix=CHECK-LEGALIZATION
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
attributes #0 = {"target-features"="+sve" uwtable} attributes #0 = {"target-features"="+sve" uwtable}
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64) declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64)
declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64) declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64)
define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %b) #0 { define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %b) #0 {
; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2i64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0> ; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2i64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0>
; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2i64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2> ; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2i64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2>
; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2i64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4> ; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2i64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4>
; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2i64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6> ; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2i64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6>
; CHECK-LABEL: test_nxv2i64_v8i64: ; CHECK-LABEL: test_nxv2i64_v8i64:
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> %a, <8 x i64> %b, i64 0) %r = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> %a, <8 x i64> %b, i64 0)
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x double> %b) #0 { define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x double> %b) #0 {
; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2f64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0> ; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2f64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0>
; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2f64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2> ; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2f64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2>
; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2f64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4> ; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2f64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4>
; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2f64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6> ; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2f64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6>
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0) %r = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0)
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }

llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll

; RUN: not --crash llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; RUN: not --crash llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
; Extracting a fixed-length vector from an illegal subvector ; Extracting a fixed-length vector from an illegal subvector
; CHECK-ERROR: ERROR: Extracting a fixed-length vector from an illegal scalable vector is not yet supported ; CHECK-ERROR: ERROR: Extracting a fixed-length vector from an illegal scalable vector is not yet supported
define <4 x i32> @extract_v4i32_nxv16i32_12(<vscale x 16 x i32> %arg) { define <4 x i32> @extract_v4i32_nxv16i32_12(<vscale x 16 x i32> %arg) {
%ext = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32> %arg, i64 12) %ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32> %arg, i64 12)
ret <4 x i32> %ext ret <4 x i32> %ext
} }
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.nxv16i32(<vscale x 16 x i32>, i64)

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK
; Should codegen to a nop, since idx is zero. ; Should codegen to a nop, since idx is zero.
define <2 x i64> @extract_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind { define <2 x i64> @extract_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind {
; CHECK-LABEL: extract_v2i64_nxv2i64: ; CHECK-LABEL: extract_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 0) %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 0)
ret <2 x i64> %retval ret <2 x i64> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <2 x i64> @extract_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec) nounwind { define <2 x i64> @extract_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec) nounwind {
; CHECK-LABEL: extract_v2i64_nxv2i64_idx2: ; CHECK-LABEL: extract_v2i64_nxv2i64_idx2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2) %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2)
ret <2 x i64> %retval ret <2 x i64> %retval
} }
; Should codegen to a nop, since idx is zero. ; Should codegen to a nop, since idx is zero.
define <4 x i32> @extract_v4i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind { define <4 x i32> @extract_v4i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
; CHECK-LABEL: extract_v4i32_nxv4i32: ; CHECK-LABEL: extract_v4i32_nxv4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0) %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
ret <4 x i32> %retval ret <4 x i32> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <4 x i32> @extract_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec) nounwind { define <4 x i32> @extract_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec) nounwind {
; CHECK-LABEL: extract_v4i32_nxv4i32_idx4: ; CHECK-LABEL: extract_v4i32_nxv4i32_idx4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntw x8 ; CHECK-NEXT: cntw x8
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: sub x8, x8, #4 ; CHECK-NEXT: sub x8, x8, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 4) %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 4)
ret <4 x i32> %retval ret <4 x i32> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <4 x i32> @extract_v4i32_nxv2i32(<vscale x 2 x i32> %vec) nounwind #1 { define <4 x i32> @extract_v4i32_nxv2i32(<vscale x 2 x i32> %vec) nounwind #1 {
; CHECK-LABEL: extract_v4i32_nxv2i32: ; CHECK-LABEL: extract_v4i32_nxv2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0) %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
ret <4 x i32> %retval ret <4 x i32> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <4 x i32> @extract_v4i32_nxv2i32_idx4(<vscale x 2 x i32> %vec) nounwind #1 { define <4 x i32> @extract_v4i32_nxv2i32_idx4(<vscale x 2 x i32> %vec) nounwind #1 {
; CHECK-LABEL: extract_v4i32_nxv2i32_idx4: ; CHECK-LABEL: extract_v4i32_nxv2i32_idx4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 4) %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 4)
ret <4 x i32> %retval ret <4 x i32> %retval
} }
; Should codegen to a nop, since idx is zero. ; Should codegen to a nop, since idx is zero.
define <8 x i16> @extract_v8i16_nxv8i16(<vscale x 8 x i16> %vec) nounwind { define <8 x i16> @extract_v8i16_nxv8i16(<vscale x 8 x i16> %vec) nounwind {
; CHECK-LABEL: extract_v8i16_nxv8i16: ; CHECK-LABEL: extract_v8i16_nxv8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 0) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 0)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <8 x i16> @extract_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec) nounwind { define <8 x i16> @extract_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec) nounwind {
; CHECK-LABEL: extract_v8i16_nxv8i16_idx8: ; CHECK-LABEL: extract_v8i16_nxv8i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cnth x8 ; CHECK-NEXT: cnth x8
; CHECK-NEXT: mov w9, #8 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: sub x8, x8, #8 ; CHECK-NEXT: sub x8, x8, #8
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: cmp x8, #8 ; CHECK-NEXT: cmp x8, #8
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: lsl x8, x8, #1
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 8) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 8)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <8 x i16> @extract_v8i16_nxv4i16(<vscale x 4 x i16> %vec) nounwind #1 { define <8 x i16> @extract_v8i16_nxv4i16(<vscale x 4 x i16> %vec) nounwind #1 {
; CHECK-LABEL: extract_v8i16_nxv4i16: ; CHECK-LABEL: extract_v8i16_nxv4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 0) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 0)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <8 x i16> @extract_v8i16_nxv4i16_idx8(<vscale x 4 x i16> %vec) nounwind #1 { define <8 x i16> @extract_v8i16_nxv4i16_idx8(<vscale x 4 x i16> %vec) nounwind #1 {
; CHECK-LABEL: extract_v8i16_nxv4i16_idx8: ; CHECK-LABEL: extract_v8i16_nxv4i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x9, x8, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x9, x8, lsl #2]
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 8) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 8)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <8 x i16> @extract_v8i16_nxv2i16(<vscale x 2 x i16> %vec) nounwind #1 { define <8 x i16> @extract_v8i16_nxv2i16(<vscale x 2 x i16> %vec) nounwind #1 {
; CHECK-LABEL: extract_v8i16_nxv2i16: ; CHECK-LABEL: extract_v8i16_nxv2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 0) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 0)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <8 x i16> @extract_v8i16_nxv2i16_idx8(<vscale x 2 x i16> %vec) nounwind #1 { define <8 x i16> @extract_v8i16_nxv2i16_idx8(<vscale x 2 x i16> %vec) nounwind #1 {
; CHECK-LABEL: extract_v8i16_nxv2i16_idx8: ; CHECK-LABEL: extract_v8i16_nxv2i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Show All 10 Lines
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 8) %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 8)
ret <8 x i16> %retval ret <8 x i16> %retval
} }
; Should codegen to a nop, since idx is zero. ; Should codegen to a nop, since idx is zero.
define <16 x i8> @extract_v16i8_nxv16i8(<vscale x 16 x i8> %vec) nounwind { define <16 x i8> @extract_v16i8_nxv16i8(<vscale x 16 x i8> %vec) nounwind {
; CHECK-LABEL: extract_v16i8_nxv16i8: ; CHECK-LABEL: extract_v16i8_nxv16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 0) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind { define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind {
; CHECK-LABEL: extract_v16i8_nxv16i8_idx16: ; CHECK-LABEL: extract_v16i8_nxv16i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: mov x8, #-16 ; CHECK-NEXT: mov x8, #-16
; CHECK-NEXT: mov w9, #16 ; CHECK-NEXT: mov w9, #16
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: cmp x8, #16 ; CHECK-NEXT: cmp x8, #16
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 16) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 16)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <16 x i8> @extract_v16i8_nxv8i8(<vscale x 8 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv8i8(<vscale x 8 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv8i8: ; CHECK-LABEL: extract_v16i8_nxv8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 0) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 0)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <16 x i8> @extract_v16i8_nxv8i8_idx16(<vscale x 8 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv8i8_idx16(<vscale x 8 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv8i8_idx16: ; CHECK-LABEL: extract_v16i8_nxv8i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x9, x8, lsl #1] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x9, x8, lsl #1]
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 16) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 16)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <16 x i8> @extract_v16i8_nxv4i8(<vscale x 4 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv4i8(<vscale x 4 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv4i8: ; CHECK-LABEL: extract_v16i8_nxv4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 0) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 0)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <16 x i8> @extract_v16i8_nxv4i8_idx16(<vscale x 4 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv4i8_idx16(<vscale x 4 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv4i8_idx16: ; CHECK-LABEL: extract_v16i8_nxv4i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x9, x8, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x9, x8, lsl #2]
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 16) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 16)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Should codegen to uzps, since idx is zero and type is illegal. ; Should codegen to uzps, since idx is zero and type is illegal.
define <16 x i8> @extract_v16i8_nxv2i8(<vscale x 2 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv2i8(<vscale x 2 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv2i8: ; CHECK-LABEL: extract_v16i8_nxv2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 0) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 0)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <16 x i8> @extract_v16i8_nxv2i8_idx16(<vscale x 2 x i8> %vec) nounwind #1 { define <16 x i8> @extract_v16i8_nxv2i8_idx16(<vscale x 2 x i8> %vec) nounwind #1 {
; CHECK-LABEL: extract_v16i8_nxv2i8_idx16: ; CHECK-LABEL: extract_v16i8_nxv2i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9, x8, lsl #3]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 16) %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 16)
ret <16 x i8> %retval ret <16 x i8> %retval
} }
; Predicates ; Predicates
define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) { define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) {
; CHECK-LABEL: extract_v2i1_nxv2i1: ; CHECK-LABEL: extract_v2i1_nxv2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: mov x8, v0.d[1] ; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0) %mask = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0)
ret <2 x i1> %mask ret <2 x i1> %mask
} }
define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) { define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) {
; CHECK-LABEL: extract_v4i1_nxv4i1: ; CHECK-LABEL: extract_v4i1_nxv4i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov w8, v1.s[1]
; CHECK-NEXT: mov w9, v1.s[2] ; CHECK-NEXT: mov w9, v1.s[2]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: mov w8, v1.s[3] ; CHECK-NEXT: mov w8, v1.s[3]
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1> %inmask, i64 0) %mask = call <4 x i1> @llvm.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1> %inmask, i64 0)
ret <4 x i1> %mask ret <4 x i1> %mask
} }
define <8 x i1> @extract_v8i1_nxv8i1(<vscale x 8 x i1> %inmask) { define <8 x i1> @extract_v8i1_nxv8i1(<vscale x 8 x i1> %inmask) {
; CHECK-LABEL: extract_v8i1_nxv8i1: ; CHECK-LABEL: extract_v8i1_nxv8i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: umov w9, v1.h[2] ; CHECK-NEXT: umov w9, v1.h[2]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: mov v0.b[1], w8 ; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: mov v0.b[2], w9 ; CHECK-NEXT: mov v0.b[2], w9
; CHECK-NEXT: umov w9, v1.h[4] ; CHECK-NEXT: umov w9, v1.h[4]
; CHECK-NEXT: mov v0.b[3], w8 ; CHECK-NEXT: mov v0.b[3], w8
; CHECK-NEXT: umov w8, v1.h[5] ; CHECK-NEXT: umov w8, v1.h[5]
; CHECK-NEXT: mov v0.b[4], w9 ; CHECK-NEXT: mov v0.b[4], w9
; CHECK-NEXT: umov w9, v1.h[6] ; CHECK-NEXT: umov w9, v1.h[6]
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: umov w8, v1.h[7] ; CHECK-NEXT: umov w8, v1.h[7]
; CHECK-NEXT: mov v0.b[6], w9 ; CHECK-NEXT: mov v0.b[6], w9
; CHECK-NEXT: mov v0.b[7], w8 ; CHECK-NEXT: mov v0.b[7], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1> %inmask, i64 0) %mask = call <8 x i1> @llvm.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1> %inmask, i64 0)
ret <8 x i1> %mask ret <8 x i1> %mask
} }
define <16 x i1> @extract_v16i1_nxv16i1(<vscale x 16 x i1> %inmask) { define <16 x i1> @extract_v16i1_nxv16i1(<vscale x 16 x i1> %inmask) {
; CHECK-LABEL: extract_v16i1_nxv16i1: ; CHECK-LABEL: extract_v16i1_nxv16i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
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; CHECK-NEXT: umov w8, v1.b[13] ; CHECK-NEXT: umov w8, v1.b[13]
; CHECK-NEXT: mov v0.b[12], w9 ; CHECK-NEXT: mov v0.b[12], w9
; CHECK-NEXT: umov w9, v1.b[14] ; CHECK-NEXT: umov w9, v1.b[14]
; CHECK-NEXT: mov v0.b[13], w8 ; CHECK-NEXT: mov v0.b[13], w8
; CHECK-NEXT: umov w8, v1.b[15] ; CHECK-NEXT: umov w8, v1.b[15]
; CHECK-NEXT: mov v0.b[14], w9 ; CHECK-NEXT: mov v0.b[14], w9
; CHECK-NEXT: mov v0.b[15], w8 ; CHECK-NEXT: mov v0.b[15], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1> %inmask, i64 0) %mask = call <16 x i1> @llvm.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1> %inmask, i64 0)
ret <16 x i1> %mask ret <16 x i1> %mask
} }
; Fixed length clamping ; Fixed length clamping
define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 { define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
; CHECK-LABEL: extract_fixed_v2i64_nxv2i64: ; CHECK-LABEL: extract_fixed_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2) %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2)
ret <2 x i64> %retval ret <2 x i64> %retval
} }
define <4 x i64> @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 { define <4 x i64> @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
; CHECK-LABEL: extract_fixed_v4i64_nxv2i64: ; CHECK-LABEL: extract_fixed_v4i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: mov w10, #4 ; CHECK-NEXT: mov w10, #4
; CHECK-NEXT: subs x9, x9, #4 ; CHECK-NEXT: subs x9, x9, #4
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: csel x9, xzr, x9, lo ; CHECK-NEXT: csel x9, xzr, x9, lo
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: cmp x9, #4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: mov x10, sp ; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x10, x9, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x10, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8] ; CHECK-NEXT: st1d { z0.d }, p0, [x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> %vec, i64 4) %retval = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> %vec, i64 4)
ret <4 x i64> %retval ret <4 x i64> %retval
} }
; Check that extract from load via bitcast-gep-of-scalar-ptr does not crash. ; Check that extract from load via bitcast-gep-of-scalar-ptr does not crash.
define <4 x i32> @typesize_regression_test_v4i32(i32* %addr, i64 %idx) { define <4 x i32> @typesize_regression_test_v4i32(i32* %addr, i64 %idx) {
; CHECK-LABEL: typesize_regression_test_v4i32: ; CHECK-LABEL: typesize_regression_test_v4i32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x1, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%ptr = getelementptr inbounds i32, i32* %addr, i64 %idx %ptr = getelementptr inbounds i32, i32* %addr, i64 %idx
%bc = bitcast i32* %ptr to <vscale x 4 x i32>* %bc = bitcast i32* %ptr to <vscale x 4 x i32>*
%ld = load <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16 %ld = load <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16
%out = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0) %out = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0)
ret <4 x i32> %out ret <4 x i32> %out
} }
; ;
; Extract fixed-width vector from a scalable vector splat. ; Extract fixed-width vector from a scalable vector splat.
; ;
define <2 x float> @extract_v2f32_nxv4f32_splat(float %f) { define <2 x float> @extract_v2f32_nxv4f32_splat(float %f) {
; CHECK-LABEL: extract_v2f32_nxv4f32_splat: ; CHECK-LABEL: extract_v2f32_nxv4f32_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: dup v0.2s, v0.s[0] ; CHECK-NEXT: dup v0.2s, v0.s[0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x float> poison, float %f, i32 0 %ins = insertelement <vscale x 4 x float> poison, float %f, i32 0
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%ext = call <2 x float> @llvm.experimental.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0) %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
ret <2 x float> %ext ret <2 x float> %ext
} }
define <2 x float> @extract_v2f32_nxv4f32_splat_const() { define <2 x float> @extract_v2f32_nxv4f32_splat_const() {
; CHECK-LABEL: extract_v2f32_nxv4f32_splat_const: ; CHECK-LABEL: extract_v2f32_nxv4f32_splat_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov v0.2s, #1.00000000 ; CHECK-NEXT: fmov v0.2s, #1.00000000
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0 %ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%ext = call <2 x float> @llvm.experimental.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0) %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
ret <2 x float> %ext ret <2 x float> %ext
} }
define <4 x i32> @extract_v4i32_nxv8i32_splat_const() { define <4 x i32> @extract_v4i32_nxv8i32_splat_const() {
; CHECK-LABEL: extract_v4i32_nxv8i32_splat_const: ; CHECK-LABEL: extract_v4i32_nxv8i32_splat_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.4s, #1 ; CHECK-NEXT: movi v0.4s, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0 %ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%ext = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0) %ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
ret <4 x i32> %ext ret <4 x i32> %ext
} }
attributes #0 = { vscale_range(2,2) } attributes #0 = { vscale_range(2,2) }
attributes #1 = { vscale_range(8,8) } attributes #1 = { vscale_range(8,8) }
declare <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64) declare <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32>, i64)
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64) declare <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64)
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16>, i64) declare <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16>, i64)
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16>, i64) declare <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8>, i64)
declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1>, i64) declare <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1>, i64)
declare <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1>, i64) declare <4 x i1> @llvm.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1>, i64)
declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1>, i64) declare <8 x i1> @llvm.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1>, i64)
declare <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1>, i64) declare <16 x i1> @llvm.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1>, i64)
declare <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64>, i64) declare <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64>, i64)
declare <2 x float> @llvm.experimental.vector.extract.v2f32.nxv4f32(<vscale x 4 x float>, i64) declare <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32>, i64)

llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK
; Extracting illegal subvectors ; Extracting illegal subvectors
define <vscale x 1 x i32> @extract_nxv1i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind { define <vscale x 1 x i32> @extract_nxv1i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
; CHECK-LABEL: extract_nxv1i32_nxv4i32: ; CHECK-LABEL: extract_nxv1i32_nxv4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0) %retval = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
ret <vscale x 1 x i32> %retval ret <vscale x 1 x i32> %retval
} }
define <vscale x 1 x i16> @extract_nxv1i16_nxv6i16(<vscale x 6 x i16> %vec) nounwind { define <vscale x 1 x i16> @extract_nxv1i16_nxv6i16(<vscale x 6 x i16> %vec) nounwind {
; CHECK-LABEL: extract_nxv1i16_nxv6i16: ; CHECK-LABEL: extract_nxv1i16_nxv6i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16> %vec, i64 0) %retval = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16> %vec, i64 0)
ret <vscale x 1 x i16> %retval ret <vscale x 1 x i16> %retval
} }
declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32>, i64) declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32>, i64)
declare <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16>, i64) declare <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16>, i64)
; ;
; Extract half i1 vector that needs promotion from legal type. ; Extract half i1 vector that needs promotion from legal type.
; ;
define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_0(<vscale x 16 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_0(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv16i1_0: ; CHECK-LABEL: extract_nxv8i1_nxv16i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_8(<vscale x 16 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_8(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv16i1_8: ; CHECK-LABEL: extract_nxv8i1_nxv16i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
declare <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64)
; ;
; Extract i1 vector that needs widening from one that needs widening. ; Extract i1 vector that needs widening from one that needs widening.
; ;
define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_0(<vscale x 28 x i1> %in) { define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_0(<vscale x 28 x i1> %in) {
; CHECK-LABEL: extract_nxv14i1_nxv28i1_0: ; CHECK-LABEL: extract_nxv14i1_nxv28i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 14 x i1> @llvm.experimental.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 0) %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 0)
ret <vscale x 14 x i1> %res ret <vscale x 14 x i1> %res
} }
define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uwtable { define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uwtable {
; CHECK-LABEL: extract_nxv14i1_nxv28i1_14: ; CHECK-LABEL: extract_nxv14i1_nxv28i1_14:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
Show All 26 Lines
; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h ; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 14 x i1> @llvm.experimental.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 14) %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 14)
ret <vscale x 14 x i1> %res ret <vscale x 14 x i1> %res
} }
declare <vscale x 14 x i1> @llvm.experimental.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1>, i64) declare <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1>, i64)
; ;
; Extract half i1 vector that needs promotion from one that needs splitting. ; Extract half i1 vector that needs promotion from one that needs splitting.
; ;
define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_0(<vscale x 32 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_0(<vscale x 32 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv32i1_0: ; CHECK-LABEL: extract_nxv8i1_nxv32i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 0) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 0)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_8(<vscale x 32 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_8(<vscale x 32 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv32i1_8: ; CHECK-LABEL: extract_nxv8i1_nxv32i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 8) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 8)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_16(<vscale x 32 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_16(<vscale x 32 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv32i1_16: ; CHECK-LABEL: extract_nxv8i1_nxv32i1_16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p1.b ; CHECK-NEXT: punpklo p0.h, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 16) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 16)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_24(<vscale x 32 x i1> %in) { define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_24(<vscale x 32 x i1> %in) {
; CHECK-LABEL: extract_nxv8i1_nxv32i1_24: ; CHECK-LABEL: extract_nxv8i1_nxv32i1_24:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p1.b ; CHECK-NEXT: punpkhi p0.h, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 24) %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 24)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
declare <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1>, i64) declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1>, i64)
; ;
; Extract 1/4th i1 vector that needs promotion from legal type. ; Extract 1/4th i1 vector that needs promotion from legal type.
; ;
define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_0(<vscale x 16 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_0(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv16i1_0: ; CHECK-LABEL: extract_nxv4i1_nxv16i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_4(<vscale x 16 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_4(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv16i1_4: ; CHECK-LABEL: extract_nxv4i1_nxv16i1_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 4) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 4)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_8(<vscale x 16 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_8(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv16i1_8: ; CHECK-LABEL: extract_nxv4i1_nxv16i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_12(<vscale x 16 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_12(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv16i1_12: ; CHECK-LABEL: extract_nxv4i1_nxv16i1_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 12) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 12)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
declare <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64)
; ;
; Extract 1/8th i1 vector that needs promotion from legal type. ; Extract 1/8th i1 vector that needs promotion from legal type.
; ;
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_0(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_0(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_0: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 0)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_2(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_2(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_2: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 2) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 2)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_4(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_4(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_4: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 4) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 4)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_6(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_6(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_6: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 6) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 6)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_8(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_8(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_8: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 8)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_10(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_10(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_10: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_10:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 10) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 10)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_12(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_12(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_12: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 12) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 12)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_14(<vscale x 16 x i1> %in) { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_14(<vscale x 16 x i1> %in) {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_14: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_14:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 14) %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 14)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
declare <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64)
; ;
; Extract i1 vector that needs promotion from one that needs widening. ; Extract i1 vector that needs promotion from one that needs widening.
; ;
define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_0(<vscale x 12 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_0(<vscale x 12 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv12i1_0: ; CHECK-LABEL: extract_nxv4i1_nxv12i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 0) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 0)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_4(<vscale x 12 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_4(<vscale x 12 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv12i1_4: ; CHECK-LABEL: extract_nxv4i1_nxv12i1_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 4) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 4)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_8(<vscale x 12 x i1> %in) { define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_8(<vscale x 12 x i1> %in) {
; CHECK-LABEL: extract_nxv4i1_nxv12i1_8: ; CHECK-LABEL: extract_nxv4i1_nxv12i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 8) %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 8)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
declare <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1>, i64) declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1>, i64)
; ;
; Extract 1/8th i8 vector that needs promotion from legal type. ; Extract 1/8th i8 vector that needs promotion from legal type.
; ;
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_0(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_0(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_0: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_2(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_2(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_2: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 2) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 2)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_4(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_4(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_4: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 4) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 4)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_6(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_6(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_6: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 6) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 6)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_8(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_8(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_8: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_10(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_10(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_10: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_10:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 10) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 10)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_12(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_12(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_12: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 12) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 12)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_14(<vscale x 16 x i8> %in) { define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_14(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv2i8_nxv16i8_14: ; CHECK-LABEL: extract_nxv2i8_nxv16i8_14:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 14) %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 14)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
declare <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8>, i64) declare <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8>, i64)
; ;
; Extract i8 vector that needs promotion from one that needs widening. ; Extract i8 vector that needs promotion from one that needs widening.
; ;
define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_0(<vscale x 12 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_0(<vscale x 12 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv12i8_0: ; CHECK-LABEL: extract_nxv4i8_nxv12i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 0) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 0)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_4(<vscale x 12 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_4(<vscale x 12 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv12i8_4: ; CHECK-LABEL: extract_nxv4i8_nxv12i8_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 4) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 4)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_8(<vscale x 12 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_8(<vscale x 12 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv12i8_8: ; CHECK-LABEL: extract_nxv4i8_nxv12i8_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 8) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 8)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
declare <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8>, i64) declare <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8>, i64)
; ;
; Extract i8 vector that needs both widening + promotion from one that needs widening. ; Extract i8 vector that needs both widening + promotion from one that needs widening.
; (nxv6i8 -> nxv8i8 -> nxv8i16) ; (nxv6i8 -> nxv8i8 -> nxv8i16)
; ;
define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_0(<vscale x 12 x i8> %in) { define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_0(<vscale x 12 x i8> %in) {
; CHECK-LABEL: extract_nxv6i8_nxv12i8_0: ; CHECK-LABEL: extract_nxv6i8_nxv12i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x i8> @llvm.experimental.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 0) %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 0)
ret <vscale x 6 x i8> %res ret <vscale x 6 x i8> %res
} }
define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_6(<vscale x 12 x i8> %in) { define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_6(<vscale x 12 x i8> %in) {
; CHECK-LABEL: extract_nxv6i8_nxv12i8_6: ; CHECK-LABEL: extract_nxv6i8_nxv12i8_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z1.h, z0.b ; CHECK-NEXT: uunpkhi z1.h, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z2.d, z1.s ; CHECK-NEXT: uunpkhi z2.d, z1.s
; CHECK-NEXT: uunpklo z1.d, z1.s ; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s ; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x i8> @llvm.experimental.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 6) %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 6)
ret <vscale x 6 x i8> %res ret <vscale x 6 x i8> %res
} }
declare <vscale x 6 x i8> @llvm.experimental.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8>, i64) declare <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8>, i64)
; ;
; Extract half i8 vector that needs promotion from one that needs splitting. ; Extract half i8 vector that needs promotion from one that needs splitting.
; ;
define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_0(<vscale x 32 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_0(<vscale x 32 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv32i8_0: ; CHECK-LABEL: extract_nxv8i8_nxv32i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 0) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 0)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_8(<vscale x 32 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_8(<vscale x 32 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv32i8_8: ; CHECK-LABEL: extract_nxv8i8_nxv32i8_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 8) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 8)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_16(<vscale x 32 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_16(<vscale x 32 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv32i8_16: ; CHECK-LABEL: extract_nxv8i8_nxv32i8_16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z1.b ; CHECK-NEXT: uunpklo z0.h, z1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 16) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 16)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_24(<vscale x 32 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_24(<vscale x 32 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv32i8_24: ; CHECK-LABEL: extract_nxv8i8_nxv32i8_24:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z1.b ; CHECK-NEXT: uunpkhi z0.h, z1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 24) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 24)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
declare <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64) declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64)
; ;
; Extract half i8 vector that needs promotion from legal type. ; Extract half i8 vector that needs promotion from legal type.
; ;
define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_0(<vscale x 16 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_0(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv16i8_0: ; CHECK-LABEL: extract_nxv8i8_nxv16i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_8(<vscale x 16 x i8> %in) { define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_8(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv8i8_nxv16i8_8: ; CHECK-LABEL: extract_nxv8i8_nxv16i8_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
declare <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64) declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64)
; ;
; Extract i8 vector that needs widening from one that needs widening. ; Extract i8 vector that needs widening from one that needs widening.
; ;
define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_0(<vscale x 28 x i8> %in) { define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_0(<vscale x 28 x i8> %in) {
; CHECK-LABEL: extract_nxv14i8_nxv28i8_0: ; CHECK-LABEL: extract_nxv14i8_nxv28i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 14 x i8> @llvm.experimental.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 0) %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 0)
ret <vscale x 14 x i8> %res ret <vscale x 14 x i8> %res
} }
define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_14(<vscale x 28 x i8> %in) { define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_14(<vscale x 28 x i8> %in) {
; CHECK-LABEL: extract_nxv14i8_nxv28i8_14: ; CHECK-LABEL: extract_nxv14i8_nxv28i8_14:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpklo z2.h, z1.b ; CHECK-NEXT: uunpklo z2.h, z1.b
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NEXT: uunpkhi z1.h, z1.b ; CHECK-NEXT: uunpkhi z1.h, z1.b
; CHECK-NEXT: uunpkhi z2.s, z1.h ; CHECK-NEXT: uunpkhi z2.s, z1.h
; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpklo z2.d, z2.s ; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s ; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h ; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 14 x i8> @llvm.experimental.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 14) %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 14)
ret <vscale x 14 x i8> %res ret <vscale x 14 x i8> %res
} }
declare <vscale x 14 x i8> @llvm.experimental.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8>, i64) declare <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8>, i64)
; ;
; Extract 1/4th i8 vector that needs promotion from legal type. ; Extract 1/4th i8 vector that needs promotion from legal type.
; ;
define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_0(<vscale x 16 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_0(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv16i8_0: ; CHECK-LABEL: extract_nxv4i8_nxv16i8_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 0)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_4(<vscale x 16 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_4(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv16i8_4: ; CHECK-LABEL: extract_nxv4i8_nxv16i8_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 4) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 4)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_8(<vscale x 16 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_8(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv16i8_8: ; CHECK-LABEL: extract_nxv4i8_nxv16i8_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 8)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_12(<vscale x 16 x i8> %in) { define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_12(<vscale x 16 x i8> %in) {
; CHECK-LABEL: extract_nxv4i8_nxv16i8_12: ; CHECK-LABEL: extract_nxv4i8_nxv16i8_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.h, z0.b ; CHECK-NEXT: uunpkhi z0.h, z0.b
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 12) %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 12)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
declare <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8>, i64) declare <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8>, i64)
; ;
; Extract f16 vector that needs promotion from one that needs widening. ; Extract f16 vector that needs promotion from one that needs widening.
; ;
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_0: ; CHECK-LABEL: extract_nxv2f16_nxv6f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 0) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 0)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_2: ; CHECK-LABEL: extract_nxv2f16_nxv6f16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 2) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 2)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_4(<vscale x 6 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_4(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_4: ; CHECK-LABEL: extract_nxv2f16_nxv6f16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 4) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 4)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
declare <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half>, i64) declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half>, i64)
; ;
; Extract half f16 vector that needs promotion from legal type. ; Extract half f16 vector that needs promotion from legal type.
; ;
define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_0(<vscale x 8 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_0(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv8f16_0: ; CHECK-LABEL: extract_nxv4f16_nxv8f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 0) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 0)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_4(<vscale x 8 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_4(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv8f16_4: ; CHECK-LABEL: extract_nxv4f16_nxv8f16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 4) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 4)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
declare <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64) declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64)
; ;
; Extract f16 vector that needs widening from one that needs widening. ; Extract f16 vector that needs widening from one that needs widening.
; ;
define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) { define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {
; CHECK-LABEL: extract_nxv6f16_nxv12f16_0: ; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0) %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)
ret <vscale x 6 x half> %res ret <vscale x 6 x half> %res
} }
define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) { define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
; CHECK-LABEL: extract_nxv6f16_nxv12f16_6: ; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z2.d, z1.s ; CHECK-NEXT: uunpkhi z2.d, z1.s
; CHECK-NEXT: uunpklo z1.d, z1.s ; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s ; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6) %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
ret <vscale x 6 x half> %res ret <vscale x 6 x half> %res
} }
declare <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64) declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)
; ;
; Extract half f16 vector that needs promotion from one that needs splitting. ; Extract half f16 vector that needs promotion from one that needs splitting.
; ;
define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_0(<vscale x 16 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_0(<vscale x 16 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv16f16_0: ; CHECK-LABEL: extract_nxv4f16_nxv16f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 0) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 0)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_4(<vscale x 16 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_4(<vscale x 16 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv16f16_4: ; CHECK-LABEL: extract_nxv4f16_nxv16f16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 4) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 4)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_8(<vscale x 16 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_8(<vscale x 16 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv16f16_8: ; CHECK-LABEL: extract_nxv4f16_nxv16f16_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z1.h ; CHECK-NEXT: uunpklo z0.s, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 8) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 8)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_12(<vscale x 16 x half> %in) { define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_12(<vscale x 16 x half> %in) {
; CHECK-LABEL: extract_nxv4f16_nxv16f16_12: ; CHECK-LABEL: extract_nxv4f16_nxv16f16_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z1.h ; CHECK-NEXT: uunpkhi z0.s, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 12) %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 12)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
declare <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64) declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64)
; ;
; Extract 1/4th f16 vector that needs promotion from legal type. ; Extract 1/4th f16 vector that needs promotion from legal type.
; ;
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_0: ; CHECK-LABEL: extract_nxv2f16_nxv8f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 0) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 0)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_2: ; CHECK-LABEL: extract_nxv2f16_nxv8f16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 2) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 2)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_4: ; CHECK-LABEL: extract_nxv2f16_nxv8f16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 4) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 4)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_6(<vscale x 8 x half> %in) { define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_6(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_6: ; CHECK-LABEL: extract_nxv2f16_nxv8f16_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 6) %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 6)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
declare <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64) declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64)
; ;
; Extract half bf16 vector that needs promotion from legal type. ; Extract half bf16 vector that needs promotion from legal type.
; ;
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_0: ; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_4: ; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
declare <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64) declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64)
; ;
; Extract bf16 vector that needs widening from one that needs widening. ; Extract bf16 vector that needs widening from one that needs widening.
; ;
define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) { define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) {
; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0: ; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x bfloat> @llvm.experimental.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0) %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0)
ret <vscale x 6 x bfloat> %res ret <vscale x 6 x bfloat> %res
} }
define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) { define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) {
; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6: ; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z2.d, z1.s ; CHECK-NEXT: uunpkhi z2.d, z1.s
; CHECK-NEXT: uunpklo z1.d, z1.s ; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s ; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x bfloat> @llvm.experimental.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6) %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6)
ret <vscale x 6 x bfloat> %res ret <vscale x 6 x bfloat> %res
} }
declare <vscale x 6 x bfloat> @llvm.experimental.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat>, i64) declare <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat>, i64)
; ;
; Extract bf16 vector that needs promotion from one that needs widening. ; Extract bf16 vector that needs promotion from one that needs widening.
; ;
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_0: ; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 0) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 0)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_2: ; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 2) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 2)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_4(<vscale x 6 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_4(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_4: ; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 4) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 4)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
declare <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat>, i64) declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat>, i64)
; ;
; Extract 1/4th bf16 vector that needs promotion from legal type. ; Extract 1/4th bf16 vector that needs promotion from legal type.
; ;
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_0: ; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_2: ; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 2) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 2)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_4: ; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_6(<vscale x 8 x bfloat> %in) { define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_6(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_6: ; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 6) %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 6)
ret <vscale x 2 x bfloat> %res ret <vscale x 2 x bfloat> %res
} }
declare <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64) declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64)
; ;
; Extract half bf16 vector that needs promotion from one that needs splitting. ; Extract half bf16 vector that needs promotion from one that needs splitting.
; ;
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_0(<vscale x 16 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_0(<vscale x 16 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_0: ; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 0) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 0)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_4(<vscale x 16 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_4(<vscale x 16 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_4: ; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 4) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 4)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_8(<vscale x 16 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_8(<vscale x 16 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_8: ; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z1.h ; CHECK-NEXT: uunpklo z0.s, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 8) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 8)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_12(<vscale x 16 x bfloat> %in) { define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_12(<vscale x 16 x bfloat> %in) {
; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_12: ; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z1.h ; CHECK-NEXT: uunpkhi z0.s, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 12) %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 12)
ret <vscale x 4 x bfloat> %res ret <vscale x 4 x bfloat> %res
} }
declare <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64) declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64)
; ;
; Extract from a splat ; Extract from a splat
; ;
define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat(float %f) { define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat(float %f) {
; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat: ; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
; CHECK-NEXT: mov z0.s, s0 ; CHECK-NEXT: mov z0.s, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x float> poison, float %f, i32 0 %ins = insertelement <vscale x 4 x float> poison, float %f, i32 0
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%ext = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0) %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
ret <vscale x 2 x float> %ext ret <vscale x 2 x float> %ext
} }
define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() { define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() {
; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat_const: ; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov z0.s, #1.00000000 ; CHECK-NEXT: fmov z0.s, #1.00000000
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0 %ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%ext = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0) %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
ret <vscale x 2 x float> %ext ret <vscale x 2 x float> %ext
} }
define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() { define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() {
; CHECK-LABEL: extract_nxv4i32_nxv8i32_splat_const: ; CHECK-LABEL: extract_nxv4i32_nxv8i32_splat_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, #1 // =0x1 ; CHECK-NEXT: mov z0.s, #1 // =0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0 %ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%ext = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0) %ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
ret <vscale x 4 x i32> %ext ret <vscale x 4 x i32> %ext
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_ones: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_ones:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0 %ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
%splat = shufflevector <vscale x 16 x i1> %ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x i1> %ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%ext = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %splat, i64 0) %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %splat, i64 0)
ret <vscale x 2 x i1> %ext ret <vscale x 2 x i1> %ext
} }
define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_zero() { define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_zero() {
; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_zero: ; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: pfalse p0.b ; CHECK-NEXT: pfalse p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> zeroinitializer, i64 0) %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> zeroinitializer, i64 0)
ret <vscale x 2 x i1> %ext ret <vscale x 2 x i1> %ext
} }
declare <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64) declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32>, i64)

llvm/test/CodeGen/AArch64/sve-extract-vector-to-predicate-store.ll

; RUN: opt -S -aarch64-sve-intrinsic-opts < %s | FileCheck %s ; RUN: opt -S -aarch64-sve-intrinsic-opts < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
define void @pred_store_v2i8(<vscale x 16 x i1> %pred, <2 x i8>* %addr) #0 { define void @pred_store_v2i8(<vscale x 16 x i1> %pred, <2 x i8>* %addr) #0 {
; CHECK-LABEL: @pred_store_v2i8( ; CHECK-LABEL: @pred_store_v2i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <2 x i8> %extract, <2 x i8>* %addr, align 4 store <2 x i8> %extract, <2 x i8>* %addr, align 4
ret void ret void
} }
define void @pred_store_v4i8(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #1 { define void @pred_store_v4i8(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #1 {
; CHECK-LABEL: @pred_store_v4i8( ; CHECK-LABEL: @pred_store_v4i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <4 x i8> %extract, <4 x i8>* %addr, align 4 store <4 x i8> %extract, <4 x i8>* %addr, align 4
ret void ret void
} }
define void @pred_store_v8i8(<vscale x 16 x i1> %pred, <8 x i8>* %addr) #2 { define void @pred_store_v8i8(<vscale x 16 x i1> %pred, <8 x i8>* %addr) #2 {
; CHECK-LABEL: @pred_store_v8i8( ; CHECK-LABEL: @pred_store_v8i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: store <vscale x 16 x i1> %pred, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <8 x i8> %extract, <8 x i8>* %addr, align 4 store <8 x i8> %extract, <8 x i8>* %addr, align 4
ret void ret void
} }
; Check that too small of a vscale prevents optimization ; Check that too small of a vscale prevents optimization
define void @pred_store_neg1(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #0 { define void @pred_store_neg1(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #0 {
; CHECK-LABEL: @pred_store_neg1( ; CHECK-LABEL: @pred_store_neg1(
; CHECK: call <4 x i8> @llvm.experimental.vector.extract ; CHECK: call <4 x i8> @llvm.vector.extract
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <4 x i8> %extract, <4 x i8>* %addr, align 4 store <4 x i8> %extract, <4 x i8>* %addr, align 4
ret void ret void
} }
; Check that too large of a vscale prevents optimization ; Check that too large of a vscale prevents optimization
define void @pred_store_neg2(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #2 { define void @pred_store_neg2(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #2 {
; CHECK-LABEL: @pred_store_neg2( ; CHECK-LABEL: @pred_store_neg2(
; CHECK: call <4 x i8> @llvm.experimental.vector.extract ; CHECK: call <4 x i8> @llvm.vector.extract
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <4 x i8> %extract, <4 x i8>* %addr, align 4 store <4 x i8> %extract, <4 x i8>* %addr, align 4
ret void ret void
} }
; Check that a non-zero index prevents optimization ; Check that a non-zero index prevents optimization
define void @pred_store_neg3(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #1 { define void @pred_store_neg3(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #1 {
; CHECK-LABEL: @pred_store_neg3( ; CHECK-LABEL: @pred_store_neg3(
; CHECK: call <4 x i8> @llvm.experimental.vector.extract ; CHECK: call <4 x i8> @llvm.vector.extract
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 4) %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 4)
store <4 x i8> %extract, <4 x i8>* %addr, align 4 store <4 x i8> %extract, <4 x i8>* %addr, align 4
ret void ret void
} }
; Check that differing vscale min/max prevents optimization ; Check that differing vscale min/max prevents optimization
define void @pred_store_neg4(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #3 { define void @pred_store_neg4(<vscale x 16 x i1> %pred, <4 x i8>* %addr) #3 {
; CHECK-LABEL: @pred_store_neg4( ; CHECK-LABEL: @pred_store_neg4(
; CHECK: call <4 x i8> @llvm.experimental.vector.extract ; CHECK: call <4 x i8> @llvm.vector.extract
%bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8> %bitcast = bitcast <vscale x 16 x i1> %pred to <vscale x 2 x i8>
%extract = tail call <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0) %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
store <4 x i8> %extract, <4 x i8>* %addr, align 4 store <4 x i8> %extract, <4 x i8>* %addr, align 4
ret void ret void
} }
declare <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8>, i64) declare <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8>, i64)
declare <4 x i8> @llvm.experimental.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8>, i64) declare <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8>, i64)
declare <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64) declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64)
attributes #0 = { "target-features"="+sve" vscale_range(1,1) } attributes #0 = { "target-features"="+sve" vscale_range(1,1) }
attributes #1 = { "target-features"="+sve" vscale_range(2,2) } attributes #1 = { "target-features"="+sve" vscale_range(2,2) }
attributes #2 = { "target-features"="+sve" vscale_range(4,4) } attributes #2 = { "target-features"="+sve" vscale_range(4,4) }
attributes #3 = { "target-features"="+sve" vscale_range(2,4) } attributes #3 = { "target-features"="+sve" vscale_range(2,4) }

llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256 ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
; i8 ; i8
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) vscale_range(2,0) #0 { define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i8: ; CHECK-LABEL: extract_subvector_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <4 x i8> @llvm.experimental.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4) %ret = call <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4)
ret <4 x i8> %ret ret <4 x i8> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) vscale_range(2,0) #0 { define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v16i8: ; CHECK-LABEL: extract_subvector_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <8 x i8> @llvm.experimental.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8) %ret = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8)
ret <8 x i8> %ret ret <8 x i8> %ret
} }
define void @extract_subvector_v32i8(<32 x i8>* %a, <16 x i8>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v32i8(<32 x i8>* %a, <16 x i8>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v32i8: ; CHECK-LABEL: extract_subvector_v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: ptrue p0.b, vl32
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <32 x i8>, <32 x i8>* %a %op = load <32 x i8>, <32 x i8>* %a
%ret = call <16 x i8> @llvm.experimental.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16) %ret = call <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16)
store <16 x i8> %ret, <16 x i8>* %b store <16 x i8> %ret, <16 x i8>* %b
ret void ret void
} }
define void @extract_subvector_v64i8(<64 x i8>* %a, <32 x i8>* %b) #0 { define void @extract_subvector_v64i8(<64 x i8>* %a, <32 x i8>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v64i8: ; VBITS_GE_256-LABEL: extract_subvector_v64i8:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov w8, #32 ; VBITS_GE_256-NEXT: mov w8, #32
; VBITS_GE_256-NEXT: ptrue p0.b, vl32 ; VBITS_GE_256-NEXT: ptrue p0.b, vl32
; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8] ; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x1] ; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v64i8: ; VBITS_GE_512-LABEL: extract_subvector_v64i8:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.b, vl64 ; VBITS_GE_512-NEXT: ptrue p0.b, vl64
; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.b, vl32 ; VBITS_GE_512-NEXT: ptrue p0.b, vl32
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x1] ; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <64 x i8>, <64 x i8>* %a %op = load <64 x i8>, <64 x i8>* %a
%ret = call <32 x i8> @llvm.experimental.vector.extract.v32i8.v64i8(<64 x i8> %op, i64 32) %ret = call <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8> %op, i64 32)
store <32 x i8> %ret, <32 x i8>* %b store <32 x i8> %ret, <32 x i8>* %b
ret void ret void
} }
define void @extract_subvector_v128i8(<128 x i8>* %a, <64 x i8>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v128i8(<128 x i8>* %a, <64 x i8>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v128i8: ; CHECK-LABEL: extract_subvector_v128i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl128 ; CHECK-NEXT: ptrue p0.b, vl128
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: st1b { z0.b }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <128 x i8>, <128 x i8>* %a %op = load <128 x i8>, <128 x i8>* %a
%ret = call <64 x i8> @llvm.experimental.vector.extract.v64i8.v128i8(<128 x i8> %op, i64 64) %ret = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %op, i64 64)
store <64 x i8> %ret, <64 x i8>* %b store <64 x i8> %ret, <64 x i8>* %b
ret void ret void
} }
define void @extract_subvector_v256i8(<256 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v256i8(<256 x i8>* %a, <128 x i8>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v256i8: ; CHECK-LABEL: extract_subvector_v256i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl256 ; CHECK-NEXT: ptrue p0.b, vl256
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.b, vl128 ; CHECK-NEXT: ptrue p0.b, vl128
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1b { z0.b }, p0, [x1] ; CHECK-NEXT: st1b { z0.b }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <256 x i8>, <256 x i8>* %a %op = load <256 x i8>, <256 x i8>* %a
%ret = call <128 x i8> @llvm.experimental.vector.extract.v128i8.v256i8(<256 x i8> %op, i64 128) %ret = call <128 x i8> @llvm.vector.extract.v128i8.v256i8(<256 x i8> %op, i64 128)
store <128 x i8> %ret, <128 x i8>* %b store <128 x i8> %ret, <128 x i8>* %b
ret void ret void
} }
; i16 ; i16
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) vscale_range(2,0) #0 { define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4i16: ; CHECK-LABEL: extract_subvector_v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: umov w9, v0.h[3] ; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <2 x i16> @llvm.experimental.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2) %ret = call <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2)
ret <2 x i16> %ret ret <2 x i16> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) vscale_range(2,0) #0 { define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i16: ; CHECK-LABEL: extract_subvector_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <4 x i16> @llvm.experimental.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4) %ret = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4)
ret <4 x i16> %ret ret <4 x i16> %ret
} }
define void @extract_subvector_v16i16(<16 x i16>* %a, <8 x i16>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v16i16(<16 x i16>* %a, <8 x i16>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v16i16: ; CHECK-LABEL: extract_subvector_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: ptrue p0.h, vl16
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <16 x i16>, <16 x i16>* %a %op = load <16 x i16>, <16 x i16>* %a
%ret = call <8 x i16> @llvm.experimental.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8) %ret = call <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8)
store <8 x i16> %ret, <8 x i16>* %b store <8 x i16> %ret, <8 x i16>* %b
ret void ret void
} }
define void @extract_subvector_v32i16(<32 x i16>* %a, <16 x i16>* %b) #0 { define void @extract_subvector_v32i16(<32 x i16>* %a, <16 x i16>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v32i16: ; VBITS_GE_256-LABEL: extract_subvector_v32i16:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #16 ; VBITS_GE_256-NEXT: mov x8, #16
; VBITS_GE_256-NEXT: ptrue p0.h, vl16 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1] ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v32i16: ; VBITS_GE_512-LABEL: extract_subvector_v32i16:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.h, vl32 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.h, vl16 ; VBITS_GE_512-NEXT: ptrue p0.h, vl16
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <32 x i16>, <32 x i16>* %a %op = load <32 x i16>, <32 x i16>* %a
%ret = call <16 x i16> @llvm.experimental.vector.extract.v16i16.v32i16(<32 x i16> %op, i64 16) %ret = call <16 x i16> @llvm.vector.extract.v16i16.v32i16(<32 x i16> %op, i64 16)
store <16 x i16> %ret, <16 x i16>* %b store <16 x i16> %ret, <16 x i16>* %b
ret void ret void
} }
define void @extract_subvector_v64i16(<64 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v64i16(<64 x i16>* %a, <32 x i16>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v64i16: ; CHECK-LABEL: extract_subvector_v64i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.h, vl32 ; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <64 x i16>, <64 x i16>* %a %op = load <64 x i16>, <64 x i16>* %a
%ret = call <32 x i16> @llvm.experimental.vector.extract.v32i16.v64i16(<64 x i16> %op, i64 32) %ret = call <32 x i16> @llvm.vector.extract.v32i16.v64i16(<64 x i16> %op, i64 32)
store <32 x i16> %ret, <32 x i16>* %b store <32 x i16> %ret, <32 x i16>* %b
ret void ret void
} }
define void @extract_subvector_v128i16(<128 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v128i16(<128 x i16>* %a, <64 x i16>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v128i16: ; CHECK-LABEL: extract_subvector_v128i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: ptrue p0.h, vl128
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <128 x i16>, <128 x i16>* %a %op = load <128 x i16>, <128 x i16>* %a
%ret = call <64 x i16> @llvm.experimental.vector.extract.v64i16.v128i16(<128 x i16> %op, i64 64) %ret = call <64 x i16> @llvm.vector.extract.v64i16.v128i16(<128 x i16> %op, i64 64)
store <64 x i16> %ret, <64 x i16>* %b store <64 x i16> %ret, <64 x i16>* %b
ret void ret void
} }
; i32 ; i32
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) vscale_range(2,0) #0 { define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2i32: ; CHECK-LABEL: extract_subvector_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.2s, v0.s[1] ; CHECK-NEXT: dup v0.2s, v0.s[1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <1 x i32> @llvm.experimental.vector.extract.v1i32.v2i32(<2 x i32> %op, i64 1) %ret = call <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32> %op, i64 1)
ret <1 x i32> %ret ret <1 x i32> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) vscale_range(2,0) #0 { define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4i32: ; CHECK-LABEL: extract_subvector_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2) %ret = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2)
ret <2 x i32> %ret ret <2 x i32> %ret
} }
define void @extract_subvector_v8i32(<8 x i32>* %a, <4 x i32>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v8i32(<8 x i32>* %a, <4 x i32>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i32: ; CHECK-LABEL: extract_subvector_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ptrue p0.s, vl8
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <8 x i32>, <8 x i32>* %a %op = load <8 x i32>, <8 x i32>* %a
%ret = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4) %ret = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4)
store <4 x i32> %ret, <4 x i32>* %b store <4 x i32> %ret, <4 x i32>* %b
ret void ret void
} }
define void @extract_subvector_v16i32(<16 x i32>* %a, <8 x i32>* %b) #0 { define void @extract_subvector_v16i32(<16 x i32>* %a, <8 x i32>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v16i32: ; VBITS_GE_256-LABEL: extract_subvector_v16i32:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #8 ; VBITS_GE_256-NEXT: mov x8, #8
; VBITS_GE_256-NEXT: ptrue p0.s, vl8 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2] ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v16i32: ; VBITS_GE_512-LABEL: extract_subvector_v16i32:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.s, vl8 ; VBITS_GE_512-NEXT: ptrue p0.s, vl8
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <16 x i32>, <16 x i32>* %a %op = load <16 x i32>, <16 x i32>* %a
%ret = call <8 x i32> @llvm.experimental.vector.extract.v8i32.v16i32(<16 x i32> %op, i64 8) %ret = call <8 x i32> @llvm.vector.extract.v8i32.v16i32(<16 x i32> %op, i64 8)
store <8 x i32> %ret, <8 x i32>* %b store <8 x i32> %ret, <8 x i32>* %b
ret void ret void
} }
define void @extract_subvector_v32i32(<32 x i32>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v32i32(<32 x i32>* %a, <16 x i32>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v32i32: ; CHECK-LABEL: extract_subvector_v32i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl16 ; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <32 x i32>, <32 x i32>* %a %op = load <32 x i32>, <32 x i32>* %a
%ret = call <16 x i32> @llvm.experimental.vector.extract.v16i32.v32i32(<32 x i32> %op, i64 16) %ret = call <16 x i32> @llvm.vector.extract.v16i32.v32i32(<32 x i32> %op, i64 16)
store <16 x i32> %ret, <16 x i32>* %b store <16 x i32> %ret, <16 x i32>* %b
ret void ret void
} }
define void @extract_subvector_v64i32(<64 x i32>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v64i32(<64 x i32>* %a, <32 x i32>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v64i32: ; CHECK-LABEL: extract_subvector_v64i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ptrue p0.s, vl64
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <64 x i32>, <64 x i32>* %a %op = load <64 x i32>, <64 x i32>* %a
%ret = call <32 x i32> @llvm.experimental.vector.extract.v32i32.v64i32(<64 x i32> %op, i64 32) %ret = call <32 x i32> @llvm.vector.extract.v32i32.v64i32(<64 x i32> %op, i64 32)
store <32 x i32> %ret, <32 x i32>* %b store <32 x i32> %ret, <32 x i32>* %b
ret void ret void
} }
; i64 ; i64
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) vscale_range(2,0) #0 { define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2i64: ; CHECK-LABEL: extract_subvector_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <1 x i64> @llvm.experimental.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1) %ret = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1)
ret <1 x i64> %ret ret <1 x i64> %ret
} }
define void @extract_subvector_v4i64(<4 x i64>* %a, <2 x i64>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v4i64(<4 x i64>* %a, <2 x i64>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4i64: ; CHECK-LABEL: extract_subvector_v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <4 x i64>, <4 x i64>* %a %op = load <4 x i64>, <4 x i64>* %a
%ret = call <2 x i64> @llvm.experimental.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2) %ret = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2)
store <2 x i64> %ret, <2 x i64>* %b store <2 x i64> %ret, <2 x i64>* %b
ret void ret void
} }
define void @extract_subvector_v8i64(<8 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v8i64(<8 x i64>* %a, <4 x i64>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i64: ; CHECK-LABEL: extract_subvector_v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #4 ; CHECK-NEXT: mov x8, #4
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <8 x i64>, <8 x i64>* %a %op = load <8 x i64>, <8 x i64>* %a
%ret = call <4 x i64> @llvm.experimental.vector.extract.v4i64.v8i64(<8 x i64> %op, i64 4) %ret = call <4 x i64> @llvm.vector.extract.v4i64.v8i64(<8 x i64> %op, i64 4)
store <4 x i64> %ret, <4 x i64>* %b store <4 x i64> %ret, <4 x i64>* %b
ret void ret void
} }
define void @extract_subvector_v16i64(<16 x i64>* %a, <8 x i64>* %b) #0 { define void @extract_subvector_v16i64(<16 x i64>* %a, <8 x i64>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v16i64: ; VBITS_GE_256-LABEL: extract_subvector_v16i64:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #8 ; VBITS_GE_256-NEXT: mov x8, #8
; VBITS_GE_256-NEXT: mov x9, #12 ; VBITS_GE_256-NEXT: mov x9, #12
; VBITS_GE_256-NEXT: ptrue p0.d, vl4 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x9, lsl #3] ; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x9, lsl #3]
; VBITS_GE_256-NEXT: mov x8, #4 ; VBITS_GE_256-NEXT: mov x8, #4
; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3] ; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]
; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
%op = load <16 x i64>, <16 x i64>* %a %op = load <16 x i64>, <16 x i64>* %a
%ret = call <8 x i64> @llvm.experimental.vector.extract.v8i64.v16i64(<16 x i64> %op, i64 8) %ret = call <8 x i64> @llvm.vector.extract.v8i64.v16i64(<16 x i64> %op, i64 8)
store <8 x i64> %ret, <8 x i64>* %b store <8 x i64> %ret, <8 x i64>* %b
ret void ret void
} }
define void @extract_subvector_v32i64(<32 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v32i64(<32 x i64>* %a, <16 x i64>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v32i64: ; CHECK-LABEL: extract_subvector_v32i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #16 ; CHECK-NEXT: mov x8, #16
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <32 x i64>, <32 x i64>* %a %op = load <32 x i64>, <32 x i64>* %a
%ret = call <16 x i64> @llvm.experimental.vector.extract.v16i64.v32i64(<32 x i64> %op, i64 16) %ret = call <16 x i64> @llvm.vector.extract.v16i64.v32i64(<32 x i64> %op, i64 16)
store <16 x i64> %ret, <16 x i64>* %b store <16 x i64> %ret, <16 x i64>* %b
ret void ret void
} }
; f16 ; f16
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <2 x half> @extract_subvector_v4f16(<4 x half> %op) vscale_range(16,0) #0 { define <2 x half> @extract_subvector_v4f16(<4 x half> %op) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v4f16: ; CHECK-LABEL: extract_subvector_v4f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.2s, v0.s[1] ; CHECK-NEXT: dup v0.2s, v0.s[1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <2 x half> @llvm.experimental.vector.extract.v2f16.v4f16(<4 x half> %op, i64 2) %ret = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %op, i64 2)
ret <2 x half> %ret ret <2 x half> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <4 x half> @extract_subvector_v8f16(<8 x half> %op) vscale_range(2,0) #0 { define <4 x half> @extract_subvector_v8f16(<8 x half> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8f16: ; CHECK-LABEL: extract_subvector_v8f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <4 x half> @llvm.experimental.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4) %ret = call <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4)
ret <4 x half> %ret ret <4 x half> %ret
} }
define void @extract_subvector_v16f16(<16 x half>* %a, <8 x half>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v16f16(<16 x half>* %a, <8 x half>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v16f16: ; CHECK-LABEL: extract_subvector_v16f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl16 ; CHECK-NEXT: ptrue p0.h, vl16
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <16 x half>, <16 x half>* %a %op = load <16 x half>, <16 x half>* %a
%ret = call <8 x half> @llvm.experimental.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8) %ret = call <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8)
store <8 x half> %ret, <8 x half>* %b store <8 x half> %ret, <8 x half>* %b
ret void ret void
} }
define void @extract_subvector_v32f16(<32 x half>* %a, <16 x half>* %b) #0 { define void @extract_subvector_v32f16(<32 x half>* %a, <16 x half>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v32f16: ; VBITS_GE_256-LABEL: extract_subvector_v32f16:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #16 ; VBITS_GE_256-NEXT: mov x8, #16
; VBITS_GE_256-NEXT: ptrue p0.h, vl16 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1] ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v32f16: ; VBITS_GE_512-LABEL: extract_subvector_v32f16:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.h, vl32 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.h, vl16 ; VBITS_GE_512-NEXT: ptrue p0.h, vl16
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1] ; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <32 x half>, <32 x half>* %a %op = load <32 x half>, <32 x half>* %a
%ret = call <16 x half> @llvm.experimental.vector.extract.v16f16.v32f16(<32 x half> %op, i64 16) %ret = call <16 x half> @llvm.vector.extract.v16f16.v32f16(<32 x half> %op, i64 16)
store <16 x half> %ret, <16 x half>* %b store <16 x half> %ret, <16 x half>* %b
ret void ret void
} }
define void @extract_subvector_v64f16(<64 x half>* %a, <32 x half>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v64f16(<64 x half>* %a, <32 x half>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v64f16: ; CHECK-LABEL: extract_subvector_v64f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.h, vl32 ; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <64 x half>, <64 x half>* %a %op = load <64 x half>, <64 x half>* %a
%ret = call <32 x half> @llvm.experimental.vector.extract.v32f16.v64f16(<64 x half> %op, i64 32) %ret = call <32 x half> @llvm.vector.extract.v32f16.v64f16(<64 x half> %op, i64 32)
store <32 x half> %ret, <32 x half>* %b store <32 x half> %ret, <32 x half>* %b
ret void ret void
} }
define void @extract_subvector_v128f16(<128 x half>* %a, <64 x half>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v128f16(<128 x half>* %a, <64 x half>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v128f16: ; CHECK-LABEL: extract_subvector_v128f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl128 ; CHECK-NEXT: ptrue p0.h, vl128
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.h, vl64 ; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1h { z0.h }, p0, [x1] ; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <128 x half>, <128 x half>* %a %op = load <128 x half>, <128 x half>* %a
%ret = call <64 x half> @llvm.experimental.vector.extract.v64f16.v128f16(<128 x half> %op, i64 64) %ret = call <64 x half> @llvm.vector.extract.v64f16.v128f16(<128 x half> %op, i64 64)
store <64 x half> %ret, <64 x half>* %b store <64 x half> %ret, <64 x half>* %b
ret void ret void
} }
; f32 ; f32
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <1 x float> @extract_subvector_v2f32(<2 x float> %op) vscale_range(2,0) #0 { define <1 x float> @extract_subvector_v2f32(<2 x float> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2f32: ; CHECK-LABEL: extract_subvector_v2f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.2s, v0.s[1] ; CHECK-NEXT: dup v0.2s, v0.s[1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <1 x float> @llvm.experimental.vector.extract.v1f32.v2f32(<2 x float> %op, i64 1) %ret = call <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float> %op, i64 1)
ret <1 x float> %ret ret <1 x float> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <2 x float> @extract_subvector_v4f32(<4 x float> %op) vscale_range(2,0) #0 { define <2 x float> @extract_subvector_v4f32(<4 x float> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4f32: ; CHECK-LABEL: extract_subvector_v4f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <2 x float> @llvm.experimental.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2) %ret = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2)
ret <2 x float> %ret ret <2 x float> %ret
} }
define void @extract_subvector_v8f32(<8 x float>* %a, <4 x float>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v8f32(<8 x float>* %a, <4 x float>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8f32: ; CHECK-LABEL: extract_subvector_v8f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ptrue p0.s, vl8
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <8 x float>, <8 x float>* %a %op = load <8 x float>, <8 x float>* %a
%ret = call <4 x float> @llvm.experimental.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4) %ret = call <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4)
store <4 x float> %ret, <4 x float>* %b store <4 x float> %ret, <4 x float>* %b
ret void ret void
} }
define void @extract_subvector_v16f32(<16 x float>* %a, <8 x float>* %b) #0 { define void @extract_subvector_v16f32(<16 x float>* %a, <8 x float>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v16f32: ; VBITS_GE_256-LABEL: extract_subvector_v16f32:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #8 ; VBITS_GE_256-NEXT: mov x8, #8
; VBITS_GE_256-NEXT: ptrue p0.s, vl8 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2] ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v16f32: ; VBITS_GE_512-LABEL: extract_subvector_v16f32:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.s, vl8 ; VBITS_GE_512-NEXT: ptrue p0.s, vl8
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <16 x float>, <16 x float>* %a %op = load <16 x float>, <16 x float>* %a
%ret = call <8 x float> @llvm.experimental.vector.extract.v8f32.v16f32(<16 x float> %op, i64 8) %ret = call <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float> %op, i64 8)
store <8 x float> %ret, <8 x float>* %b store <8 x float> %ret, <8 x float>* %b
ret void ret void
} }
define void @extract_subvector_v32f32(<32 x float>* %a, <16 x float>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v32f32(<32 x float>* %a, <16 x float>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v32f32: ; CHECK-LABEL: extract_subvector_v32f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl16 ; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <32 x float>, <32 x float>* %a %op = load <32 x float>, <32 x float>* %a
%ret = call <16 x float> @llvm.experimental.vector.extract.v16f32.v32f32(<32 x float> %op, i64 16) %ret = call <16 x float> @llvm.vector.extract.v16f32.v32f32(<32 x float> %op, i64 16)
store <16 x float> %ret, <16 x float>* %b store <16 x float> %ret, <16 x float>* %b
ret void ret void
} }
define void @extract_subvector_v64f32(<64 x float>* %a, <32 x float>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v64f32(<64 x float>* %a, <32 x float>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v64f32: ; CHECK-LABEL: extract_subvector_v64f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ptrue p0.s, vl64
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <64 x float>, <64 x float>* %a %op = load <64 x float>, <64 x float>* %a
%ret = call <32 x float> @llvm.experimental.vector.extract.v32f32.v64f32(<64 x float> %op, i64 32) %ret = call <32 x float> @llvm.vector.extract.v32f32.v64f32(<64 x float> %op, i64 32)
store <32 x float> %ret, <32 x float>* %b store <32 x float> %ret, <32 x float>* %b
ret void ret void
} }
; f64 ; f64
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <1 x double> @extract_subvector_v2f64(<2 x double> %op) vscale_range(2,0) #0 { define <1 x double> @extract_subvector_v2f64(<2 x double> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2f64: ; CHECK-LABEL: extract_subvector_v2f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <1 x double> @llvm.experimental.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1) %ret = call <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1)
ret <1 x double> %ret ret <1 x double> %ret
} }
define void @extract_subvector_v4f64(<4 x double>* %a, <2 x double>* %b) vscale_range(2,0) #0 { define void @extract_subvector_v4f64(<4 x double>* %a, <2 x double>* %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4f64: ; CHECK-LABEL: extract_subvector_v4f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <4 x double>, <4 x double>* %a %op = load <4 x double>, <4 x double>* %a
%ret = call <2 x double> @llvm.experimental.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2) %ret = call <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2)
store <2 x double> %ret, <2 x double>* %b store <2 x double> %ret, <2 x double>* %b
ret void ret void
} }
define void @extract_subvector_v8f64(<8 x double>* %a, <4 x double>* %b) #0 { define void @extract_subvector_v8f64(<8 x double>* %a, <4 x double>* %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v8f64: ; VBITS_GE_256-LABEL: extract_subvector_v8f64:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #4 ; VBITS_GE_256-NEXT: mov x8, #4
; VBITS_GE_256-NEXT: ptrue p0.d, vl4 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3] ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: extract_subvector_v8f64: ; VBITS_GE_512-LABEL: extract_subvector_v8f64:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d, vl4 ; VBITS_GE_512-NEXT: ptrue p0.d, vl4
; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32 ; VBITS_GE_512-NEXT: ext z0.b, z0.b, z0.b, #32
; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op = load <8 x double>, <8 x double>* %a %op = load <8 x double>, <8 x double>* %a
%ret = call <4 x double> @llvm.experimental.vector.extract.v4f64.v8f64(<8 x double> %op, i64 4) %ret = call <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double> %op, i64 4)
store <4 x double> %ret, <4 x double>* %b store <4 x double> %ret, <4 x double>* %b
ret void ret void
} }
define void @extract_subvector_v16f64(<16 x double>* %a, <8 x double>* %b) vscale_range(8,0) #0 { define void @extract_subvector_v16f64(<16 x double>* %a, <8 x double>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v16f64: ; CHECK-LABEL: extract_subvector_v16f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl8 ; CHECK-NEXT: ptrue p0.d, vl8
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <16 x double>, <16 x double>* %a %op = load <16 x double>, <16 x double>* %a
%ret = call <8 x double> @llvm.experimental.vector.extract.v8f64.v16f64(<16 x double> %op, i64 8) %ret = call <8 x double> @llvm.vector.extract.v8f64.v16f64(<16 x double> %op, i64 8)
store <8 x double> %ret, <8 x double>* %b store <8 x double> %ret, <8 x double>* %b
ret void ret void
} }
define void @extract_subvector_v32f64(<32 x double>* %a, <16 x double>* %b) vscale_range(16,0) #0 { define void @extract_subvector_v32f64(<32 x double>* %a, <16 x double>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: extract_subvector_v32f64: ; CHECK-LABEL: extract_subvector_v32f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <32 x double>, <32 x double>* %a %op = load <32 x double>, <32 x double>* %a
%ret = call <16 x double> @llvm.experimental.vector.extract.v16f64.v32f64(<32 x double> %op, i64 16) %ret = call <16 x double> @llvm.vector.extract.v16f64.v32f64(<32 x double> %op, i64 16)
store <16 x double> %ret, <16 x double>* %b store <16 x double> %ret, <16 x double>* %b
ret void ret void
} }
declare <4 x i8> @llvm.experimental.vector.extract.v4i8.v8i8(<8 x i8>, i64) declare <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8>, i64)
declare <8 x i8> @llvm.experimental.vector.extract.v8i8.v16i8(<16 x i8>, i64) declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.v32i8(<32 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8>, i64)
declare <32 x i8> @llvm.experimental.vector.extract.v32i8.v64i8(<64 x i8>, i64) declare <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8>, i64)
declare <64 x i8> @llvm.experimental.vector.extract.v64i8.v128i8(<128 x i8>, i64) declare <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8>, i64)
declare <128 x i8> @llvm.experimental.vector.extract.v128i8.v256i8(<256 x i8>, i64) declare <128 x i8> @llvm.vector.extract.v128i8.v256i8(<256 x i8>, i64)
declare <2 x i16> @llvm.experimental.vector.extract.v2i16.v4i16(<4 x i16>, i64) declare <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16>, i64)
declare <4 x i16> @llvm.experimental.vector.extract.v4i16.v8i16(<8 x i16>, i64) declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.v16i16(<16 x i16>, i64) declare <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16>, i64)
declare <16 x i16> @llvm.experimental.vector.extract.v16i16.v32i16(<32 x i16>, i64) declare <16 x i16> @llvm.vector.extract.v16i16.v32i16(<32 x i16>, i64)
declare <32 x i16> @llvm.experimental.vector.extract.v32i16.v64i16(<64 x i16>, i64) declare <32 x i16> @llvm.vector.extract.v32i16.v64i16(<64 x i16>, i64)
declare <64 x i16> @llvm.experimental.vector.extract.v64i16.v128i16(<128 x i16>, i64) declare <64 x i16> @llvm.vector.extract.v64i16.v128i16(<128 x i16>, i64)
declare <1 x i32> @llvm.experimental.vector.extract.v1i32.v2i32(<2 x i32>, i64) declare <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32>, i64)
declare <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<4 x i32>, i64) declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64)
declare <8 x i32> @llvm.experimental.vector.extract.v8i32.v16i32(<16 x i32>, i64) declare <8 x i32> @llvm.vector.extract.v8i32.v16i32(<16 x i32>, i64)
declare <16 x i32> @llvm.experimental.vector.extract.v16i32.v32i32(<32 x i32>, i64) declare <16 x i32> @llvm.vector.extract.v16i32.v32i32(<32 x i32>, i64)
declare <32 x i32> @llvm.experimental.vector.extract.v32i32.v64i32(<64 x i32>, i64) declare <32 x i32> @llvm.vector.extract.v32i32.v64i32(<64 x i32>, i64)
declare <1 x i64> @llvm.experimental.vector.extract.v1i64.v2i64(<2 x i64>, i64) declare <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64>, i64)
declare <2 x i64> @llvm.experimental.vector.extract.v2i64.v4i64(<4 x i64>, i64) declare <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64>, i64)
declare <4 x i64> @llvm.experimental.vector.extract.v4i64.v8i64(<8 x i64>, i64) declare <4 x i64> @llvm.vector.extract.v4i64.v8i64(<8 x i64>, i64)
declare <8 x i64> @llvm.experimental.vector.extract.v8i64.v16i64(<16 x i64>, i64) declare <8 x i64> @llvm.vector.extract.v8i64.v16i64(<16 x i64>, i64)
declare <16 x i64> @llvm.experimental.vector.extract.v16i64.v32i64(<32 x i64>, i64) declare <16 x i64> @llvm.vector.extract.v16i64.v32i64(<32 x i64>, i64)
declare <2 x half> @llvm.experimental.vector.extract.v2f16.v4f16(<4 x half>, i64) declare <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half>, i64)
declare <4 x half> @llvm.experimental.vector.extract.v4f16.v8f16(<8 x half>, i64) declare <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half>, i64)
declare <8 x half> @llvm.experimental.vector.extract.v8f16.v16f16(<16 x half>, i64) declare <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half>, i64)
declare <16 x half> @llvm.experimental.vector.extract.v16f16.v32f16(<32 x half>, i64) declare <16 x half> @llvm.vector.extract.v16f16.v32f16(<32 x half>, i64)
declare <32 x half> @llvm.experimental.vector.extract.v32f16.v64f16(<64 x half>, i64) declare <32 x half> @llvm.vector.extract.v32f16.v64f16(<64 x half>, i64)
declare <64 x half> @llvm.experimental.vector.extract.v64f16.v128f16(<128 x half>, i64) declare <64 x half> @llvm.vector.extract.v64f16.v128f16(<128 x half>, i64)
declare <1 x float> @llvm.experimental.vector.extract.v1f32.v2f32(<2 x float>, i64) declare <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float>, i64)
declare <2 x float> @llvm.experimental.vector.extract.v2f32.v4f32(<4 x float>, i64) declare <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float>, i64)
declare <4 x float> @llvm.experimental.vector.extract.v4f32.v8f32(<8 x float>, i64) declare <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float>, i64)
declare <8 x float> @llvm.experimental.vector.extract.v8f32.v16f32(<16 x float>, i64) declare <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float>, i64)
declare <16 x float> @llvm.experimental.vector.extract.v16f32.v32f32(<32 x float>, i64) declare <16 x float> @llvm.vector.extract.v16f32.v32f32(<32 x float>, i64)
declare <32 x float> @llvm.experimental.vector.extract.v32f32.v64f32(<64 x float>, i64) declare <32 x float> @llvm.vector.extract.v32f32.v64f32(<64 x float>, i64)
declare <1 x double> @llvm.experimental.vector.extract.v1f64.v2f64(<2 x double>, i64) declare <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double>, i64)
declare <2 x double> @llvm.experimental.vector.extract.v2f64.v4f64(<4 x double>, i64) declare <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double>, i64)
declare <4 x double> @llvm.experimental.vector.extract.v4f64.v8f64(<8 x double>, i64) declare <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double>, i64)
declare <8 x double> @llvm.experimental.vector.extract.v8f64.v16f64(<16 x double>, i64) declare <8 x double> @llvm.vector.extract.v8f64.v16f64(<16 x double>, i64)
declare <16 x double> @llvm.experimental.vector.extract.v16f64.v32f64(<32 x double>, i64) declare <16 x double> @llvm.vector.extract.v16f64.v32f64(<32 x double>, i64)
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll

; RUN: opt -S -aarch64-sve-intrinsic-opts < %s | FileCheck %s ; RUN: opt -S -aarch64-sve-intrinsic-opts < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
define <vscale x 16 x i1> @pred_load_v2i8(<2 x i8>* %addr) #0 { define <vscale x 16 x i1> @pred_load_v2i8(<2 x i8>* %addr) #0 {
; CHECK-LABEL: @pred_load_v2i8( ; CHECK-LABEL: @pred_load_v2i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] ; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
%load = load <2 x i8>, <2 x i8>* %addr, align 4 %load = load <2 x i8>, <2 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
define <vscale x 16 x i1> @pred_load_v4i8(<4 x i8>* %addr) #1 { define <vscale x 16 x i1> @pred_load_v4i8(<4 x i8>* %addr) #1 {
; CHECK-LABEL: @pred_load_v4i8( ; CHECK-LABEL: @pred_load_v4i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] ; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
define <vscale x 16 x i1> @pred_load_v8i8(<8 x i8>* %addr) #2 { define <vscale x 16 x i1> @pred_load_v8i8(<8 x i8>* %addr) #2 {
; CHECK-LABEL: @pred_load_v8i8( ; CHECK-LABEL: @pred_load_v8i8(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] ; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
%load = load <8 x i8>, <8 x i8>* %addr, align 4 %load = load <8 x i8>, <8 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Ensure the insertion point is at the load ; Ensure the insertion point is at the load
define <vscale x 16 x i1> @pred_load_insertion_point(<2 x i8>* %addr) #0 { define <vscale x 16 x i1> @pred_load_insertion_point(<2 x i8>* %addr) #0 {
; CHECK-LABEL: @pred_load_insertion_point( ; CHECK-LABEL: @pred_load_insertion_point(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i8>* %addr to <vscale x 16 x i1>*
; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i1>, <vscale x 16 x i1>* [[TMP1]]
; CHECK-NEXT: br label %bb1 ; CHECK-NEXT: br label %bb1
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] ; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
entry: entry:
%load = load <2 x i8>, <2 x i8>* %addr, align 4 %load = load <2 x i8>, <2 x i8>* %addr, align 4
br label %bb1 br label %bb1
bb1: bb1:
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> undef, <2 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Check that too small of a vscale prevents optimization ; Check that too small of a vscale prevents optimization
define <vscale x 16 x i1> @pred_load_neg1(<4 x i8>* %addr) #0 { define <vscale x 16 x i1> @pred_load_neg1(<4 x i8>* %addr) #0 {
; CHECK-LABEL: @pred_load_neg1( ; CHECK-LABEL: @pred_load_neg1(
; CHECK: call <vscale x 2 x i8> @llvm.experimental.vector.insert ; CHECK: call <vscale x 2 x i8> @llvm.vector.insert
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Check that too large of a vscale prevents optimization ; Check that too large of a vscale prevents optimization
define <vscale x 16 x i1> @pred_load_neg2(<4 x i8>* %addr) #2 { define <vscale x 16 x i1> @pred_load_neg2(<4 x i8>* %addr) #2 {
; CHECK-LABEL: @pred_load_neg2( ; CHECK-LABEL: @pred_load_neg2(
; CHECK: call <vscale x 2 x i8> @llvm.experimental.vector.insert ; CHECK: call <vscale x 2 x i8> @llvm.vector.insert
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Check that a non-zero index prevents optimization ; Check that a non-zero index prevents optimization
define <vscale x 16 x i1> @pred_load_neg3(<4 x i8>* %addr) #1 { define <vscale x 16 x i1> @pred_load_neg3(<4 x i8>* %addr) #1 {
; CHECK-LABEL: @pred_load_neg3( ; CHECK-LABEL: @pred_load_neg3(
; CHECK: call <vscale x 2 x i8> @llvm.experimental.vector.insert ; CHECK: call <vscale x 2 x i8> @llvm.vector.insert
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 4) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 4)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Check that differing vscale min/max prevents optimization ; Check that differing vscale min/max prevents optimization
define <vscale x 16 x i1> @pred_load_neg4(<4 x i8>* %addr) #3 { define <vscale x 16 x i1> @pred_load_neg4(<4 x i8>* %addr) #3 {
; CHECK-LABEL: @pred_load_neg4( ; CHECK-LABEL: @pred_load_neg4(
; CHECK: call <vscale x 2 x i8> @llvm.experimental.vector.insert ; CHECK: call <vscale x 2 x i8> @llvm.vector.insert
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
; Check that insertion into a non-undef vector prevents optimization ; Check that insertion into a non-undef vector prevents optimization
define <vscale x 16 x i1> @pred_load_neg5(<4 x i8>* %addr, <vscale x 2 x i8> %passthru) #1 { define <vscale x 16 x i1> @pred_load_neg5(<4 x i8>* %addr, <vscale x 2 x i8> %passthru) #1 {
; CHECK-LABEL: @pred_load_neg5( ; CHECK-LABEL: @pred_load_neg5(
; CHECK: call <vscale x 2 x i8> @llvm.experimental.vector.insert ; CHECK: call <vscale x 2 x i8> @llvm.vector.insert
%load = load <4 x i8>, <4 x i8>* %addr, align 4 %load = load <4 x i8>, <4 x i8>* %addr, align 4
%insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> %passthru, <4 x i8> %load, i64 0) %insert = tail call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> %passthru, <4 x i8> %load, i64 0)
%ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1> %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
ret <vscale x 16 x i1> %ret ret <vscale x 16 x i1> %ret
} }
declare <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8>, <2 x i8>, i64) declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8>, <2 x i8>, i64)
declare <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8>, <4 x i8>, i64) declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8>, <4 x i8>, i64)
declare <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64) declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64)
attributes #0 = { "target-features"="+sve" vscale_range(1,1) } attributes #0 = { "target-features"="+sve" vscale_range(1,1) }
attributes #1 = { "target-features"="+sve" vscale_range(2,2) } attributes #1 = { "target-features"="+sve" vscale_range(2,2) }
attributes #2 = { "target-features"="+sve" vscale_range(4,4) } attributes #2 = { "target-features"="+sve" vscale_range(4,4) }
attributes #3 = { "target-features"="+sve" vscale_range(2,4) } attributes #3 = { "target-features"="+sve" vscale_range(2,4) }

llvm/test/CodeGen/AArch64/sve-insert-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s --check-prefixes=CHECK
define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
; CHECK-LABEL: insert_v2i64_nxv2i64: ; CHECK-LABEL: insert_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov z0.d, p0/m, z1.d ; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0) %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
ret <vscale x 2 x i64> %retval ret <vscale x 2 x i64> %retval
} }
define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
; CHECK-LABEL: insert_v2i64_nxv2i64_idx2: ; CHECK-LABEL: insert_v2i64_nxv2i64_idx2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
ret <vscale x 2 x i64> %retval ret <vscale x 2 x i64> %retval
} }
define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
; CHECK-LABEL: insert_v4i32_nxv4i32: ; CHECK-LABEL: insert_v4i32_nxv4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov z0.s, p0/m, z1.s ; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0) %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
ret <vscale x 4 x i32> %retval ret <vscale x 4 x i32> %retval
} }
define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
; CHECK-LABEL: insert_v4i32_nxv4i32_idx4: ; CHECK-LABEL: insert_v4i32_nxv4i32_idx4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntw x8 ; CHECK-NEXT: cntw x8
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: sub x8, x8, #4 ; CHECK-NEXT: sub x8, x8, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4) %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4)
ret <vscale x 4 x i32> %retval ret <vscale x 4 x i32> %retval
} }
define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
; CHECK-LABEL: insert_v8i16_nxv8i16: ; CHECK-LABEL: insert_v8i16_nxv8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov z0.h, p0/m, z1.h ; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0) %retval = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
ret <vscale x 8 x i16> %retval ret <vscale x 8 x i16> %retval
} }
define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
; CHECK-LABEL: insert_v8i16_nxv8i16_idx8: ; CHECK-LABEL: insert_v8i16_nxv8i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cnth x8 ; CHECK-NEXT: cnth x8
; CHECK-NEXT: mov w9, #8 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: sub x8, x8, #8 ; CHECK-NEXT: sub x8, x8, #8
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: cmp x8, #8 ; CHECK-NEXT: cmp x8, #8
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: lsl x8, x8, #1
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8) %retval = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8)
ret <vscale x 8 x i16> %retval ret <vscale x 8 x i16> %retval
} }
define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
; CHECK-LABEL: insert_v16i8_nxv16i8: ; CHECK-LABEL: insert_v16i8_nxv16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl16 ; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov z0.b, p0/m, z1.b ; CHECK-NEXT: mov z0.b, p0/m, z1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0) %retval = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
ret <vscale x 16 x i8> %retval ret <vscale x 16 x i8> %retval
} }
define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
; CHECK-LABEL: insert_v16i8_nxv16i8_idx16: ; CHECK-LABEL: insert_v16i8_nxv16i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: mov x8, #-16 ; CHECK-NEXT: mov x8, #-16
; CHECK-NEXT: mov w9, #16 ; CHECK-NEXT: mov w9, #16
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: cmp x8, #16 ; CHECK-NEXT: cmp x8, #16
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16) %retval = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16)
ret <vscale x 16 x i8> %retval ret <vscale x 16 x i8> %retval
} }
; Insert subvectors into illegal vectors ; Insert subvectors into illegal vectors
define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64: ; CHECK-LABEL: insert_nxv8i64_nxv16i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] ; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl]
; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] ; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl]
; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] ; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl]
; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] ; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl]
; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo: ; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi: ; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) uwtable { define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) uwtable {
; CHECK-LABEL: insert_v2i64_nxv16i64: ; CHECK-LABEL: insert_v2i64_nxv16i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64_lo0: ; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) uwtable { define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) uwtable {
; CHECK-LABEL: insert_v2i64_nxv16i64_lo2: ; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
; Insert subvectors that need widening ; Insert subvectors that need widening
define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind { define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind {
; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef: ; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.s, #1 // =0x1 ; CHECK-NEXT: mov z0.s, #1 // =0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0 %0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
%subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer %subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0) %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0)
ret <vscale x 4 x i32> %retval ret <vscale x 4 x i32> %retval
} }
define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind { define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind {
; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef: ; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z0.h, #1 // =0x1 ; CHECK-NEXT: mov z0.h, #1 // =0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0 %0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
%subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer %subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0) %retval = call <vscale x 6 x i16> @llvm.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0)
ret <vscale x 6 x i16> %retval ret <vscale x 6 x i16> %retval
} }
define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_undef(<vscale x 1 x float> %subvec) nounwind { define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_undef(<vscale x 1 x float> %subvec) nounwind {
; CHECK-LABEL: insert_nxv1f32_nxv4f32_undef: ; CHECK-LABEL: insert_nxv1f32_nxv4f32_undef:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%retval = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> %subvec, i64 0) %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> undef, <vscale x 1 x float> %subvec, i64 0)
ret <vscale x 4 x float> %retval ret <vscale x 4 x float> %retval
} }
; This tests promotion of the input operand to INSERT_SUBVECTOR. ; This tests promotion of the input operand to INSERT_SUBVECTOR.
define <vscale x 8 x i16> @insert_nxv8i16_nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in) nounwind { define <vscale x 8 x i16> @insert_nxv8i16_nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in) nounwind {
; CHECK-LABEL: insert_nxv8i16_nxv2i16: ; CHECK-LABEL: insert_nxv8i16_nxv2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z2.s, z0.h ; CHECK-NEXT: uunpklo z2.s, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z2.d, z2.s ; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s ; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in, i64 2) %r = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in, i64 2)
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_0(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind { define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_0(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4f16_nxv2f16_0: ; CHECK-LABEL: insert_nxv4f16_nxv2f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 0) %v0 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 0)
ret <vscale x 4 x half> %v0 ret <vscale x 4 x half> %v0
} }
define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_2(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind { define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_2(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4f16_nxv2f16_2: ; CHECK-LABEL: insert_nxv4f16_nxv2f16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 2) %v0 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 2)
ret <vscale x 4 x half> %v0 ret <vscale x 4 x half> %v0
} }
; Test that the index is scaled by vscale if the subvector is scalable. ; Test that the index is scaled by vscale if the subvector is scalable.
define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind { define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind {
; CHECK-LABEL: insert_nxv8f16_nxv2f16: ; CHECK-LABEL: insert_nxv8f16_nxv2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ptrue p1.d ; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.d }, p1, [sp, #1, mul vl] ; CHECK-NEXT: st1h { z1.d }, p1, [sp, #1, mul vl]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2) %r = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2)
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_0(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind { define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_0(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind {
; CHECK-LABEL: insert_nxv8f16_nxv4f16_0: ; CHECK-LABEL: insert_nxv8f16_nxv4f16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 0) %v0 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 0)
ret <vscale x 8 x half> %v0 ret <vscale x 8 x half> %v0
} }
define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_4(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind { define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_4(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind {
; CHECK-LABEL: insert_nxv8f16_nxv4f16_4: ; CHECK-LABEL: insert_nxv8f16_nxv4f16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 4) %v0 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 4)
ret <vscale x 8 x half> %v0 ret <vscale x 8 x half> %v0
} }
; Fixed length clamping ; Fixed length clamping
define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 { define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 {
; CHECK-LABEL: insert_fixed_v2i64_nxv2i64: ; CHECK-LABEL: insert_fixed_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
ret <vscale x 2 x i64> %retval ret <vscale x 2 x i64> %retval
} }
define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 { define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 {
; CHECK-LABEL: insert_fixed_v4i64_nxv2i64: ; CHECK-LABEL: insert_fixed_v4i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: subs x8, x8, #4 ; CHECK-NEXT: subs x8, x8, #4
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
; CHECK-NEXT: csel x8, xzr, x8, lo ; CHECK-NEXT: csel x8, xzr, x8, lo
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3] ; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%subvec = load <4 x i64>, <4 x i64>* %ptr %subvec = load <4 x i64>, <4 x i64>* %ptr
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4) %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4)
ret <vscale x 2 x i64> %retval ret <vscale x 2 x i64> %retval
} }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Upacked types that need result widening ;; Upacked types that need result widening
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) { define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) {
; CHECK-LABEL: insert_nxv3i32_nxv2i32: ; CHECK-LABEL: insert_nxv3i32_nxv2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) %v0 = call <vscale x 3 x i32> @llvm.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> undef, <vscale x 2 x i32> %sv0, i64 0)
ret <vscale x 3 x i32> %v0 ret <vscale x 3 x i32> %v0
} }
;; Check that the Subvector is not widen so it does not crash. ;; Check that the Subvector is not widen so it does not crash.
define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) { define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) {
; CHECK-LABEL: insert_nxv3i32_nxv2i32_2: ; CHECK-LABEL: insert_nxv3i32_nxv2i32_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0) %v0 = call <vscale x 3 x i32> @llvm.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0)
ret <vscale x 3 x i32> %v0 ret <vscale x 3 x i32> %v0
} }
define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0) nounwind { define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0) nounwind {
; CHECK-LABEL: insert_nxv3f32_nxv2f32: ; CHECK-LABEL: insert_nxv3f32_nxv2f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float> undef, <vscale x 2 x float> %sv0, i64 0) %v0 = call <vscale x 3 x float> @llvm.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float> undef, <vscale x 2 x float> %sv0, i64 0)
ret <vscale x 3 x float> %v0 ret <vscale x 3 x float> %v0
} }
define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_0(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind { define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_0(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4f32_nxv2f32_0: ; CHECK-LABEL: insert_nxv4f32_nxv2f32_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 0) %v0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 0)
ret <vscale x 4 x float> %v0 ret <vscale x 4 x float> %v0
} }
define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_2(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind { define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_2(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4f32_nxv2f32_2: ; CHECK-LABEL: insert_nxv4f32_nxv2f32_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 2) %v0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 2)
ret <vscale x 4 x float> %v0 ret <vscale x 4 x float> %v0
} }
define <vscale x 6 x i32> @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind { define <vscale x 6 x i32> @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind {
; CHECK-LABEL: insert_nxv6i32_nxv2i32: ; CHECK-LABEL: insert_nxv6i32_nxv2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: ld1w { z1.s }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1w { z1.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) %v0 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> undef, <vscale x 2 x i32> %sv0, i64 0)
%v1 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2) %v1 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2)
ret <vscale x 6 x i32> %v1 ret <vscale x 6 x i32> %v1
} }
;; This only works because the input vector is undef and index is zero ;; This only works because the input vector is undef and index is zero
define <vscale x 6 x i32> @insert_nxv6i32_nxv3i32(<vscale x 3 x i32> %sv0) { define <vscale x 6 x i32> @insert_nxv6i32_nxv3i32(<vscale x 3 x i32> %sv0) {
; CHECK-LABEL: insert_nxv6i32_nxv3i32: ; CHECK-LABEL: insert_nxv6i32_nxv3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32> undef, <vscale x 3 x i32> %sv0, i64 0) %v0 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32> undef, <vscale x 3 x i32> %sv0, i64 0)
ret <vscale x 6 x i32> %v0 ret <vscale x 6 x i32> %v0
} }
define <vscale x 12 x i32> @insert_nxv12i32_nxv4i32(<vscale x 4 x i32> %sv0, <vscale x 4 x i32> %sv1, <vscale x 4 x i32> %sv2) { define <vscale x 12 x i32> @insert_nxv12i32_nxv4i32(<vscale x 4 x i32> %sv0, <vscale x 4 x i32> %sv1, <vscale x 4 x i32> %sv2) {
; CHECK-LABEL: insert_nxv12i32_nxv4i32: ; CHECK-LABEL: insert_nxv12i32_nxv4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> undef, <vscale x 4 x i32> %sv0, i64 0) %v0 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> undef, <vscale x 4 x i32> %sv0, i64 0)
%v1 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v0, <vscale x 4 x i32> %sv1, i64 4) %v1 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v0, <vscale x 4 x i32> %sv1, i64 4)
%v2 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v1, <vscale x 4 x i32> %sv2, i64 8) %v2 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v1, <vscale x 4 x i32> %sv2, i64 8)
ret <vscale x 12 x i32> %v2 ret <vscale x 12 x i32> %v2
} }
define <vscale x 2 x bfloat> @insert_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { define <vscale x 2 x bfloat> @insert_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv2bf16_nxv2bf16: ; CHECK-LABEL: insert_nxv2bf16_nxv2bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0) %v0 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0)
ret <vscale x 2 x bfloat> %v0 ret <vscale x 2 x bfloat> %v0
} }
define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4bf16_nxv4bf16: ; CHECK-LABEL: insert_nxv4bf16_nxv4bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0) %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0)
ret <vscale x 4 x bfloat> %v0 ret <vscale x 4 x bfloat> %v0
} }
define <vscale x 4 x bfloat> @insert_nxv4bf16_v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1) nounwind { define <vscale x 4 x bfloat> @insert_nxv4bf16_v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1) nounwind {
; CHECK-LABEL: insert_nxv4bf16_v4bf16: ; CHECK-LABEL: insert_nxv4bf16_v4bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl] ; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
; CHECK-NEXT: addpl x8, sp, #4 ; CHECK-NEXT: addpl x8, sp, #4
; CHECK-NEXT: str d1, [x8] ; CHECK-NEXT: str d1, [x8]
; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1, i64 0) %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1, i64 0)
ret <vscale x 4 x bfloat> %v0 ret <vscale x 4 x bfloat> %v0
} }
define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1) nounwind { define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv8bf16_nxv8bf16: ; CHECK-LABEL: insert_nxv8bf16_nxv8bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1, i64 0) %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1, i64 0)
ret <vscale x 8 x bfloat> %v0 ret <vscale x 8 x bfloat> %v0
} }
define <vscale x 8 x bfloat> @insert_nxv8bf16_v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1) nounwind { define <vscale x 8 x bfloat> @insert_nxv8bf16_v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1) nounwind {
; CHECK-LABEL: insert_nxv8bf16_v8bf16: ; CHECK-LABEL: insert_nxv8bf16_v8bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov z0.h, p0/m, z1.h ; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1, i64 0) %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1, i64 0)
ret <vscale x 8 x bfloat> %v0 ret <vscale x 8 x bfloat> %v0
} }
define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_0(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_0(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_0: ; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0) %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0)
ret <vscale x 8 x bfloat> %v0 ret <vscale x 8 x bfloat> %v0
} }
define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_4(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_4(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_4: ; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 4) %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 4)
ret <vscale x 8 x bfloat> %v0 ret <vscale x 8 x bfloat> %v0
} }
define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_0(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_0(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_0: ; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0) %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0)
ret <vscale x 4 x bfloat> %v0 ret <vscale x 4 x bfloat> %v0
} }
define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_2(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_2(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {
; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_2: ; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 2) %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 2)
ret <vscale x 4 x bfloat> %v0 ret <vscale x 4 x bfloat> %v0
} }
; Test predicate inserts of half size. ; Test predicate inserts of half size.
define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_0(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_0(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv8i1_0: ; CHECK-LABEL: insert_nxv16i1_nxv8i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b ; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 0) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 0)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_8(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_8(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv8i1_8: ; CHECK-LABEL: insert_nxv16i1_nxv8i1_8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 8) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 8)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
; Test predicate inserts of less than half the size. ; Test predicate inserts of less than half the size.
define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_0(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_0(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv4i1_0: ; CHECK-LABEL: insert_nxv16i1_nxv4i1_0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p2.h, p0.b ; CHECK-NEXT: punpklo p2.h, p0.b
; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: punpkhi p0.h, p0.b
; CHECK-NEXT: punpkhi p2.h, p2.b ; CHECK-NEXT: punpkhi p2.h, p2.b
; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h ; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h
; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b ; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 0) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 0)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_12(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_12(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv4i1_12: ; CHECK-LABEL: insert_nxv16i1_nxv4i1_12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpkhi p2.h, p0.b ; CHECK-NEXT: punpkhi p2.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p2.h, p2.b ; CHECK-NEXT: punpklo p2.h, p2.b
; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h ; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 12) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 12)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
; Test predicate insert into undef/zero ; Test predicate insert into undef/zero
define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_zero(<vscale x 4 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_zero(<vscale x 4 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_zero: ; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: pfalse p1.b ; CHECK-NEXT: pfalse p1.b
; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h ; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_poison(<vscale x 4 x i1> %sv) { define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_poison(<vscale x 4 x i1> %sv) {
; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_poison: ; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_poison:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 p0.h, p0.h, p0.h ; CHECK-NEXT: uzp1 p0.h, p0.h, p0.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p0.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %sv, i64 0) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %sv, i64 0)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
; Test constant predicate insert into undef ; Test constant predicate insert into undef
define <vscale x 2 x i1> @insert_nxv2i1_v8i1_const_true_into_undef() vscale_range(4,8) { define <vscale x 2 x i1> @insert_nxv2i1_v8i1_const_true_into_undef() vscale_range(4,8) {
; CHECK-LABEL: insert_nxv2i1_v8i1_const_true_into_undef: ; CHECK-LABEL: insert_nxv2i1_v8i1_const_true_into_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1 (<vscale x 2 x i1> undef, <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) %v0 = call <vscale x 2 x i1> @llvm.vector.insert.nxv2i1.v8i1 (<vscale x 2 x i1> undef, <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0)
ret <vscale x 2 x i1> %v0 ret <vscale x 2 x i1> %v0
} }
define <vscale x 4 x i1> @insert_nxv4i1_v16i1_const_true_into_undef() vscale_range(4,8) { define <vscale x 4 x i1> @insert_nxv4i1_v16i1_const_true_into_undef() vscale_range(4,8) {
; CHECK-LABEL: insert_nxv4i1_v16i1_const_true_into_undef: ; CHECK-LABEL: insert_nxv4i1_v16i1_const_true_into_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1 (<vscale x 4 x i1> undef, <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) %v0 = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.v16i1 (<vscale x 4 x i1> undef, <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0)
ret <vscale x 4 x i1> %v0 ret <vscale x 4 x i1> %v0
} }
define <vscale x 8 x i1> @insert_nxv8i1_v32i1_const_true_into_undef() vscale_range(4,8) { define <vscale x 8 x i1> @insert_nxv8i1_v32i1_const_true_into_undef() vscale_range(4,8) {
; CHECK-LABEL: insert_nxv8i1_v32i1_const_true_into_undef: ; CHECK-LABEL: insert_nxv8i1_v32i1_const_true_into_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1 (<vscale x 8 x i1> undef, <32 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) %v0 = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.v32i1 (<vscale x 8 x i1> undef, <32 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0)
ret <vscale x 8 x i1> %v0 ret <vscale x 8 x i1> %v0
} }
define <vscale x 16 x i1> @insert_nxv16i1_v64i1_const_true_into_undef() vscale_range(4,8) { define <vscale x 16 x i1> @insert_nxv16i1_v64i1_const_true_into_undef() vscale_range(4,8) {
; CHECK-LABEL: insert_nxv16i1_v64i1_const_true_into_undef: ; CHECK-LABEL: insert_nxv16i1_v64i1_const_true_into_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1 (<vscale x 16 x i1> undef, <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.v64i1 (<vscale x 16 x i1> undef, <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0)
ret <vscale x 16 x i1> %v0 ret <vscale x 16 x i1> %v0
} }
attributes #0 = { vscale_range(2,2) } attributes #0 = { vscale_range(2,2) }
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64) declare <vscale x 6 x i16> @llvm.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64)
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16>, <vscale x 2 x i16>, i64) declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16>, <vscale x 2 x i16>, i64)
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
declare <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32>, <vscale x 2 x i32>, i64) declare <vscale x 3 x i32> @llvm.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32>, <vscale x 2 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
declare <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32>, <vscale x 4 x i32>, i64) declare <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32>, <vscale x 4 x i32>, i64)
declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32>, <vscale x 2 x i32>, i64) declare <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32>, <vscale x 2 x i32>, i64)
declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32>, <vscale x 3 x i32>, i64) declare <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32>, <vscale x 3 x i32>, i64)
declare <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64)
declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64) declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64)
declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64)
declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat>, <4 x bfloat>, i64) declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat>, <4 x bfloat>, i64)
declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64)
declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64) declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64)
declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64) declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64)
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64) declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64)
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64) declare <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) declare <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
declare <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64) declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64)
declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64) declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64)
declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64) declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64)
declare <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float>, <vscale x 2 x float>, i64) declare <vscale x 3 x float> @llvm.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float>, <vscale x 2 x float>, i64)
declare <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float>, <vscale x 1 x float>, i64) declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float>, <vscale x 1 x float>, i64)
declare <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64) declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64)
declare <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1(<vscale x 2 x i1>, <8 x i1>, i64) declare <vscale x 2 x i1> @llvm.vector.insert.nxv2i1.v8i1(<vscale x 2 x i1>, <8 x i1>, i64)
declare <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1(<vscale x 4 x i1>, <16 x i1>, i64) declare <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.v16i1(<vscale x 4 x i1>, <16 x i1>, i64)
declare <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1(<vscale x 8 x i1>, <32 x i1>, i64) declare <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.v32i1(<vscale x 8 x i1>, <32 x i1>, i64)
declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64) declare <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64)
declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i64) declare <vscale x 16 x i1> @llvm.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i64)
declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1(<vscale x 16 x i1>, <64 x i1>, i64) declare <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.v64i1(<vscale x 16 x i1>, <64 x i1>, i64)

llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

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define dso_local <vscale x 2 x double> @dupq_ld1rqd_f64() { define dso_local <vscale x 2 x double> @dupq_ld1rqd_f64() {
; CHECK-LABEL: dupq_ld1rqd_f64: ; CHECK-LABEL: dupq_ld1rqd_f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI49_0 ; CHECK-NEXT: adrp x8, .LCPI49_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI49_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI49_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call fast <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> <double 1.000000e+00, double 2.000000e+00>, i64 0) %1 = tail call fast <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> undef, <2 x double> <double 1.000000e+00, double 2.000000e+00>, i64 0)
%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %1, i64 0) %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %1, i64 0)
ret <vscale x 2 x double> %2 ret <vscale x 2 x double> %2
} }
define dso_local <vscale x 4 x float> @dupq_ld1rqw_f32() { define dso_local <vscale x 4 x float> @dupq_ld1rqw_f32() {
; CHECK-LABEL: dupq_ld1rqw_f32: ; CHECK-LABEL: dupq_ld1rqw_f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI50_0 ; CHECK-NEXT: adrp x8, .LCPI50_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI50_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI50_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call fast <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, i64 0) %1 = tail call fast <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, i64 0)
%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %1, i64 0) %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %1, i64 0)
ret <vscale x 4 x float> %2 ret <vscale x 4 x float> %2
} }
define dso_local <vscale x 8 x half> @dupq_ld1rqh_f16() { define dso_local <vscale x 8 x half> @dupq_ld1rqh_f16() {
; CHECK-LABEL: dupq_ld1rqh_f16: ; CHECK-LABEL: dupq_ld1rqh_f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI51_0 ; CHECK-NEXT: adrp x8, .LCPI51_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI51_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI51_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call fast <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400, half 0xH4500, half 0xH4600, half 0xH4700, half 0xH4800>, i64 0) %1 = tail call fast <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half> undef, <8 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400, half 0xH4500, half 0xH4600, half 0xH4700, half 0xH4800>, i64 0)
%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %1, i64 0) %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %1, i64 0)
ret <vscale x 8 x half> %2 ret <vscale x 8 x half> %2
} }
define dso_local <vscale x 8 x bfloat> @dupq_ld1rqh_bf16() #0 { define dso_local <vscale x 8 x bfloat> @dupq_ld1rqh_bf16() #0 {
; CHECK-LABEL: dupq_ld1rqh_bf16: ; CHECK-LABEL: dupq_ld1rqh_bf16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI52_0 ; CHECK-NEXT: adrp x8, .LCPI52_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI52_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI52_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> <bfloat 1.000e+00, bfloat 2.000e+00, bfloat 3.000e+00, bfloat 4.000e+00, bfloat 5.000e+00, bfloat 6.000e+00, bfloat 7.000e+00, bfloat 8.000e+00>, i64 0) %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> undef, <8 x bfloat> <bfloat 1.000e+00, bfloat 2.000e+00, bfloat 3.000e+00, bfloat 4.000e+00, bfloat 5.000e+00, bfloat 6.000e+00, bfloat 7.000e+00, bfloat 8.000e+00>, i64 0)
%2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> %1, i64 0) %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> %1, i64 0)
ret <vscale x 8 x bfloat> %2 ret <vscale x 8 x bfloat> %2
} }
define dso_local <vscale x 2 x i64> @dupq_ld1rqd_i64() { define dso_local <vscale x 2 x i64> @dupq_ld1rqd_i64() {
; CHECK-LABEL: dupq_ld1rqd_i64: ; CHECK-LABEL: dupq_ld1rqd_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI53_0 ; CHECK-NEXT: adrp x8, .LCPI53_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI53_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI53_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> <i64 1, i64 2>, i64 0) %1 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, <2 x i64> <i64 1, i64 2>, i64 0)
%2 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %1, i64 0) %2 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %1, i64 0)
ret <vscale x 2 x i64> %2 ret <vscale x 2 x i64> %2
} }
define dso_local <vscale x 4 x i32> @dupq_ld1rqd_i32() { define dso_local <vscale x 4 x i32> @dupq_ld1rqd_i32() {
; CHECK-LABEL: dupq_ld1rqd_i32: ; CHECK-LABEL: dupq_ld1rqd_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI54_0 ; CHECK-NEXT: adrp x8, .LCPI54_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI54_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI54_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i64 0) %1 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i64 0)
%2 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %1, i64 0) %2 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %1, i64 0)
ret <vscale x 4 x i32> %2 ret <vscale x 4 x i32> %2
} }
define dso_local <vscale x 8 x i16> @dupq_ld1rqd_i16() { define dso_local <vscale x 8 x i16> @dupq_ld1rqd_i16() {
; CHECK-LABEL: dupq_ld1rqd_i16: ; CHECK-LABEL: dupq_ld1rqd_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI55_0 ; CHECK-NEXT: adrp x8, .LCPI55_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI55_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI55_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i64 0) %1 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i64 0)
%2 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %1, i64 0) %2 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %1, i64 0)
ret <vscale x 8 x i16> %2 ret <vscale x 8 x i16> %2
} }
define dso_local <vscale x 16 x i8> @dupq_ld1rqd_i8() { define dso_local <vscale x 16 x i8> @dupq_ld1rqd_i8() {
; CHECK-LABEL: dupq_ld1rqd_i8: ; CHECK-LABEL: dupq_ld1rqd_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI56_0 ; CHECK-NEXT: adrp x8, .LCPI56_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI56_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI56_0]
; CHECK-NEXT: mov z0.q, q0 ; CHECK-NEXT: mov z0.q, q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, i64 0) %1 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, i64 0)
%2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %1, i64 0) %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %1, i64 0)
ret <vscale x 16 x i8> %2 ret <vscale x 16 x i8> %2
} }
; ;
; EXT ; EXT
; ;
▲ Show 20 Lines • Show All 1,870 Lines • ▼ Show 20 Lines
declare <vscale x 2 x half> @llvm.aarch64.sve.zip2.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>) declare <vscale x 2 x half> @llvm.aarch64.sve.zip2.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>)
declare <vscale x 4 x half> @llvm.aarch64.sve.zip2.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>) declare <vscale x 4 x half> @llvm.aarch64.sve.zip2.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)
declare <vscale x 2 x float> @llvm.aarch64.sve.zip2.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>) declare <vscale x 2 x float> @llvm.aarch64.sve.zip2.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>)
declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)
declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v2f64(<vscale x 2 x double>, <2 x double>, i64) declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double>, <2 x double>, i64)
declare <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v4f32(<vscale x 4 x float>, <4 x float>, i64) declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float>, <4 x float>, i64)
declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v8f16(<vscale x 8 x half>, <8 x half>, i64) declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v8f16(<vscale x 8 x half>, <8 x half>, i64)
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64) declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64)
; +bf16 is required for the bfloat version. ; +bf16 is required for the bfloat version.
attributes #0 = { "target-features"="+sve,+bf16" } attributes #0 = { "target-features"="+sve,+bf16" }

llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
define <4 x i32> @sve_no_typesize_warning(<vscale x 8 x i16> %a, <4 x i16> %b) #0 { define <4 x i32> @sve_no_typesize_warning(<vscale x 8 x i16> %a, <4 x i16> %b) #0 {
; CHECK-LABEL: sve_no_typesize_warning: ; CHECK-LABEL: sve_no_typesize_warning:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h ; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a.lo = call <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16> %a, i64 0) %a.lo = call <4 x i16> @llvm.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16> %a, i64 0)
%a.lo.zext = zext <4 x i16> %a.lo to <4 x i32> %a.lo.zext = zext <4 x i16> %a.lo to <4 x i32>
%b.zext = zext <4 x i16> %b to <4 x i32> %b.zext = zext <4 x i16> %b to <4 x i32>
%add = add <4 x i32> %a.lo.zext, %b.zext %add = add <4 x i32> %a.lo.zext, %b.zext
ret <4 x i32> %add ret <4 x i32> %add
} }
declare <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16>, i64) declare <4 x i16> @llvm.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16>, i64)
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-punpklo-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
define <vscale x 8 x i1> @masked_load_sext_i8i16(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 8 x i1> @masked_load_sext_i8i16(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i16: ; CHECK-LABEL: masked_load_sext_i8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: ptrue p0.b, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16> %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10) %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer) %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
ret <vscale x 8 x i1> %cmp1 ret <vscale x 8 x i1> %cmp1
} }
; This negative test ensures the two ptrues have the same vl ; This negative test ensures the two ptrues have the same vl
define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i16_ptrue_vl: ; CHECK-LABEL: masked_load_sext_i8i16_ptrue_vl:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ptrue p1.h, vl32 ; CHECK-NEXT: ptrue p1.h, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16> %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10) %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer) %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
ret <vscale x 8 x i1> %cmp1 ret <vscale x 8 x i1> %cmp1
} }
; This negative test enforces that both predicates are ptrues ; This negative test enforces that both predicates are ptrues
define <vscale x 8 x i1> @masked_load_sext_i8i16_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 { define <vscale x 8 x i1> @masked_load_sext_i8i16_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
; CHECK-LABEL: masked_load_sext_i8i16_parg: ; CHECK-LABEL: masked_load_sext_i8i16_parg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: ptrue p1.h, vl32 ; CHECK-NEXT: ptrue p1.h, vl32
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16> %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10) %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer) %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
ret <vscale x 8 x i1> %cmp1 ret <vscale x 8 x i1> %cmp1
} }
define <vscale x 4 x i1> @masked_load_sext_i8i32(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 4 x i1> @masked_load_sext_i8i32(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i32: ; CHECK-LABEL: masked_load_sext_i8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: ptrue p0.b, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32> %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10) %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer) %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i1> %cmp1 ret <vscale x 4 x i1> %cmp1
} }
; This negative test ensures the two ptrues have the same vl ; This negative test ensures the two ptrues have the same vl
define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i32_ptrue_vl: ; CHECK-LABEL: masked_load_sext_i8i32_ptrue_vl:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ptrue p1.s, vl32 ; CHECK-NEXT: ptrue p1.s, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32> %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10) %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer) %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i1> %cmp1 ret <vscale x 4 x i1> %cmp1
} }
; This negative test enforces that both predicates are ptrues ; This negative test enforces that both predicates are ptrues
define <vscale x 4 x i1> @masked_load_sext_i8i32_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 { define <vscale x 4 x i1> @masked_load_sext_i8i32_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
; CHECK-LABEL: masked_load_sext_i8i32_parg: ; CHECK-LABEL: masked_load_sext_i8i32_parg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: ptrue p1.s, vl32 ; CHECK-NEXT: ptrue p1.s, vl32
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32> %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10) %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer) %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i1> %cmp1 ret <vscale x 4 x i1> %cmp1
} }
define <vscale x 2 x i1> @masked_load_sext_i8i64(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 2 x i1> @masked_load_sext_i8i64(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i64: ; CHECK-LABEL: masked_load_sext_i8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl32 ; CHECK-NEXT: ptrue p0.b, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64> %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10) %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer) %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
ret <vscale x 2 x i1> %cmp1 ret <vscale x 2 x i1> %cmp1
} }
; This negative test ensures the two ptrues have the same vl ; This negative test ensures the two ptrues have the same vl
define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_vl(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i64_ptrue_vl: ; CHECK-LABEL: masked_load_sext_i8i64_ptrue_vl:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ptrue p1.d, vl32 ; CHECK-NEXT: ptrue p1.d, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64> %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10) %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer) %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
ret <vscale x 2 x i1> %cmp1 ret <vscale x 2 x i1> %cmp1
} }
; This negative test enforces that both predicates are ptrues ; This negative test enforces that both predicates are ptrues
define <vscale x 2 x i1> @masked_load_sext_i8i64_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 { define <vscale x 2 x i1> @masked_load_sext_i8i64_parg(i8* %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
; CHECK-LABEL: masked_load_sext_i8i64_parg: ; CHECK-LABEL: masked_load_sext_i8i64_parg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: ptrue p1.d, vl32 ; CHECK-NEXT: ptrue p1.d, vl32
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64> %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10) %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer) %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
ret <vscale x 2 x i1> %cmp1 ret <vscale x 2 x i1> %cmp1
} }
; This negative test enforces that the ptrues have a specified vl ; This negative test enforces that the ptrues have a specified vl
define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i16_ptrue_all: ; CHECK-LABEL: masked_load_sext_i8i16_ptrue_all:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ptrue p1.h, vl32 ; CHECK-NEXT: ptrue p1.h, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16> %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10) %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer) %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
ret <vscale x 8 x i1> %cmp1 ret <vscale x 8 x i1> %cmp1
} }
; This negative test enforces that the ptrues have a specified vl ; This negative test enforces that the ptrues have a specified vl
define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i32_ptrue_all: ; CHECK-LABEL: masked_load_sext_i8i32_ptrue_all:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl64 ; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: ptrue p1.s, vl32 ; CHECK-NEXT: ptrue p1.s, vl32
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32> %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10) %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer) %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i1> %cmp1 ret <vscale x 4 x i1> %cmp1
} }
; This negative test enforces that the ptrues have a specified vl ; This negative test enforces that the ptrues have a specified vl
define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 { define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_all(i8* %ap, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: masked_load_sext_i8i64_ptrue_all: ; CHECK-LABEL: masked_load_sext_i8i64_ptrue_all:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0 ; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: punpklo p0.h, p0.b ; CHECK-NEXT: punpklo p0.h, p0.b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer) %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
%extract = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0) %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64> %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer) %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
ret <vscale x 2 x i1> %cmp1 ret <vscale x 2 x i1> %cmp1
} }
declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32) declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32) declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32) declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32) declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
declare <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64)
declare <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64)
declare <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64) declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64)
declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
; ;
; OR reductions ; OR reductions
; ;
define i1 @reduce_or_insert_subvec_into_zero(<vscale x 4 x i1> %in) { define i1 @reduce_or_insert_subvec_into_zero(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_or_insert_subvec_into_zero: ; CHECK-LABEL: reduce_or_insert_subvec_into_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptest p0, p0.b ; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
define i1 @reduce_or_insert_subvec_into_poison(<vscale x 4 x i1> %in) { define i1 @reduce_or_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_or_insert_subvec_into_poison: ; CHECK-LABEL: reduce_or_insert_subvec_into_poison:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptest p0, p0.b ; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
define i1 @reduce_or_insert_subvec_into_nonzero(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) { define i1 @reduce_or_insert_subvec_into_nonzero(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {
; CHECK-LABEL: reduce_or_insert_subvec_into_nonzero: ; CHECK-LABEL: reduce_or_insert_subvec_into_nonzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p2.h, p1.b ; CHECK-NEXT: punpklo p2.h, p1.b
; CHECK-NEXT: punpkhi p1.h, p1.b ; CHECK-NEXT: punpkhi p1.h, p1.b
; CHECK-NEXT: punpkhi p2.h, p2.b ; CHECK-NEXT: punpkhi p2.h, p2.b
; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h ; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: ptest p0, p0.b ; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
; ;
; AND reductions ; AND reductions
; ;
define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) { define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_and_insert_subvec_into_ones: ; CHECK-LABEL: reduce_and_insert_subvec_into_ones:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: not p0.b, p1/z, p0.b ; CHECK-NEXT: not p0.b, p1/z, p0.b
; CHECK-NEXT: ptest p1, p0.b ; CHECK-NEXT: ptest p1, p0.b
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%allones.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0 %allones.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
%allones = shufflevector <vscale x 16 x i1> %allones.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %allones = shufflevector <vscale x 16 x i1> %allones.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %allones, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %allones, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) { define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_and_insert_subvec_into_poison: ; CHECK-LABEL: reduce_and_insert_subvec_into_poison:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: not p0.b, p1/z, p0.b ; CHECK-NEXT: not p0.b, p1/z, p0.b
; CHECK-NEXT: ptest p1, p0.b ; CHECK-NEXT: ptest p1, p0.b
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) { define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {
; CHECK-LABEL: reduce_and_insert_subvec_into_var: ; CHECK-LABEL: reduce_and_insert_subvec_into_var:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: punpklo p3.h, p1.b ; CHECK-NEXT: punpklo p3.h, p1.b
; CHECK-NEXT: punpkhi p1.h, p1.b ; CHECK-NEXT: punpkhi p1.h, p1.b
; CHECK-NEXT: punpkhi p3.h, p3.b ; CHECK-NEXT: punpkhi p3.h, p3.b
; CHECK-NEXT: ptrue p2.b ; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h ; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: not p0.b, p2/z, p0.b ; CHECK-NEXT: not p0.b, p2/z, p0.b
; CHECK-NEXT: ptest p2, p0.b ; CHECK-NEXT: ptest p2, p0.b
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0) %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t) %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
ret i1 %res ret i1 %res
} }
declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>) declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>) declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64) declare <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64)

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv4i32_4: ; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv2i32_0: ; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv2i32_2: ; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv2i32_4: ; CHECK-LABEL: extract_nxv8i32_nxv2i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) {
; CHECK-LABEL: extract_nxv8i32_nxv2i32_6: ; CHECK-LABEL: extract_nxv8i32_nxv2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) { define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv8i32_0: ; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
ret <vscale x 8 x i32> %c ret <vscale x 8 x i32> %c
} }
define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) { define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv8i32_8: ; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
ret <vscale x 8 x i32> %c ret <vscale x 8 x i32> %c
} }
define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv4i32_0: ; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv4i32_4: ; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv4i32_8: ; CHECK-LABEL: extract_nxv16i32_nxv4i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) { define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv4i32_12: ; CHECK-LABEL: extract_nxv16i32_nxv4i32_12:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v14 ; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12) %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
ret <vscale x 4 x i32> %c ret <vscale x 4 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_0: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_2: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_4: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_6: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v11 ; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_8: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v12 ; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_10: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v13 ; CHECK-NEXT: vmv1r.v v8, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_12: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_12:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v14 ; CHECK-NEXT: vmv1r.v v8, v14
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) { define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv2i32_14: ; CHECK-LABEL: extract_nxv16i32_nxv2i32_14:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v15 ; CHECK-NEXT: vmv1r.v v8, v15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14) %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)
ret <vscale x 2 x i32> %c ret <vscale x 2 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv1i32_0: ; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv1i32_1: ; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_3(<vscale x 16 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_3(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv1i32_3: ; CHECK-LABEL: extract_nxv16i32_nxv1i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 3) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 3)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_15(<vscale x 16 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_15(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv1i32_15: ; CHECK-LABEL: extract_nxv16i32_nxv1i32_15:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v15, a0 ; CHECK-NEXT: vslidedown.vx v8, v15, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 15) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 15)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) {
; CHECK-LABEL: extract_nxv16i32_nxv1i32_2: ; CHECK-LABEL: extract_nxv16i32_nxv1i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) { define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) {
; CHECK-LABEL: extract_nxv2i32_nxv1i32_0: ; CHECK-LABEL: extract_nxv2i32_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0) %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
ret <vscale x 1 x i32> %c ret <vscale x 1 x i32> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_0: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_2: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 2) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 2)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_4(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_4(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_4: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 4) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 4)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_6: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: li a1, 6 ; CHECK-NEXT: li a1, 6
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 6) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 6)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_8(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_8(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_8: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 8) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 8)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) { define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_22: ; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: li a1, 6 ; CHECK-NEXT: li a1, 6
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 22) %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 22)
ret <vscale x 2 x i8> %c ret <vscale x 2 x i8> %c
} }
define <vscale x 1 x i8> @extract_nxv8i8_nxv1i8_7(<vscale x 8 x i8> %vec) { define <vscale x 1 x i8> @extract_nxv8i8_nxv1i8_7(<vscale x 8 x i8> %vec) {
; CHECK-LABEL: extract_nxv8i8_nxv1i8_7: ; CHECK-LABEL: extract_nxv8i8_nxv1i8_7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: sub a0, a0, a1 ; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 7) %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 7)
ret <vscale x 1 x i8> %c ret <vscale x 1 x i8> %c
} }
define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) { define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
; CHECK-LABEL: extract_nxv4i8_nxv1i8_3: ; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3) %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)
ret <vscale x 1 x i8> %c ret <vscale x 1 x i8> %c
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) { define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {
; CHECK-LABEL: extract_nxv2f16_nxv16f16_0: ; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0) %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)
ret <vscale x 2 x half> %c ret <vscale x 2 x half> %c
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) { define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {
; CHECK-LABEL: extract_nxv2f16_nxv16f16_2: ; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 2) %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 2)
ret <vscale x 2 x half> %c ret <vscale x 2 x half> %c
} }
define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_4(<vscale x 16 x half> %vec) { define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_4(<vscale x 16 x half> %vec) {
; CHECK-LABEL: extract_nxv2f16_nxv16f16_4: ; CHECK-LABEL: extract_nxv2f16_nxv16f16_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 4) %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 4)
ret <vscale x 2 x half> %c ret <vscale x 2 x half> %c
} }
define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_0(<vscale x 64 x i1> %mask) { define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_0(<vscale x 64 x i1> %mask) {
; CHECK-LABEL: extract_nxv64i1_nxv8i1_0: ; CHECK-LABEL: extract_nxv64i1_nxv8i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0) %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_8(<vscale x 64 x i1> %mask) { define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_8(<vscale x 64 x i1> %mask) {
; CHECK-LABEL: extract_nxv64i1_nxv8i1_8: ; CHECK-LABEL: extract_nxv64i1_nxv8i1_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v0, a0 ; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8) %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_0(<vscale x 64 x i1> %mask) { define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_0(<vscale x 64 x i1> %mask) {
; CHECK-LABEL: extract_nxv64i1_nxv2i1_0: ; CHECK-LABEL: extract_nxv64i1_nxv2i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0) %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0)
ret <vscale x 2 x i1> %c ret <vscale x 2 x i1> %c
} }
define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) { define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) {
; CHECK-LABEL: extract_nxv64i1_nxv2i1_2: ; CHECK-LABEL: extract_nxv64i1_nxv2i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2) %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)
ret <vscale x 2 x i1> %c ret <vscale x 2 x i1> %c
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_0(<vscale x 32 x i1> %x) { define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_0(<vscale x 32 x i1> %x) {
; CHECK-LABEL: extract_nxv4i1_nxv32i1_0: ; CHECK-LABEL: extract_nxv4i1_nxv32i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0) %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0)
ret <vscale x 4 x i1> %c ret <vscale x 4 x i1> %c
} }
define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) { define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) {
; CHECK-LABEL: extract_nxv4i1_nxv32i1_4: ; CHECK-LABEL: extract_nxv4i1_nxv32i1_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4) %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)
ret <vscale x 4 x i1> %c ret <vscale x 4 x i1> %c
} }
define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_0(<vscale x 32 x i1> %x) { define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_0(<vscale x 32 x i1> %x) {
; CHECK-LABEL: extract_nxv16i1_nxv32i1_0: ; CHECK-LABEL: extract_nxv16i1_nxv32i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0) %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0)
ret <vscale x 16 x i1> %c ret <vscale x 16 x i1> %c
} }
define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_16(<vscale x 32 x i1> %x) { define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_16(<vscale x 32 x i1> %x) {
; CHECK-LABEL: extract_nxv16i1_nxv32i1_16: ; CHECK-LABEL: extract_nxv16i1_nxv32i1_16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v0, a0 ; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 16) %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 16)
ret <vscale x 16 x i1> %c ret <vscale x 16 x i1> %c
} }
; ;
; Extract f16 vector that needs widening from one that needs widening. ; Extract f16 vector that needs widening from one that needs widening.
; ;
define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) { define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {
; CHECK-LABEL: extract_nxv6f16_nxv12f16_0: ; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0) %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)
ret <vscale x 6 x half> %res ret <vscale x 6 x half> %res
} }
define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) { define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
; CHECK-LABEL: extract_nxv6f16_nxv12f16_6: ; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v11, v10, a0 ; CHECK-NEXT: vslidedown.vx v11, v10, a0
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v11, 0 ; CHECK-NEXT: vslideup.vi v9, v11, 0
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6) %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
ret <vscale x 6 x half> %res ret <vscale x 6 x half> %res
} }
declare <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64) declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)
declare <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx) declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx)
declare <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 %idx) declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 %idx)
declare <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 %idx) declare <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 %idx)
declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx) declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx)
declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx) declare <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx) declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
declare <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
declare <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 %idx) declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 %idx)
declare <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %vec, i64 %idx) declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %vec, i64 %idx)
declare <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %vec, i64 %idx) declare <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %vec, i64 %idx)
declare <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %vec, i64 %idx) declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %vec, i64 %idx)
declare <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %vec, i64 %idx) declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %vec, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) { define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v4i8_0: ; CHECK-LABEL: extract_v2i8_v4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x %a = load <4 x i8>, <4 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0) %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v2i8_v4i8_2(<4 x i8>* %x, <2 x i8>* %y) { define void @extract_v2i8_v4i8_2(<4 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v4i8_2: ; CHECK-LABEL: extract_v2i8_v4i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x %a = load <4 x i8>, <4 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2) %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v2i8_v8i8_0(<8 x i8>* %x, <2 x i8>* %y) { define void @extract_v2i8_v8i8_0(<8 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v8i8_0: ; CHECK-LABEL: extract_v2i8_v8i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x %a = load <8 x i8>, <8 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0) %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v2i8_v8i8_6(<8 x i8>* %x, <2 x i8>* %y) { define void @extract_v2i8_v8i8_6(<8 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v8i8_6: ; CHECK-LABEL: extract_v2i8_v8i8_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6 ; CHECK-NEXT: vslidedown.vi v8, v8, 6
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x %a = load <8 x i8>, <8 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6) %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v2i32_v8i32_0(<8 x i32>* %x, <2 x i32>* %y) { define void @extract_v2i32_v8i32_0(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_0: ; LMULMAX2-LABEL: extract_v2i32_v8i32_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vse32.v v8, (a1) ; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i32_v8i32_0: ; LMULMAX1-LABEL: extract_v2i32_v8i32_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0) %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
store <2 x i32> %c, <2 x i32>* %y store <2 x i32> %c, <2 x i32>* %y
ret void ret void
} }
define void @extract_v2i32_v8i32_2(<8 x i32>* %x, <2 x i32>* %y) { define void @extract_v2i32_v8i32_2(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_2: ; LMULMAX2-LABEL: extract_v2i32_v8i32_2:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2) %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
store <2 x i32> %c, <2 x i32>* %y store <2 x i32> %c, <2 x i32>* %y
ret void ret void
} }
define void @extract_v2i32_v8i32_6(<8 x i32>* %x, <2 x i32>* %y) { define void @extract_v2i32_v8i32_6(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_6: ; LMULMAX2-LABEL: extract_v2i32_v8i32_6:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6) %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
store <2 x i32> %c, <2 x i32>* %y store <2 x i32> %c, <2 x i32>* %y
ret void ret void
} }
define void @extract_v2i32_nxv16i32_0(<vscale x 16 x i32> %x, <2 x i32>* %y) { define void @extract_v2i32_nxv16i32_0(<vscale x 16 x i32> %x, <2 x i32>* %y) {
; CHECK-LABEL: extract_v2i32_nxv16i32_0: ; CHECK-LABEL: extract_v2i32_nxv16i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 0) %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 0)
store <2 x i32> %c, <2 x i32>* %y store <2 x i32> %c, <2 x i32>* %y
ret void ret void
} }
define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, <2 x i32>* %y) { define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, <2 x i32>* %y) {
; CHECK-LABEL: extract_v2i32_nxv16i32_8: ; CHECK-LABEL: extract_v2i32_nxv16i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6 ; CHECK-NEXT: vslidedown.vi v8, v8, 6
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6) %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6)
store <2 x i32> %c, <2 x i32>* %y store <2 x i32> %c, <2 x i32>* %y
ret void ret void
} }
define void @extract_v2i8_nxv2i8_0(<vscale x 2 x i8> %x, <2 x i8>* %y) { define void @extract_v2i8_nxv2i8_0(<vscale x 2 x i8> %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_nxv2i8_0: ; CHECK-LABEL: extract_v2i8_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 0) %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 0)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, <2 x i8>* %y) { define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_nxv2i8_2: ; CHECK-LABEL: extract_v2i8_nxv2i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2) %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2)
store <2 x i8> %c, <2 x i8>* %y store <2 x i8> %c, <2 x i8>* %y
ret void ret void
} }
define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, <8 x i32>* %y) { define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: extract_v8i32_nxv16i32_8: ; LMULMAX2-LABEL: extract_v8i32_nxv16i32_8:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m8, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m8, ta, mu
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 8 ; LMULMAX2-NEXT: vslidedown.vi v8, v8, 8
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v8i32_nxv16i32_8: ; LMULMAX1-LABEL: extract_v8i32_nxv16i32_8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m8, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m8, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v16, v8, 8 ; LMULMAX1-NEXT: vslidedown.vi v16, v8, 8
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 12 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 12
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: vse32.v v16, (a0) ; LMULMAX1-NEXT: vse32.v v16, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%c = call <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8) %c = call <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
store <8 x i32> %c, <8 x i32>* %y store <8 x i32> %c, <8 x i32>* %y
ret void ret void
} }
define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) { define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2-LABEL: extract_v8i1_v64i1_0: ; LMULMAX2-LABEL: extract_v8i1_v64i1_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v8i1_v64i1_0: ; LMULMAX1-LABEL: extract_v8i1_v64i1_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0) %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) { define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2-LABEL: extract_v8i1_v64i1_8: ; LMULMAX2-LABEL: extract_v8i1_v64i1_8:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
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; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8) %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) { define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2-LABEL: extract_v8i1_v64i1_48: ; LMULMAX2-LABEL: extract_v8i1_v64i1_48:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a0, a0, 4 ; LMULMAX2-NEXT: addi a0, a0, 4
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; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 6 ; LMULMAX1-NEXT: addi a0, a0, 6
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48) %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv2i1_0: ; CHECK-LABEL: extract_v8i1_nxv2i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0) %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_0: ; CHECK-LABEL: extract_v8i1_nxv64i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v0, (a0) ; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0) %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_8: ; CHECK-LABEL: extract_v8i1_nxv64i1_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v0, 1 ; CHECK-NEXT: vslidedown.vi v8, v0, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8) %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_48: ; CHECK-LABEL: extract_v8i1_nxv64i1_48:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v0, 6 ; CHECK-NEXT: vslidedown.vi v8, v0, 6
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48) %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_0: ; LMULMAX2-LABEL: extract_v2i1_v64i1_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
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; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0) %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_2: ; LMULMAX2-LABEL: extract_v2i1_v64i1_2:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
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; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2) %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_42: ; LMULMAX2-LABEL: extract_v2i1_v64i1_42:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a0, a0, 4 ; LMULMAX2-NEXT: addi a0, a0, 4
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; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42) %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_0: ; CHECK-LABEL: extract_v2i1_nxv2i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_2: ; CHECK-LABEL: extract_v2i1_nxv2i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_0: ; CHECK-LABEL: extract_v2i1_nxv64i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_2: ; CHECK-LABEL: extract_v2i1_nxv64i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_42: ; CHECK-LABEL: extract_v2i1_nxv64i1_42:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv32i1_26: ; CHECK-LABEL: extract_v2i1_nxv32i1_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 26 ; CHECK-NEXT: vslidedown.vi v8, v8, 26
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26) %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv32i1_16: ; CHECK-LABEL: extract_v8i1_nxv32i1_16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v0, 2 ; CHECK-NEXT: vslidedown.vi v8, v0, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16) %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
store <8 x i1> %c, <8 x i1>* %y store <8 x i1> %c, <8 x i1>* %y
ret void ret void
} }
declare <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx) declare <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx)
declare <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %vec, i64 %idx) declare <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %vec, i64 %idx)
declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx) declare <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx)
declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx) declare <8 x i1> @llvm.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx)
declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx) declare <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx)
declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx) declare <8 x i1> @llvm.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx)
declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx) declare <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx)
declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx) declare <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx)
declare <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %vec, i64 %idx) declare <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %vec, i64 %idx)
declare <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %vec, i64 %idx) declare <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %vec, i64 %idx)
declare <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %vec, i64 %idx) declare <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %vec, i64 %idx)
declare <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %vec, i64 %idx) declare <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %vec, i64 %idx)
declare <2 x i32> @llvm.experimental.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
declare <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) declare <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

Show All 12 Lines
; CHECK-LABEL: insert_nxv8i32_v2i32_0: ; CHECK-LABEL: insert_nxv8i32_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vi v8, v12, 0 ; CHECK-NEXT: vslideup.vi v8, v12, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_2: ; CHECK-LABEL: insert_nxv8i32_v2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vi v8, v12, 2 ; CHECK-NEXT: vslideup.vi v8, v12, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_6: ; CHECK-LABEL: insert_nxv8i32_v2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vi v8, v12, 6 ; CHECK-NEXT: vslideup.vi v8, v12, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6) %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, <8 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, <8 x i32>* %svp) {
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu
; LMULMAX2-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX2-NEXT: vslideup.vi v8, v12, 0
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v16, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v16, 4
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp %sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0) %v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, <8 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, <8 x i32>* %svp) {
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu
; LMULMAX2-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX2-NEXT: vslideup.vi v8, v12, 8
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v12, 8
; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v16, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v16, 12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp %sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8) %v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(<2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(<2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_undef_v2i32_0: ; CHECK-LABEL: insert_nxv8i32_undef_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> undef, <2 x i32> %sv, i64 0) %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> undef, <2 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_0: ; CHECK-LABEL: insert_v4i32_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp %vec = load <4 x i32>, <4 x i32>* %vp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
} }
define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_2: ; CHECK-LABEL: insert_v4i32_v2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp %vec = load <4 x i32>, <4 x i32>* %vp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
} }
define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_undef_v2i32_0: ; CHECK-LABEL: insert_v4i32_undef_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0) %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_0: ; LMULMAX2-LABEL: insert_v8i32_v2i32_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_2: ; LMULMAX2-LABEL: insert_v8i32_v2i32_2:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_6: ; LMULMAX2-LABEL: insert_v8i32_v2i32_6:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6) %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_undef_v2i32_6: ; LMULMAX2-LABEL: insert_v8i32_undef_v2i32_6:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; LMULMAX2-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX2-NEXT: vslideup.vi v10, v8, 6
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6: ; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6) %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) { define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_0: ; CHECK-LABEL: insert_v4i16_v2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp %v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0) %c = call <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0)
store <4 x i16> %c, <4 x i16>* %vp store <4 x i16> %c, <4 x i16>* %vp
ret void ret void
} }
define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) { define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_2: ; CHECK-LABEL: insert_v4i16_v2i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp %v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2) %c = call <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2)
store <4 x i16> %c, <4 x i16>* %vp store <4 x i16> %c, <4 x i16>* %vp
ret void ret void
} }
define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) { define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2-LABEL: insert_v32i1_v8i1_0: ; LMULMAX2-LABEL: insert_v32i1_v8i1_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
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; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp %v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0) %c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)
store <32 x i1> %c, <32 x i1>* %vp store <32 x i1> %c, <32 x i1>* %vp
ret void ret void
} }
define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) { define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2-LABEL: insert_v32i1_v8i1_16: ; LMULMAX2-LABEL: insert_v32i1_v8i1_16:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
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; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp %v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16) %c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
store <32 x i1> %c, <32 x i1>* %vp store <32 x i1> %c, <32 x i1>* %vp
ret void ret void
} }
define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) { define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-LABEL: insert_v8i1_v4i1_0: ; CHECK-LABEL: insert_v8i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp %v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0) %c = call <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0)
store <8 x i1> %c, <8 x i1>* %vp store <8 x i1> %c, <8 x i1>* %vp
ret void ret void
} }
define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) { define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-LABEL: insert_v8i1_v4i1_4: ; CHECK-LABEL: insert_v8i1_v4i1_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp %v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4) %c = call <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)
store <8 x i1> %c, <8 x i1>* %vp store <8 x i1> %c, <8 x i1>* %vp
ret void ret void
} }
define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i16>* %svp) { define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
; CHECK-LABEL: insert_nxv2i16_v2i16_0: ; CHECK-LABEL: insert_nxv2i16_v2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0) %c = call <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)
ret <vscale x 2 x i16> %c ret <vscale x 2 x i16> %c
} }
define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i16>* %svp) { define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
; CHECK-LABEL: insert_nxv2i16_v2i16_2: ; CHECK-LABEL: insert_nxv2i16_v2i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4) %c = call <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)
ret <vscale x 2 x i16> %c ret <vscale x 2 x i16> %c
} }
define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) { define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) {
; CHECK-LABEL: insert_nxv2i1_v4i1_0: ; CHECK-LABEL: insert_nxv2i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0) %c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
ret <vscale x 2 x i1> %c ret <vscale x 2 x i1> %c
} }
define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) { define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
; CHECK-LABEL: insert_nxv8i1_v4i1_0: ; CHECK-LABEL: insert_nxv8i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vi v0, v8, 0 ; CHECK-NEXT: vslideup.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0) %c = call <vscale x 8 x i1> @llvm.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) { define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
; CHECK-LABEL: insert_nxv8i1_v8i1_16: ; CHECK-LABEL: insert_nxv8i1_v8i1_16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16) %c = call <vscale x 8 x i1> @llvm.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) declare <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
define void @insert_v2i64_nxv16i64(<2 x i64>* %psv0, <2 x i64>* %psv1, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64(<2 x i64>* %psv0, <2 x i64>* %psv1, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64: ; CHECK-LABEL: insert_v2i64_nxv16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v16, (a1) ; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: vsetivli zero, 6, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 6, e64, m8, tu, mu
; CHECK-NEXT: vslideup.vi v8, v16, 4 ; CHECK-NEXT: vslideup.vi v8, v16, 4
; CHECK-NEXT: vs8r.v v8, (a2) ; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv0 = load <2 x i64>, <2 x i64>* %psv0 %sv0 = load <2 x i64>, <2 x i64>* %psv0
%sv1 = load <2 x i64>, <2 x i64>* %psv1 %sv1 = load <2 x i64>, <2 x i64>* %psv1
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64_lo0: ; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vs8r.v v8, (a1) ; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64_lo2: ; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu
; CHECK-NEXT: vslideup.vi v16, v8, 2 ; CHECK-NEXT: vslideup.vi v16, v8, 2
; CHECK-NEXT: vs8r.v v16, (a1) ; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
; Check we don't mistakenly optimize this: we don't know whether this is ; Check we don't mistakenly optimize this: we don't know whether this is
; inserted into the low or high split vector. ; inserted into the low or high split vector.
define void @insert_v2i64_nxv16i64_hi(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64_hi(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64_hi: ; CHECK-LABEL: insert_v2i64_nxv16i64_hi:
Show All 19 Lines
; CHECK-NEXT: vl8re64.v v16, (a2) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vs8r.v v16, (a1) ; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: addi sp, s0, -64 ; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 8) %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 8)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
declare <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1>, <4 x i1>, i64) declare <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1>, <4 x i1>, i64)
declare <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1>, <8 x i1>, i64) declare <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1>, <8 x i1>, i64)
declare <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16>, <2 x i16>, i64) declare <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16>, <2 x i16>, i64)
declare <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32>, <2 x i32>, i64) declare <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32>, <2 x i32>, i64)
declare <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32>, <2 x i32>, i64) declare <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32>, <2 x i32>, i64)
declare <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1>, <4 x i1>, i64) declare <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1>, <4 x i1>, i64)
declare <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1>, <8 x i1>, i64) declare <vscale x 8 x i1> @llvm.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1>, <8 x i1>, i64)
declare <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16>, <2 x i16>, i64) declare <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16>, <2 x i16>, i64)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32>, <2 x i32>, i64) declare <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32>, <2 x i32>, i64)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.v4i32.nxv8i32(<vscale x 8 x i32>, <4 x i32>, i64) declare <vscale x 8 x i32> @llvm.vector.insert.v4i32.nxv8i32(<vscale x 8 x i32>, <4 x i32>, i64)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32>, <8 x i32>, i64) declare <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32>, <8 x i32>, i64)

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv4i32_0: ; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv4i32_4: ; CHECK-LABEL: insert_nxv8i32_nxv4i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v10, v12 ; CHECK-NEXT: vmv2r.v v10, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv2i32_0: ; CHECK-LABEL: insert_nxv8i32_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v12 ; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv2i32_2: ; CHECK-LABEL: insert_nxv8i32_nxv2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v9, v12 ; CHECK-NEXT: vmv1r.v v9, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv2i32_4: ; CHECK-LABEL: insert_nxv8i32_nxv2i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v12 ; CHECK-NEXT: vmv1r.v v10, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv8i32_nxv2i32_6: ; CHECK-LABEL: insert_nxv8i32_nxv2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v11, v12 ; CHECK-NEXT: vmv1r.v v11, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6) %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv1i8_nxv4i8_0: ; CHECK-LABEL: insert_nxv1i8_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0) %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv1i8_nxv4i8_3: ; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3) %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv8i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv8i32_8: ; CHECK-LABEL: insert_nxv16i32_nxv8i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv4r.v v12, v16 ; CHECK-NEXT: vmv4r.v v12, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv4i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v8, v16 ; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv4i32_4: ; CHECK-LABEL: insert_nxv16i32_nxv4i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v10, v16 ; CHECK-NEXT: vmv2r.v v10, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv4i32_8: ; CHECK-LABEL: insert_nxv16i32_nxv4i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v12, v16 ; CHECK-NEXT: vmv2r.v v12, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv4i32_12: ; CHECK-LABEL: insert_nxv16i32_nxv4i32_12:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v14, v16 ; CHECK-NEXT: vmv2r.v v14, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v16 ; CHECK-NEXT: vmv1r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_2: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v9, v16 ; CHECK-NEXT: vmv1r.v v9, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_4: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v10, v16 ; CHECK-NEXT: vmv1r.v v10, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_6: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v11, v16 ; CHECK-NEXT: vmv1r.v v11, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_8: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v16 ; CHECK-NEXT: vmv1r.v v12, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_10: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v13, v16 ; CHECK-NEXT: vmv1r.v v13, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_12: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_12:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v14, v16 ; CHECK-NEXT: vmv1r.v v14, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv2i32_14: ; CHECK-LABEL: insert_nxv16i32_nxv2i32_14:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v15, v16 ; CHECK-NEXT: vmv1r.v v15, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v8, v16, 0 ; CHECK-NEXT: vslideup.vi v8, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_1: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_6: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v11, v16, 0 ; CHECK-NEXT: vslideup.vi v11, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6) %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_0: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vi v8, v10, 0 ; CHECK-NEXT: vslideup.vi v8, v10, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_1: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_2: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_3: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_7: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: sub a1, a0, a1 ; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_15: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_15:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: sub a1, a0, a1 ; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v9, v10, a1 ; CHECK-NEXT: vslideup.vx v9, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15) %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_0: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vi v8, v16, 0 ; CHECK-NEXT: vslideup.vi v8, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0) %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_2: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2) %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_26: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v14, v16, a0 ; CHECK-NEXT: vslideup.vx v14, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26) %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0: ; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 0) %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 0)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26: ; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v14, v8, a0 ; CHECK-NEXT: vslideup.vx v14, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 26) %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 26)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) { define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv32i1_nxv8i1_0: ; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v0, v8, 0 ; CHECK-NEXT: vslideup.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0) %vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0)
ret <vscale x 32 x i1> %vec ret <vscale x 32 x i1> %vec
} }
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) { define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv32i1_nxv8i1_8: ; CHECK-LABEL: insert_nxv32i1_nxv8i1_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v0, v8, a0 ; CHECK-NEXT: vslideup.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8) %vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8)
ret <vscale x 32 x i1> %vec ret <vscale x 32 x i1> %vec
} }
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) { define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
; CHECK-LABEL: insert_nxv4i1_nxv1i1_0: ; CHECK-LABEL: insert_nxv4i1_nxv1i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0) %vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)
ret <vscale x 4 x i1> %vec ret <vscale x 4 x i1> %vec
} }
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) { define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
; CHECK-LABEL: insert_nxv4i1_nxv1i1_2: ; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vslideup.vx v9, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2) %vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
ret <vscale x 4 x i1> %vec ret <vscale x 4 x i1> %vec
} }
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64) declare <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64: ; CHECK-LABEL: insert_nxv8i64_nxv16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vs8r.v v16, (a0) ; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo: ; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi: ; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8) %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
declare <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1>, <vscale x 1 x i1>, i64) declare <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1>, <vscale x 1 x i1>, i64)
declare <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1>, <vscale x 8 x i1>, i64) declare <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1>, <vscale x 8 x i1>, i64)
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8>, <vscale x 1 x i8>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8>, <vscale x 1 x i8>, i64)
declare <vscale x 32 x half> @llvm.experimental.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half>, <vscale x 1 x half>, i64) declare <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half>, <vscale x 1 x half>, i64)
declare <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half>, <vscale x 2 x half>, i64) declare <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half>, <vscale x 2 x half>, i64)
declare <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8>, <vscale x 1 x i8>, i64 %idx) declare <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8>, <vscale x 1 x i8>, i64 %idx)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32>, <vscale x 2 x i32>, i64 %idx) declare <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32>, <vscale x 2 x i32>, i64 %idx)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32>, <vscale x 4 x i32>, i64 %idx) declare <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32>, <vscale x 4 x i32>, i64 %idx)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32>, <vscale x 1 x i32>, i64 %idx) declare <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32>, <vscale x 1 x i32>, i64 %idx)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32>, <vscale x 2 x i32>, i64 %idx) declare <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32>, <vscale x 2 x i32>, i64 %idx)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64 %idx) declare <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64 %idx)
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32>, <vscale x 8 x i32>, i64 %idx) declare <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32>, <vscale x 8 x i32>, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

Show First 20 Lines • Show All 1,260 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %idxs %ptrs = getelementptr inbounds i64, i64* %base, <vscale x 8 x i64> %idxs
%v = call <vscale x 8 x i64> @llvm.masked.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru) %v = call <vscale x 8 x i64> @llvm.masked.gather.nxv8i64.nxv8p0i64(<vscale x 8 x i64*> %ptrs, i32 8, <vscale x 8 x i1> %m, <vscale x 8 x i64> %passthru)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
declare <vscale x 16 x i64> @llvm.masked.gather.nxv16i64.nxv16p0f64(<vscale x 16 x i64*>, i32, <vscale x 16 x i1>, <vscale x 16 x i64>) declare <vscale x 16 x i64> @llvm.masked.gather.nxv16i64.nxv16p0f64(<vscale x 16 x i64*>, i32, <vscale x 16 x i1>, <vscale x 16 x i64>)
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64 %idx) declare <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64 %idx)
declare <vscale x 16 x i64*> @llvm.experimental.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*>, <vscale x 8 x i64*>, i64 %idx) declare <vscale x 16 x i64*> @llvm.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*>, <vscale x 8 x i64*>, i64 %idx)
define void @mgather_nxv16i64(<vscale x 8 x i64*> %ptrs0, <vscale x 8 x i64*> %ptrs1, <vscale x 16 x i1> %m, <vscale x 8 x i64> %passthru0, <vscale x 8 x i64> %passthru1, <vscale x 16 x i64>* %out) { define void @mgather_nxv16i64(<vscale x 8 x i64*> %ptrs0, <vscale x 8 x i64*> %ptrs1, <vscale x 16 x i1> %m, <vscale x 8 x i64> %passthru0, <vscale x 8 x i64> %passthru1, <vscale x 16 x i64>* %out) {
; RV32-LABEL: mgather_nxv16i64: ; RV32-LABEL: mgather_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vl8re64.v v24, (a0) ; RV32-NEXT: vl8re64.v v24, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t ; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
Show All 34 Lines
; RV64-NEXT: add a0, a2, a0 ; RV64-NEXT: add a0, a2, a0
; RV64-NEXT: vs8r.v v8, (a0) ; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vs8r.v v24, (a2) ; RV64-NEXT: vs8r.v v24, (a2)
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%p0 = call <vscale x 16 x i64*> @llvm.experimental.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*> undef, <vscale x 8 x i64*> %ptrs0, i64 0) %p0 = call <vscale x 16 x i64*> @llvm.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*> undef, <vscale x 8 x i64*> %ptrs0, i64 0)
%p1 = call <vscale x 16 x i64*> @llvm.experimental.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*> %p0, <vscale x 8 x i64*> %ptrs1, i64 8) %p1 = call <vscale x 16 x i64*> @llvm.vector.insert.nxv8p0i64.nxv16p0i64(<vscale x 16 x i64*> %p0, <vscale x 8 x i64*> %ptrs1, i64 8)
%pt0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %passthru0, i64 0) %pt0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %passthru0, i64 0)
%pt1 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %pt0, <vscale x 8 x i64> %passthru1, i64 8) %pt1 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %pt0, <vscale x 8 x i64> %passthru1, i64 8)
%v = call <vscale x 16 x i64> @llvm.masked.gather.nxv16i64.nxv16p0f64(<vscale x 16 x i64*> %p1, i32 8, <vscale x 16 x i1> %m, <vscale x 16 x i64> %pt1) %v = call <vscale x 16 x i64> @llvm.masked.gather.nxv16i64.nxv16p0f64(<vscale x 16 x i64*> %p1, i32 8, <vscale x 16 x i1> %m, <vscale x 16 x i64> %pt1)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
declare <vscale x 1 x half> @llvm.masked.gather.nxv1f16.nxv1p0f16(<vscale x 1 x half*>, i32, <vscale x 1 x i1>, <vscale x 1 x half>) declare <vscale x 1 x half> @llvm.masked.gather.nxv1f16.nxv1p0f16(<vscale x 1 x half*>, i32, <vscale x 1 x i1>, <vscale x 1 x half>)
▲ Show 20 Lines • Show All 951 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

Show First 20 Lines • Show All 1,813 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %idxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 8 x i64> %idxs
call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m) call void @llvm.masked.scatter.nxv8f64.nxv8p0f64(<vscale x 8 x double> %val, <vscale x 8 x double*> %ptrs, i32 8, <vscale x 8 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double>, <vscale x 16 x double*>, i32, <vscale x 16 x i1>) declare void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double>, <vscale x 16 x double*>, i32, <vscale x 16 x i1>)
declare <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double>, <vscale x 8 x double>, i64) declare <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double>, <vscale x 8 x double>, i64)
declare <vscale x 16 x double*> @llvm.experimental.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*>, <vscale x 8 x double*>, i64) declare <vscale x 16 x double*> @llvm.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*>, <vscale x 8 x double*>, i64)
define void @mscatter_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, <vscale x 8 x double*> %ptrs0, <vscale x 8 x double*> %ptrs1, <vscale x 16 x i1> %m) { define void @mscatter_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, <vscale x 8 x double*> %ptrs0, <vscale x 8 x double*> %ptrs1, <vscale x 16 x i1> %m) {
; RV32-LABEL: mscatter_nxv16f64: ; RV32-LABEL: mscatter_nxv16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vl4re32.v v24, (a0) ; RV32-NEXT: vl4re32.v v24, (a0)
; RV32-NEXT: vl4re32.v v28, (a1) ; RV32-NEXT: vl4re32.v v28, (a1)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t
Show All 26 Lines
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vsoxei64.v v8, (zero), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v16, v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%p0 = call <vscale x 16 x double*> @llvm.experimental.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*> undef, <vscale x 8 x double*> %ptrs0, i64 0) %p0 = call <vscale x 16 x double*> @llvm.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*> undef, <vscale x 8 x double*> %ptrs0, i64 0)
%p1 = call <vscale x 16 x double*> @llvm.experimental.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*> %p0, <vscale x 8 x double*> %ptrs1, i64 8) %p1 = call <vscale x 16 x double*> @llvm.vector.insert.nxv8p0f64.nxv16p0f64(<vscale x 16 x double*> %p0, <vscale x 8 x double*> %ptrs1, i64 8)
%v0 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0) %v0 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0)
%v1 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8) %v1 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8)
call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %p1, i32 8, <vscale x 16 x i1> %m) call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %p1, i32 8, <vscale x 16 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv16i8_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, double* %base, <vscale x 16 x i8> %idxs, <vscale x 16 x i1> %m) { define void @mscatter_baseidx_nxv16i8_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, double* %base, <vscale x 16 x i8> %idxs, <vscale x 16 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv16i8_nxv16f64: ; RV32-LABEL: mscatter_baseidx_nxv16i8_nxv16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vl2r.v v2, (a1) ; RV32-NEXT: vl2r.v v2, (a1)
Show All 22 Lines
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vx v0, v0, a1 ; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v8, v3 ; RV64-NEXT: vsext.vf8 v8, v3
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t ; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i8> %idxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i8> %idxs
%v0 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0) %v0 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0)
%v1 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8) %v1 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8)
call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %ptrs, i32 8, <vscale x 16 x i1> %m) call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %ptrs, i32 8, <vscale x 16 x i1> %m)
ret void ret void
} }
define void @mscatter_baseidx_nxv16i16_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m) { define void @mscatter_baseidx_nxv16i16_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, double* %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m) {
; RV32-LABEL: mscatter_baseidx_nxv16i16_nxv16f64: ; RV32-LABEL: mscatter_baseidx_nxv16i16_nxv16f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vl4re16.v v4, (a1) ; RV32-NEXT: vl4re16.v v4, (a1)
Show All 22 Lines
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, mu ; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vx v0, v0, a1 ; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf4 v8, v6 ; RV64-NEXT: vsext.vf4 v8, v6
; RV64-NEXT: vsll.vi v8, v8, 3 ; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t ; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i16> %idxs %ptrs = getelementptr inbounds double, double* %base, <vscale x 16 x i16> %idxs
%v0 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0) %v0 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> undef, <vscale x 8 x double> %val0, i64 0)
%v1 = call <vscale x 16 x double> @llvm.experimental.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8) %v1 = call <vscale x 16 x double> @llvm.vector.insert.nxv8f64.nxv16f64(<vscale x 16 x double> %v0, <vscale x 8 x double> %val1, i64 8)
call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %ptrs, i32 8, <vscale x 16 x i1> %m) call void @llvm.masked.scatter.nxv16f64.nxv16p0f64(<vscale x 16 x double> %v1, <vscale x 16 x double*> %ptrs, i32 8, <vscale x 16 x i1> %m)
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/vpload.ll

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%load = call <vscale x 16 x double> @llvm.vp.load.nxv16f64.p0nxv16f64(<vscale x 16 x double>* %ptr, <vscale x 16 x i1> %m, i32 %evl) %load = call <vscale x 16 x double> @llvm.vp.load.nxv16f64.p0nxv16f64(<vscale x 16 x double>* %ptr, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x double> %load ret <vscale x 16 x double> %load
} }
declare <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>*, <vscale x 17 x i1>, i32) declare <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>*, <vscale x 17 x i1>, i32)
declare <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %vec, i64 %idx) declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64(<vscale x 17 x double> %vec, i64 %idx)
declare <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %vec, i64 %idx) declare <vscale x 16 x double> @llvm.vector.extract.nxv16f64(<vscale x 17 x double> %vec, i64 %idx)
; Note: We can't return <vscale x 17 x double> as that introduces a vector ; Note: We can't return <vscale x 17 x double> as that introduces a vector
; store can't yet be legalized through widening. In order to test purely the ; store can't yet be legalized through widening. In order to test purely the
; vp.load legalization, manually split it. ; vp.load legalization, manually split it.
; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty. ; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty.
define <vscale x 16 x double> @vpload_nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 1 x double>* %out, <vscale x 17 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vpload_nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 1 x double>* %out, <vscale x 17 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mv a4, a3 ; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB38_10: ; CHECK-NEXT: .LBB38_10:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: vs1r.v v24, (a1) ; CHECK-NEXT: vs1r.v v24, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%load = call <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl) %load = call <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl)
%lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %load, i64 0) %lo = call <vscale x 16 x double> @llvm.vector.extract.nxv16f64(<vscale x 17 x double> %load, i64 0)
%hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %load, i64 16) %hi = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64(<vscale x 17 x double> %load, i64 16)
store <vscale x 1 x double> %hi, <vscale x 1 x double>* %out store <vscale x 1 x double> %hi, <vscale x 1 x double>* %out
ret <vscale x 16 x double> %lo ret <vscale x 16 x double> %lo
} }

llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll

; RUN: opt -S -passes=instcombine < %s | FileCheck %s ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu" target triple = "aarch64-unknown-linux-gnu"
; DUPQ b8 ; DUPQ b8
define <vscale x 16 x i1> @dupq_b_0() #0 { define <vscale x 16 x i1> @dupq_b_0() #0 {
; CHECK-LABEL: @dupq_b_0( ; CHECK-LABEL: @dupq_b_0(
; CHECK: ret <vscale x 16 x i1> zeroinitializer ; CHECK: ret <vscale x 16 x i1> zeroinitializer
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%2 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, %2 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef,
<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i64 0) i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i64 0)
%3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0) %3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4)
ret <vscale x 16 x i1> %5 ret <vscale x 16 x i1> %5
} }
define <vscale x 16 x i1> @dupq_b_d() #0 { define <vscale x 16 x i1> @dupq_b_d() #0 {
; CHECK-LABEL: @dupq_b_d( ; CHECK-LABEL: @dupq_b_d(
; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
; CHECK-NEXT: ret <vscale x 16 x i1> %2 ; CHECK-NEXT: ret <vscale x 16 x i1> %2
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%2 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, %2 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef,
<16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i64 0) i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i64 0)
%3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0) %3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4)
ret <vscale x 16 x i1> %5 ret <vscale x 16 x i1> %5
} }
define <vscale x 16 x i1> @dupq_b_w() #0 { define <vscale x 16 x i1> @dupq_b_w() #0 {
; CHECK-LABEL: @dupq_b_w( ; CHECK-LABEL: @dupq_b_w(
; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
; CHECK-NEXT: ret <vscale x 16 x i1> %2 ; CHECK-NEXT: ret <vscale x 16 x i1> %2
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%2 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, %2 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef,
<16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0,
i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>, i64 0) i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>, i64 0)
%3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0) %3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4)
ret <vscale x 16 x i1> %5 ret <vscale x 16 x i1> %5
} }
define <vscale x 16 x i1> @dupq_b_h() #0 { define <vscale x 16 x i1> @dupq_b_h() #0 {
; CHECK-LABEL: @dupq_b_h( ; CHECK-LABEL: @dupq_b_h(
; CHECK: %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK: %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
; CHECK-NEXT: ret <vscale x 16 x i1> %2 ; CHECK-NEXT: ret <vscale x 16 x i1> %2
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%2 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, %2 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef,
<16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0,
i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, i64 0) i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, i64 0)
%3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0) %3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4)
ret <vscale x 16 x i1> %5 ret <vscale x 16 x i1> %5
} }
define <vscale x 16 x i1> @dupq_b_b() #0 { define <vscale x 16 x i1> @dupq_b_b() #0 {
; CHECK-LABEL: @dupq_b_b( ; CHECK-LABEL: @dupq_b_b(
; CHECK: %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) ; CHECK: %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
; CHECK-NEXT: ret <vscale x 16 x i1> %1 ; CHECK-NEXT: ret <vscale x 16 x i1> %1
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%2 = tail call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, %2 = tail call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef,
<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i64 0) i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i64 0)
%3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0) %3 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x i8> %3, <vscale x 2 x i64> %4)
ret <vscale x 16 x i1> %5 ret <vscale x 16 x i1> %5
} }
; DUPQ b16 ; DUPQ b16
define <vscale x 8 x i1> @dupq_h_0() #0 { define <vscale x 8 x i1> @dupq_h_0() #0 {
; CHECK-LABEL: @dupq_h_0( ; CHECK-LABEL: @dupq_h_0(
; CHECK: ret <vscale x 8 x i1> zeroinitializer ; CHECK: ret <vscale x 8 x i1> zeroinitializer
%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%2 = tail call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, %2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef,
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i64 0) <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i64 0)
%3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0) %3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4)
ret <vscale x 8 x i1> %5 ret <vscale x 8 x i1> %5
} }
define <vscale x 8 x i1> @dupq_h_d() #0 { define <vscale x 8 x i1> @dupq_h_d() #0 {
; CHECK-LABEL: @dupq_h_d( ; CHECK-LABEL: @dupq_h_d(
; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
; CHECK-NEXT: %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2) ; CHECK-NEXT: %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
; CHECK-NEXT: ret <vscale x 8 x i1> %3 ; CHECK-NEXT: ret <vscale x 8 x i1> %3
%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%2 = tail call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, %2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef,
<8 x i16> <i16 1, i16 0, i16 0, i16 0, i16 1, i16 0, i16 0, i16 0>, i64 0) <8 x i16> <i16 1, i16 0, i16 0, i16 0, i16 1, i16 0, i16 0, i16 0>, i64 0)
%3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0) %3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4)
ret <vscale x 8 x i1> %5 ret <vscale x 8 x i1> %5
} }
define <vscale x 8 x i1> @dupq_h_w() #0 { define <vscale x 8 x i1> @dupq_h_w() #0 {
; CHECK-LABEL: @dupq_h_w( ; CHECK-LABEL: @dupq_h_w(
; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
; CHECK-NEXT: %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2) ; CHECK-NEXT: %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
; CHECK-NEXT: ret <vscale x 8 x i1> %3 ; CHECK-NEXT: ret <vscale x 8 x i1> %3
%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%2 = tail call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, %2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef,
<8 x i16> <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>, i64 0) <8 x i16> <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>, i64 0)
%3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0) %3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4)
ret <vscale x 8 x i1> %5 ret <vscale x 8 x i1> %5
} }
define <vscale x 8 x i1> @dupq_h_h() #0 { define <vscale x 8 x i1> @dupq_h_h() #0 {
; CHECK-LABEL: @dupq_h_h( ; CHECK-LABEL: @dupq_h_h(
; CHECK: %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK: %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: ret <vscale x 8 x i1> %1 ; CHECK-NEXT: ret <vscale x 8 x i1> %1
%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%2 = tail call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef, %2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> undef,
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i64 0) <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i64 0)
%3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0) %3 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %3, <vscale x 2 x i64> %4)
ret <vscale x 8 x i1> %5 ret <vscale x 8 x i1> %5
} }
; DUPQ b32 ; DUPQ b32
define <vscale x 4 x i1> @dupq_w_0() #0 { define <vscale x 4 x i1> @dupq_w_0() #0 {
; CHECK-LABEL: @dupq_w_0( ; CHECK-LABEL: @dupq_w_0(
; CHECK: ret <vscale x 4 x i1> zeroinitializer ; CHECK: ret <vscale x 4 x i1> zeroinitializer
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0) <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_w_d() #0 { define <vscale x 4 x i1> @dupq_w_d() #0 {
; CHECK-LABEL: @dupq_w_d( ; CHECK-LABEL: @dupq_w_d(
; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1) ; CHECK-NEXT: %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
; CHECK-NEXT: %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2) ; CHECK-NEXT: %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
; CHECK-NEXT: ret <vscale x 4 x i1> %3 ; CHECK-NEXT: ret <vscale x 4 x i1> %3
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 1, i32 0, i32 1, i32 0>, i64 0) <4 x i32> <i32 1, i32 0, i32 1, i32 0>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_w_w() #0 { define <vscale x 4 x i1> @dupq_w_w() #0 {
; CHECK-LABEL: @dupq_w_w( ; CHECK-LABEL: @dupq_w_w(
; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK: %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: ret <vscale x 4 x i1> %1 ; CHECK-NEXT: ret <vscale x 4 x i1> %1
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>, i64 0) <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
; DUPQ b64 ; DUPQ b64
define <vscale x 2 x i1> @dupq_d_0() #0 { define <vscale x 2 x i1> @dupq_d_0() #0 {
; CHECK-LABEL: @dupq_d_0( ; CHECK-LABEL: @dupq_d_0(
; CHECK: ret <vscale x 2 x i1> zeroinitializer ; CHECK: ret <vscale x 2 x i1> zeroinitializer
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 0, i64 0>, i64 0) <2 x i64> <i64 0, i64 0>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_d_d() #0 { define <vscale x 2 x i1> @dupq_d_d() #0 {
; CHECK-LABEL: @dupq_d_d( ; CHECK-LABEL: @dupq_d_d(
; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK: %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: ret <vscale x 2 x i1> %1 ; CHECK-NEXT: ret <vscale x 2 x i1> %1
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
; Cases that cannot be converted ; Cases that cannot be converted
define <vscale x 2 x i1> @dupq_neg1() #0 { define <vscale x 2 x i1> @dupq_neg1() #0 {
; CHECK-LABEL: @dupq_neg1( ; CHECK-LABEL: @dupq_neg1(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 0>, i64 0) <2 x i64> <i64 1, i64 0>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 4 x i1> @dupq_neg2() #0 { define <vscale x 4 x i1> @dupq_neg2() #0 {
; CHECK-LABEL: @dupq_neg2( ; CHECK-LABEL: @dupq_neg2(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 1, i32 0, i32 0, i32 1>, i64 0) <4 x i32> <i32 1, i32 0, i32 0, i32 1>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_neg3() #0 { define <vscale x 4 x i1> @dupq_neg3() #0 {
; CHECK-LABEL: @dupq_neg3( ; CHECK-LABEL: @dupq_neg3(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 0, i32 1, i32 0, i32 1>, i64 0) <4 x i32> <i32 0, i32 1, i32 0, i32 1>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_neg4() #0 { define <vscale x 4 x i1> @dupq_neg4() #0 {
; CHECK-LABEL: @dupq_neg4( ; CHECK-LABEL: @dupq_neg4(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 1, i32 1, i32 0, i32 0>, i64 0) <4 x i32> <i32 1, i32 1, i32 0, i32 0>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_neg5() #0 { define <vscale x 4 x i1> @dupq_neg5() #0 {
; CHECK-LABEL: @dupq_neg5( ; CHECK-LABEL: @dupq_neg5(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, %2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef,
<4 x i32> <i32 0, i32 0, i32 0, i32 1>, i64 0) <4 x i32> <i32 0, i32 0, i32 0, i32 1>, i64 0)
%3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0) %3 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 2 x i64> %4)
ret <vscale x 4 x i1> %5 ret <vscale x 4 x i1> %5
} }
define <vscale x 4 x i1> @dupq_neg6(i1 %a) #0 { define <vscale x 4 x i1> @dupq_neg6(i1 %a) #0 {
; CHECK-LABEL: @dupq_neg6( ; CHECK-LABEL: @dupq_neg6(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%2 = zext i1 %a to i32 %2 = zext i1 %a to i32
%3 = insertelement <4 x i32> <i32 1, i32 1, i32 1, i32 poison>, i32 %2, i32 3 %3 = insertelement <4 x i32> <i32 1, i32 1, i32 1, i32 poison>, i32 %2, i32 3
%4 = tail call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> %3, i64 0) %4 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> %3, i64 0)
%5 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %4 , i64 0) %5 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %4 , i64 0)
%6 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %6 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%7 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %5, <vscale x 2 x i64> %6) %7 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %5, <vscale x 2 x i64> %6)
ret <vscale x 4 x i1> %7 ret <vscale x 4 x i1> %7
} }
define <vscale x 2 x i1> @dupq_neg7() #0 { define <vscale x 2 x i1> @dupq_neg7() #0 {
; CHECK-LABEL: @dupq_neg7( ; CHECK-LABEL: @dupq_neg7(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 2) <2 x i64> <i64 1, i64 1>, i64 2)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_neg8() #0 { define <vscale x 2 x i1> @dupq_neg8() #0 {
; CHECK-LABEL: @dupq_neg8( ; CHECK-LABEL: @dupq_neg8(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 1) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 1)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_neg9(<vscale x 2 x i64> %x) #0 { define <vscale x 2 x i1> @dupq_neg9(<vscale x 2 x i64> %x) #0 {
; CHECK-LABEL: @dupq_neg9( ; CHECK-LABEL: @dupq_neg9(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %x, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %x,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_neg10() #0 { define <vscale x 2 x i1> @dupq_neg10() #0 {
; CHECK-LABEL: @dupq_neg10( ; CHECK-LABEL: @dupq_neg10(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 1) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 1)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_neg11(<vscale x 2 x i1> %pg) #0 { define <vscale x 2 x i1> @dupq_neg11(<vscale x 2 x i1> %pg) #0 {
; CHECK-LABEL: @dupq_neg11( ; CHECK-LABEL: @dupq_neg11(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %1 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%2 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %1 , i64 0) %2 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %1 , i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%4 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3) %4 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
ret <vscale x 2 x i1> %4 ret <vscale x 2 x i1> %4
} }
define <vscale x 2 x i1> @dupq_neg12() #0 { define <vscale x 2 x i1> @dupq_neg12() #0 {
; CHECK-LABEL: @dupq_neg12( ; CHECK-LABEL: @dupq_neg12(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 15) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 15)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0) %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
%5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4) %5 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %4)
ret <vscale x 2 x i1> %5 ret <vscale x 2 x i1> %5
} }
define <vscale x 2 x i1> @dupq_neg13(<vscale x 2 x i64> %x) #0 { define <vscale x 2 x i1> @dupq_neg13(<vscale x 2 x i64> %x) #0 {
; CHECK-LABEL: @dupq_neg13( ; CHECK-LABEL: @dupq_neg13(
; CHECK: cmpne ; CHECK: cmpne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
%2 = tail call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef, %2 = tail call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> undef,
<2 x i64> <i64 1, i64 1>, i64 0) <2 x i64> <i64 1, i64 1>, i64 0)
%3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0) %3 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %2 , i64 0)
%4 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %x) %4 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %3, <vscale x 2 x i64> %x)
ret <vscale x 2 x i1> %4 ret <vscale x 2 x i1> %4
} }
declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32) declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32) declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32) declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32) declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64)
declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64)
declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64)
declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64)
declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>) declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>) declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>) declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }

llvm/test/Transforms/InstCombine/canonicalize-vector-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; llvm.experimental.vector.extract canonicalizes to shufflevector in the fixed case. In the ; llvm.vector.extract canonicalizes to shufflevector in the fixed case. In the
; scalable case, we lower to the EXTRACT_SUBVECTOR ISD node. ; scalable case, we lower to the EXTRACT_SUBVECTOR ISD node.
declare <10 x i32> @llvm.experimental.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 %idx) declare <10 x i32> @llvm.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 %idx)
declare <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 %idx) declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 %idx)
declare <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx) declare <3 x i32> @llvm.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 %idx) declare <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 %idx)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 %idx) declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 %idx)
declare <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 %idx) declare <8 x i32> @llvm.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 %idx)
; ============================================================================ ; ; ============================================================================ ;
; Trivial cases ; Trivial cases
; ============================================================================ ; ; ============================================================================ ;
; Extracting the entirety of a vector is a nop. ; Extracting the entirety of a vector is a nop.
define <8 x i32> @trivial_nop(<8 x i32> %vec) { define <8 x i32> @trivial_nop(<8 x i32> %vec) {
; CHECK-LABEL: @trivial_nop( ; CHECK-LABEL: @trivial_nop(
; CHECK-NEXT: ret <8 x i32> [[VEC:%.*]] ; CHECK-NEXT: ret <8 x i32> [[VEC:%.*]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 0) %1 = call <8 x i32> @llvm.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 0)
ret <8 x i32> %1 ret <8 x i32> %1
} }
; ============================================================================ ; ; ============================================================================ ;
; Valid canonicalizations ; Valid canonicalizations
; ============================================================================ ; ; ============================================================================ ;
define <2 x i32> @valid_extraction_a(<8 x i32> %vec) { define <2 x i32> @valid_extraction_a(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_a( ; CHECK-LABEL: @valid_extraction_a(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: ret <2 x i32> [[TMP1]] ; CHECK-NEXT: ret <2 x i32> [[TMP1]]
; ;
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 0) %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 0)
ret <2 x i32> %1 ret <2 x i32> %1
} }
define <2 x i32> @valid_extraction_b(<8 x i32> %vec) { define <2 x i32> @valid_extraction_b(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_b( ; CHECK-LABEL: @valid_extraction_b(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: ret <2 x i32> [[TMP1]] ; CHECK-NEXT: ret <2 x i32> [[TMP1]]
; ;
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 2) %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 2)
ret <2 x i32> %1 ret <2 x i32> %1
} }
define <2 x i32> @valid_extraction_c(<8 x i32> %vec) { define <2 x i32> @valid_extraction_c(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_c( ; CHECK-LABEL: @valid_extraction_c(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 4, i32 5> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: ret <2 x i32> [[TMP1]] ; CHECK-NEXT: ret <2 x i32> [[TMP1]]
; ;
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 4) %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 4)
ret <2 x i32> %1 ret <2 x i32> %1
} }
define <2 x i32> @valid_extraction_d(<8 x i32> %vec) { define <2 x i32> @valid_extraction_d(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_d( ; CHECK-LABEL: @valid_extraction_d(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 6, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; CHECK-NEXT: ret <2 x i32> [[TMP1]] ; CHECK-NEXT: ret <2 x i32> [[TMP1]]
; ;
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 6) %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 6)
ret <2 x i32> %1 ret <2 x i32> %1
} }
define <4 x i32> @valid_extraction_e(<8 x i32> %vec) { define <4 x i32> @valid_extraction_e(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_e( ; CHECK-LABEL: @valid_extraction_e(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
; ;
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 0) %1 = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 0)
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <4 x i32> @valid_extraction_f(<8 x i32> %vec) { define <4 x i32> @valid_extraction_f(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_f( ; CHECK-LABEL: @valid_extraction_f(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
; ;
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 4) %1 = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 4)
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <3 x i32> @valid_extraction_g(<8 x i32> %vec) { define <3 x i32> @valid_extraction_g(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_g( ; CHECK-LABEL: @valid_extraction_g(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: ret <3 x i32> [[TMP1]] ; CHECK-NEXT: ret <3 x i32> [[TMP1]]
; ;
%1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 0) %1 = call <3 x i32> @llvm.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 0)
ret <3 x i32> %1 ret <3 x i32> %1
} }
define <3 x i32> @valid_extraction_h(<8 x i32> %vec) { define <3 x i32> @valid_extraction_h(<8 x i32> %vec) {
; CHECK-LABEL: @valid_extraction_h( ; CHECK-LABEL: @valid_extraction_h(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i32 3, i32 4, i32 5> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i32 3, i32 4, i32 5>
; CHECK-NEXT: ret <3 x i32> [[TMP1]] ; CHECK-NEXT: ret <3 x i32> [[TMP1]]
; ;
%1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 3) %1 = call <3 x i32> @llvm.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 3)
ret <3 x i32> %1 ret <3 x i32> %1
} }
; ============================================================================ ; ; ============================================================================ ;
; Scalable cases ; Scalable cases
; ============================================================================ ; ; ============================================================================ ;
; Scalable extractions should not be canonicalized. This will be lowered to the ; Scalable extractions should not be canonicalized. This will be lowered to the
; EXTRACT_SUBVECTOR ISD node later. ; EXTRACT_SUBVECTOR ISD node later.
define <4 x i32> @scalable_extract(<vscale x 4 x i32> %vec) { define <4 x i32> @scalable_extract(<vscale x 4 x i32> %vec) {
; CHECK-LABEL: @scalable_extract( ; CHECK-LABEL: @scalable_extract(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[VEC:%.*]], i64 0) ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[VEC:%.*]], i64 0)
; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
; ;
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0) %1 = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
ret <4 x i32> %1 ret <4 x i32> %1
} }

llvm/test/Transforms/InstCombine/canonicalize-vector-insert.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; llvm.experimental.vector.insert canonicalizes to shufflevector in the fixed case. In the ; llvm.vector.insert canonicalizes to shufflevector in the fixed case. In the
; scalable case, we lower to the INSERT_SUBVECTOR ISD node. ; scalable case, we lower to the INSERT_SUBVECTOR ISD node.
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 %idx) declare <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 %idx)
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 %idx) declare <8 x i32> @llvm.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 %idx)
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 %idx) declare <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 %idx)
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 %idx) declare <8 x i32> @llvm.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 %idx)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 %idx) declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 %idx)
; ============================================================================ ; ; ============================================================================ ;
; Trivial cases ; Trivial cases
; ============================================================================ ; ; ============================================================================ ;
; An insert that entirely overwrites an <n x ty> with another <n x ty> is a ; An insert that entirely overwrites an <n x ty> with another <n x ty> is a
; nop. ; nop.
define <8 x i32> @trivial_nop(<8 x i32> %vec, <8 x i32> %subvec) { define <8 x i32> @trivial_nop(<8 x i32> %vec, <8 x i32> %subvec) {
; CHECK-LABEL: @trivial_nop( ; CHECK-LABEL: @trivial_nop(
; CHECK-NEXT: ret <8 x i32> [[SUBVEC:%.*]] ; CHECK-NEXT: ret <8 x i32> [[SUBVEC:%.*]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 0) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 0)
ret <8 x i32> %1 ret <8 x i32> %1
} }
; ============================================================================ ; ; ============================================================================ ;
; Valid canonicalizations ; Valid canonicalizations
; ============================================================================ ; ; ============================================================================ ;
define <8 x i32> @valid_insertion_a(<8 x i32> %vec, <2 x i32> %subvec) { define <8 x i32> @valid_insertion_a(<8 x i32> %vec, <2 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_a( ; CHECK-LABEL: @valid_insertion_a(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 0) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 0)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_b(<8 x i32> %vec, <2 x i32> %subvec) { define <8 x i32> @valid_insertion_b(<8 x i32> %vec, <2 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_b( ; CHECK-LABEL: @valid_insertion_b(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 2) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 2)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_c(<8 x i32> %vec, <2 x i32> %subvec) { define <8 x i32> @valid_insertion_c(<8 x i32> %vec, <2 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_c( ; CHECK-LABEL: @valid_insertion_c(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 4) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 4)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_d(<8 x i32> %vec, <2 x i32> %subvec) { define <8 x i32> @valid_insertion_d(<8 x i32> %vec, <2 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_d( ; CHECK-LABEL: @valid_insertion_d(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 6) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 6)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_e(<8 x i32> %vec, <4 x i32> %subvec) { define <8 x i32> @valid_insertion_e(<8 x i32> %vec, <4 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_e( ; CHECK-LABEL: @valid_insertion_e(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 0) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 0)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_f(<8 x i32> %vec, <4 x i32> %subvec) { define <8 x i32> @valid_insertion_f(<8 x i32> %vec, <4 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_f( ; CHECK-LABEL: @valid_insertion_f(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 4) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 4)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_g(<8 x i32> %vec, <3 x i32> %subvec) { define <8 x i32> @valid_insertion_g(<8 x i32> %vec, <3 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_g( ; CHECK-LABEL: @valid_insertion_g(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 0) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 0)
ret <8 x i32> %1 ret <8 x i32> %1
} }
define <8 x i32> @valid_insertion_h(<8 x i32> %vec, <3 x i32> %subvec) { define <8 x i32> @valid_insertion_h(<8 x i32> %vec, <3 x i32> %subvec) {
; CHECK-LABEL: @valid_insertion_h( ; CHECK-LABEL: @valid_insertion_h(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 10, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 10, i32 6, i32 7>
; CHECK-NEXT: ret <8 x i32> [[TMP2]] ; CHECK-NEXT: ret <8 x i32> [[TMP2]]
; ;
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 3) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 3)
ret <8 x i32> %1 ret <8 x i32> %1
} }
; ============================================================================ ; ; ============================================================================ ;
; Scalable cases ; Scalable cases
; ============================================================================ ; ; ============================================================================ ;
; Scalable insertions should not be canonicalized. This will be lowered to the ; Scalable insertions should not be canonicalized. This will be lowered to the
; INSERT_SUBVECTOR ISD node later. ; INSERT_SUBVECTOR ISD node later.
define <vscale x 4 x i32> @scalable_insert(<vscale x 4 x i32> %vec, <4 x i32> %subvec) { define <vscale x 4 x i32> @scalable_insert(<vscale x 4 x i32> %vec, <4 x i32> %subvec) {
; CHECK-LABEL: @scalable_insert( ; CHECK-LABEL: @scalable_insert(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[VEC:%.*]], <4 x i32> [[SUBVEC:%.*]], i64 0) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[VEC:%.*]], <4 x i32> [[SUBVEC:%.*]], i64 0)
; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
; ;
%1 = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0) %1 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
ret <vscale x 4 x i32> %1 ret <vscale x 4 x i32> %1
} }

llvm/test/Transforms/InstSimplify/extract-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instsimplify -S | FileCheck %s ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
define <16 x i8> @redundant_insert_extract_chain(<16 x i8> %x) { define <16 x i8> @redundant_insert_extract_chain(<16 x i8> %x) {
; CHECK-LABEL: @redundant_insert_extract_chain( ; CHECK-LABEL: @redundant_insert_extract_chain(
; CHECK-NEXT: ret <16 x i8> [[X:%.*]] ; CHECK-NEXT: ret <16 x i8> [[X:%.*]]
; ;
%inserted = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> %x, i64 0) %inserted = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> %x, i64 0)
%extracted = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8(<vscale x 32 x i8> %inserted, i64 0) %extracted = call <16 x i8> @llvm.vector.extract.v16i8.nxv32i8(<vscale x 32 x i8> %inserted, i64 0)
ret <16 x i8> %extracted ret <16 x i8> %extracted
} }
define <8 x i8> @non_redundant_insert_extract_chain(<16 x i8> %x) { define <8 x i8> @non_redundant_insert_extract_chain(<16 x i8> %x) {
; CHECK-LABEL: @non_redundant_insert_extract_chain( ; CHECK-LABEL: @non_redundant_insert_extract_chain(
; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> [[X:%.*]], i64 0) ; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> [[X:%.*]], i64 0)
; CHECK-NEXT: [[EXTRACTED:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8> [[INSERTED]], i64 0) ; CHECK-NEXT: [[EXTRACTED:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8> [[INSERTED]], i64 0)
; CHECK-NEXT: ret <8 x i8> [[EXTRACTED]] ; CHECK-NEXT: ret <8 x i8> [[EXTRACTED]]
; ;
%inserted = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> %x, i64 0) %inserted = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8> undef, <16 x i8> %x, i64 0)
%extracted = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8> %inserted, i64 0) %extracted = call <8 x i8> @llvm.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8> %inserted, i64 0)
ret <8 x i8> %extracted ret <8 x i8> %extracted
} }
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8(<vscale x 32 x i8>, i64) declare <16 x i8> @llvm.vector.extract.v16i8.nxv32i8(<vscale x 32 x i8>, i64)
declare <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8>, i64) declare <8 x i8> @llvm.vector.extract.v8i8.nxv32i8(<vscale x 32 x i8>, i64)
declare <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8>, <16 x i8>, i64) declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.v16i8(<vscale x 32 x i8>, <16 x i8>, i64)

llvm/test/Transforms/InstSimplify/insert-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instsimplify -S | FileCheck %s ; RUN: opt < %s -passes=instsimplify -S | FileCheck %s
define <vscale x 16 x i8> @redundant_extract_insert_chain(<vscale x 16 x i8> %x) { define <vscale x 16 x i8> @redundant_extract_insert_chain(<vscale x 16 x i8> %x) {
; CHECK-LABEL: @redundant_extract_insert_chain( ; CHECK-LABEL: @redundant_extract_insert_chain(
; CHECK-NEXT: ret <vscale x 16 x i8> [[X:%.*]] ; CHECK-NEXT: ret <vscale x 16 x i8> [[X:%.*]]
; ;
%extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> %x, i64 0) %extracted = call <32 x i8> @llvm.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> %x, i64 0)
%inserted = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> %extracted, i64 0) %inserted = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> %extracted, i64 0)
ret <vscale x 16 x i8> %inserted ret <vscale x 16 x i8> %inserted
} }
define <vscale x 16 x i8> @non_redundant_extract_insert_chain_0(<vscale x 32 x i8> %x) { define <vscale x 16 x i8> @non_redundant_extract_insert_chain_0(<vscale x 32 x i8> %x) {
; CHECK-LABEL: @non_redundant_extract_insert_chain_0( ; CHECK-LABEL: @non_redundant_extract_insert_chain_0(
; CHECK-NEXT: [[EXTRACTED:%.*]] = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8> [[X:%.*]], i64 0) ; CHECK-NEXT: [[EXTRACTED:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8> [[X:%.*]], i64 0)
; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> [[EXTRACTED]], i64 0) ; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> [[EXTRACTED]], i64 0)
; CHECK-NEXT: ret <vscale x 16 x i8> [[INSERTED]] ; CHECK-NEXT: ret <vscale x 16 x i8> [[INSERTED]]
; ;
%extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8> %x, i64 0) %extracted = call <32 x i8> @llvm.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8> %x, i64 0)
%inserted = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> %extracted, i64 0) %inserted = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> undef, <32 x i8> %extracted, i64 0)
ret <vscale x 16 x i8> %inserted ret <vscale x 16 x i8> %inserted
} }
define <vscale x 16 x i8> @non_redundant_extract_insert_chain_1(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) { define <vscale x 16 x i8> @non_redundant_extract_insert_chain_1(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
; CHECK-LABEL: @non_redundant_extract_insert_chain_1( ; CHECK-LABEL: @non_redundant_extract_insert_chain_1(
; CHECK-NEXT: [[EXTRACTED:%.*]] = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> [[X:%.*]], i64 0) ; CHECK-NEXT: [[EXTRACTED:%.*]] = call <32 x i8> @llvm.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> [[X:%.*]], i64 0)
; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> [[Y:%.*]], <32 x i8> [[EXTRACTED]], i64 0) ; CHECK-NEXT: [[INSERTED:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> [[Y:%.*]], <32 x i8> [[EXTRACTED]], i64 0)
; CHECK-NEXT: ret <vscale x 16 x i8> [[INSERTED]] ; CHECK-NEXT: ret <vscale x 16 x i8> [[INSERTED]]
; ;
%extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> %x, i64 0) %extracted = call <32 x i8> @llvm.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8> %x, i64 0)
%inserted = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> %y, <32 x i8> %extracted, i64 0) %inserted = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8> %y, <32 x i8> %extracted, i64 0)
ret <vscale x 16 x i8> %inserted ret <vscale x 16 x i8> %inserted
} }
declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8>, i64) declare <32 x i8> @llvm.vector.extract.v32i8.nxv16i8(<vscale x 16 x i8>, i64)
declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8>, i64) declare <32 x i8> @llvm.vector.extract.v32i8.nxv32i8(<vscale x 32 x i8>, i64)
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8>, <32 x i8>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v32i8(<vscale x 16 x i8>, <32 x i8>, i64)

llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll

; RUN: opt < %s -interleaved-access -S | FileCheck %s ; RUN: opt < %s -interleaved-access -S | FileCheck %s
target triple = "aarch64-linux-gnu" target triple = "aarch64-linux-gnu"
define void @load_factor2(<32 x i16>* %ptr) #0 { define void @load_factor2(<32 x i16>* %ptr) #0 {
; CHECK-LABEL: @load_factor2( ; CHECK-LABEL: @load_factor2(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <32 x i16>* %ptr to i16* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <32 x i16>* %ptr to i16*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16(<vscale x 8 x i1> [[PTRUE]], i16* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16(<vscale x 8 x i1> [[PTRUE]], i16* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[LDN]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[LDN]], 1
; CHECK-NEXT: [[EXT1:%.*]] = call <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv8i16(<vscale x 8 x i16> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv8i16(<vscale x 8 x i16> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[LDN]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[LDN]], 0
; CHECK-NEXT: [[EXT2:%.*]] = call <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv8i16(<vscale x 8 x i16> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <16 x i16> @llvm.vector.extract.v16i16.nxv8i16(<vscale x 8 x i16> [[TMP3]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <32 x i16>, <32 x i16>* %ptr, align 4 %interleaved.vec = load <32 x i16>, <32 x i16>* %ptr, align 4
%v0 = shufflevector <32 x i16> %interleaved.vec, <32 x i16> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, %v0 = shufflevector <32 x i16> %interleaved.vec, <32 x i16> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14,
i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%v1 = shufflevector <32 x i16> %interleaved.vec, <32 x i16> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, %v1 = shufflevector <32 x i16> %interleaved.vec, <32 x i16> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15,
i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret void ret void
} }
define void @load_factor3(<24 x i32>* %ptr) #0 { define void @load_factor3(<24 x i32>* %ptr) #0 {
; CHECK-LABEL: @load_factor3( ; CHECK-LABEL: @load_factor3(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <24 x i32>* %ptr to i32* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <24 x i32>* %ptr to i32*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1> [[PTRUE]], i32* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1> [[PTRUE]], i32* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 2
; CHECK-NEXT: [[EXT1:%.*]] = call <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 1
; CHECK-NEXT: [[EXT2:%.*]] = call <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[LDN]], 0
; CHECK-NEXT: [[EXT3:%.*]] = call <8 x i32> @llvm.experimental.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0) ; CHECK-NEXT: [[EXT3:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv4i32(<vscale x 4 x i32> [[TMP4]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <24 x i32>, <24 x i32>* %ptr, align 4 %interleaved.vec = load <24 x i32>, <24 x i32>* %ptr, align 4
%v0 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %v0 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%v1 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %v1 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%v2 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %v2 = shufflevector <24 x i32> %interleaved.vec, <24 x i32> poison, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
ret void ret void
} }
define void @load_factor4(<16 x i64>* %ptr) #0 { define void @load_factor4(<16 x i64>* %ptr) #0 {
; CHECK-LABEL: @load_factor4( ; CHECK-LABEL: @load_factor4(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 3
; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2
; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0) ; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <16 x i64>, <16 x i64>* %ptr, align 4 %interleaved.vec = load <16 x i64>, <16 x i64>* %ptr, align 4
%v0 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %v0 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%v1 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %v1 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%v2 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %v2 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%v3 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %v3 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
ret void ret void
} }
define void @store_factor2(<32 x i16>* %ptr, <16 x i16> %v0, <16 x i16> %v1) #0 { define void @store_factor2(<32 x i16>* %ptr, <16 x i16> %v0, <16 x i16> %v1) #0 {
; CHECK-LABEL: @store_factor2( ; CHECK-LABEL: @store_factor2(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i16> %v0, <16 x i16> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i16> %v0, <16 x i16> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v16i16(<vscale x 8 x i16> undef, <16 x i16> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v16i16(<vscale x 8 x i16> undef, <16 x i16> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> %v0, <16 x i16> %v1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> %v0, <16 x i16> %v1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v16i16(<vscale x 8 x i16> undef, <16 x i16> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v16i16(<vscale x 8 x i16> undef, <16 x i16> [[TMP2]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <32 x i16>* %ptr to i16* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <32 x i16>* %ptr to i16*
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> [[INS1]], <vscale x 8 x i16> [[INS2]], <vscale x 8 x i1> [[PTRUE]], i16* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> [[INS1]], <vscale x 8 x i16> [[INS2]], <vscale x 8 x i1> [[PTRUE]], i16* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = shufflevector <16 x i16> %v0, <16 x i16> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, %interleaved.vec = shufflevector <16 x i16> %v0, <16 x i16> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23,
i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x i16> %interleaved.vec, <32 x i16>* %ptr, align 4 store <32 x i16> %interleaved.vec, <32 x i16>* %ptr, align 4
ret void ret void
} }
define void @store_factor3(<24 x i32>* %ptr, <8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) #0 { define void @store_factor3(<24 x i32>* %ptr, <8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) #0 {
; CHECK-LABEL: @store_factor3( ; CHECK-LABEL: @store_factor3(
; CHECK: [[PTRUE:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK: [[PTRUE:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> %s0, <16 x i32> %s1, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP3]], i64 0) ; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32> undef, <8 x i32> [[TMP3]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <24 x i32>* %ptr to i32* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <24 x i32>* %ptr to i32*
; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> [[INS1]], <vscale x 4 x i32> [[INS2]], <vscale x 4 x i32> [[INS3]], <vscale x 4 x i1> [[PTRUE]], i32* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> [[INS1]], <vscale x 4 x i32> [[INS2]], <vscale x 4 x i32> [[INS3]], <vscale x 4 x i1> [[PTRUE]], i32* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%s0 = shufflevector <8 x i32> %v0, <8 x i32> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, %s0 = shufflevector <8 x i32> %v0, <8 x i32> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%s1 = shufflevector <8 x i32> %v2, <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, %s1 = shufflevector <8 x i32> %v2, <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%interleaved.vec = shufflevector <16 x i32> %s0, <16 x i32> %s1, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, %interleaved.vec = shufflevector <16 x i32> %s0, <16 x i32> %s1, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19,
i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x i32> %interleaved.vec, <24 x i32>* %ptr, align 4 store <24 x i32> %interleaved.vec, <24 x i32>* %ptr, align 4
ret void ret void
} }
define void @store_factor4(<16 x i64>* %ptr, <4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, <4 x i64> %v3) #0 { define void @store_factor4(<16 x i64>* %ptr, <4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, <4 x i64> %v3) #0 {
; CHECK-LABEL: @store_factor4( ; CHECK-LABEL: @store_factor4(
; CHECK: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> %s0, <8 x i64> %s1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <16 x i64>* %ptr to i64* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <16 x i64>* %ptr to i64*
; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%s0 = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s0 = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s1 = shufflevector <4 x i64> %v2, <4 x i64> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s1 = shufflevector <4 x i64> %v2, <4 x i64> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%interleaved.vec = shufflevector <8 x i64> %s0, <8 x i64> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> %interleaved.vec = shufflevector <8 x i64> %s0, <8 x i64> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
store <16 x i64> %interleaved.vec, <16 x i64>* %ptr, align 4 store <16 x i64> %interleaved.vec, <16 x i64>* %ptr, align 4
ret void ret void
} }
define void @load_ptrvec_factor2(<8 x i32*>* %ptr) #0 { define void @load_ptrvec_factor2(<8 x i32*>* %ptr) #0 {
; CHECK-LABEL: @load_ptrvec_factor2( ; CHECK-LABEL: @load_ptrvec_factor2(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i32*>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i32*>* %ptr to i64*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*> ; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*>
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*> ; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*>
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <8 x i32*>, <8 x i32*>* %ptr, align 4 %interleaved.vec = load <8 x i32*>, <8 x i32*>* %ptr, align 4
%v0 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %v0 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%v1 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %v1 = shufflevector <8 x i32*> %interleaved.vec, <8 x i32*> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret void ret void
} }
define void @load_ptrvec_factor3(<12 x i32*>* %ptr) #0 { define void @load_ptrvec_factor3(<12 x i32*>* %ptr) #0 {
; CHECK-LABEL: @load_ptrvec_factor3( ; CHECK-LABEL: @load_ptrvec_factor3(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <12 x i32*>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <12 x i32*>* %ptr to i64*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2
; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*> ; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*>
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*> ; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*>
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[TOP3:%.*]] = inttoptr <4 x i64> [[EXT3]] to <4 x i32*> ; CHECK-NEXT: [[TOP3:%.*]] = inttoptr <4 x i64> [[EXT3]] to <4 x i32*>
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <12 x i32*>, <12 x i32*>* %ptr, align 4 %interleaved.vec = load <12 x i32*>, <12 x i32*>* %ptr, align 4
%v0 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %v0 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%v1 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %v1 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%v2 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %v2 = shufflevector <12 x i32*> %interleaved.vec, <12 x i32*> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
ret void ret void
} }
define void @load_ptrvec_factor4(<16 x i32*>* %ptr) #0 { define void @load_ptrvec_factor4(<16 x i32*>* %ptr) #0 {
; CHECK-LABEL: @load_ptrvec_factor4( ; CHECK-LABEL: @load_ptrvec_factor4(
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i32*>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i32*>* %ptr to i64*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 3
; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*> ; CHECK-NEXT: [[TOP1:%.*]] = inttoptr <4 x i64> [[EXT1]] to <4 x i32*>
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 2
; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*> ; CHECK-NEXT: [[TOP2:%.*]] = inttoptr <4 x i64> [[EXT2]] to <4 x i32*>
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[TOP3:%.*]] = inttoptr <4 x i64> [[EXT3]] to <4 x i32*> ; CHECK-NEXT: [[TOP3:%.*]] = inttoptr <4 x i64> [[EXT3]] to <4 x i32*>
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0) ; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0)
; CHECK-NEXT: [[TOP4:%.*]] = inttoptr <4 x i64> [[EXT4]] to <4 x i32*> ; CHECK-NEXT: [[TOP4:%.*]] = inttoptr <4 x i64> [[EXT4]] to <4 x i32*>
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <16 x i32*>, <16 x i32*>* %ptr, align 4 %interleaved.vec = load <16 x i32*>, <16 x i32*>* %ptr, align 4
%v0 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %v0 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%v1 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %v1 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%v2 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %v2 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%v3 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %v3 = shufflevector <16 x i32*> %interleaved.vec, <16 x i32*> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
ret void ret void
} }
define void @store_ptrvec_factor2(<8 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1) #0 { define void @store_ptrvec_factor2(<8 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1) #0 {
; CHECK-LABEL: @store_ptrvec_factor2( ; CHECK-LABEL: @store_ptrvec_factor2(
; CHECK-NEXT: [[TOI1:%.*]] = ptrtoint <4 x i32*> %v0 to <4 x i64> ; CHECK-NEXT: [[TOI1:%.*]] = ptrtoint <4 x i32*> %v0 to <4 x i64>
; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <4 x i32*> %v1 to <4 x i64> ; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <4 x i32*> %v1 to <4 x i64>
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TOI1]], <4 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TOI1]], <4 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TOI1]], <4 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TOI1]], <4 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <8 x i32*>* %ptr to i64* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <8 x i32*>* %ptr to i64*
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %interleaved.vec = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x i32*> %interleaved.vec, <8 x i32*>* %ptr, align 4 store <8 x i32*> %interleaved.vec, <8 x i32*>* %ptr, align 4
ret void ret void
} }
define void @store_ptrvec_factor3(<12 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1, <4 x i32*> %v2) #0 { define void @store_ptrvec_factor3(<12 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1, <4 x i32*> %v2) #0 {
; CHECK-LABEL: @store_ptrvec_factor3( ; CHECK-LABEL: @store_ptrvec_factor3(
; CHECK: [[TOI1:%.*]] = ptrtoint <8 x i32*> %s0 to <8 x i64> ; CHECK: [[TOI1:%.*]] = ptrtoint <8 x i32*> %s0 to <8 x i64>
; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <8 x i32*> %s1 to <8 x i64> ; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <8 x i32*> %s1 to <8 x i64>
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <12 x i32*>* %ptr to i64* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <12 x i32*>* %ptr to i64*
; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%s0 = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s0 = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s1 = shufflevector <4 x i32*> %v2, <4 x i32*> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %s1 = shufflevector <4 x i32*> %v2, <4 x i32*> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%interleaved.vec = shufflevector <8 x i32*> %s0, <8 x i32*> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %interleaved.vec = shufflevector <8 x i32*> %s0, <8 x i32*> %s1, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i32*> %interleaved.vec, <12 x i32*>* %ptr, align 4 store <12 x i32*> %interleaved.vec, <12 x i32*>* %ptr, align 4
ret void ret void
} }
define void @store_ptrvec_factor4(<16 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1, <4 x i32*> %v2, <4 x i32*> %v3) #0 { define void @store_ptrvec_factor4(<16 x i32*>* %ptr, <4 x i32*> %v0, <4 x i32*> %v1, <4 x i32*> %v2, <4 x i32*> %v3) #0 {
; CHECK-LABEL: @store_ptrvec_factor4( ; CHECK-LABEL: @store_ptrvec_factor4(
; CHECK: [[TOI1:%.*]] = ptrtoint <8 x i32*> %s0 to <8 x i64> ; CHECK: [[TOI1:%.*]] = ptrtoint <8 x i32*> %s0 to <8 x i64>
; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <8 x i32*> %s1 to <8 x i64> ; CHECK-NEXT: [[TOI2:%.*]] = ptrtoint <8 x i32*> %s1 to <8 x i64>
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP1]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> [[TOI1]], <8 x i64> [[TOI2]], <4 x i32> <i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[PTR:%.*]] = bitcast <16 x i32*>* %ptr to i64* ; CHECK-NEXT: [[PTR:%.*]] = bitcast <16 x i32*>* %ptr to i64*
; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[PTR]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%s0 = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s0 = shufflevector <4 x i32*> %v0, <4 x i32*> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s1 = shufflevector <4 x i32*> %v2, <4 x i32*> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s1 = shufflevector <4 x i32*> %v2, <4 x i32*> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%interleaved.vec = shufflevector <8 x i32*> %s0, <8 x i32*> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, %interleaved.vec = shufflevector <8 x i32*> %s0, <8 x i32*> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13,
i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
store <16 x i32*> %interleaved.vec, <16 x i32*>* %ptr, align 4 store <16 x i32*> %interleaved.vec, <16 x i32*>* %ptr, align 4
ret void ret void
} }
define void @load_factor2_wide(<16 x i64>* %ptr) #0 { define void @load_factor2_wide(<16 x i64>* %ptr) #0 {
; CHECK-LABEL: @load_factor2_wide( ; CHECK-LABEL: @load_factor2_wide(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64*
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[EXT1:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[EXT2:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, i64* [[TMP1]], i32 8 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, i64* [[TMP1]], i32 8
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP4]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> [[PTRUE]], i64* [[TMP4]])
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 1
; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0) ; CHECK-NEXT: [[EXT3:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP5]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[LDN]], 0
; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP6]], i64 0) ; CHECK-NEXT: [[EXT4:%.*]] = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> [[TMP6]], i64 0)
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[EXT1]], <4 x i64> [[EXT3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[EXT1]], <4 x i64> [[EXT3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i64> [[EXT2]], <4 x i64> [[EXT4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i64> [[EXT2]], <4 x i64> [[EXT4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = load <16 x i64>, <16 x i64>* %ptr, align 4 %interleaved.vec = load <16 x i64>, <16 x i64>* %ptr, align 4
%v0 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %v0 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%v1 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %v1 = shufflevector <16 x i64> %interleaved.vec, <16 x i64> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret void ret void
} }
define void @store_factor2_wide(<16 x i64>* %ptr, <8 x i64> %v0, <8 x i64> %v1) #0 { define void @store_factor2_wide(<16 x i64>* %ptr, <8 x i64> %v0, <8 x i64> %v1) #0 {
; CHECK-LABEL: @store_factor2_wide( ; CHECK-LABEL: @store_factor2_wide(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i64>* %ptr to i64*
; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[PTRUE:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0) ; CHECK-NEXT: [[INS1:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0) ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP3]], i64 0)
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i1> [[PTRUE]], i64* [[TMP1]])
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0) ; CHECK-NEXT: [[INS3:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i64> %v0, <8 x i64> %v1, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP5]], i64 0) ; CHECK-NEXT: [[INS4:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> undef, <4 x i64> [[TMP5]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, i64* [[TMP1]], i32 8 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, i64* [[TMP1]], i32 8
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[TMP6]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS3]], <vscale x 2 x i64> [[INS4]], <vscale x 2 x i1> [[PTRUE]], i64* [[TMP6]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
%interleaved.vec = shufflevector <8 x i64> %v0, <8 x i64> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %interleaved.vec = shufflevector <8 x i64> %v0, <8 x i64> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x i64> %interleaved.vec, <16 x i64>* %ptr, align 4 store <16 x i64> %interleaved.vec, <16 x i64>* %ptr, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
} }
define void @load_double_factor4(<16 x double>* %ptr) #0 { define void @load_double_factor4(<16 x double>* %ptr) #0 {
; CHECK-LABEL: @load_double_factor4( ; CHECK-LABEL: @load_double_factor4(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x double>* [[PTR:%.*]] to double* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x double>* [[PTR:%.*]] to double*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> [[TMP1]], double* [[TMP2]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> [[TMP1]], double* [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 3 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.experimental.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP3]], i64 0) ; CHECK-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 2
; CHECK-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.experimental.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP5]], i64 0) ; CHECK-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP5]], i64 0)
; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 1 ; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 1
; CHECK-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.experimental.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP7]], i64 0) ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP7]], i64 0)
; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[LDN]], 0
; CHECK-NEXT: [[TMP10:%.*]] = call <4 x double> @llvm.experimental.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP9]], i64 0) ; CHECK-NEXT: [[TMP10:%.*]] = call <4 x double> @llvm.vector.extract.v4f64.nxv2f64(<vscale x 2 x double> [[TMP9]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = load <16 x double>, <16 x double>* %ptr, align 4 %interleaved.vec = load <16 x double>, <16 x double>* %ptr, align 4
%v0 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %v0 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%v1 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %v1 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%v2 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %v2 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%v3 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %v3 = shufflevector <16 x double> %interleaved.vec, <16 x double> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
ret void ret void
} }
define void @load_float_factor3(<24 x float>* %ptr) #0 { define void @load_float_factor3(<24 x float>* %ptr) #0 {
; CHECK-LABEL: @load_float_factor3( ; CHECK-LABEL: @load_float_factor3(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <24 x float>* [[PTR:%.*]] to float* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <24 x float>* [[PTR:%.*]] to float*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1> [[TMP1]], float* [[TMP2]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1> [[TMP1]], float* [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 2
; CHECK-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.experimental.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP3]], i64 0) ; CHECK-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 1
; CHECK-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.experimental.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP5]], i64 0) ; CHECK-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP5]], i64 0)
; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[LDN]], 0
; CHECK-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.experimental.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP7]], i64 0) ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.vector.extract.v8f32.nxv4f32(<vscale x 4 x float> [[TMP7]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = load <24 x float>, <24 x float>* %ptr, align 4 %interleaved.vec = load <24 x float>, <24 x float>* %ptr, align 4
%v0 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %v0 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%v1 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %v1 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%v2 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %v2 = shufflevector <24 x float> %interleaved.vec, <24 x float> poison, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
ret void ret void
} }
define void @load_half_factor2(<32 x half>* %ptr) #0 { define void @load_half_factor2(<32 x half>* %ptr) #0 {
; CHECK-LABEL: @load_half_factor2( ; CHECK-LABEL: @load_half_factor2(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x half>* [[PTR:%.*]] to half* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x half>* [[PTR:%.*]] to half*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16(<vscale x 8 x i1> [[TMP1]], half* [[TMP2]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16(<vscale x 8 x i1> [[TMP1]], half* [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } [[LDN]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } [[LDN]], 1
; CHECK-NEXT: [[TMP4:%.*]] = call <16 x half> @llvm.experimental.vector.extract.v16f16.nxv8f16(<vscale x 8 x half> [[TMP3]], i64 0) ; CHECK-NEXT: [[TMP4:%.*]] = call <16 x half> @llvm.vector.extract.v16f16.nxv8f16(<vscale x 8 x half> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } [[LDN]], 0 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } [[LDN]], 0
; CHECK-NEXT: [[TMP6:%.*]] = call <16 x half> @llvm.experimental.vector.extract.v16f16.nxv8f16(<vscale x 8 x half> [[TMP5]], i64 0) ; CHECK-NEXT: [[TMP6:%.*]] = call <16 x half> @llvm.vector.extract.v16f16.nxv8f16(<vscale x 8 x half> [[TMP5]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = load <32 x half>, <32 x half>* %ptr, align 4 %interleaved.vec = load <32 x half>, <32 x half>* %ptr, align 4
%v0 = shufflevector <32 x half> %interleaved.vec, <32 x half> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %v0 = shufflevector <32 x half> %interleaved.vec, <32 x half> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%v1 = shufflevector <32 x half> %interleaved.vec, <32 x half> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %v1 = shufflevector <32 x half> %interleaved.vec, <32 x half> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret void ret void
} }
define void @load_bfloat_factor2(<32 x bfloat>* %ptr) #0 { define void @load_bfloat_factor2(<32 x bfloat>* %ptr) #0 {
; CHECK-LABEL: @load_bfloat_factor2( ; CHECK-LABEL: @load_bfloat_factor2(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x bfloat>* [[PTR:%.*]] to bfloat* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x bfloat>* [[PTR:%.*]] to bfloat*
; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2.sret.nxv8bf16(<vscale x 8 x i1> [[TMP1]], bfloat* [[TMP2]]) ; CHECK-NEXT: [[LDN:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2.sret.nxv8bf16(<vscale x 8 x i1> [[TMP1]], bfloat* [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[LDN]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[LDN]], 1
; CHECK-NEXT: [[TMP4:%.*]] = call <16 x bfloat> @llvm.experimental.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[TMP3]], i64 0) ; CHECK-NEXT: [[TMP4:%.*]] = call <16 x bfloat> @llvm.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[TMP3]], i64 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[LDN]], 0 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[LDN]], 0
; CHECK-NEXT: [[TMP6:%.*]] = call <16 x bfloat> @llvm.experimental.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[TMP5]], i64 0) ; CHECK-NEXT: [[TMP6:%.*]] = call <16 x bfloat> @llvm.vector.extract.v16bf16.nxv8bf16(<vscale x 8 x bfloat> [[TMP5]], i64 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = load <32 x bfloat>, <32 x bfloat>* %ptr, align 4 %interleaved.vec = load <32 x bfloat>, <32 x bfloat>* %ptr, align 4
%v0 = shufflevector <32 x bfloat> %interleaved.vec, <32 x bfloat> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %v0 = shufflevector <32 x bfloat> %interleaved.vec, <32 x bfloat> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%v1 = shufflevector <32 x bfloat> %interleaved.vec, <32 x bfloat> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %v1 = shufflevector <32 x bfloat> %interleaved.vec, <32 x bfloat> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret void ret void
} }
define void @store_double_factor4(<16 x double>* %ptr, <4 x double> %v0, <4 x double> %v1, <4 x double> %v2, <4 x double> %v3) #0 { define void @store_double_factor4(<16 x double>* %ptr, <4 x double> %v0, <4 x double> %v1, <4 x double> %v2, <4 x double> %v3) #0 {
; CHECK-LABEL: @store_double_factor4( ; CHECK-LABEL: @store_double_factor4(
; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x double> [[V2:%.*]], <4 x double> [[V3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x double> [[V2:%.*]], <4 x double> [[V3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP2]], i64 0) ; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP4]], i64 0) ; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP6]], i64 0) ; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP6]], i64 0)
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP8]], i64 0) ; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v4f64(<vscale x 2 x double> undef, <4 x double> [[TMP8]], i64 0)
; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x double>* [[PTR:%.*]] to double* ; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x double>* [[PTR:%.*]] to double*
; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> [[TMP3]], <vscale x 2 x double> [[TMP5]], <vscale x 2 x double> [[TMP7]], <vscale x 2 x double> [[TMP9]], <vscale x 2 x i1> [[TMP1]], double* [[TMP10]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> [[TMP3]], <vscale x 2 x double> [[TMP5]], <vscale x 2 x double> [[TMP7]], <vscale x 2 x double> [[TMP9]], <vscale x 2 x i1> [[TMP1]], double* [[TMP10]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%s0 = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s0 = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s1 = shufflevector <4 x double> %v2, <4 x double> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %s1 = shufflevector <4 x double> %v2, <4 x double> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%interleaved.vec = shufflevector <8 x double> %s0, <8 x double> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> %interleaved.vec = shufflevector <8 x double> %s0, <8 x double> %s1, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
store <16 x double> %interleaved.vec, <16 x double>* %ptr, align 4 store <16 x double> %interleaved.vec, <16 x double>* %ptr, align 4
ret void ret void
} }
define void @store_float_factor3(<24 x float>* %ptr, <8 x float> %v0, <8 x float> %v1, <8 x float> %v2) #0 { define void @store_float_factor3(<24 x float>* %ptr, <8 x float> %v0, <8 x float> %v1, <8 x float> %v2) #0 {
; CHECK-LABEL: @store_float_factor3( ; CHECK-LABEL: @store_float_factor3(
; CHECK-NEXT: [[S0:%.*]] = shufflevector <8 x float> [[V0:%.*]], <8 x float> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[S0:%.*]] = shufflevector <8 x float> [[V0:%.*]], <8 x float> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x float> [[V2:%.*]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x float> [[V2:%.*]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP2]], i64 0) ; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP4]], i64 0) ; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <16 x float> [[S0]], <16 x float> [[S1]], <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP6]], i64 0) ; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v8f32(<vscale x 4 x float> undef, <8 x float> [[TMP6]], i64 0)
; CHECK-NEXT: [[TMP8:%.*]] = bitcast <24 x float>* [[PTR:%.*]] to float* ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <24 x float>* [[PTR:%.*]] to float*
; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> [[TMP3]], <vscale x 4 x float> [[TMP5]], <vscale x 4 x float> [[TMP7]], <vscale x 4 x i1> [[TMP1]], float* [[TMP8]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> [[TMP3]], <vscale x 4 x float> [[TMP5]], <vscale x 4 x float> [[TMP7]], <vscale x 4 x i1> [[TMP1]], float* [[TMP8]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%s0 = shufflevector <8 x float> %v0, <8 x float> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, %s0 = shufflevector <8 x float> %v0, <8 x float> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%s1 = shufflevector <8 x float> %v2, <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, %s1 = shufflevector <8 x float> %v2, <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%interleaved.vec = shufflevector <16 x float> %s0, <16 x float> %s1, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, %interleaved.vec = shufflevector <16 x float> %s0, <16 x float> %s1, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19,
i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x float> %interleaved.vec, <24 x float>* %ptr, align 4 store <24 x float> %interleaved.vec, <24 x float>* %ptr, align 4
ret void ret void
} }
define void @store_half_factor2(<32 x half>* %ptr, <16 x half> %v0, <16 x half> %v1) #0 { define void @store_half_factor2(<32 x half>* %ptr, <16 x half> %v0, <16 x half> %v1) #0 {
; CHECK-LABEL: @store_half_factor2( ; CHECK-LABEL: @store_half_factor2(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x half> [[V0:%.*]], <16 x half> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x half> [[V0:%.*]], <16 x half> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v16f16(<vscale x 8 x half> undef, <16 x half> [[TMP2]], i64 0) ; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v16f16(<vscale x 8 x half> undef, <16 x half> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x half> [[V0]], <16 x half> [[V1]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x half> [[V0]], <16 x half> [[V1]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.v16f16(<vscale x 8 x half> undef, <16 x half> [[TMP4]], i64 0) ; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.v16f16(<vscale x 8 x half> undef, <16 x half> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x half>* [[PTR:%.*]] to half* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x half>* [[PTR:%.*]] to half*
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> [[TMP3]], <vscale x 8 x half> [[TMP5]], <vscale x 8 x i1> [[TMP1]], half* [[TMP6]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> [[TMP3]], <vscale x 8 x half> [[TMP5]], <vscale x 8 x i1> [[TMP1]], half* [[TMP6]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = shufflevector <16 x half> %v0, <16 x half> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, %interleaved.vec = shufflevector <16 x half> %v0, <16 x half> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23,
i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x half> %interleaved.vec, <32 x half>* %ptr, align 4 store <32 x half> %interleaved.vec, <32 x half>* %ptr, align 4
ret void ret void
} }
define void @store_bfloat_factor2(<32 x bfloat>* %ptr, <16 x bfloat> %v0, <16 x bfloat> %v1) #0 { define void @store_bfloat_factor2(<32 x bfloat>* %ptr, <16 x bfloat> %v0, <16 x bfloat> %v1) #0 {
; CHECK-LABEL: @store_bfloat_factor2( ; CHECK-LABEL: @store_bfloat_factor2(
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) ; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x bfloat> [[V0:%.*]], <16 x bfloat> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x bfloat> [[V0:%.*]], <16 x bfloat> [[V1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP2]], i64 0) ; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP2]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x bfloat> [[V0]], <16 x bfloat> [[V1]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x bfloat> [[V0]], <16 x bfloat> [[V1]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP4]], i64 0) ; CHECK-NEXT: [[TMP5:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v16bf16(<vscale x 8 x bfloat> undef, <16 x bfloat> [[TMP4]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x bfloat>* [[PTR:%.*]] to bfloat* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x bfloat>* [[PTR:%.*]] to bfloat*
; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8bf16(<vscale x 8 x bfloat> [[TMP3]], <vscale x 8 x bfloat> [[TMP5]], <vscale x 8 x i1> [[TMP1]], bfloat* [[TMP6]]) ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv8bf16(<vscale x 8 x bfloat> [[TMP3]], <vscale x 8 x bfloat> [[TMP5]], <vscale x 8 x i1> [[TMP1]], bfloat* [[TMP6]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%interleaved.vec = shufflevector <16 x bfloat> %v0, <16 x bfloat> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, %interleaved.vec = shufflevector <16 x bfloat> %v0, <16 x bfloat> %v1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23,
i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x bfloat> %interleaved.vec, <32 x bfloat>* %ptr, align 4 store <32 x bfloat> %interleaved.vec, <32 x bfloat>* %ptr, align 4
ret void ret void
} }
attributes #0 = { vscale_range(2,2) "target-features"="+sve" } attributes #0 = { vscale_range(2,2) "target-features"="+sve" }
attributes #1 = { vscale_range(2,4) "target-features"="+sve" } attributes #1 = { vscale_range(2,4) "target-features"="+sve" }
attributes #2 = { vscale_range(4,4) "target-features"="+sve" } attributes #2 = { vscale_range(4,4) "target-features"="+sve" }

llvm/test/Verifier/extract-vector-mismatched-element-types.ll

; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s ; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s
; CHECK: experimental_vector_extract result must have the same element type as the input vector. ; CHECK: vector_extract result must have the same element type as the input vector.
define <16 x i16> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec) nounwind { define <16 x i16> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec) nounwind {
%retval = call <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8> %vec, i64 0) %retval = call <16 x i16> @llvm.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
ret <16 x i16> %retval ret <16 x i16> %retval
} }
declare <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8>, i64) declare <16 x i16> @llvm.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8>, i64)

llvm/test/Verifier/insert-extract-intrinsics-invalid.ll

; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s ; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s
; ;
; Test that extractions/insertion indices are validated. ; Test that extractions/insertion indices are validated.
; ;
; CHECK: experimental_vector_extract index must be a constant multiple of the result type's known minimum vector length. ; CHECK: vector_extract index must be a constant multiple of the result type's known minimum vector length.
define <4 x i32> @extract_idx_not_constant_multiple(<8 x i32> %vec) { define <4 x i32> @extract_idx_not_constant_multiple(<8 x i32> %vec) {
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 1) %1 = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 1)
ret <4 x i32> %1 ret <4 x i32> %1
} }
; CHECK: experimental_vector_insert index must be a constant multiple of the subvector's known minimum vector length. ; CHECK: vector_insert index must be a constant multiple of the subvector's known minimum vector length.
define <8 x i32> @insert_idx_not_constant_multiple(<8 x i32> %vec, <4 x i32> %subvec) { define <8 x i32> @insert_idx_not_constant_multiple(<8 x i32> %vec, <4 x i32> %subvec) {
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 2) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 2)
ret <8 x i32> %1 ret <8 x i32> %1
} }
; ;
; Test that extractions/insertions which 'overrun' are captured. ; Test that extractions/insertions which 'overrun' are captured.
; ;
; CHECK: experimental_vector_extract would overrun. ; CHECK: vector_extract would overrun.
define <3 x i32> @extract_overrun_fixed_fixed(<8 x i32> %vec) { define <3 x i32> @extract_overrun_fixed_fixed(<8 x i32> %vec) {
%1 = call <3 x i32> @llvm.experimental.vector.extract.v8i32.v3i32(<8 x i32> %vec, i64 6) %1 = call <3 x i32> @llvm.vector.extract.v8i32.v3i32(<8 x i32> %vec, i64 6)
ret <3 x i32> %1 ret <3 x i32> %1
} }
; CHECK: experimental_vector_extract would overrun. ; CHECK: vector_extract would overrun.
define <vscale x 3 x i32> @extract_overrun_scalable_scalable(<vscale x 8 x i32> %vec) { define <vscale x 3 x i32> @extract_overrun_scalable_scalable(<vscale x 8 x i32> %vec) {
%1 = call <vscale x 3 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv3i32(<vscale x 8 x i32> %vec, i64 6) %1 = call <vscale x 3 x i32> @llvm.vector.extract.nxv8i32.nxv3i32(<vscale x 8 x i32> %vec, i64 6)
ret <vscale x 3 x i32> %1 ret <vscale x 3 x i32> %1
} }
; We cannot statically check whether or not an extraction of a fixed vector ; We cannot statically check whether or not an extraction of a fixed vector
; from a scalable vector would overrun, because we can't compare the sizes of ; from a scalable vector would overrun, because we can't compare the sizes of
; the two. Therefore, this function should not raise verifier errors. ; the two. Therefore, this function should not raise verifier errors.
; CHECK-NOT: experimental_vector_extract ; CHECK-NOT: vector_extract
define <3 x i32> @extract_overrun_scalable_fixed(<vscale x 8 x i32> %vec) { define <3 x i32> @extract_overrun_scalable_fixed(<vscale x 8 x i32> %vec) {
%1 = call <3 x i32> @llvm.experimental.vector.extract.nxv8i32.v3i32(<vscale x 8 x i32> %vec, i64 6) %1 = call <3 x i32> @llvm.vector.extract.nxv8i32.v3i32(<vscale x 8 x i32> %vec, i64 6)
ret <3 x i32> %1 ret <3 x i32> %1
} }
; CHECK: subvector operand of experimental_vector_insert would overrun the vector being inserted into. ; CHECK: subvector operand of vector_insert would overrun the vector being inserted into.
define <8 x i32> @insert_overrun_fixed_fixed(<8 x i32> %vec, <3 x i32> %subvec) { define <8 x i32> @insert_overrun_fixed_fixed(<8 x i32> %vec, <3 x i32> %subvec) {
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 6) %1 = call <8 x i32> @llvm.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 6)
ret <8 x i32> %1 ret <8 x i32> %1
} }
; CHECK: subvector operand of experimental_vector_insert would overrun the vector being inserted into. ; CHECK: subvector operand of vector_insert would overrun the vector being inserted into.
define <vscale x 8 x i32> @insert_overrun_scalable_scalable(<vscale x 8 x i32> %vec, <vscale x 3 x i32> %subvec) { define <vscale x 8 x i32> @insert_overrun_scalable_scalable(<vscale x 8 x i32> %vec, <vscale x 3 x i32> %subvec) {
%1 = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv3i32(<vscale x 8 x i32> %vec, <vscale x 3 x i32> %subvec, i64 6) %1 = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv3i32(<vscale x 8 x i32> %vec, <vscale x 3 x i32> %subvec, i64 6)
ret <vscale x 8 x i32> %1 ret <vscale x 8 x i32> %1
} }
; We cannot statically check whether or not an insertion of a fixed vector into ; We cannot statically check whether or not an insertion of a fixed vector into
; a scalable vector would overrun, because we can't compare the sizes of the ; a scalable vector would overrun, because we can't compare the sizes of the
; two. Therefore, this function should not raise verifier errors. ; two. Therefore, this function should not raise verifier errors.
; CHECK-NOT: experimental_vector_insert ; CHECK-NOT: vector_insert
define <vscale x 8 x i32> @insert_overrun_scalable_fixed(<vscale x 8 x i32> %vec, <3 x i32> %subvec) { define <vscale x 8 x i32> @insert_overrun_scalable_fixed(<vscale x 8 x i32> %vec, <3 x i32> %subvec) {
%1 = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.v3i32(<vscale x 8 x i32> %vec, <3 x i32> %subvec, i64 6) %1 = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.v3i32(<vscale x 8 x i32> %vec, <3 x i32> %subvec, i64 6)
ret <vscale x 8 x i32> %1 ret <vscale x 8 x i32> %1
} }
declare <vscale x 3 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv3i32(<vscale x 8 x i32>, i64) declare <vscale x 3 x i32> @llvm.vector.extract.nxv8i32.nxv3i32(<vscale x 8 x i32>, i64)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv3i32(<vscale x 8 x i32>, <vscale x 3 x i32>, i64) declare <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv3i32(<vscale x 8 x i32>, <vscale x 3 x i32>, i64)
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.v3i32(<vscale x 8 x i32>, <3 x i32>, i64) declare <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.v3i32(<vscale x 8 x i32>, <3 x i32>, i64)
declare <3 x i32> @llvm.experimental.vector.extract.nxv8i32.v3i32(<vscale x 8 x i32>, i64) declare <3 x i32> @llvm.vector.extract.nxv8i32.v3i32(<vscale x 8 x i32>, i64)
declare <3 x i32> @llvm.experimental.vector.extract.v8i32.v3i32(<8 x i32>, i64) declare <3 x i32> @llvm.vector.extract.v8i32.v3i32(<8 x i32>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32>, i64) declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64)
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32>, <3 x i32>, i64) declare <8 x i32> @llvm.vector.insert.v8i32.v3i32(<8 x i32>, <3 x i32>, i64)
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32>, <4 x i32>, i64) declare <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32>, <4 x i32>, i64)

llvm/test/Verifier/insert-vector-mismatched-element-types.ll

; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s ; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s
; CHECK: experimental_vector_insert parameters must have the same element type. ; CHECK: vector_insert parameters must have the same element type.
define <vscale x 16 x i8> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec, <4 x i16> %subvec) nounwind { define <vscale x 16 x i8> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec, <4 x i16> %subvec) nounwind {
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8> %vec, <4 x i16> %subvec, i64 0) %retval = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8> %vec, <4 x i16> %subvec, i64 0)
ret <vscale x 16 x i8> %retval ret <vscale x 16 x i8> %retval
} }
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8>, <4 x i16>, i64) declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8>, <4 x i16>, i64)