[RISCV][TargetLowering] Special case overflow expansion for (uaddo X, C).

[HsiangKai]

Summary

Follow-up to D122933.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8823–8826

Do we have any tests where RHS is a constant, but not a simm12 and needs to be placed in a register.

Would also be good to test cases where the setcc result is used by a branch. Even a simm12 would need to be put in a register for that case.

[HsiangKai]

Add test cases.

[HsiangKai]

Move new test cases to the end of the test file to remove unnecessary noises.

[HsiangKai]

Update failed PowerPC test cases.

[reames]

It's not clear to my why preferring a comparison involving RHS over one involving LHS is generally profitable just because RHS happens to be a constant. Correct me if I'm wrong, but nothing has ensured that RHS is a small constant has it? Meaning, we may have to materialize it into a register and pay the same cost as the LHS based compare? By using RHS, we loose the ability to do CSE of repeated uadds.

I think you want some predicate to check that the comparison can fold into an immediate form at the minimum.

I'm new to this area, so I may simply be missing something here.

[craig.topper]

llvm/test/CodeGen/RISCV/xaluo.ll

4460

This is materializing a constant in a register which we didn't need to do before. Looking at the generated code before this patch, there was a move instruction, but I think that was because of register allocation constraints from above and below.

If we change the test to this, then this patch increases instructions.

define i64 @uaddo.i64.constant_setcc_on_overflow_flag(i64* %p) {
entry:
  %v1 = load i64, i64* %p
  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
  %val = extractvalue {i64, i1} %t, 0
  %obit = extractvalue {i64, i1} %t, 1
  br i1 %obit, label %IfOverflow, label %IfNoOverflow
IfOverflow:
  ret i64 0
IfNoOverflow:
  ret i64 %val
}

[HsiangKai]

Add predicate for (uaddo X, C).

[HsiangKai]

llvm/test/CodeGen/RISCV/xaluo.ll

4460

Indeed, this patch increases instructions in this case. I have to think about it.

[HsiangKai]

Revert the change and modify the comments only.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8822–8823

"necessary benefits" -> "necessarily beneficial"

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6971–6972

Here too

6973

"especially the setcc" -> "especially when the setcc"

[HsiangKai]

Address comments.

[craig.topper]

LGTM

[craig.topper]

Kind of late now, but I didn't notice the title wasn't updated. So it doesn't match the contents of the patch.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

void TargetLowering::expandUADDSUBO(
   }
 
   Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
                             LHS.getValueType(), LHS, RHS);
 
   EVT ResultType = Node->getValueType(1);
   EVT SetCCType = getSetCCResultType(
       DAG.getDataLayout(), *DAG.getContext(), Node->getValueType(0));
   SDValue SetCC;
-  if (IsAdd && isOneConstant(RHS)) {
-    // Special case: uaddo X, 1 overflowed if X+1 is 0. This potential reduces
-    // the live range of X. We assume comparing with 0 is cheap.
-    // TODO: This generalizes to (X + C) < C.
-    SetCC =
-        DAG.getSetCC(dl, SetCCType, Result,
-                     DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETEQ);
+  if (IsAdd && isa<ConstantSDNode>(RHS)) {
+    // Special case: uaddo X, C overflowed if X+C < C. This potential reduces
+    // the live range of X.
+    SetCC = DAG.getSetCC(dl, SetCCType, Result, RHS, ISD::SETULT);
   } else {
     ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
     SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC);
   }
   Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
 }
 
 void TargetLowering::expandSADDSUBO(

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case ISD::USUBO: {
     // Create an ADDW or SUBW.
     SDValue LHS = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
     SDValue RHS = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
     SDValue Res =
         DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);
     Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Res,
                       DAG.getValueType(MVT::i32));
 
     SDValue Overflow;
-    if (IsAdd && isOneConstant(RHS)) {
-      // Special case uaddo X, 1 overflowed if the addition result is 0.
-      // FIXME: We can do this for any constant RHS by using (X + C) < C.
-      Overflow = DAG.getSetCC(DL, N->getValueType(1), Res,
-                              DAG.getConstant(0, DL, MVT::i64), ISD::SETEQ);
+    if (IsAdd && isa<ConstantSDNode>(RHS)) {
+      // Special case uaddo X, C overflowed if the addition result is less than
+      // C.
+      Overflow = DAG.getSetCC(DL, N->getValueType(1), Res, RHS, ISD::SETULT);
     } else {
       // Sign extend the LHS and perform an unsigned compare with the ADDW
       // result. Since the inputs are sign extended from i32, this is equivalent
       // to comparing the lower 32 bits.
       LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(0));
       Overflow = DAG.getSetCC(DL, N->getValueType(1), Res, LHS,
                               IsAdd ? ISD::SETULT : ISD::SETUGT);
     }

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   store i32 %val, i32* %res
   ret i1 %obit
 }
 
 define zeroext i1 @uaddo.i32.constant(i32 %v1, i32* %res) {
 ; RV32-LABEL: uaddo.i32.constant:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi a2, a0, -2
-; RV32-NEXT:    sltu a0, a2, a0
+; RV32-NEXT:    sltiu a0, a2, -2
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.i32.constant:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sext.w a2, a0
-; RV64-NEXT:    addiw a3, a0, -2
-; RV64-NEXT:    sltu a0, a3, a2
-; RV64-NEXT:    sw a3, 0(a1)
+; RV64-NEXT:    addiw a2, a0, -2
+; RV64-NEXT:    sltiu a0, a2, -2
+; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.i32.constant:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi a2, a0, -2
-; RV32ZBA-NEXT:    sltu a0, a2, a0
+; RV32ZBA-NEXT:    sltiu a0, a2, -2
 ; RV32ZBA-NEXT:    sw a2, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.i32.constant:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    sext.w a2, a0
-; RV64ZBA-NEXT:    addiw a3, a0, -2
-; RV64ZBA-NEXT:    sltu a0, a3, a2
-; RV64ZBA-NEXT:    sw a3, 0(a1)
+; RV64ZBA-NEXT:    addiw a2, a0, -2
+; RV64ZBA-NEXT:    sltiu a0, a2, -2
+; RV64ZBA-NEXT:    sw a2, 0(a1)
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }

 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit
 }
 
+define zeroext i1 @uaddo.i64.constant(i64 %v1, i64* %res) {
+; RV32-LABEL: uaddo.i64.constant:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    addi a4, a0, 2
+; RV32-NEXT:    sltu a0, a4, a0
+; RV32-NEXT:    add a5, a1, a0
+; RV32-NEXT:    bgeu a4, a3, .LBB11_2
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    sltu a0, a5, a1
+; RV32-NEXT:  .LBB11_2: # %entry
+; RV32-NEXT:    sw a4, 0(a2)
+; RV32-NEXT:    sw a5, 4(a2)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: uaddo.i64.constant:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a2, a0, 2
+; RV64-NEXT:    sltiu a0, a2, 2
+; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: uaddo.i64.constant:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    mv a3, a0
+; RV32ZBA-NEXT:    addi a4, a0, 2
+; RV32ZBA-NEXT:    sltu a0, a4, a0
+; RV32ZBA-NEXT:    add a5, a1, a0
+; RV32ZBA-NEXT:    bgeu a4, a3, .LBB11_2
+; RV32ZBA-NEXT:  # %bb.1: # %entry
+; RV32ZBA-NEXT:    sltu a0, a5, a1
+; RV32ZBA-NEXT:  .LBB11_2: # %entry
+; RV32ZBA-NEXT:    sw a4, 0(a2)
+; RV32ZBA-NEXT:    sw a5, 4(a2)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a2, a0, 2
+; RV64ZBA-NEXT:    sltiu a0, a2, 2
+; RV64ZBA-NEXT:    sd a2, 0(a1)
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
+  %val = extractvalue {i64, i1} %t, 0
+  %obit = extractvalue {i64, i1} %t, 1
+  store i64 %val, i64* %res
+  ret i1 %obit
+}
+
 define zeroext i1 @uaddo.i64.constant_one(i64 %v1, i64* %res) {
 ; RV32-LABEL: uaddo.i64.constant_one:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mv a3, a0
 ; RV32-NEXT:    addi a4, a0, 1
 ; RV32-NEXT:    sltu a0, a4, a0
 ; RV32-NEXT:    add a5, a1, a0
-; RV32-NEXT:    bgeu a4, a3, .LBB11_2
+; RV32-NEXT:    bgeu a4, a3, .LBB12_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a5, a1
-; RV32-NEXT:  .LBB11_2: # %entry
+; RV32-NEXT:  .LBB12_2: # %entry
 ; RV32-NEXT:    sw a4, 0(a2)
 ; RV32-NEXT:    sw a5, 4(a2)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.i64.constant_one:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi a2, a0, 1
 ; RV64-NEXT:    seqz a0, a2
 ; RV64-NEXT:    sd a2, 0(a1)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.i64.constant_one:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mv a3, a0
 ; RV32ZBA-NEXT:    addi a4, a0, 1
 ; RV32ZBA-NEXT:    sltu a0, a4, a0
 ; RV32ZBA-NEXT:    add a5, a1, a0
-; RV32ZBA-NEXT:    bgeu a4, a3, .LBB11_2
+; RV32ZBA-NEXT:    bgeu a4, a3, .LBB12_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a5, a1
-; RV32ZBA-NEXT:  .LBB11_2: # %entry
+; RV32ZBA-NEXT:  .LBB12_2: # %entry
 ; RV32ZBA-NEXT:    sw a4, 0(a2)
 ; RV32ZBA-NEXT:    sw a5, 4(a2)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.i64.constant_one:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    addi a2, a0, 1
 ; RV64ZBA-NEXT:    seqz a0, a2
 ; RV64ZBA-NEXT:    sd a2, 0(a1)
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   store i64 %val, i64* %res
   ret i1 %obit
 }
 
+define zeroext i1 @uaddo.i64.constant_2048(i64 %v1, i64* %res) {
+; RV32-LABEL: uaddo.i64.constant_2048:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    addi a0, a0, 1024
+; RV32-NEXT:    addi a4, a0, 1024
+; RV32-NEXT:    sltu a0, a4, a3
+; RV32-NEXT:    add a5, a1, a0
+; RV32-NEXT:    bgeu a4, a3, .LBB13_2
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    sltu a0, a5, a1
+; RV32-NEXT:  .LBB13_2: # %entry
+; RV32-NEXT:    sw a4, 0(a2)
+; RV32-NEXT:    sw a5, 4(a2)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: uaddo.i64.constant_2048:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a0, a0, 1024
+; RV64-NEXT:    addi a2, a0, 1024
+; RV64-NEXT:    srli a0, a2, 11
+; RV64-NEXT:    seqz a0, a0
+; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: uaddo.i64.constant_2048:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    mv a3, a0
+; RV32ZBA-NEXT:    addi a0, a0, 1024
+; RV32ZBA-NEXT:    addi a4, a0, 1024
+; RV32ZBA-NEXT:    sltu a0, a4, a3
+; RV32ZBA-NEXT:    add a5, a1, a0
+; RV32ZBA-NEXT:    bgeu a4, a3, .LBB13_2
+; RV32ZBA-NEXT:  # %bb.1: # %entry
+; RV32ZBA-NEXT:    sltu a0, a5, a1
+; RV32ZBA-NEXT:  .LBB13_2: # %entry
+; RV32ZBA-NEXT:    sw a4, 0(a2)
+; RV32ZBA-NEXT:    sw a5, 4(a2)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_2048:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a0, a0, 1024
+; RV64ZBA-NEXT:    addi a2, a0, 1024
+; RV64ZBA-NEXT:    srli a0, a2, 11
+; RV64ZBA-NEXT:    seqz a0, a0
+; RV64ZBA-NEXT:    sd a2, 0(a1)
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2048)
+  %val = extractvalue {i64, i1} %t, 0
+  %obit = extractvalue {i64, i1} %t, 1
+  store i64 %val, i64* %res
+  ret i1 %obit
+}
+
+define zeroext i1 @uaddo.i64.constant_2049(i64 %v1, i64* %res) {
+; RV32-LABEL: uaddo.i64.constant_2049:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    addi a0, a0, 1025
+; RV32-NEXT:    addi a4, a0, 1024
+; RV32-NEXT:    sltu a0, a4, a3
+; RV32-NEXT:    add a5, a1, a0
+; RV32-NEXT:    bgeu a4, a3, .LBB14_2
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    sltu a0, a5, a1
+; RV32-NEXT:  .LBB14_2: # %entry
+; RV32-NEXT:    sw a4, 0(a2)
+; RV32-NEXT:    sw a5, 4(a2)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: uaddo.i64.constant_2049:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    lui a2, 1
+; RV64-NEXT:    addiw a2, a2, -2047
+; RV64-NEXT:    add a3, a0, a2
+; RV64-NEXT:    sltu a0, a3, a2
+; RV64-NEXT:    sd a3, 0(a1)
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: uaddo.i64.constant_2049:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    mv a3, a0
+; RV32ZBA-NEXT:    addi a0, a0, 1025
+; RV32ZBA-NEXT:    addi a4, a0, 1024
+; RV32ZBA-NEXT:    sltu a0, a4, a3
+; RV32ZBA-NEXT:    add a5, a1, a0
+; RV32ZBA-NEXT:    bgeu a4, a3, .LBB14_2
+; RV32ZBA-NEXT:  # %bb.1: # %entry
+; RV32ZBA-NEXT:    sltu a0, a5, a1
+; RV32ZBA-NEXT:  .LBB14_2: # %entry
+; RV32ZBA-NEXT:    sw a4, 0(a2)
+; RV32ZBA-NEXT:    sw a5, 4(a2)
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_2049:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    lui a2, 1
+; RV64ZBA-NEXT:    addiw a2, a2, -2047
+; RV64ZBA-NEXT:    add a3, a0, a2
+; RV64ZBA-NEXT:    sltu a0, a3, a2
+; RV64ZBA-NEXT:    sd a3, 0(a1)
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2049)
+  %val = extractvalue {i64, i1} %t, 0
+  %obit = extractvalue {i64, i1} %t, 1
+  store i64 %val, i64* %res
+  ret i1 %obit
+}
+
+define i64 @uaddo.i64.constant_setcc_on_overflow_flag(i64 %v1) {
+; RV32-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    mv a2, a1
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    addi a0, a0, 2
+; RV32-NEXT:    sltu a4, a0, a3
+; RV32-NEXT:    add a1, a1, a4
+; RV32-NEXT:    bltu a0, a3, .LBB15_3
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    bnez a4, .LBB15_4
+; RV32-NEXT:  .LBB15_2: # %IfNoOverflow
+; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB15_3: # %entry
+; RV32-NEXT:    sltu a4, a1, a2
+; RV32-NEXT:    beqz a4, .LBB15_2
+; RV32-NEXT:  .LBB15_4: # %IfOverflow
+; RV32-NEXT:    li a0, 0
+; RV32-NEXT:    li a1, 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi a0, a0, 2
+; RV64-NEXT:    li a1, 2
+; RV64-NEXT:    bgeu a0, a1, .LBB15_2
+; RV64-NEXT:  # %bb.1: # %IfOverflow
+; RV64-NEXT:    li a0, 0
+; RV64-NEXT:  .LBB15_2: # %IfNoOverflow
+; RV64-NEXT:    ret
+;
+; RV32ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV32ZBA:       # %bb.0: # %entry
+; RV32ZBA-NEXT:    mv a2, a1
+; RV32ZBA-NEXT:    mv a3, a0
+; RV32ZBA-NEXT:    addi a0, a0, 2
+; RV32ZBA-NEXT:    sltu a4, a0, a3
+; RV32ZBA-NEXT:    add a1, a1, a4
+; RV32ZBA-NEXT:    bltu a0, a3, .LBB15_3
+; RV32ZBA-NEXT:  # %bb.1: # %entry
+; RV32ZBA-NEXT:    bnez a4, .LBB15_4
+; RV32ZBA-NEXT:  .LBB15_2: # %IfNoOverflow
+; RV32ZBA-NEXT:    ret
+; RV32ZBA-NEXT:  .LBB15_3: # %entry
+; RV32ZBA-NEXT:    sltu a4, a1, a2
+; RV32ZBA-NEXT:    beqz a4, .LBB15_2
+; RV32ZBA-NEXT:  .LBB15_4: # %IfOverflow
+; RV32ZBA-NEXT:    li a0, 0
+; RV32ZBA-NEXT:    li a1, 0
+; RV32ZBA-NEXT:    ret
+;
+; RV64ZBA-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    addi a0, a0, 2
+; RV64ZBA-NEXT:    li a1, 2
+; RV64ZBA-NEXT:    bgeu a0, a1, .LBB15_2
+; RV64ZBA-NEXT:  # %bb.1: # %IfOverflow
+; RV64ZBA-NEXT:    li a0, 0
+; RV64ZBA-NEXT:  .LBB15_2: # %IfNoOverflow
+; RV64ZBA-NEXT:    ret
+entry:
+  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 2)
+  %val = extractvalue {i64, i1} %t, 0
+  %obit = extractvalue {i64, i1} %t, 1
+  br i1 %obit, label %IfOverflow, label %IfNoOverflow
+IfOverflow:
+  ret i64 0
+IfNoOverflow:
+  ret i64 %val
+}
+
 define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
 ; RV32-LABEL: ssubo1.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sgtz a3, a1
 ; RV32-NEXT:    sub a1, a0, a1
 ; RV32-NEXT:    slt a0, a1, a0
 ; RV32-NEXT:    xor a0, a3, a0
 ; RV32-NEXT:    sw a1, 0(a2)

 
 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 ; RV32-LABEL: usubo.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a5, a0, a2
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a5
 ; RV32-NEXT:    sub a2, a0, a2
-; RV32-NEXT:    beq a3, a1, .LBB18_2
+; RV32-NEXT:    beq a3, a1, .LBB22_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
-; RV32-NEXT:    j .LBB18_3
-; RV32-NEXT:  .LBB18_2:
+; RV32-NEXT:    j .LBB22_3
+; RV32-NEXT:  .LBB22_2:
 ; RV32-NEXT:    sltu a0, a0, a2
-; RV32-NEXT:  .LBB18_3: # %entry
+; RV32-NEXT:  .LBB22_3: # %entry
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    sltu a0, a0, a1
 ; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a5, a0, a2
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a5
 ; RV32ZBA-NEXT:    sub a2, a0, a2
-; RV32ZBA-NEXT:    beq a3, a1, .LBB18_2
+; RV32ZBA-NEXT:    beq a3, a1, .LBB22_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
-; RV32ZBA-NEXT:    j .LBB18_3
-; RV32ZBA-NEXT:  .LBB18_2:
+; RV32ZBA-NEXT:    j .LBB22_3
+; RV32ZBA-NEXT:  .LBB22_2:
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
-; RV32ZBA-NEXT:  .LBB18_3: # %entry
+; RV32ZBA-NEXT:  .LBB22_3: # %entry
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a3, 4(a4)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a1, a0, a1
 ; RV64ZBA-NEXT:    sltu a0, a0, a1

 ; Check the use of the overflow bit in combination with a select instruction.
 ;
 define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: saddo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    slt a2, a2, a0
 ; RV32-NEXT:    slti a3, a1, 0
-; RV32-NEXT:    bne a3, a2, .LBB28_2
+; RV32-NEXT:    bne a3, a2, .LBB32_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB28_2: # %entry
+; RV32-NEXT:  .LBB32_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    add a4, a3, a2
 ; RV64-NEXT:    addw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB28_2
+; RV64-NEXT:    bne a2, a4, .LBB32_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB28_2: # %entry
+; RV64-NEXT:  .LBB32_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a1
 ; RV32ZBA-NEXT:    slt a2, a2, a0
 ; RV32ZBA-NEXT:    slti a3, a1, 0
-; RV32ZBA-NEXT:    bne a3, a2, .LBB28_2
+; RV32ZBA-NEXT:    bne a3, a2, .LBB32_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB28_2: # %entry
+; RV32ZBA-NEXT:  .LBB32_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a2, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    add a4, a3, a2
 ; RV64ZBA-NEXT:    addw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB28_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB32_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB28_2: # %entry
+; RV64ZBA-NEXT:  .LBB32_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 ; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a5, a0, a2
 ; RV32-NEXT:    sltu a5, a5, a0
 ; RV32-NEXT:    add a4, a4, a5
 ; RV32-NEXT:    xor a4, a1, a4
 ; RV32-NEXT:    xor a5, a1, a3
 ; RV32-NEXT:    not a5, a5
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    bltz a4, .LBB30_2
+; RV32-NEXT:    bltz a4, .LBB34_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB30_2: # %entry
+; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a2, a2, a0
 ; RV64-NEXT:    slti a3, a1, 0
-; RV64-NEXT:    bne a3, a2, .LBB30_2
+; RV64-NEXT:    bne a3, a2, .LBB34_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB30_2: # %entry
+; RV64-NEXT:  .LBB34_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a4, a1, a3
 ; RV32ZBA-NEXT:    add a5, a0, a2
 ; RV32ZBA-NEXT:    sltu a5, a5, a0
 ; RV32ZBA-NEXT:    add a4, a4, a5
 ; RV32ZBA-NEXT:    xor a4, a1, a4
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    not a5, a5
 ; RV32ZBA-NEXT:    and a4, a5, a4
-; RV32ZBA-NEXT:    bltz a4, .LBB30_2
+; RV32ZBA-NEXT:    bltz a4, .LBB34_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB30_2: # %entry
+; RV32ZBA-NEXT:  .LBB34_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    slt a2, a2, a0
 ; RV64ZBA-NEXT:    slti a3, a1, 0
-; RV64ZBA-NEXT:    bne a3, a2, .LBB30_2
+; RV64ZBA-NEXT:    bne a3, a2, .LBB34_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB30_2: # %entry
+; RV64ZBA-NEXT:  .LBB34_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: uaddo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
-; RV32-NEXT:    bltu a2, a0, .LBB32_2
+; RV32-NEXT:    bltu a2, a0, .LBB36_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB32_2: # %entry
+; RV32-NEXT:  .LBB36_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addw a2, a0, a1
 ; RV64-NEXT:    sext.w a3, a0
-; RV64-NEXT:    bltu a2, a3, .LBB32_2
+; RV64-NEXT:    bltu a2, a3, .LBB36_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB32_2: # %entry
+; RV64-NEXT:  .LBB36_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a1
-; RV32ZBA-NEXT:    bltu a2, a0, .LBB32_2
+; RV32ZBA-NEXT:    bltu a2, a0, .LBB36_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB32_2: # %entry
+; RV32ZBA-NEXT:  .LBB36_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    addw a2, a0, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
-; RV64ZBA-NEXT:    bltu a2, a3, .LBB32_2
+; RV64ZBA-NEXT:    bltu a2, a3, .LBB36_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB32_2: # %entry
+; RV64ZBA-NEXT:  .LBB36_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 
 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a5, a1, a3
 ; RV32-NEXT:    add a4, a0, a2
 ; RV32-NEXT:    sltu a4, a4, a0
 ; RV32-NEXT:    add a5, a5, a4
-; RV32-NEXT:    bne a5, a1, .LBB34_3
+; RV32-NEXT:    bne a5, a1, .LBB38_3
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    beqz a4, .LBB34_4
-; RV32-NEXT:  .LBB34_2: # %entry
+; RV32-NEXT:    beqz a4, .LBB38_4
+; RV32-NEXT:  .LBB38_2: # %entry
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB34_3: # %entry
+; RV32-NEXT:  .LBB38_3: # %entry
 ; RV32-NEXT:    sltu a4, a5, a1
-; RV32-NEXT:    bnez a4, .LBB34_2
-; RV32-NEXT:  .LBB34_4: # %entry
+; RV32-NEXT:    bnez a4, .LBB38_2
+; RV32-NEXT:  .LBB38_4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
-; RV64-NEXT:    bltu a2, a0, .LBB34_2
+; RV64-NEXT:    bltu a2, a0, .LBB38_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB34_2: # %entry
+; RV64-NEXT:  .LBB38_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a5, a1, a3
 ; RV32ZBA-NEXT:    add a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a4, a0
 ; RV32ZBA-NEXT:    add a5, a5, a4
-; RV32ZBA-NEXT:    bne a5, a1, .LBB34_3
+; RV32ZBA-NEXT:    bne a5, a1, .LBB38_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
-; RV32ZBA-NEXT:    beqz a4, .LBB34_4
-; RV32ZBA-NEXT:  .LBB34_2: # %entry
+; RV32ZBA-NEXT:    beqz a4, .LBB38_4
+; RV32ZBA-NEXT:  .LBB38_2: # %entry
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB34_3: # %entry
+; RV32ZBA-NEXT:  .LBB38_3: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a5, a1
-; RV32ZBA-NEXT:    bnez a4, .LBB34_2
-; RV32ZBA-NEXT:  .LBB34_4: # %entry
+; RV32ZBA-NEXT:    bnez a4, .LBB38_2
+; RV32ZBA-NEXT:  .LBB38_4: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a2, a0, a1
-; RV64ZBA-NEXT:    bltu a2, a0, .LBB34_2
+; RV64ZBA-NEXT:    bltu a2, a0, .LBB38_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB34_2: # %entry
+; RV64ZBA-NEXT:  .LBB38_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
-; RV32-NEXT:    beq a2, a1, .LBB35_2
+; RV32-NEXT:    beq a2, a1, .LBB39_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB35_2: # %entry
+; RV32-NEXT:  .LBB39_2: # %entry
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a1
 ; RV64-NEXT:    sltu a0, a1, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB35_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB39_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB35_2: # %entry
+; RV32ZBA-NEXT:  .LBB39_2: # %entry
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a1, a0, a1
 ; RV64ZBA-NEXT:    sltu a0, a1, a0
 ; RV64ZBA-NEXT:    xori a0, a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sgtz a2, a1
 ; RV32-NEXT:    sub a3, a0, a1
 ; RV32-NEXT:    slt a3, a3, a0
-; RV32-NEXT:    bne a2, a3, .LBB36_2
+; RV32-NEXT:    bne a2, a3, .LBB40_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB36_2: # %entry
+; RV32-NEXT:  .LBB40_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    sub a4, a3, a2
 ; RV64-NEXT:    subw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB36_2
+; RV64-NEXT:    bne a2, a4, .LBB40_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB36_2: # %entry
+; RV64-NEXT:  .LBB40_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sgtz a2, a1
 ; RV32ZBA-NEXT:    sub a3, a0, a1
 ; RV32ZBA-NEXT:    slt a3, a3, a0
-; RV32ZBA-NEXT:    bne a2, a3, .LBB36_2
+; RV32ZBA-NEXT:    bne a2, a3, .LBB40_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB36_2: # %entry
+; RV32ZBA-NEXT:  .LBB40_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a2, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    sub a4, a3, a2
 ; RV64ZBA-NEXT:    subw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB36_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB40_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB36_2: # %entry
+; RV64ZBA-NEXT:  .LBB40_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 ; RV32-LABEL: ssubo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a5, a1, a3
 ; RV32-NEXT:    sub a4, a5, a4
 ; RV32-NEXT:    xor a4, a1, a4
 ; RV32-NEXT:    xor a5, a1, a3
 ; RV32-NEXT:    and a4, a5, a4
-; RV32-NEXT:    bltz a4, .LBB38_2
+; RV32-NEXT:    bltz a4, .LBB42_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB38_2: # %entry
+; RV32-NEXT:  .LBB42_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    slt a3, a3, a0
-; RV64-NEXT:    bne a2, a3, .LBB38_2
+; RV64-NEXT:    bne a2, a3, .LBB42_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB38_2: # %entry
+; RV64-NEXT:  .LBB42_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a5, a1, a3
 ; RV32ZBA-NEXT:    sub a4, a5, a4
 ; RV32ZBA-NEXT:    xor a4, a1, a4
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    and a4, a5, a4
-; RV32ZBA-NEXT:    bltz a4, .LBB38_2
+; RV32ZBA-NEXT:    bltz a4, .LBB42_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB38_2: # %entry
+; RV32ZBA-NEXT:  .LBB42_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sgtz a2, a1
 ; RV64ZBA-NEXT:    sub a3, a0, a1
 ; RV64ZBA-NEXT:    slt a3, a3, a0
-; RV64ZBA-NEXT:    bne a2, a3, .LBB38_2
+; RV64ZBA-NEXT:    bne a2, a3, .LBB42_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB38_2: # %entry
+; RV64ZBA-NEXT:  .LBB42_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: usubo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sub a2, a0, a1
-; RV32-NEXT:    bltu a0, a2, .LBB40_2
+; RV32-NEXT:    bltu a0, a2, .LBB44_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB40_2: # %entry
+; RV32-NEXT:  .LBB44_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    subw a2, a0, a1
 ; RV64-NEXT:    sext.w a3, a0
-; RV64-NEXT:    bltu a3, a2, .LBB40_2
+; RV64-NEXT:    bltu a3, a2, .LBB44_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB40_2: # %entry
+; RV64-NEXT:  .LBB44_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sub a2, a0, a1
-; RV32ZBA-NEXT:    bltu a0, a2, .LBB40_2
+; RV32ZBA-NEXT:    bltu a0, a2, .LBB44_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB40_2: # %entry
+; RV32ZBA-NEXT:  .LBB44_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    subw a2, a0, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
-; RV64ZBA-NEXT:    bltu a3, a2, .LBB40_2
+; RV64ZBA-NEXT:    bltu a3, a2, .LBB44_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB40_2: # %entry
+; RV64ZBA-NEXT:  .LBB44_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 }
 
 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a5, a1, a3
 ; RV32-NEXT:    sub a4, a5, a4
-; RV32-NEXT:    beq a4, a1, .LBB42_2
+; RV32-NEXT:    beq a4, a1, .LBB46_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a4, a1, a4
-; RV32-NEXT:    beqz a4, .LBB42_3
-; RV32-NEXT:    j .LBB42_4
-; RV32-NEXT:  .LBB42_2:
+; RV32-NEXT:    beqz a4, .LBB46_3
+; RV32-NEXT:    j .LBB46_4
+; RV32-NEXT:  .LBB46_2:
 ; RV32-NEXT:    sub a4, a0, a2
 ; RV32-NEXT:    sltu a4, a0, a4
-; RV32-NEXT:    bnez a4, .LBB42_4
-; RV32-NEXT:  .LBB42_3: # %entry
+; RV32-NEXT:    bnez a4, .LBB46_4
+; RV32-NEXT:  .LBB46_3: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB42_4: # %entry
+; RV32-NEXT:  .LBB46_4: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a2, a0, a1
-; RV64-NEXT:    bltu a0, a2, .LBB42_2
+; RV64-NEXT:    bltu a0, a2, .LBB46_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB42_2: # %entry
+; RV64-NEXT:  .LBB46_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a5, a1, a3
 ; RV32ZBA-NEXT:    sub a4, a5, a4
-; RV32ZBA-NEXT:    beq a4, a1, .LBB42_2
+; RV32ZBA-NEXT:    beq a4, a1, .LBB46_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a1, a4
-; RV32ZBA-NEXT:    beqz a4, .LBB42_3
-; RV32ZBA-NEXT:    j .LBB42_4
-; RV32ZBA-NEXT:  .LBB42_2:
+; RV32ZBA-NEXT:    beqz a4, .LBB46_3
+; RV32ZBA-NEXT:    j .LBB46_4
+; RV32ZBA-NEXT:  .LBB46_2:
 ; RV32ZBA-NEXT:    sub a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a0, a4
-; RV32ZBA-NEXT:    bnez a4, .LBB42_4
-; RV32ZBA-NEXT:  .LBB42_3: # %entry
+; RV32ZBA-NEXT:    bnez a4, .LBB46_4
+; RV32ZBA-NEXT:  .LBB46_3: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB42_4: # %entry
+; RV32ZBA-NEXT:  .LBB46_4: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a2, a0, a1
-; RV64ZBA-NEXT:    bltu a0, a2, .LBB42_2
+; RV64ZBA-NEXT:    bltu a0, a2, .LBB46_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB42_2: # %entry
+; RV64ZBA-NEXT:  .LBB46_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a4
-; RV32-NEXT:    beq a3, a1, .LBB43_2
+; RV32-NEXT:    beq a3, a1, .LBB47_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB43_2:
+; RV32-NEXT:  .LBB47_2:
 ; RV32-NEXT:    sub a1, a0, a2
 ; RV32-NEXT:    sltu a0, a0, a1
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    sltu a0, a0, a1
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a4
-; RV32ZBA-NEXT:    beq a3, a1, .LBB43_2
+; RV32ZBA-NEXT:    beq a3, a1, .LBB47_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB43_2:
+; RV32ZBA-NEXT:  .LBB47_2:
 ; RV32ZBA-NEXT:    sub a1, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a0, a1
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a1, a0, a1
 ; RV64ZBA-NEXT:    sltu a0, a0, a1
 ; RV64ZBA-NEXT:    xori a0, a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: smulo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulh a2, a0, a1
 ; RV32-NEXT:    mul a3, a0, a1
 ; RV32-NEXT:    srai a3, a3, 31
-; RV32-NEXT:    bne a2, a3, .LBB44_2
+; RV32-NEXT:    bne a2, a3, .LBB48_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB44_2: # %entry
+; RV32-NEXT:  .LBB48_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1
 ; RV64-NEXT:    sext.w a3, a0
 ; RV64-NEXT:    mul a4, a3, a2
 ; RV64-NEXT:    mulw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB44_2
+; RV64-NEXT:    bne a2, a4, .LBB48_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB44_2: # %entry
+; RV64-NEXT:  .LBB48_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a3, a0, a1
 ; RV32ZBA-NEXT:    srai a3, a3, 31
-; RV32ZBA-NEXT:    bne a2, a3, .LBB44_2
+; RV32ZBA-NEXT:    bne a2, a3, .LBB48_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB44_2: # %entry
+; RV32ZBA-NEXT:  .LBB48_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a2, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
 ; RV64ZBA-NEXT:    mul a4, a3, a2
 ; RV64ZBA-NEXT:    mulw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB44_2
+; RV64ZBA-NEXT:    bne a2, a4, .LBB48_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB44_2: # %entry
+; RV64ZBA-NEXT:  .LBB48_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 ; RV32-NEXT:    sltu a7, t5, t4
 ; RV32-NEXT:    add a6, a6, a7
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    add a5, a5, s0
 ; RV32-NEXT:    srai a4, a4, 31
 ; RV32-NEXT:    xor a5, a5, a4
 ; RV32-NEXT:    xor a4, t6, a4
 ; RV32-NEXT:    or a4, a4, a5
-; RV32-NEXT:    bnez a4, .LBB46_2
+; RV32-NEXT:    bnez a4, .LBB50_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB46_2: # %entry
+; RV32-NEXT:  .LBB50_2: # %entry
 ; RV32-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a3, a0, a1
 ; RV64-NEXT:    srai a3, a3, 63
-; RV64-NEXT:    bne a2, a3, .LBB46_2
+; RV64-NEXT:    bne a2, a3, .LBB50_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB46_2: # %entry
+; RV64-NEXT:  .LBB50_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi sp, sp, -16
 ; RV32ZBA-NEXT:    .cfi_def_cfa_offset 16
 ; RV32ZBA-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
 ; RV32ZBA-NEXT:    .cfi_offset s0, -4

 ; RV32ZBA-NEXT:    sltu a7, t5, t4
 ; RV32ZBA-NEXT:    add a6, a6, a7
 ; RV32ZBA-NEXT:    add a5, a5, a6
 ; RV32ZBA-NEXT:    add a5, a5, s0
 ; RV32ZBA-NEXT:    srai a4, a4, 31
 ; RV32ZBA-NEXT:    xor a5, a5, a4
 ; RV32ZBA-NEXT:    xor a4, t6, a4
 ; RV32ZBA-NEXT:    or a4, a4, a5
-; RV32ZBA-NEXT:    bnez a4, .LBB46_2
+; RV32ZBA-NEXT:    bnez a4, .LBB50_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB46_2: # %entry
+; RV32ZBA-NEXT:  .LBB50_2: # %entry
 ; RV32ZBA-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBA-NEXT:    addi sp, sp, 16
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a3, a0, a1
 ; RV64ZBA-NEXT:    srai a3, a3, 63
-; RV64ZBA-NEXT:    bne a2, a3, .LBB46_2
+; RV64ZBA-NEXT:    bne a2, a3, .LBB50_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB46_2: # %entry
+; RV64ZBA-NEXT:  .LBB50_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: umulo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulhu a2, a0, a1
-; RV32-NEXT:    bnez a2, .LBB48_2
+; RV32-NEXT:    bnez a2, .LBB52_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:  .LBB48_2: # %entry
+; RV32-NEXT:  .LBB52_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    slli a2, a1, 32
 ; RV64-NEXT:    slli a3, a0, 32
 ; RV64-NEXT:    mulhu a2, a3, a2
 ; RV64-NEXT:    srli a2, a2, 32
-; RV64-NEXT:    bnez a2, .LBB48_2
+; RV64-NEXT:    bnez a2, .LBB52_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB48_2: # %entry
+; RV64-NEXT:  .LBB52_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulhu a2, a0, a1
-; RV32ZBA-NEXT:    bnez a2, .LBB48_2
+; RV32ZBA-NEXT:    bnez a2, .LBB52_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
-; RV32ZBA-NEXT:  .LBB48_2: # %entry
+; RV32ZBA-NEXT:  .LBB52_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    zext.w a2, a1
 ; RV64ZBA-NEXT:    zext.w a3, a0
 ; RV64ZBA-NEXT:    mul a2, a3, a2
 ; RV64ZBA-NEXT:    srli a2, a2, 32
-; RV64ZBA-NEXT:    bnez a2, .LBB48_2
+; RV64ZBA-NEXT:    bnez a2, .LBB52_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB48_2: # %entry
+; RV64ZBA-NEXT:  .LBB52_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 

 ; RV32-NEXT:    and a5, a6, a5
 ; RV32-NEXT:    mulhu a6, a1, a2
 ; RV32-NEXT:    snez a6, a6
 ; RV32-NEXT:    or a5, a5, a6
 ; RV32-NEXT:    mulhu a6, a3, a0
 ; RV32-NEXT:    snez a6, a6
 ; RV32-NEXT:    or a5, a5, a6
 ; RV32-NEXT:    or a4, a5, a4
-; RV32-NEXT:    bnez a4, .LBB50_2
+; RV32-NEXT:    bnez a4, .LBB54_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
-; RV32-NEXT:  .LBB50_2: # %entry
+; RV32-NEXT:  .LBB54_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a2, a0, a1
-; RV64-NEXT:    bnez a2, .LBB50_2
+; RV64-NEXT:    bnez a2, .LBB54_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:  .LBB50_2: # %entry
+; RV64-NEXT:  .LBB54_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a4, a3, a0
 ; RV32ZBA-NEXT:    mul a5, a1, a2
 ; RV32ZBA-NEXT:    add a4, a5, a4
 ; RV32ZBA-NEXT:    mulhu a5, a0, a2
 ; RV32ZBA-NEXT:    add a4, a5, a4
 ; RV32ZBA-NEXT:    sltu a4, a4, a5
 ; RV32ZBA-NEXT:    snez a5, a3
 ; RV32ZBA-NEXT:    snez a6, a1
 ; RV32ZBA-NEXT:    and a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a6, a1, a2
 ; RV32ZBA-NEXT:    snez a6, a6
 ; RV32ZBA-NEXT:    or a5, a5, a6
 ; RV32ZBA-NEXT:    mulhu a6, a3, a0
 ; RV32ZBA-NEXT:    snez a6, a6
 ; RV32ZBA-NEXT:    or a5, a5, a6
 ; RV32ZBA-NEXT:    or a4, a5, a4
-; RV32ZBA-NEXT:    bnez a4, .LBB50_2
+; RV32ZBA-NEXT:    bnez a4, .LBB54_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
-; RV32ZBA-NEXT:  .LBB50_2: # %entry
+; RV32ZBA-NEXT:  .LBB54_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.select.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulhu a2, a0, a1
-; RV64ZBA-NEXT:    bnez a2, .LBB50_2
+; RV64ZBA-NEXT:    bnez a2, .LBB54_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
-; RV64ZBA-NEXT:  .LBB50_2: # %entry
+; RV64ZBA-NEXT:  .LBB54_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 

 ; Check the use of the overflow bit in combination with a branch instruction.
 ;
 define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: saddo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    slt a0, a2, a0
 ; RV32-NEXT:    slti a1, a1, 0
-; RV32-NEXT:    beq a1, a0, .LBB52_2
+; RV32-NEXT:    beq a1, a0, .LBB56_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB52_2: # %continue
+; RV32-NEXT:  .LBB56_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    addw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB52_2
+; RV64-NEXT:    beq a0, a2, .LBB56_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB52_2: # %continue
+; RV64-NEXT:  .LBB56_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a1
 ; RV32ZBA-NEXT:    slt a0, a2, a0
 ; RV32ZBA-NEXT:    slti a1, a1, 0
-; RV32ZBA-NEXT:    beq a1, a0, .LBB52_2
+; RV32ZBA-NEXT:    beq a1, a0, .LBB56_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB52_2: # %continue
+; RV32ZBA-NEXT:  .LBB56_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    addw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB52_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB56_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB52_2: # %continue
+; RV64ZBA-NEXT:  .LBB56_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 

 ; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a0, a4, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    bgez a0, .LBB53_2
+; RV32-NEXT:    bgez a0, .LBB57_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB53_2: # %continue
+; RV32-NEXT:  .LBB57_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a0, a2, a0
 ; RV64-NEXT:    slti a1, a1, 0
-; RV64-NEXT:    beq a1, a0, .LBB53_2
+; RV64-NEXT:    beq a1, a0, .LBB57_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB53_2: # %continue
+; RV64-NEXT:  .LBB57_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a4, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a0, a4, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    bgez a0, .LBB53_2
+; RV32ZBA-NEXT:    bgez a0, .LBB57_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB53_2: # %continue
+; RV32ZBA-NEXT:  .LBB57_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: saddo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a2, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a2, a0
 ; RV64ZBA-NEXT:    slti a1, a1, 0
-; RV64ZBA-NEXT:    beq a1, a0, .LBB53_2
+; RV64ZBA-NEXT:    beq a1, a0, .LBB57_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB53_2: # %continue
+; RV64ZBA-NEXT:  .LBB57_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: uaddo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a1, a0, a1
-; RV32-NEXT:    bgeu a1, a0, .LBB54_2
+; RV32-NEXT:    bgeu a1, a0, .LBB58_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB54_2: # %continue
+; RV32-NEXT:  .LBB58_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addw a1, a0, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    bgeu a1, a0, .LBB54_2
+; RV64-NEXT:    bgeu a1, a0, .LBB58_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB54_2: # %continue
+; RV64-NEXT:  .LBB58_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a1, a0, a1
-; RV32ZBA-NEXT:    bgeu a1, a0, .LBB54_2
+; RV32ZBA-NEXT:    bgeu a1, a0, .LBB58_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB54_2: # %continue
+; RV32ZBA-NEXT:  .LBB58_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    addw a1, a0, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB54_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB58_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB54_2: # %continue
+; RV64ZBA-NEXT:  .LBB58_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
-; RV32-NEXT:    beq a2, a1, .LBB55_2
+; RV32-NEXT:    beq a2, a1, .LBB59_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB55_2: # %entry
-; RV32-NEXT:    beqz a0, .LBB55_4
+; RV32-NEXT:  .LBB59_2: # %entry
+; RV32-NEXT:    beqz a0, .LBB59_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB55_4: # %continue
+; RV32-NEXT:  .LBB59_4: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a1
-; RV64-NEXT:    bgeu a1, a0, .LBB55_2
+; RV64-NEXT:    bgeu a1, a0, .LBB59_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB55_2: # %continue
+; RV64-NEXT:  .LBB59_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB55_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB59_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB55_2: # %entry
-; RV32ZBA-NEXT:    beqz a0, .LBB55_4
+; RV32ZBA-NEXT:  .LBB59_2: # %entry
+; RV32ZBA-NEXT:    beqz a0, .LBB59_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB55_4: # %continue
+; RV32ZBA-NEXT:  .LBB59_4: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a1, a0, a1
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB55_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB59_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB55_2: # %continue
+; RV64ZBA-NEXT:  .LBB59_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: ssubo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sgtz a2, a1
 ; RV32-NEXT:    sub a1, a0, a1
 ; RV32-NEXT:    slt a0, a1, a0
-; RV32-NEXT:    beq a2, a0, .LBB56_2
+; RV32-NEXT:    beq a2, a0, .LBB60_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB56_2: # %continue
+; RV32-NEXT:  .LBB60_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sub a2, a0, a1
 ; RV64-NEXT:    subw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB56_2
+; RV64-NEXT:    beq a0, a2, .LBB60_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB56_2: # %continue
+; RV64-NEXT:  .LBB60_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sgtz a2, a1
 ; RV32ZBA-NEXT:    sub a1, a0, a1
 ; RV32ZBA-NEXT:    slt a0, a1, a0
-; RV32ZBA-NEXT:    beq a2, a0, .LBB56_2
+; RV32ZBA-NEXT:    beq a2, a0, .LBB60_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB56_2: # %continue
+; RV32ZBA-NEXT:  .LBB60_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    sub a2, a0, a1
 ; RV64ZBA-NEXT:    subw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB56_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB60_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB56_2: # %continue
+; RV64ZBA-NEXT:  .LBB60_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: ssubo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a2, a1, a3
 ; RV32-NEXT:    sub a0, a2, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    bgez a0, .LBB57_2
+; RV32-NEXT:    bgez a0, .LBB61_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB57_2: # %continue
+; RV32-NEXT:  .LBB61_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
-; RV64-NEXT:    beq a2, a0, .LBB57_2
+; RV64-NEXT:    beq a2, a0, .LBB61_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB57_2: # %continue
+; RV64-NEXT:  .LBB61_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
 ; RV32ZBA-NEXT:    sub a2, a1, a3
 ; RV32ZBA-NEXT:    sub a0, a2, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a0, a1, a0
-; RV32ZBA-NEXT:    bgez a0, .LBB57_2
+; RV32ZBA-NEXT:    bgez a0, .LBB61_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB57_2: # %continue
+; RV32ZBA-NEXT:  .LBB61_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sgtz a2, a1
 ; RV64ZBA-NEXT:    sub a1, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a1, a0
-; RV64ZBA-NEXT:    beq a2, a0, .LBB57_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB61_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB57_2: # %continue
+; RV64ZBA-NEXT:  .LBB61_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: usubo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sub a1, a0, a1
-; RV32-NEXT:    bgeu a0, a1, .LBB58_2
+; RV32-NEXT:    bgeu a0, a1, .LBB62_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB58_2: # %continue
+; RV32-NEXT:  .LBB62_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    subw a1, a0, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    bgeu a0, a1, .LBB58_2
+; RV64-NEXT:    bgeu a0, a1, .LBB62_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB58_2: # %continue
+; RV64-NEXT:  .LBB62_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sub a1, a0, a1
-; RV32ZBA-NEXT:    bgeu a0, a1, .LBB58_2
+; RV32ZBA-NEXT:    bgeu a0, a1, .LBB62_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB58_2: # %continue
+; RV32ZBA-NEXT:  .LBB62_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    subw a1, a0, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    bgeu a0, a1, .LBB58_2
+; RV64ZBA-NEXT:    bgeu a0, a1, .LBB62_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB58_2: # %continue
+; RV64ZBA-NEXT:  .LBB62_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
 ; RV32-NEXT:    sub a3, a1, a3
 ; RV32-NEXT:    sub a3, a3, a4
-; RV32-NEXT:    beq a3, a1, .LBB59_3
+; RV32-NEXT:    beq a3, a1, .LBB63_3
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
-; RV32-NEXT:    bnez a0, .LBB59_4
-; RV32-NEXT:  .LBB59_2: # %continue
+; RV32-NEXT:    bnez a0, .LBB63_4
+; RV32-NEXT:  .LBB63_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB59_3:
+; RV32-NEXT:  .LBB63_3:
 ; RV32-NEXT:    sub a1, a0, a2
 ; RV32-NEXT:    sltu a0, a0, a1
-; RV32-NEXT:    beqz a0, .LBB59_2
-; RV32-NEXT:  .LBB59_4: # %overflow
+; RV32-NEXT:    beqz a0, .LBB63_2
+; RV32-NEXT:  .LBB63_4: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
-; RV64-NEXT:    bgeu a0, a1, .LBB59_2
+; RV64-NEXT:    bgeu a0, a1, .LBB63_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB59_2: # %continue
+; RV64-NEXT:  .LBB63_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
 ; RV32ZBA-NEXT:    sub a3, a1, a3
 ; RV32ZBA-NEXT:    sub a3, a3, a4
-; RV32ZBA-NEXT:    beq a3, a1, .LBB59_3
+; RV32ZBA-NEXT:    beq a3, a1, .LBB63_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
-; RV32ZBA-NEXT:    bnez a0, .LBB59_4
-; RV32ZBA-NEXT:  .LBB59_2: # %continue
+; RV32ZBA-NEXT:    bnez a0, .LBB63_4
+; RV32ZBA-NEXT:  .LBB63_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB59_3:
+; RV32ZBA-NEXT:  .LBB63_3:
 ; RV32ZBA-NEXT:    sub a1, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a0, a1
-; RV32ZBA-NEXT:    beqz a0, .LBB59_2
-; RV32ZBA-NEXT:  .LBB59_4: # %overflow
+; RV32ZBA-NEXT:    beqz a0, .LBB63_2
+; RV32ZBA-NEXT:  .LBB63_4: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sub a1, a0, a1
-; RV64ZBA-NEXT:    bgeu a0, a1, .LBB59_2
+; RV64ZBA-NEXT:    bgeu a0, a1, .LBB63_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB59_2: # %continue
+; RV64ZBA-NEXT:  .LBB63_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: smulo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulh a2, a0, a1
 ; RV32-NEXT:    mul a0, a0, a1
 ; RV32-NEXT:    srai a0, a0, 31
-; RV32-NEXT:    beq a2, a0, .LBB60_2
+; RV32-NEXT:    beq a2, a0, .LBB64_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB60_2: # %continue
+; RV32-NEXT:  .LBB64_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    mul a2, a0, a1
 ; RV64-NEXT:    mulw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB60_2
+; RV64-NEXT:    beq a0, a2, .LBB64_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB60_2: # %continue
+; RV64-NEXT:  .LBB64_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    srai a0, a0, 31
-; RV32ZBA-NEXT:    beq a2, a0, .LBB60_2
+; RV32ZBA-NEXT:    beq a2, a0, .LBB64_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB60_2: # %continue
+; RV32ZBA-NEXT:  .LBB64_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    mul a2, a0, a1
 ; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB60_2
+; RV64ZBA-NEXT:    beq a0, a2, .LBB64_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB60_2: # %continue
+; RV64ZBA-NEXT:  .LBB64_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 

 ; RV32-NEXT:    sltu a1, t5, t4
 ; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    add a0, a5, a0
 ; RV32-NEXT:    add a0, a0, s0
 ; RV32-NEXT:    srai a1, a4, 31
 ; RV32-NEXT:    xor a0, a0, a1
 ; RV32-NEXT:    xor a1, t6, a1
 ; RV32-NEXT:    or a0, a1, a0
-; RV32-NEXT:    beqz a0, .LBB61_2
+; RV32-NEXT:    beqz a0, .LBB65_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    j .LBB61_3
-; RV32-NEXT:  .LBB61_2: # %continue
+; RV32-NEXT:    j .LBB65_3
+; RV32-NEXT:  .LBB65_2: # %continue
 ; RV32-NEXT:    li a0, 1
-; RV32-NEXT:  .LBB61_3: # %overflow
+; RV32-NEXT:  .LBB65_3: # %overflow
 ; RV32-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srai a0, a0, 63
-; RV64-NEXT:    beq a2, a0, .LBB61_2
+; RV64-NEXT:    beq a2, a0, .LBB65_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB61_2: # %continue
+; RV64-NEXT:  .LBB65_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi sp, sp, -16
 ; RV32ZBA-NEXT:    .cfi_def_cfa_offset 16
 ; RV32ZBA-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill

 ; RV32ZBA-NEXT:    sltu a1, t5, t4
 ; RV32ZBA-NEXT:    add a0, a0, a1
 ; RV32ZBA-NEXT:    add a0, a5, a0
 ; RV32ZBA-NEXT:    add a0, a0, s0
 ; RV32ZBA-NEXT:    srai a1, a4, 31
 ; RV32ZBA-NEXT:    xor a0, a0, a1
 ; RV32ZBA-NEXT:    xor a1, t6, a1
 ; RV32ZBA-NEXT:    or a0, a1, a0
-; RV32ZBA-NEXT:    beqz a0, .LBB61_2
+; RV32ZBA-NEXT:    beqz a0, .LBB65_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
-; RV32ZBA-NEXT:    j .LBB61_3
-; RV32ZBA-NEXT:  .LBB61_2: # %continue
+; RV32ZBA-NEXT:    j .LBB65_3
+; RV32ZBA-NEXT:  .LBB65_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
-; RV32ZBA-NEXT:  .LBB61_3: # %overflow
+; RV32ZBA-NEXT:  .LBB65_3: # %overflow
 ; RV32ZBA-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBA-NEXT:    addi sp, sp, 16
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srai a0, a0, 63
-; RV64ZBA-NEXT:    beq a2, a0, .LBB61_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB65_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB61_2: # %continue
+; RV64ZBA-NEXT:  .LBB65_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 

 ; RV32-NEXT:    add a0, a0, a2
 ; RV32-NEXT:    add a0, a0, a5
 ; RV32-NEXT:    add a0, a4, a0
 ; RV32-NEXT:    add a0, a0, t5
 ; RV32-NEXT:    srai a1, a3, 31
 ; RV32-NEXT:    xor a0, a0, a1
 ; RV32-NEXT:    xor a1, t4, a1
 ; RV32-NEXT:    or a0, a1, a0
-; RV32-NEXT:    beqz a0, .LBB62_2
+; RV32-NEXT:    beqz a0, .LBB66_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB62_2: # %continue
+; RV32-NEXT:  .LBB66_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo2.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    li a1, -13
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srai a0, a0, 63
-; RV64-NEXT:    beq a2, a0, .LBB62_2
+; RV64-NEXT:    beq a2, a0, .LBB66_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB62_2: # %continue
+; RV64-NEXT:  .LBB66_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo2.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    li a2, -13
 ; RV32ZBA-NEXT:    mulhu a3, a0, a2
 ; RV32ZBA-NEXT:    mul a4, a1, a2

 ; RV32ZBA-NEXT:    add a0, a0, a2
 ; RV32ZBA-NEXT:    add a0, a0, a5
 ; RV32ZBA-NEXT:    add a0, a4, a0
 ; RV32ZBA-NEXT:    add a0, a0, t5
 ; RV32ZBA-NEXT:    srai a1, a3, 31
 ; RV32ZBA-NEXT:    xor a0, a0, a1
 ; RV32ZBA-NEXT:    xor a1, t4, a1
 ; RV32ZBA-NEXT:    or a0, a1, a0
-; RV32ZBA-NEXT:    beqz a0, .LBB62_2
+; RV32ZBA-NEXT:    beqz a0, .LBB66_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB62_2: # %continue
+; RV32ZBA-NEXT:  .LBB66_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo2.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    li a1, -13
 ; RV64ZBA-NEXT:    mulh a2, a0, a1
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srai a0, a0, 63
-; RV64ZBA-NEXT:    beq a2, a0, .LBB62_2
+; RV64ZBA-NEXT:    beq a2, a0, .LBB66_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB62_2: # %continue
+; RV64ZBA-NEXT:  .LBB66_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 -13)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: umulo.br.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulhu a0, a0, a1
-; RV32-NEXT:    beqz a0, .LBB63_2
+; RV32-NEXT:    beqz a0, .LBB67_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB63_2: # %continue
+; RV32-NEXT:  .LBB67_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    slli a1, a1, 32
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    mulhu a0, a0, a1
 ; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    beqz a0, .LBB63_2
+; RV64-NEXT:    beqz a0, .LBB67_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB63_2: # %continue
+; RV64-NEXT:  .LBB67_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulhu a0, a0, a1
-; RV32ZBA-NEXT:    beqz a0, .LBB63_2
+; RV32ZBA-NEXT:    beqz a0, .LBB67_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB63_2: # %continue
+; RV32ZBA-NEXT:  .LBB67_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    zext.w a1, a1
 ; RV64ZBA-NEXT:    zext.w a0, a0
 ; RV64ZBA-NEXT:    mul a0, a0, a1
 ; RV64ZBA-NEXT:    srli a0, a0, 32
-; RV64ZBA-NEXT:    beqz a0, .LBB63_2
+; RV64ZBA-NEXT:    beqz a0, .LBB67_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB63_2: # %continue
+; RV64ZBA-NEXT:  .LBB67_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 

 ; RV32-NEXT:    and a5, a6, a5
 ; RV32-NEXT:    mulhu a1, a1, a2
 ; RV32-NEXT:    snez a1, a1
 ; RV32-NEXT:    or a1, a5, a1
 ; RV32-NEXT:    mulhu a0, a3, a0
 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    or a0, a0, a4
-; RV32-NEXT:    beqz a0, .LBB64_2
+; RV32-NEXT:    beqz a0, .LBB68_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB64_2: # %continue
+; RV32-NEXT:  .LBB68_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a0, a0, a1
-; RV64-NEXT:    beqz a0, .LBB64_2
+; RV64-NEXT:    beqz a0, .LBB68_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB64_2: # %continue
+; RV64-NEXT:  .LBB68_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a4, a3, a0
 ; RV32ZBA-NEXT:    mul a5, a1, a2
 ; RV32ZBA-NEXT:    add a4, a5, a4
 ; RV32ZBA-NEXT:    mulhu a5, a0, a2
 ; RV32ZBA-NEXT:    add a4, a5, a4
 ; RV32ZBA-NEXT:    sltu a4, a4, a5
 ; RV32ZBA-NEXT:    snez a5, a3
 ; RV32ZBA-NEXT:    snez a6, a1
 ; RV32ZBA-NEXT:    and a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a1, a1, a2
 ; RV32ZBA-NEXT:    snez a1, a1
 ; RV32ZBA-NEXT:    or a1, a5, a1
 ; RV32ZBA-NEXT:    mulhu a0, a3, a0
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    or a0, a0, a4
-; RV32ZBA-NEXT:    beqz a0, .LBB64_2
+; RV32ZBA-NEXT:    beqz a0, .LBB68_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB64_2: # %continue
+; RV32ZBA-NEXT:  .LBB68_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulhu a0, a0, a1
-; RV64ZBA-NEXT:    beqz a0, .LBB64_2
+; RV64ZBA-NEXT:    beqz a0, .LBB68_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB64_2: # %continue
+; RV64ZBA-NEXT:  .LBB68_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 
 overflow:
   ret i1 false
 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @umulo2.br.i64(i64 %v1) {
 ; RV32-LABEL: umulo2.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a0
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a1, a1
 ; RV32-NEXT:    add a2, a2, a0
-; RV32-NEXT:    beq a2, a1, .LBB65_2
+; RV32-NEXT:    beq a2, a1, .LBB69_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
-; RV32-NEXT:  .LBB65_2: # %entry
-; RV32-NEXT:    beqz a0, .LBB65_4
+; RV32-NEXT:  .LBB69_2: # %entry
+; RV32-NEXT:    beqz a0, .LBB69_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB65_4: # %continue
+; RV32-NEXT:  .LBB69_4: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo2.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a0
-; RV64-NEXT:    bgeu a1, a0, .LBB65_2
+; RV64-NEXT:    bgeu a1, a0, .LBB69_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB65_2: # %continue
+; RV64-NEXT:  .LBB69_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo2.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a0
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a1, a1
 ; RV32ZBA-NEXT:    add a2, a2, a0
-; RV32ZBA-NEXT:    beq a2, a1, .LBB65_2
+; RV32ZBA-NEXT:    beq a2, a1, .LBB69_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
-; RV32ZBA-NEXT:  .LBB65_2: # %entry
-; RV32ZBA-NEXT:    beqz a0, .LBB65_4
+; RV32ZBA-NEXT:  .LBB69_2: # %entry
+; RV32ZBA-NEXT:    beqz a0, .LBB69_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
-; RV32ZBA-NEXT:  .LBB65_4: # %continue
+; RV32ZBA-NEXT:  .LBB69_4: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo2.br.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    add a1, a0, a0
-; RV64ZBA-NEXT:    bgeu a1, a0, .LBB65_2
+; RV64ZBA-NEXT:    bgeu a1, a0, .LBB69_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    li a0, 0
 ; RV64ZBA-NEXT:    ret
-; RV64ZBA-NEXT:  .LBB65_2: # %continue
+; RV64ZBA-NEXT:  .LBB69_2: # %continue
 ; RV64ZBA-NEXT:    li a0, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
   br i1 %obit, label %overflow, label %continue
 

 declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
 declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone