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[RISCV][AMDGPU][TargetLowering] Special case overflow expansion for (uaddo X, 1).
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Authored by craig.topper on Apr 1 2022, 12:50 PM.

Details

Summary

If we expand (uaddo X, 1) we previously expanded the overflow calculation
as (X + 1) <u X. This potentially increases the live range of X and
can prevent X+1 from reusing the register that previously held X.

Since we're adding 1, overflow only occurs if X was UINT_MAX in which
case (X+1) would be 0. So this patch adds a special case to expand
the overflow calculation to (X+1) == 0.

This seems to help with uaddo intrinsics that get introduced by
CodeGenPrepare after LSR. Alternatively, we could block the uaddo
transform in CodeGenPrepare for this case.

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Event Timeline

craig.topper created this revision.Apr 1 2022, 12:50 PM
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craig.topper requested review of this revision.Apr 1 2022, 12:50 PM
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arsenm accepted this revision.Apr 1 2022, 1:11 PM

LGTM. Since this also seems to only show up in the AMDGPU division expansion, presumably we could avoid this from happening in the first place

This revision is now accepted and ready to land.Apr 1 2022, 1:11 PM
This revision was landed with ongoing or failed builds.Apr 1 2022, 1:16 PM
This revision was automatically updated to reflect the committed changes.