[RISCV] support fcmp in zfinx,zdinx,zhinx

[realqhc]

Summary

Co-Author: @liaolucy @s
add support for fcmp in zfinx and its double and half instructions.

[realqhc]

[RISCV] Remove fcmp-strict instructions in zfinx, zdinx, and zhinx

[realqhc]

[RISCV] remove strict_fcmp and arith

[realqhc]

[RISCV] revert target-abi test and abi error string format

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

101

I think you need to check Subtarget.is64Bit() here. You can't assign a type to two register classes. The type is used as the key to a map. The second call overwrites the first.

[realqhc]

address concerns, add test for rv32

[realqhc]

revert changes to buildpairf64pesudo, fix test for rv32 zdinx

[realqhc]

revert changes to splitpairf64pesudo, remove SplitPairF64Pseudo_INX

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

private:
   bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI,
                               MachineBasicBlock::iterator &NextMBBI);
   bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, unsigned Opcode);
   bool expandVSPILL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool expandVRELOAD(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
+  bool expandpair(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
 };
 
 char RISCVExpandPseudo::ID = 0;
 
 bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
   bool Modified = false;
   for (auto &MBB : MF)
while (MBBI != E) {
     MachineBasicBlock::iterator NMBBI = std::next(MBBI);
     Modified |= expandMI(MBB, MBBI, NMBBI);
     MBBI = NMBBI;
   }
 
   return Modified;
 }
 
+bool RISCVExpandPseudo::expandpair(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator MBBI) {
+  MBBI->eraseFromParent();
+
+  return true;
+}
+
 bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  MachineBasicBlock::iterator &NextMBBI) {
   // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
   // expanded instructions for each pseudo is correct in the Size field of the
   // tablegen definition for the pseudo.
   switch (MBBI->getOpcode()) {
+  case RISCV::BuildPairF64Pseudo_INX:
+    return expandpair(MBB, MBBI);
   case RISCV::PseudoLLA:
     return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA:
     return expandLoadAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA_TLS_IE:
     return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA_TLS_GD:
     return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
   if (Subtarget.hasStdExtZfh())
     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
+  if (Subtarget.hasStdExtZhinx())
+    addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass);
+  if (Subtarget.hasStdExtZfinx())
+    addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass);
+  if (Subtarget.hasStdExtZdinx()) {
+    if (Subtarget.is64Bit())
+      addRegisterClass(MVT::f64, &RISCV::GPRF64RegClass);
+    else
+      addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass);
+  }
 
   static const MVT::SimpleValueType BoolVecVTs[] = {
       MVT::nxv1i1,  MVT::nxv2i1,  MVT::nxv4i1, MVT::nxv8i1,
       MVT::nxv16i1, MVT::nxv32i1, MVT::nxv64i1};
   static const MVT::SimpleValueType IntVecVTs[] = {
       MVT::nxv1i8,  MVT::nxv2i8,   MVT::nxv4i8,   MVT::nxv8i8,  MVT::nxv16i8,
       MVT::nxv32i8, MVT::nxv64i8,  MVT::nxv1i16,  MVT::nxv2i16, MVT::nxv4i16,
       MVT::nxv8i16, MVT::nxv16i16, MVT::nxv32i16, MVT::nxv1i32, MVT::nxv2i32,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   static const ISD::NodeType FPOpToExpand[] = {
       ISD::FSIN, ISD::FCOS,       ISD::FSINCOS,   ISD::FPOW,
       ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
 
   if (Subtarget.hasStdExtZfh())
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
-  if (Subtarget.hasStdExtZfh()) {
+  if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZhinx()) {
     for (auto NT : FPLegalNodeTypes)
       setOperationAction(NT, MVT::f16, Legal);
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f16, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
     setOperationAction(ISD::SELECT, MVT::f16, Custom);
if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZhinx()) {
     // FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have
     // complete support for all operations in LegalizeDAG.
 
     // We need to custom promote this.
     if (Subtarget.is64Bit())
       setOperationAction(ISD::FPOWI, MVT::i32, Custom);
   }
 
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) {
     for (auto NT : FPLegalNodeTypes)
       setOperationAction(NT, MVT::f32, Legal);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT, MVT::f32, Custom);
     setOperationAction(ISD::BR_CC, MVT::f32, Expand);
     for (auto Op : FPOpToExpand)
       setOperationAction(Op, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
   }
 
-  if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
+  if ((Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) &&
+      Subtarget.is64Bit())
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
 
-  if (Subtarget.hasStdExtD()) {
+  if (Subtarget.hasStdExtD() || Subtarget.hasStdExtZdinx()) {
     for (auto NT : FPLegalNodeTypes)
       setOperationAction(NT, MVT::f64, Legal);
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
     for (auto CC : FPCCToExpand)
       setCondCodeAction(CC, MVT::f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
     setOperationAction(ISD::SELECT, MVT::f64, Custom);
     setOperationAction(ISD::BR_CC, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
     setTruncStoreAction(MVT::f64, MVT::f32, Expand);
     for (auto Op : FPOpToExpand)
       setOperationAction(Op, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
     setTruncStoreAction(MVT::f64, MVT::f16, Expand);
   }
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) {
     setOperationAction(ISD::FP_TO_UINT_SAT, XLenVT, Custom);
     setOperationAction(ISD::FP_TO_SINT_SAT, XLenVT, Custom);
 
     setOperationAction(ISD::STRICT_FP_TO_UINT, XLenVT, Legal);
     setOperationAction(ISD::STRICT_FP_TO_SINT, XLenVT, Legal);
     setOperationAction(ISD::STRICT_UINT_TO_FP, XLenVT, Legal);
     setOperationAction(ISD::STRICT_SINT_TO_FP, XLenVT, Legal);
 
if (Subtarget.useRVVForFixedLengthVectors()) {
           setOperationAction(VPOpc, VT, Custom);
       }
 
       // Custom-legalize bitcasts from fixed-length vectors to scalar types.
       setOperationAction(ISD::BITCAST, MVT::i8, Custom);
       setOperationAction(ISD::BITCAST, MVT::i16, Custom);
       setOperationAction(ISD::BITCAST, MVT::i32, Custom);
       setOperationAction(ISD::BITCAST, MVT::i64, Custom);
-      if (Subtarget.hasStdExtZfh())
+      if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZhinx())
         setOperationAction(ISD::BITCAST, MVT::f16, Custom);
-      if (Subtarget.hasStdExtF())
+      if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx())
         setOperationAction(ISD::BITCAST, MVT::f32, Custom);
-      if (Subtarget.hasStdExtD())
+      if (Subtarget.hasStdExtD() || Subtarget.hasStdExtZdinx())
         setOperationAction(ISD::BITCAST, MVT::f64, Custom);
     }
   }
 
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
if (Subtarget.hasStdExtZbp()) {
     setTargetDAGCombine(ISD::ROTL);
     setTargetDAGCombine(ISD::ROTR);
   }
   if (Subtarget.hasStdExtZbkb())
     setTargetDAGCombine(ISD::BITREVERSE);
   setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
   if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
-  if (Subtarget.hasStdExtF()) {
+  if (Subtarget.hasStdExtF() || Subtarget.hasStdExtZfinx()) {
     setTargetDAGCombine(ISD::ZERO_EXTEND);
     setTargetDAGCombine(ISD::FP_TO_SINT);
     setTargetDAGCombine(ISD::FP_TO_UINT);
     setTargetDAGCombine(ISD::FP_TO_SINT_SAT);
     setTargetDAGCombine(ISD::FP_TO_UINT_SAT);
   }
   if (Subtarget.hasVInstructions()) {
     setTargetDAGCombine(ISD::FCOPYSIGN);
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   std::pair<Register, const TargetRegisterClass *> Res =
       TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 
   // If we picked one of the Zfinx register classes, remap it to the GPR class.
   // FIXME: When Zfinx is supported in CodeGen this will need to take the
   // Subtarget into account.
   if (Res.second == &RISCV::GPRF16RegClass ||
       Res.second == &RISCV::GPRF32RegClass ||
-      Res.second == &RISCV::GPRF64RegClass)
+      Res.second == &RISCV::GPRF64RegClass ||
+      Res.second == &RISCV::GPRPF64RegClass)
     return std::make_pair(Res.first, &RISCV::GPRRegClass);
 
   return Res;
 }
 
 unsigned
 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
   // Currently only support length 1 constraints.

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
-class PseudoQuietFCMP<RegisterClass Ty>
+class PseudoQuietFCMP<DAGOperand Ty>
     : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> {
   let hasSideEffects = 1;
   let mayLoad = 0;
   let mayStore = 0;
 }
 
 // Pseudo load instructions.
 class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.d $rd, $rs, $rt",
                 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 def : InstAlias<"fge.d $rd, $rs, $rt",
                 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 
 def PseudoFLD  : PseudoFloatLoad<"fld", FPR64>;
 def PseudoFSD  : PseudoStore<"fsd", FPR64>;
+} // Predicates = [HasStdExtD]
+
 let usesCustomInserter = 1 in {
-def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>;
-def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>;
+defm PseudoQuietFLE_D : PseudoQuietFCMP_m<DINX>;
+defm PseudoQuietFLT_D : PseudoQuietFCMP_m<DINX>;
 }
-} // Predicates = [HasStdExtD]
 
 let Predicates = [HasStdExtZdinx, IsRV64] in {
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
 
 def : InstAlias<"fgt.d $rd, $rs, $rt",
                 (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>;
 def : InstAlias<"fge.d $rd, $rs, $rt",

 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
           (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum.
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 def : PatFprFpr<fminnum, FMIN_D, FPR64>;
 def : PatFprFpr<fmaxnum, FMAX_D, FPR64>;
+} // Predicates = [HasStdExtD]
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
 // strict versions of those.
 
 // Match non-signaling FEQ_D
-def : PatSetCC<FPR64, any_fsetcc, SETEQ, FEQ_D>;
-def : PatSetCC<FPR64, any_fsetcc, SETOEQ, FEQ_D>;
-def : PatSetCC<FPR64, strict_fsetcc, SETLT, PseudoQuietFLT_D>;
-def : PatSetCC<FPR64, strict_fsetcc, SETOLT, PseudoQuietFLT_D>;
-def : PatSetCC<FPR64, strict_fsetcc, SETLE, PseudoQuietFLE_D>;
-def : PatSetCC<FPR64, strict_fsetcc, SETOLE, PseudoQuietFLE_D>;
+defm : PatSetCC_m<any_fsetcc, SETEQ,  FEQ_D,            DINX>;
+defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_D,            DINX>;
+def : PatSetCC<strict_fsetcc, SETLT,  PseudoQuietFLT_D, FPR64>;
+def : PatSetCC<strict_fsetcc, SETOLT, PseudoQuietFLT_D, FPR64>;
+def : PatSetCC<strict_fsetcc, SETLE,  PseudoQuietFLE_D, FPR64>;
+def : PatSetCC<strict_fsetcc, SETOLE, PseudoQuietFLE_D, FPR64>;
 
+let Predicates = [HasStdExtD] in {
 // Match signaling FEQ_D
 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ),
           (AND (FLE_D $rs1, $rs2),
                (FLE_D $rs2, $rs1))>;
 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ),
           (AND (FLE_D $rs1, $rs2),
                (FLE_D $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ),
           (FLE_D $rs1, $rs1)>;
 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ),
           (FLE_D $rs1, $rs1)>;
+} // Predicates = [HasStdExtD]
 
-def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D>;
-def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D>;
-def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D>;
-def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D>;
+defm : PatSetCC_m<any_fsetccs, SETLT,  FLT_D, DINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_D, DINX>;
+defm : PatSetCC_m<any_fsetccs, SETLE,  FLE_D, DINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_D, DINX>;
 
+let Predicates = [HasStdExtD] in {
 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
 
 /// Loads
 
 defm : LdPat<load, FLD, f64>;
 
 /// Stores
 

 // Moves an FPR to two GPRs.
 let usesCustomInserter = 1 in
 def SplitF64Pseudo
     : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
              [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
 
 } // Predicates = [HasStdExtD]
 
+let Predicates = [HasStdExtZdinx] in {
+
+// Moves two GPRs to an FPR.
+def BuildPairF64Pseudo_INX
+    : Pseudo<(outs GPRPF64:$dst), (ins GPR:$src1, GPR:$src2),
+             [(set GPRPF64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
+
+} // Predicates = [HasStdExtZdinx]
+
 let Predicates = [HasStdExtD, IsRV32] in {
 
 /// Float constants
 def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>;
 def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FCVT_D_W (i32 X0)),
                                        (FCVT_D_W (i32 X0)))>;
 
 // double->[u]int. Round-to-zero must be used.

 // float->int32 rounded to nearest with ties rounded away from zero.
 def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, 0b100)>;
 
 // [u]int->double.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>;
 } // Predicates = [HasStdExtD, IsRV32]
 
+let Predicates = [HasStdExtZdinx, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(f64 (bitconvert (i64 GPR:$rs1))), (COPY GPR:$rs1)>;
+def : Pat<(i64 (bitconvert GPRF64:$rs1)), (COPY GPRF64:$rs1)>;
+} // Predicates = [HasStdExtZdinx, IsRV64]
+
 let Predicates = [HasStdExtD, IsRV64] in {
 
 /// Float constants
 def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>;
 def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FMV_D_X (i64 X0)),
                                        (FMV_D_X (i64 X0)))>;
 
 // Moves (no conversion)

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

: RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 multiclass FPCmp_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr,
                       list<ExtInfo_r> Exts> {
   foreach Ext = Exts in
     let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
     def Ext.Suffix : FPCmp_rr<funct7, funct3, opcodestr, Ext.Reg>;
 }
 
+multiclass PseudoQuietFCMP_m<list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PseudoQuietFCMP<Ext.Reg>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
 def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
 
 // Operands for stores are in the order srcreg, base, offset rather than

 
 // fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
 // spellings should be supported by standard tools.
 def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
 def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
 
 def PseudoFLW  : PseudoFloatLoad<"flw", FPR32>;
 def PseudoFSW  : PseudoStore<"fsw", FPR32>;
+} // Predicates = [HasStdExtF]
+
 let usesCustomInserter = 1 in {
-def PseudoQuietFLE_S : PseudoQuietFCMP<FPR32>;
-def PseudoQuietFLT_S : PseudoQuietFCMP<FPR32>;
+defm PseudoQuietFLE_S : PseudoQuietFCMP_m<FINX>;
+defm PseudoQuietFLT_S : PseudoQuietFCMP_m<FINX>;
 }
-} // Predicates = [HasStdExtF]
 
 let Predicates = [HasStdExtZfinx] in {
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
 
 def : InstAlias<"fgt.s $rd, $rs, $rt",
                 (FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
 def : InstAlias<"fge.s $rd, $rs, $rt",
                 (FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
 } // Predicates = [HasStdExtZfinx]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 /// Floating point constants
 def fpimm0    : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
 
 /// Generic pattern classes
-class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst>
+class PatSetCC<SDPatternOperator OpNode, CondCode Cond, RVInst Inst,
+               DAGOperand Ty>
     : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>;
+multiclass PatSetCC_m<SDPatternOperator OpNode, CondCode Cond,
+                      RVInst Inst, list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PatSetCC<OpNode, Cond, !cast<RVInst>(Inst#Ext.Suffix),
+                              Ext.Reg>;
+}
 
 class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst,
-                RegisterClass RegTy>
+                DAGOperand RegTy>
     : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
 
 class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
-                      RegisterClass RegTy>
+                      DAGOperand RegTy>
     : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>;
+multiclass PatFprFprDynFrm_m<SDPatternOperator OpNode, RVInstRFrm Inst,
+                             list<ExtInfo_r> Exts> {
+  foreach Ext = Exts in
+    let Predicates = Ext.Predicates in
+    def Ext.Suffix : PatFprFprDynFrm<OpNode,
+                                     !cast<RVInstRFrm>(Inst#Ext.Suffix),
+                                     Ext.Reg>;
+}
 
 let Predicates = [HasStdExtF] in {
 
 /// Float constants
 def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
 def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
+} // Predicates = [HasStdExtF]
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
 def : PatFprFprDynFrm<any_fadd, FADD_S, FPR32>;
 def : PatFprFprDynFrm<any_fsub, FSUB_S, FPR32>;
 def : PatFprFprDynFrm<any_fmul, FMUL_S, FPR32>;
 def : PatFprFprDynFrm<any_fdiv, FDIV_S, FPR32>;
 
+let Predicates = [HasStdExtF] in {
 def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
 
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
 
 def : PatFprFpr<fcopysign, FSGNJ_S, FPR32>;
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
 

 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
           (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
 
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 def : PatFprFpr<fminnum, FMIN_S, FPR32>;
 def : PatFprFpr<fmaxnum, FMAX_S, FPR32>;
+} // Predicates = [HasStdExtF]
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
 // strict versions of those.
 
 // Match non-signaling FEQ_S
-def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>;
-def : PatSetCC<FPR32, any_fsetcc, SETOEQ, FEQ_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETLT, PseudoQuietFLT_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETOLT, PseudoQuietFLT_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETLE, PseudoQuietFLE_S>;
-def : PatSetCC<FPR32, strict_fsetcc, SETOLE, PseudoQuietFLE_S>;
+defm : PatSetCC_m<any_fsetcc, SETEQ,  FEQ_S,            FINX>;
+defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_S,            FINX>;
+def : PatSetCC<strict_fsetcc, SETLT,  PseudoQuietFLT_S, FPR32>;
+def : PatSetCC<strict_fsetcc, SETOLT, PseudoQuietFLT_S, FPR32>;
+def : PatSetCC<strict_fsetcc, SETLE,  PseudoQuietFLE_S, FPR32>;
+def : PatSetCC<strict_fsetcc, SETOLE, PseudoQuietFLE_S, FPR32>;
 
+let Predicates = [HasStdExtF] in {
 // Match signaling FEQ_S
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
           (FLE_S $rs1, $rs1)>;
 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ),
           (FLE_S $rs1, $rs1)>;
+} // Predicates = [HasStdExtF]
 
-def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETLE, FLE_S>;
-def : PatSetCC<FPR32, any_fsetccs, SETOLE, FLE_S>;
+defm : PatSetCC_m<any_fsetccs, SETLT,  FLT_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETLE,  FLE_S, FINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_S, FINX>;
 
+let Predicates = [HasStdExtF] in {
 def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
 
 /// Loads
 
 defm : LdPat<load, FLW, f32>;
 
 /// Stores
 
 defm : StPat<store, FSW, FPR32, f32>;
 
 } // Predicates = [HasStdExtF]
 
+let Predicates = [HasStdExtZfinx, IsRV32] in {
+// Moves (no conversion)
+def : Pat<(f32 (bitconvert (i32 GPR:$rs1))), (COPY GPR:$rs1)>;
+def : Pat<(i32 (bitconvert GPRF32:$rs1)), (COPY GPRF32:$rs1)>;
+} // Predicates = [HasStdExtZfinx, IsRV32]
+
 let Predicates = [HasStdExtF, IsRV32] in {
 // Moves (no conversion)
 def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
 def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>;
 
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>;
 
 // Saturating float->[u]int32.
 def : Pat<(i32 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_W_S $rs1, timm:$frm)>;
 def : Pat<(i32 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_WU_S $rs1, timm:$frm)>;
 
 // float->int32 with current rounding mode.
 def : Pat<(i32 (any_lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>;
 
 // float->int32 rounded to nearest with ties rounded away from zero.
 def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>;
 
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
+let Predicates = [HasStdExtZfinx, IsRV64] in {
+// Moves (no conversion)
+def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (COPY GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyextw_rv64 GPRF32:$src), (COPY GPRF32:$src)>;
+def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 GPRF32:$src), i32),
+          (COPY GPRF32:$src)>;
+} // Predicates = [HasStdExtZfinx, IsRV64]
+
 let Predicates = [HasStdExtF, IsRV64] in {
 // Moves (no conversion)
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
           (FMV_X_W FPR32:$src)>;
 
 // Use target specific isd nodes to help us remember the result is sign

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 } // Predicates = [HasStdExtZfh]
 
 let Predicates = [HasStdExtZfhOrZfhmin] in {
 def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
 def PseudoFSH  : PseudoStore<"fsh", FPR16>;
+} // Predicates = [HasStdExtZfhOrZfhmin]
+
 let usesCustomInserter = 1 in {
-def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;
-def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
+defm PseudoQuietFLE_H : PseudoQuietFCMP_m<HINX>;
+defm PseudoQuietFLT_H : PseudoQuietFCMP_m<HINX>;
 }
-} // Predicates = [HasStdExtZfhOrZfhmin]
 
 let Predicates = [HasStdExtZhinx] in {
 def : InstAlias<"fmv.h $rd, $rs",  (FSGNJ_H_INX  FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 
 def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>;

 def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
           (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
 
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 def : PatFprFpr<fminnum, FMIN_H, FPR16>;
 def : PatFprFpr<fmaxnum, FMAX_H, FPR16>;
+} // Predicates = [HasStdExtZfh]
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
 // strict versions of those.
 
-// Match non-signaling FEQ_D
-def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>;
-def : PatSetCC<FPR16, any_fsetcc, SETOEQ, FEQ_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETLT, PseudoQuietFLT_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETOLT, PseudoQuietFLT_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETLE, PseudoQuietFLE_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETOLE, PseudoQuietFLE_H>;
+// Match non-signaling FEQ_H
+defm : PatSetCC_m<any_fsetcc, SETEQ,  FEQ_H,            HINX>;
+defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_H,            HINX>;
+def : PatSetCC<strict_fsetcc, SETLT,  PseudoQuietFLT_H, FPR16>;
+def : PatSetCC<strict_fsetcc, SETOLT, PseudoQuietFLT_H, FPR16>;
+def : PatSetCC<strict_fsetcc, SETLE,  PseudoQuietFLE_H, FPR16>;
+def : PatSetCC<strict_fsetcc, SETOLE, PseudoQuietFLE_H, FPR16>;
 
+let Predicates = [HasStdExtZfh] in {
 // Match signaling FEQ_H
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ),
           (FLE_H $rs1, $rs1)>;
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ),
           (FLE_H $rs1, $rs1)>;
+} // Predicates = [HasStdExtZfh]
 
-def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETLE, FLE_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETOLE, FLE_H>;
+defm : PatSetCC_m<any_fsetccs, SETLT,  FLT_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETLE,  FLE_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_H, HINX>;
 
+let Predicates = [HasStdExtZfh] in {
 def Select_FPR16_Using_CC_GPR : SelectCC_rrirr<FPR16, GPR>;
 } // Predicates = [HasStdExtZfh]
 
+let Predicates = [HasStdExtZhinx] in {
+// Moves (no conversion)
+def : Pat<(riscv_fmv_h_x GPR:$src), (COPY GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyexth GPRF16:$src), (COPY GPRF16:$src)>;
+def : Pat<(riscv_fmv_x_signexth GPRF16:$src), (COPY GPRF16:$src)>;
+} // Predicates = [HasStdExtZhinx]
+
 let Predicates = [HasStdExtZfhOrZfhmin] in {
 /// Loads
 
 defm : LdPat<load, FLH, f16>;
 
 /// Stores
 
 defm : StPat<store, FSH, FPR16, f16>;

llvm/test/CodeGen/RISCV/double-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ZDINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64ZDINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fcmp_false:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_false:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    li a0, 0
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_false:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    li a0, 0
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_false:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    li a0, 0
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0

 ; RV32IFD-NEXT:    feq.d a0, fa0, fa1
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_oeq:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_oeq:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    feq.d a0, a0, a2
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_oeq:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    feq.d a0, a0, a1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqdf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    flt.d a0, fa1, fa0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_ogt:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ogt:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a0, a2, a0
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ogt:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a0, a1, a0
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_oge:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_oge:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    fle.d a0, a2, a0
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_oge:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    fle.d a0, a1, a0
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV32IFD-NEXT:    flt.d a0, fa0, fa1
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_olt:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_olt:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a0, a0, a2
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_olt:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a0, a0, a1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    fle.d a0, fa0, fa1
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_ole:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa0, fa1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ole:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    fle.d a0, a0, a2
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ole:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    fle.d a0, a0, a1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ;
 ; RV64IFD-LABEL: fcmp_one:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa0, fa1
 ; RV64IFD-NEXT:    flt.d a1, fa1, fa0
 ; RV64IFD-NEXT:    or a0, a1, a0
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_one:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a4, a0, a2
+; RV32ZDINX-NEXT:    flt.d a0, a2, a0
+; RV32ZDINX-NEXT:    or a0, a0, a4
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_one:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a2, a0, a1
+; RV64ZDINX-NEXT:    flt.d a0, a1, a0
+; RV64ZDINX-NEXT:    or a0, a0, a2
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ;
 ; RV64IFD-LABEL: fcmp_ord:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa1, fa1
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    and a0, a1, a0
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ord:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    feq.d a2, a2, a2
+; RV32ZDINX-NEXT:    feq.d a0, a0, a0
+; RV32ZDINX-NEXT:    and a0, a0, a2
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ord:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    feq.d a1, a1, a1
+; RV64ZDINX-NEXT:    feq.d a0, a0, a0
+; RV64ZDINX-NEXT:    and a0, a0, a1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IFD-LABEL: fcmp_ueq:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa0, fa1
 ; RV64IFD-NEXT:    flt.d a1, fa1, fa0
 ; RV64IFD-NEXT:    or a0, a1, a0
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ueq:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a4, a0, a2
+; RV32ZDINX-NEXT:    flt.d a0, a2, a0
+; RV32ZDINX-NEXT:    or a0, a0, a4
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ueq:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a2, a0, a1
+; RV64ZDINX-NEXT:    flt.d a0, a1, a0
+; RV64ZDINX-NEXT:    or a0, a0, a2
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_ugt:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa0, fa1
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ugt:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    fle.d a0, a0, a2
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ugt:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    fle.d a0, a0, a1
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_uge:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa0, fa1
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_uge:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a0, a0, a2
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_uge:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a0, a0, a1
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_ult:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fle.d a0, fa1, fa0
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ult:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    fle.d a0, a2, a0
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ult:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    fle.d a0, a1, a0
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_ule:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    flt.d a0, fa1, fa0
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_ule:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    flt.d a0, a2, a0
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_ule:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    flt.d a0, a1, a0
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_une:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa1
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_une:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    feq.d a0, a0, a2
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_une:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    feq.d a0, a0, a1
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nedf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IFD-LABEL: fcmp_uno:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa1, fa1
 ; RV64IFD-NEXT:    feq.d a1, fa0, fa0
 ; RV64IFD-NEXT:    and a0, a1, a0
 ; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_uno:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    feq.d a2, a2, a2
+; RV32ZDINX-NEXT:    feq.d a0, a0, a0
+; RV32ZDINX-NEXT:    and a0, a0, a2
+; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_uno:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    feq.d a1, a1, a1
+; RV64ZDINX-NEXT:    feq.d a0, a0, a0
+; RV64ZDINX-NEXT:    and a0, a0, a1
+; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcmp_true:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    li a0, 1
 ; RV64IFD-NEXT:    ret
 ;
+; RV32ZDINX-LABEL: fcmp_true:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    li a0, 1
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: fcmp_true:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    li a0, 1
+; RV64ZDINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64ZFINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fcmp_false:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_false:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    li a0, 0
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_false:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    li a0, 0
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_false:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    li a0, 0
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0

 ; RV32IF-NEXT:    feq.s a0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_oeq:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_oeq:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    feq.s a0, a0, a1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_oeq:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    feq.s a0, a0, a1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    flt.s a0, fa1, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_ogt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ogt:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a0, a1, a0
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ogt:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a0, a1, a0
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    fle.s a0, fa1, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_oge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_oge:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    fle.s a0, a1, a0
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_oge:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    fle.s a0, a1, a0
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV32IF-NEXT:    flt.s a0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_olt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_olt:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a0, a0, a1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_olt:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a0, a0, a1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    fle.s a0, fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_ole:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ole:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    fle.s a0, a0, a1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ole:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    fle.s a0, a0, a1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ;
 ; RV64IF-LABEL: fcmp_one:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    flt.s a1, fa1, fa0
 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_one:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a2, a0, a1
+; RV32ZFINX-NEXT:    flt.s a0, a1, a0
+; RV32ZFINX-NEXT:    or a0, a0, a2
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_one:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a2, a0, a1
+; RV64ZFINX-NEXT:    flt.s a0, a1, a0
+; RV64ZFINX-NEXT:    or a0, a0, a2
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; RV64IF-LABEL: fcmp_ord:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa1, fa1
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ord:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    feq.s a1, a1, a1
+; RV32ZFINX-NEXT:    feq.s a0, a0, a0
+; RV32ZFINX-NEXT:    and a0, a0, a1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ord:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    feq.s a1, a1, a1
+; RV64ZFINX-NEXT:    feq.s a0, a0, a0
+; RV64ZFINX-NEXT:    and a0, a0, a1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IF-LABEL: fcmp_ueq:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    flt.s a1, fa1, fa0
 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ueq:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a2, a0, a1
+; RV32ZFINX-NEXT:    flt.s a0, a1, a0
+; RV32ZFINX-NEXT:    or a0, a0, a2
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ueq:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a2, a0, a1
+; RV64ZFINX-NEXT:    flt.s a0, a1, a0
+; RV64ZFINX-NEXT:    or a0, a0, a2
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_ugt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ugt:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    fle.s a0, a0, a1
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ugt:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    fle.s a0, a0, a1
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_uge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_uge:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a0, a0, a1
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_uge:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a0, a0, a1
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_ult:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ult:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    fle.s a0, a1, a0
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ult:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    fle.s a0, a1, a0
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_ule:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_ule:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    flt.s a0, a1, a0
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_ule:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    flt.s a0, a1, a0
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_une:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_une:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    feq.s a0, a0, a1
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_une:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    feq.s a0, a0, a1
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64IF-LABEL: fcmp_uno:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa1, fa1
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_uno:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    feq.s a1, a1, a1
+; RV32ZFINX-NEXT:    feq.s a0, a0, a0
+; RV32ZFINX-NEXT:    and a0, a0, a1
+; RV32ZFINX-NEXT:    xori a0, a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_uno:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    feq.s a1, a1, a1
+; RV64ZFINX-NEXT:    feq.s a0, a0, a0
+; RV64ZFINX-NEXT:    and a0, a0, a1
+; RV64ZFINX-NEXT:    xori a0, a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_true:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    li a0, 1
 ; RV64IF-NEXT:    ret
 ;
+; RV32ZFINX-LABEL: fcmp_true:
+; RV32ZFINX:       # %bb.0:
+; RV32ZFINX-NEXT:    li a0, 1
+; RV32ZFINX-NEXT:    ret
+;
+; RV64ZFINX-LABEL: fcmp_true:
+; RV64ZFINX:       # %bb.0:
+; RV64ZFINX-NEXT:    li a0, 1
+; RV64ZFINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64ZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fcmp_false:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    li a0, 0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_false:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    li a0, 0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_false:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    li a0, 0
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_false:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    li a0, 0
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0

 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_oeq:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_oeq:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    feq.h a0, a0, a1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_oeq:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    feq.h a0, a0, a1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    feq.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oeq:

 ; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_ogt:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ogt:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a0, a1, a0
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ogt:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a0, a1, a0
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:

 ; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_oge:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_oge:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    fle.h a0, a1, a0
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_oge:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    fle.h a0, a1, a0
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:

 ; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_olt:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_olt:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a0, a0, a1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_olt:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a0, a0, a1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_olt:

 ; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_ole:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ole:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    fle.h a0, a0, a1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ole:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    fle.h a0, a0, a1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ole:

 ;
 ; RV64IZFH-LABEL: fcmp_one:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
 ; RV64IZFH-NEXT:    or a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_one:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a2, a0, a1
+; RV32ZHINX-NEXT:    flt.h a0, a1, a0
+; RV32ZHINX-NEXT:    or a0, a0, a2
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_one:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a2, a0, a1
+; RV64ZHINX-NEXT:    flt.h a0, a1, a0
+; RV64ZHINX-NEXT:    or a0, a0, a2
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    flt.h a1, ft0, ft1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret

 ;
 ; RV64IZFH-LABEL: fcmp_ord:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ord:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    feq.h a1, a1, a1
+; RV32ZHINX-NEXT:    feq.h a0, a0, a0
+; RV32ZHINX-NEXT:    and a0, a0, a1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ord:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    feq.h a1, a1, a1
+; RV64ZHINX-NEXT:    feq.h a0, a0, a0
+; RV64ZHINX-NEXT:    and a0, a0, a1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    feq.h a0, ft1, ft1
 ; RV32I-NEXT:    feq.h a1, ft0, ft0
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret

 ; RV64IZFH-LABEL: fcmp_ueq:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
 ; RV64IZFH-NEXT:    or a0, a1, a0
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ueq:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a2, a0, a1
+; RV32ZHINX-NEXT:    flt.h a0, a1, a0
+; RV32ZHINX-NEXT:    or a0, a0, a2
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ueq:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a2, a0, a1
+; RV64ZHINX-NEXT:    flt.h a0, a1, a0
+; RV64ZHINX-NEXT:    or a0, a0, a2
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    flt.h a1, ft0, ft1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_ugt:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ugt:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    fle.h a0, a0, a1
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ugt:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    fle.h a0, a0, a1
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_uge:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_uge:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a0, a0, a1
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_uge:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a0, a0, a1
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_ult:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ult:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    fle.h a0, a1, a0
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ult:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    fle.h a0, a1, a0
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_ule:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_ule:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    flt.h a0, a1, a0
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_ule:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    flt.h a0, a1, a0
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_une:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_une:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    feq.h a0, a0, a1
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_une:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    feq.h a0, a0, a1
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    feq.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; RV64IZFH-LABEL: fcmp_uno:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_uno:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    feq.h a1, a1, a1
+; RV32ZHINX-NEXT:    feq.h a0, a0, a0
+; RV32ZHINX-NEXT:    and a0, a0, a1
+; RV32ZHINX-NEXT:    xori a0, a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_uno:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    feq.h a1, a1, a1
+; RV64ZHINX-NEXT:    feq.h a0, a0, a0
+; RV64ZHINX-NEXT:    and a0, a0, a1
+; RV64ZHINX-NEXT:    xori a0, a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    feq.h a0, ft1, ft1
 ; RV32I-NEXT:    feq.h a1, ft0, ft0
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV32IZFH-NEXT:    li a0, 1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_true:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    li a0, 1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32ZHINX-LABEL: fcmp_true:
+; RV32ZHINX:       # %bb.0:
+; RV32ZHINX-NEXT:    li a0, 1
+; RV32ZHINX-NEXT:    ret
+;
+; RV64ZHINX-LABEL: fcmp_true:
+; RV64ZHINX:       # %bb.0:
+; RV64ZHINX-NEXT:    li a0, 1
+; RV64ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }