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Differential D117647

[RISCV] Add passthru operand for RVV nomask load intrinsics.
ClosedPublic

Authored by khchen on Jan 19 2022, 1:30 AM.

Details

Reviewers
craig.topper
rogfer01
evandro
arcbbb
monkchiang
Commits
rG9273378b8576: [RISCV] Add the passthru operand for RVV nomask load intrinsics.
Summary

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru is undef, we use tail agnostic, otherwise
use tail undisturbed.

Co-Authored-by: Hsiangkai Wang <Hsiangkai@gmail.com>

Diff Detail

Unit TestsFailed

TimeTest
5,980 msx64 debian > libarcher.races::critical-unrelated.c
4,840 msx64 debian > libarcher.races::lock-nested-unrelated.c
5,230 msx64 debian > libarcher.races::lock-unrelated.c
6,100 msx64 debian > libarcher.races::parallel-simple.c
6,100 msx64 debian > libarcher.races::task-dependency.c
View Full Test Results (9 Failed)

Event Timeline

khchen created this revision.Jan 19 2022, 1:30 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptJan 19 2022, 1:30 AM
khchen requested review of this revision.Jan 19 2022, 1:30 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 19 2022, 1:30 AM
Herald added subscribers: llvm-commits, cfe-commits, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B144224: Diff 401131.Jan 19 2022, 2:21 AM
craig.topper added inline comments.Jan 19 2022, 3:30 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1267
bool IsTU = IntNo != Intrinsic::riscv_vlm && (!Node->getOperand(CurOp).isUndef() || IsMasked);
NOTE: I changed it so IsMask is also only checked when it's not vlm. That makes the non vlm part of the condition look like the other intrinsic handling earlier.
1281

Why aren't we using the default value for IndexVT now?

craig.topper mentioned this in D117561: [RISCV][VP] Lower VP_MERGE to RVV instructions.Jan 19 2022, 3:55 PM
khchen updated this revision to Diff 401446.Jan 19 2022, 4:46 PM

Address Craig's comments, thanks!

Harbormaster completed remote builds in B144445: Diff 401446.Jan 19 2022, 5:52 PM
frasercrmck added a comment.Jan 20 2022, 4:50 AM

Is "destination operand" the terminology we want? I'd have thought "passthru" was more conventional.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1222

If I'm reading this right, isn't it possible that we could have a masked/tu intrinsic, so push back the passthru operand, increment CurOp then check whether the pointer operand is Undef, then wrongly increment CurOp a second time? So basically an undef base pointer has the potential to (presumably) crash the compiler somewhere later?

Don't we unconditionally want to increment CurOp (a single time) since we now always have a passthru operand that we want to skip over?

khchen updated this revision to Diff 401899.Jan 21 2022, 1:32 AM

address frasercrmck's comments.
rewrite snippet of code to fix potential bug and make more readable.

Harbormaster completed remote builds in B144772: Diff 401899.Jan 21 2022, 2:15 AM
frasercrmck added a comment.Jan 21 2022, 7:17 AM

Thanks, LGTM.

As a heads up, I've pinched the use of _TU as a suffix in D117561. The conflicts should be minor (one location) for whichever patch is merged second.

khchen retitled this revision from [RISCV] Add destination operand for RVV nomask load intrinsics. to [RISCV] Add passthru operand for RVV nomask load intrinsics..Jan 21 2022, 8:01 AM
khchen edited the summary of this revision. (Show Details)
khchen updated this revision to Diff 402776.Jan 25 2022, 12:11 AM

rebase and ping.

Herald added a subscriber: • pcwang-thead. · View Herald TranscriptJan 25 2022, 12:11 AM
craig.topper accepted this revision.Jan 25 2022, 8:43 AM

LGTM

This revision is now accepted and ready to land.Jan 25 2022, 8:43 AM
This revision was landed with ongoing or failed builds.Jan 25 2022, 5:36 PM
Closed by commit rG9273378b8576: [RISCV] Add the passthru operand for RVV nomask load intrinsics. (authored by khchen). · Explain Why
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rG9273378b8576: [RISCV] Add the passthru operand for RVV nomask load intrinsics..
Harbormaster completed remote builds in B145406: Diff 402776.Jan 26 2022, 1:43 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
4 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
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382 lines
rvv-intrinsics/
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llvm/
include/
llvm/
IR/
47 lines
lib/
Target/
RISCV/
2 lines
49 lines
20 lines
96 lines
test/
CodeGen/
RISCV/
rvv/
6 lines
6 lines
4 lines
120 lines
74 lines
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77 lines
77 lines
212 lines
268 lines
74 lines
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Diff 402776

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 589 Lines • ▼ Show 20 Lines class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
let HasMask = false; let HasMask = false;
} }
} }
let HasNoMaskedOverloaded = false, let HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED)); Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
IntrinsicTypes = {ResultType, Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[3]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
Show All 17 Lines let Name = NAME # "_v",
IRNameMask = "vleff_mask", IRNameMask = "vleff_mask",
HasNoMaskedOverloaded = false, HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
IntrinsicTypes = {ResultType, Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
Value *NewVL = Ops[1]; Value *NewVL = Ops[1];
Ops.erase(Ops.begin() + 1); Ops.erase(Ops.begin() + 1);
Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0}); llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
// Store new_vl. // Store new_vl.
clang::CharUnits Align = clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType()); CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {1}), Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {1}),
Address(NewVL, Align)); Address(NewVL, Align));
Show All 33 Lines
multiclass RVVVLSEBuiltin<list<string> types> { multiclass RVVVLSEBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vlse", IRName = "vlse",
IRNameMask ="vlse_mask", IRNameMask ="vlse_mask",
HasNoMaskedOverloaded = false, HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED)); Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
IntrinsicTypes = {ResultType, Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "vPCet", type>; def : RVVBuiltin<"v", "vPCet", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUet", type>; def : RVVBuiltin<"Uv", "UvPCUet", type>;
} }
} }
} }
} }
multiclass RVVIndexedLoad<string op> { multiclass RVVIndexedLoad<string op> {
let ManualCodegen = [{ let ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED)); Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
▲ Show 20 Lines • Show All 1,457 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) { vint8mf8_t test_vloxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) { vint8mf4_t test_vloxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) { vint8mf2_t test_vloxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) { vint8m1_t test_vloxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) { vint8m2_t test_vloxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vloxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) { vint8m4_t test_vloxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vloxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) { vint8m8_t test_vloxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) { vint8mf8_t test_vloxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) { vint8mf4_t test_vloxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) { vint8mf2_t test_vloxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) { vint8m1_t test_vloxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) { vint8m2_t test_vloxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vloxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) { vint8m4_t test_vloxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) { vint8mf8_t test_vloxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) { vint8mf4_t test_vloxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) { vint8mf2_t test_vloxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) { vint8m1_t test_vloxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) { vint8m2_t test_vloxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) { vint8mf8_t test_vloxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) { vint8mf4_t test_vloxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) { vint8mf2_t test_vloxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) { vint16mf4_t test_vloxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) { vint16mf2_t test_vloxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) { vint16m1_t test_vloxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) { vint16m2_t test_vloxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) { vint16m4_t test_vloxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vloxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) { vint16m8_t test_vloxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) { vint16mf4_t test_vloxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) { vint16mf2_t test_vloxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) { vint16m1_t test_vloxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) { vint16m2_t test_vloxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) { vint16m4_t test_vloxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vloxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) { vint16m8_t test_vloxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) { vint16mf4_t test_vloxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) { vint16mf2_t test_vloxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) { vint16m1_t test_vloxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) { vint16m2_t test_vloxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) { vint16m4_t test_vloxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) { vint16mf4_t test_vloxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) { vint16mf2_t test_vloxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) { vint16m1_t test_vloxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) { vint16m2_t test_vloxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) { vint32mf2_t test_vloxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) { vint32m1_t test_vloxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) { vint32m2_t test_vloxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) { vint32m4_t test_vloxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) { vint32m8_t test_vloxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) { vint32mf2_t test_vloxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) { vint32m1_t test_vloxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) { vint32m2_t test_vloxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) { vint32m4_t test_vloxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) { vint32m8_t test_vloxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) { vint32mf2_t test_vloxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { vint32m1_t test_vloxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) { vint32m2_t test_vloxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) { vint32m4_t test_vloxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) { vint32m8_t test_vloxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) { vint32mf2_t test_vloxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) { vint32m1_t test_vloxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) { vint32m2_t test_vloxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) { vint32m4_t test_vloxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) { vint64m1_t test_vloxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) { vint64m2_t test_vloxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) { vint64m4_t test_vloxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) { vint64m8_t test_vloxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) { vint64m1_t test_vloxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) { vint64m2_t test_vloxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) { vint64m4_t test_vloxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) { vint64m8_t test_vloxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) { vint64m1_t test_vloxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) { vint64m2_t test_vloxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) { vint64m4_t test_vloxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) { vint64m8_t test_vloxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) { vint64m1_t test_vloxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) { vint64m2_t test_vloxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) { vint64m4_t test_vloxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) { vint64m8_t test_vloxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) { vuint8mf8_t test_vloxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) { vuint8mf4_t test_vloxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) { vuint8mf2_t test_vloxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) { vuint8m1_t test_vloxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) { vuint8m2_t test_vloxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vloxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) { vuint8m4_t test_vloxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vloxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) { vuint8m8_t test_vloxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) { vuint8mf8_t test_vloxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) { vuint8mf4_t test_vloxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) { vuint8mf2_t test_vloxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) { vuint8m1_t test_vloxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) { vuint8m2_t test_vloxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vloxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) { vuint8m4_t test_vloxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) { vuint8mf8_t test_vloxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) { vuint8mf4_t test_vloxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) { vuint8mf2_t test_vloxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) { vuint8m1_t test_vloxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) { vuint8m2_t test_vloxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) { vuint8mf8_t test_vloxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) { vuint8mf4_t test_vloxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) { vuint8mf2_t test_vloxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) { vuint8m1_t test_vloxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) { vuint16mf4_t test_vloxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) { vuint16mf2_t test_vloxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) { vuint16m1_t test_vloxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) { vuint16m2_t test_vloxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) { vuint16m4_t test_vloxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vloxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) { vuint16m8_t test_vloxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) { vuint16mf4_t test_vloxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) { vuint16mf2_t test_vloxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) { vuint16m1_t test_vloxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) { vuint16m2_t test_vloxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) { vuint16m4_t test_vloxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vloxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) { vuint16m8_t test_vloxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) { vuint16mf4_t test_vloxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) { vuint16mf2_t test_vloxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) { vuint16m1_t test_vloxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) { vuint16m2_t test_vloxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) { vuint16m4_t test_vloxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) { vuint16mf4_t test_vloxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) { vuint16mf2_t test_vloxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) { vuint16m1_t test_vloxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) {
// //
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) { vuint16m2_t test_vloxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) { vuint32mf2_t test_vloxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) { vuint32m1_t test_vloxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) { vuint32m2_t test_vloxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) { vuint32m4_t test_vloxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) { vuint32m8_t test_vloxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) { vuint32mf2_t test_vloxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) { vuint32m1_t test_vloxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) { vuint32m2_t test_vloxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) { vuint32m4_t test_vloxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) { vuint32m8_t test_vloxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) { vuint32mf2_t test_vloxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) { vuint32m1_t test_vloxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) { vuint32m2_t test_vloxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) { vuint32m4_t test_vloxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) { vuint32m8_t test_vloxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) { vuint32mf2_t test_vloxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) { vuint32m1_t test_vloxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) { vuint32m2_t test_vloxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) { vuint32m4_t test_vloxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) { vuint64m1_t test_vloxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) { vuint64m2_t test_vloxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) { vuint64m4_t test_vloxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) { vuint64m8_t test_vloxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) { vuint64m1_t test_vloxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) { vuint64m2_t test_vloxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) { vuint64m4_t test_vloxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) { vuint64m8_t test_vloxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) { vuint64m1_t test_vloxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) { vuint64m2_t test_vloxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) { vuint64m4_t test_vloxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) { vuint64m8_t test_vloxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) { vuint64m1_t test_vloxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) { vuint64m2_t test_vloxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) { vuint64m4_t test_vloxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) { vuint64m8_t test_vloxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) { vfloat32mf2_t test_vloxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) { vfloat32m1_t test_vloxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) { vfloat32m2_t test_vloxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) { vfloat32m4_t test_vloxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) { vfloat32m8_t test_vloxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) { vfloat32mf2_t test_vloxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) { vfloat32m1_t test_vloxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) { vfloat32m2_t test_vloxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) { vfloat32m4_t test_vloxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) { vfloat32m8_t test_vloxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) { vfloat32mf2_t test_vloxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) { vfloat32m1_t test_vloxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) { vfloat32m2_t test_vloxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) { vfloat32m4_t test_vloxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) { vfloat32m8_t test_vloxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) { vfloat32mf2_t test_vloxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) { vfloat32m1_t test_vloxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) { vfloat32m2_t test_vloxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) { vfloat32m4_t test_vloxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) { vfloat64m1_t test_vloxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) { vfloat64m2_t test_vloxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) { vfloat64m4_t test_vloxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) { vfloat64m8_t test_vloxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) {
return vloxei8(base, bindex, vl); return vloxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) { vfloat64m1_t test_vloxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) { vfloat64m2_t test_vloxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) { vfloat64m4_t test_vloxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) { vfloat64m8_t test_vloxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) {
return vloxei16(base, bindex, vl); return vloxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) { vfloat64m1_t test_vloxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) { vfloat64m2_t test_vloxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) { vfloat64m4_t test_vloxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) { vfloat64m8_t test_vloxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) {
return vloxei32(base, bindex, vl); return vloxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) { vfloat64m1_t test_vloxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) { vfloat64m2_t test_vloxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) { vfloat64m4_t test_vloxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vloxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) {
return vloxei64(base, bindex, vl); return vloxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) { vint8mf8_t test_vluxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) { vint8mf4_t test_vluxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) { vint8mf2_t test_vluxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) { vint8m1_t test_vluxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) { vint8m2_t test_vluxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vluxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) { vint8m4_t test_vluxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vluxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) { vint8m8_t test_vluxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) { vint8mf8_t test_vluxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) { vint8mf4_t test_vluxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) { vint8mf2_t test_vluxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) { vint8m1_t test_vluxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) { vint8m2_t test_vluxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vluxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) { vint8m4_t test_vluxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) { vint8mf8_t test_vluxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) { vint8mf4_t test_vluxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) { vint8mf2_t test_vluxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) { vint8m1_t test_vluxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) { vint8m2_t test_vluxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) { vint8mf8_t test_vluxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) { vint8mf4_t test_vluxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) { vint8mf2_t test_vluxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { vint8m1_t test_vluxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) { vint16mf4_t test_vluxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) { vint16mf2_t test_vluxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) { vint16m1_t test_vluxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) { vint16m2_t test_vluxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) { vint16m4_t test_vluxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vluxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) { vint16m8_t test_vluxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) { vint16mf4_t test_vluxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) { vint16mf2_t test_vluxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) { vint16m1_t test_vluxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) { vint16m2_t test_vluxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) { vint16m4_t test_vluxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vluxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) { vint16m8_t test_vluxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) { vint16mf4_t test_vluxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) { vint16mf2_t test_vluxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) { vint16m1_t test_vluxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) { vint16m2_t test_vluxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) { vint16m4_t test_vluxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) { vint16mf4_t test_vluxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) { vint16mf2_t test_vluxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) { vint16m1_t test_vluxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) { vint16m2_t test_vluxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) { vint32mf2_t test_vluxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) { vint32m1_t test_vluxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) { vint32m2_t test_vluxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) { vint32m4_t test_vluxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) { vint32m8_t test_vluxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) { vint32mf2_t test_vluxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) { vint32m1_t test_vluxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) { vint32m2_t test_vluxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) { vint32m4_t test_vluxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) { vint32m8_t test_vluxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) { vint32mf2_t test_vluxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { vint32m1_t test_vluxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) { vint32m2_t test_vluxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) { vint32m4_t test_vluxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) { vint32m8_t test_vluxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) { vint32mf2_t test_vluxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) { vint32m1_t test_vluxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) { vint32m2_t test_vluxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) { vint32m4_t test_vluxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) { vint64m1_t test_vluxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) { vint64m2_t test_vluxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) { vint64m4_t test_vluxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) { vint64m8_t test_vluxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) { vint64m1_t test_vluxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) { vint64m2_t test_vluxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) { vint64m4_t test_vluxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) { vint64m8_t test_vluxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) { vint64m1_t test_vluxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) { vint64m2_t test_vluxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) { vint64m4_t test_vluxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) { vint64m8_t test_vluxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) { vint64m1_t test_vluxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) { vint64m2_t test_vluxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) { vint64m4_t test_vluxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) { vint64m8_t test_vluxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) { vuint8mf8_t test_vluxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) { vuint8mf4_t test_vluxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) { vuint8mf2_t test_vluxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) { vuint8m1_t test_vluxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) { vuint8m2_t test_vluxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vluxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) { vuint8m4_t test_vluxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vluxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) { vuint8m8_t test_vluxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) { vuint8mf8_t test_vluxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) { vuint8mf4_t test_vluxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) { vuint8mf2_t test_vluxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) { vuint8m1_t test_vluxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) { vuint8m2_t test_vluxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vluxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) { vuint8m4_t test_vluxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) { vuint8mf8_t test_vluxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) { vuint8mf4_t test_vluxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) { vuint8mf2_t test_vluxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) { vuint8m1_t test_vluxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) { vuint8m2_t test_vluxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) { vuint8mf8_t test_vluxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) { vuint8mf4_t test_vluxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) { vuint8mf2_t test_vluxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) { vuint8m1_t test_vluxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) { vuint16mf4_t test_vluxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) { vuint16mf2_t test_vluxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) { vuint16m1_t test_vluxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) { vuint16m2_t test_vluxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) { vuint16m4_t test_vluxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vluxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) { vuint16m8_t test_vluxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) { vuint16mf4_t test_vluxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) { vuint16mf2_t test_vluxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) { vuint16m1_t test_vluxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) { vuint16m2_t test_vluxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) { vuint16m4_t test_vluxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vluxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) { vuint16m8_t test_vluxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) { vuint16mf4_t test_vluxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) { vuint16mf2_t test_vluxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) { vuint16m1_t test_vluxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) { vuint16m2_t test_vluxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) { vuint16m4_t test_vluxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) { vuint16mf4_t test_vluxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) { vuint16mf2_t test_vluxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) { vuint16m1_t test_vluxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) { vuint16m2_t test_vluxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) { vuint32mf2_t test_vluxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) { vuint32m1_t test_vluxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) { vuint32m2_t test_vluxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) { vuint32m4_t test_vluxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) { vuint32m8_t test_vluxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) { vuint32mf2_t test_vluxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) { vuint32m1_t test_vluxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) { vuint32m2_t test_vluxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) { vuint32m4_t test_vluxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) { vuint32m8_t test_vluxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) { vuint32mf2_t test_vluxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) { vuint32m1_t test_vluxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) { vuint32m2_t test_vluxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) { vuint32m4_t test_vluxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) { vuint32m8_t test_vluxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) { vuint32mf2_t test_vluxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) { vuint32m1_t test_vluxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) { vuint32m2_t test_vluxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) { vuint32m4_t test_vluxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) { vuint64m1_t test_vluxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) { vuint64m2_t test_vluxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) { vuint64m4_t test_vluxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) { vuint64m8_t test_vluxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) { vuint64m1_t test_vluxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) { vuint64m2_t test_vluxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) { vuint64m4_t test_vluxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) { vuint64m8_t test_vluxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) { vuint64m1_t test_vluxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) { vuint64m2_t test_vluxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) { vuint64m4_t test_vluxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) { vuint64m8_t test_vluxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) { vuint64m1_t test_vluxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) { vuint64m2_t test_vluxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) { vuint64m4_t test_vluxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) { vuint64m8_t test_vluxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) { vfloat32mf2_t test_vluxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) { vfloat32m1_t test_vluxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) { vfloat32m2_t test_vluxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) { vfloat32m4_t test_vluxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) { vfloat32m8_t test_vluxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) { vfloat32mf2_t test_vluxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) { vfloat32m1_t test_vluxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) { vfloat32m2_t test_vluxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) { vfloat32m4_t test_vluxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) { vfloat32m8_t test_vluxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) { vfloat32mf2_t test_vluxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) { vfloat32m1_t test_vluxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) { vfloat32m2_t test_vluxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) { vfloat32m4_t test_vluxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) { vfloat32m8_t test_vluxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) { vfloat32mf2_t test_vluxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) { vfloat32m1_t test_vluxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) { vfloat32m2_t test_vluxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) { vfloat32m4_t test_vluxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) { vfloat64m1_t test_vluxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) { vfloat64m2_t test_vluxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) { vfloat64m4_t test_vluxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) { vfloat64m8_t test_vluxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) {
return vluxei8(base, bindex, vl); return vluxei8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) { vfloat64m1_t test_vluxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) { vfloat64m2_t test_vluxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) { vfloat64m4_t test_vluxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) { vfloat64m8_t test_vluxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) {
return vluxei16(base, bindex, vl); return vluxei16(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) { vfloat64m1_t test_vluxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) { vfloat64m2_t test_vluxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) { vfloat64m4_t test_vluxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) { vfloat64m8_t test_vluxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) {
return vluxei32(base, bindex, vl); return vluxei32(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) { vfloat64m1_t test_vluxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) { vfloat64m2_t test_vluxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) { vfloat64m4_t test_vluxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vluxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(base, bindex, vl); return vluxei64(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vle8_v_i8mf8( // CHECK-RV64-LABEL: @test_vle8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vle8_v_i8mf8(const int8_t *base, size_t vl) { vint8mf8_t test_vle8_v_i8mf8(const int8_t *base, size_t vl) {
return vle8_v_i8mf8(base, vl); return vle8_v_i8mf8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8mf4( // CHECK-RV64-LABEL: @test_vle8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vle8_v_i8mf4(const int8_t *base, size_t vl) { vint8mf4_t test_vle8_v_i8mf4(const int8_t *base, size_t vl) {
return vle8_v_i8mf4(base, vl); return vle8_v_i8mf4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8mf2( // CHECK-RV64-LABEL: @test_vle8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vle8_v_i8mf2(const int8_t *base, size_t vl) { vint8mf2_t test_vle8_v_i8mf2(const int8_t *base, size_t vl) {
return vle8_v_i8mf2(base, vl); return vle8_v_i8mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8m1( // CHECK-RV64-LABEL: @test_vle8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vle8_v_i8m1(const int8_t *base, size_t vl) { vint8m1_t test_vle8_v_i8m1(const int8_t *base, size_t vl) {
return vle8_v_i8m1(base, vl); return vle8_v_i8m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8m2( // CHECK-RV64-LABEL: @test_vle8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vle8_v_i8m2(const int8_t *base, size_t vl) { vint8m2_t test_vle8_v_i8m2(const int8_t *base, size_t vl) {
return vle8_v_i8m2(base, vl); return vle8_v_i8m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8m4( // CHECK-RV64-LABEL: @test_vle8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vle8_v_i8m4(const int8_t *base, size_t vl) { vint8m4_t test_vle8_v_i8m4(const int8_t *base, size_t vl) {
return vle8_v_i8m4(base, vl); return vle8_v_i8m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8m8( // CHECK-RV64-LABEL: @test_vle8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vle8_v_i8m8(const int8_t *base, size_t vl) { vint8m8_t test_vle8_v_i8m8(const int8_t *base, size_t vl) {
return vle8_v_i8m8(base, vl); return vle8_v_i8m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16mf4( // CHECK-RV64-LABEL: @test_vle16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vle16_v_i16mf4(const int16_t *base, size_t vl) { vint16mf4_t test_vle16_v_i16mf4(const int16_t *base, size_t vl) {
return vle16_v_i16mf4(base, vl); return vle16_v_i16mf4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16mf2( // CHECK-RV64-LABEL: @test_vle16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vle16_v_i16mf2(const int16_t *base, size_t vl) { vint16mf2_t test_vle16_v_i16mf2(const int16_t *base, size_t vl) {
return vle16_v_i16mf2(base, vl); return vle16_v_i16mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16m1( // CHECK-RV64-LABEL: @test_vle16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vle16_v_i16m1(const int16_t *base, size_t vl) { vint16m1_t test_vle16_v_i16m1(const int16_t *base, size_t vl) {
return vle16_v_i16m1(base, vl); return vle16_v_i16m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16m2( // CHECK-RV64-LABEL: @test_vle16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vle16_v_i16m2(const int16_t *base, size_t vl) { vint16m2_t test_vle16_v_i16m2(const int16_t *base, size_t vl) {
return vle16_v_i16m2(base, vl); return vle16_v_i16m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16m4( // CHECK-RV64-LABEL: @test_vle16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vle16_v_i16m4(const int16_t *base, size_t vl) { vint16m4_t test_vle16_v_i16m4(const int16_t *base, size_t vl) {
return vle16_v_i16m4(base, vl); return vle16_v_i16m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_i16m8( // CHECK-RV64-LABEL: @test_vle16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vle16_v_i16m8(const int16_t *base, size_t vl) { vint16m8_t test_vle16_v_i16m8(const int16_t *base, size_t vl) {
return vle16_v_i16m8(base, vl); return vle16_v_i16m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_i32mf2( // CHECK-RV64-LABEL: @test_vle32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vle32_v_i32mf2(const int32_t *base, size_t vl) { vint32mf2_t test_vle32_v_i32mf2(const int32_t *base, size_t vl) {
return vle32_v_i32mf2(base, vl); return vle32_v_i32mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_i32m1( // CHECK-RV64-LABEL: @test_vle32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vle32_v_i32m1(const int32_t *base, size_t vl) { vint32m1_t test_vle32_v_i32m1(const int32_t *base, size_t vl) {
return vle32_v_i32m1(base, vl); return vle32_v_i32m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_i32m2( // CHECK-RV64-LABEL: @test_vle32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vle32_v_i32m2(const int32_t *base, size_t vl) { vint32m2_t test_vle32_v_i32m2(const int32_t *base, size_t vl) {
return vle32_v_i32m2(base, vl); return vle32_v_i32m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_i32m4( // CHECK-RV64-LABEL: @test_vle32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vle32_v_i32m4(const int32_t *base, size_t vl) { vint32m4_t test_vle32_v_i32m4(const int32_t *base, size_t vl) {
return vle32_v_i32m4(base, vl); return vle32_v_i32m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_i32m8( // CHECK-RV64-LABEL: @test_vle32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vle32_v_i32m8(const int32_t *base, size_t vl) { vint32m8_t test_vle32_v_i32m8(const int32_t *base, size_t vl) {
return vle32_v_i32m8(base, vl); return vle32_v_i32m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_i64m1( // CHECK-RV64-LABEL: @test_vle64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vle64_v_i64m1(const int64_t *base, size_t vl) { vint64m1_t test_vle64_v_i64m1(const int64_t *base, size_t vl) {
return vle64_v_i64m1(base, vl); return vle64_v_i64m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_i64m2( // CHECK-RV64-LABEL: @test_vle64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vle64_v_i64m2(const int64_t *base, size_t vl) { vint64m2_t test_vle64_v_i64m2(const int64_t *base, size_t vl) {
return vle64_v_i64m2(base, vl); return vle64_v_i64m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_i64m4( // CHECK-RV64-LABEL: @test_vle64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vle64_v_i64m4(const int64_t *base, size_t vl) { vint64m4_t test_vle64_v_i64m4(const int64_t *base, size_t vl) {
return vle64_v_i64m4(base, vl); return vle64_v_i64m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_i64m8( // CHECK-RV64-LABEL: @test_vle64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vle64_v_i64m8(const int64_t *base, size_t vl) { vint64m8_t test_vle64_v_i64m8(const int64_t *base, size_t vl) {
return vle64_v_i64m8(base, vl); return vle64_v_i64m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8mf8( // CHECK-RV64-LABEL: @test_vle8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vle8_v_u8mf8(const uint8_t *base, size_t vl) { vuint8mf8_t test_vle8_v_u8mf8(const uint8_t *base, size_t vl) {
return vle8_v_u8mf8(base, vl); return vle8_v_u8mf8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8mf4( // CHECK-RV64-LABEL: @test_vle8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vle8_v_u8mf4(const uint8_t *base, size_t vl) { vuint8mf4_t test_vle8_v_u8mf4(const uint8_t *base, size_t vl) {
return vle8_v_u8mf4(base, vl); return vle8_v_u8mf4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8mf2( // CHECK-RV64-LABEL: @test_vle8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vle8_v_u8mf2(const uint8_t *base, size_t vl) { vuint8mf2_t test_vle8_v_u8mf2(const uint8_t *base, size_t vl) {
return vle8_v_u8mf2(base, vl); return vle8_v_u8mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8m1( // CHECK-RV64-LABEL: @test_vle8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vle8_v_u8m1(const uint8_t *base, size_t vl) { vuint8m1_t test_vle8_v_u8m1(const uint8_t *base, size_t vl) {
return vle8_v_u8m1(base, vl); return vle8_v_u8m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8m2( // CHECK-RV64-LABEL: @test_vle8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vle8_v_u8m2(const uint8_t *base, size_t vl) { vuint8m2_t test_vle8_v_u8m2(const uint8_t *base, size_t vl) {
return vle8_v_u8m2(base, vl); return vle8_v_u8m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8m4( // CHECK-RV64-LABEL: @test_vle8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vle8_v_u8m4(const uint8_t *base, size_t vl) { vuint8m4_t test_vle8_v_u8m4(const uint8_t *base, size_t vl) {
return vle8_v_u8m4(base, vl); return vle8_v_u8m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_u8m8( // CHECK-RV64-LABEL: @test_vle8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vle8_v_u8m8(const uint8_t *base, size_t vl) { vuint8m8_t test_vle8_v_u8m8(const uint8_t *base, size_t vl) {
return vle8_v_u8m8(base, vl); return vle8_v_u8m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16mf4( // CHECK-RV64-LABEL: @test_vle16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vle16_v_u16mf4(const uint16_t *base, size_t vl) { vuint16mf4_t test_vle16_v_u16mf4(const uint16_t *base, size_t vl) {
return vle16_v_u16mf4(base, vl); return vle16_v_u16mf4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16mf2( // CHECK-RV64-LABEL: @test_vle16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vle16_v_u16mf2(const uint16_t *base, size_t vl) { vuint16mf2_t test_vle16_v_u16mf2(const uint16_t *base, size_t vl) {
return vle16_v_u16mf2(base, vl); return vle16_v_u16mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16m1( // CHECK-RV64-LABEL: @test_vle16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vle16_v_u16m1(const uint16_t *base, size_t vl) { vuint16m1_t test_vle16_v_u16m1(const uint16_t *base, size_t vl) {
return vle16_v_u16m1(base, vl); return vle16_v_u16m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16m2( // CHECK-RV64-LABEL: @test_vle16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vle16_v_u16m2(const uint16_t *base, size_t vl) { vuint16m2_t test_vle16_v_u16m2(const uint16_t *base, size_t vl) {
return vle16_v_u16m2(base, vl); return vle16_v_u16m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16m4( // CHECK-RV64-LABEL: @test_vle16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vle16_v_u16m4(const uint16_t *base, size_t vl) { vuint16m4_t test_vle16_v_u16m4(const uint16_t *base, size_t vl) {
return vle16_v_u16m4(base, vl); return vle16_v_u16m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_u16m8( // CHECK-RV64-LABEL: @test_vle16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vle16_v_u16m8(const uint16_t *base, size_t vl) { vuint16m8_t test_vle16_v_u16m8(const uint16_t *base, size_t vl) {
return vle16_v_u16m8(base, vl); return vle16_v_u16m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_u32mf2( // CHECK-RV64-LABEL: @test_vle32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vle32_v_u32mf2(const uint32_t *base, size_t vl) { vuint32mf2_t test_vle32_v_u32mf2(const uint32_t *base, size_t vl) {
return vle32_v_u32mf2(base, vl); return vle32_v_u32mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_u32m1( // CHECK-RV64-LABEL: @test_vle32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vle32_v_u32m1(const uint32_t *base, size_t vl) { vuint32m1_t test_vle32_v_u32m1(const uint32_t *base, size_t vl) {
return vle32_v_u32m1(base, vl); return vle32_v_u32m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_u32m2( // CHECK-RV64-LABEL: @test_vle32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vle32_v_u32m2(const uint32_t *base, size_t vl) { vuint32m2_t test_vle32_v_u32m2(const uint32_t *base, size_t vl) {
return vle32_v_u32m2(base, vl); return vle32_v_u32m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_u32m4( // CHECK-RV64-LABEL: @test_vle32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vle32_v_u32m4(const uint32_t *base, size_t vl) { vuint32m4_t test_vle32_v_u32m4(const uint32_t *base, size_t vl) {
return vle32_v_u32m4(base, vl); return vle32_v_u32m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_u32m8( // CHECK-RV64-LABEL: @test_vle32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vle32_v_u32m8(const uint32_t *base, size_t vl) { vuint32m8_t test_vle32_v_u32m8(const uint32_t *base, size_t vl) {
return vle32_v_u32m8(base, vl); return vle32_v_u32m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_u64m1( // CHECK-RV64-LABEL: @test_vle64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vle64_v_u64m1(const uint64_t *base, size_t vl) { vuint64m1_t test_vle64_v_u64m1(const uint64_t *base, size_t vl) {
return vle64_v_u64m1(base, vl); return vle64_v_u64m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_u64m2( // CHECK-RV64-LABEL: @test_vle64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vle64_v_u64m2(const uint64_t *base, size_t vl) { vuint64m2_t test_vle64_v_u64m2(const uint64_t *base, size_t vl) {
return vle64_v_u64m2(base, vl); return vle64_v_u64m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_u64m4( // CHECK-RV64-LABEL: @test_vle64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vle64_v_u64m4(const uint64_t *base, size_t vl) { vuint64m4_t test_vle64_v_u64m4(const uint64_t *base, size_t vl) {
return vle64_v_u64m4(base, vl); return vle64_v_u64m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_u64m8( // CHECK-RV64-LABEL: @test_vle64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vle64_v_u64m8(const uint64_t *base, size_t vl) { vuint64m8_t test_vle64_v_u64m8(const uint64_t *base, size_t vl) {
return vle64_v_u64m8(base, vl); return vle64_v_u64m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_f32mf2( // CHECK-RV64-LABEL: @test_vle32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.i64(<vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vle32_v_f32mf2(const float *base, size_t vl) { vfloat32mf2_t test_vle32_v_f32mf2(const float *base, size_t vl) {
return vle32_v_f32mf2(base, vl); return vle32_v_f32mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_f32m1( // CHECK-RV64-LABEL: @test_vle32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.i64(<vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vle32_v_f32m1(const float *base, size_t vl) { vfloat32m1_t test_vle32_v_f32m1(const float *base, size_t vl) {
return vle32_v_f32m1(base, vl); return vle32_v_f32m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_f32m2( // CHECK-RV64-LABEL: @test_vle32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.i64(<vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vle32_v_f32m2(const float *base, size_t vl) { vfloat32m2_t test_vle32_v_f32m2(const float *base, size_t vl) {
return vle32_v_f32m2(base, vl); return vle32_v_f32m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_f32m4( // CHECK-RV64-LABEL: @test_vle32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.i64(<vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vle32_v_f32m4(const float *base, size_t vl) { vfloat32m4_t test_vle32_v_f32m4(const float *base, size_t vl) {
return vle32_v_f32m4(base, vl); return vle32_v_f32m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle32_v_f32m8( // CHECK-RV64-LABEL: @test_vle32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vle32_v_f32m8(const float *base, size_t vl) { vfloat32m8_t test_vle32_v_f32m8(const float *base, size_t vl) {
return vle32_v_f32m8(base, vl); return vle32_v_f32m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_f64m1( // CHECK-RV64-LABEL: @test_vle64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.i64(<vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vle64_v_f64m1(const double *base, size_t vl) { vfloat64m1_t test_vle64_v_f64m1(const double *base, size_t vl) {
return vle64_v_f64m1(base, vl); return vle64_v_f64m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_f64m2( // CHECK-RV64-LABEL: @test_vle64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.i64(<vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vle64_v_f64m2(const double *base, size_t vl) { vfloat64m2_t test_vle64_v_f64m2(const double *base, size_t vl) {
return vle64_v_f64m2(base, vl); return vle64_v_f64m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_f64m4( // CHECK-RV64-LABEL: @test_vle64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.i64(<vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vle64_v_f64m4(const double *base, size_t vl) { vfloat64m4_t test_vle64_v_f64m4(const double *base, size_t vl) {
return vle64_v_f64m4(base, vl); return vle64_v_f64m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle64_v_f64m8( // CHECK-RV64-LABEL: @test_vle64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.i64(<vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vle64_v_f64m8(const double *base, size_t vl) { vfloat64m8_t test_vle64_v_f64m8(const double *base, size_t vl) {
return vle64_v_f64m8(base, vl); return vle64_v_f64m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vle8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vle64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) { vfloat64m8_t test_vle64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) {
return vle64_v_f64m8_m(mask, maskedoff, base, vl); return vle64_v_f64m8_m(mask, maskedoff, base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16mf4( // CHECK-RV64-LABEL: @test_vle16_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.i64(<vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vle16_v_f16mf4(const _Float16 *base, size_t vl) { vfloat16mf4_t test_vle16_v_f16mf4(const _Float16 *base, size_t vl) {
return vle16_v_f16mf4(base, vl); return vle16_v_f16mf4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16mf2( // CHECK-RV64-LABEL: @test_vle16_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.i64(<vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vle16_v_f16mf2(const _Float16 *base, size_t vl) { vfloat16mf2_t test_vle16_v_f16mf2(const _Float16 *base, size_t vl) {
return vle16_v_f16mf2(base, vl); return vle16_v_f16mf2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16m1( // CHECK-RV64-LABEL: @test_vle16_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.i64(<vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) { vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
return vle16_v_f16m1(base, vl); return vle16_v_f16m1(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16m2( // CHECK-RV64-LABEL: @test_vle16_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.i64(<vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vle16_v_f16m2(const _Float16 *base, size_t vl) { vfloat16m2_t test_vle16_v_f16m2(const _Float16 *base, size_t vl) {
return vle16_v_f16m2(base, vl); return vle16_v_f16m2(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16m4( // CHECK-RV64-LABEL: @test_vle16_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vle16_v_f16m4(const _Float16 *base, size_t vl) { vfloat16m4_t test_vle16_v_f16m4(const _Float16 *base, size_t vl) {
return vle16_v_f16m4(base, vl); return vle16_v_f16m4(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16m8( // CHECK-RV64-LABEL: @test_vle16_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vle16_v_f16m8(const _Float16 *base, size_t vl) { vfloat16m8_t test_vle16_v_f16m8(const _Float16 *base, size_t vl) {
return vle16_v_f16m8(base, vl); return vle16_v_f16m8(base, vl);
} }
// CHECK-RV64-LABEL: @test_vle16_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vle16_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8( // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
// //
vint8mf8_t test_vle8ff_v_i8mf8 (const int8_t *base, size_t *new_vl, size_t vl) { vint8mf8_t test_vle8ff_v_i8mf8 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf8(base, new_vl, vl); return vle8ff_v_i8mf8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8mf4( // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
// //
vint8mf4_t test_vle8ff_v_i8mf4 (const int8_t *base, size_t *new_vl, size_t vl) { vint8mf4_t test_vle8ff_v_i8mf4 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf4(base, new_vl, vl); return vle8ff_v_i8mf4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8mf2( // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
// //
vint8mf2_t test_vle8ff_v_i8mf2 (const int8_t *base, size_t *new_vl, size_t vl) { vint8mf2_t test_vle8ff_v_i8mf2 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf2(base, new_vl, vl); return vle8ff_v_i8mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8m1( // CHECK-RV64-LABEL: @test_vle8ff_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
// //
vint8m1_t test_vle8ff_v_i8m1 (const int8_t *base, size_t *new_vl, size_t vl) { vint8m1_t test_vle8ff_v_i8m1 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m1(base, new_vl, vl); return vle8ff_v_i8m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8m2( // CHECK-RV64-LABEL: @test_vle8ff_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
// //
vint8m2_t test_vle8ff_v_i8m2 (const int8_t *base, size_t *new_vl, size_t vl) { vint8m2_t test_vle8ff_v_i8m2 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m2(base, new_vl, vl); return vle8ff_v_i8m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8m4( // CHECK-RV64-LABEL: @test_vle8ff_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
// //
vint8m4_t test_vle8ff_v_i8m4 (const int8_t *base, size_t *new_vl, size_t vl) { vint8m4_t test_vle8ff_v_i8m4 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m4(base, new_vl, vl); return vle8ff_v_i8m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_i8m8( // CHECK-RV64-LABEL: @test_vle8ff_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
// //
vint8m8_t test_vle8ff_v_i8m8 (const int8_t *base, size_t *new_vl, size_t vl) { vint8m8_t test_vle8ff_v_i8m8 (const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m8(base, new_vl, vl); return vle8ff_v_i8m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8mf8( // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
// //
vuint8mf8_t test_vle8ff_v_u8mf8 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8mf8_t test_vle8ff_v_u8mf8 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf8(base, new_vl, vl); return vle8ff_v_u8mf8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8mf4( // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
// //
vuint8mf4_t test_vle8ff_v_u8mf4 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8mf4_t test_vle8ff_v_u8mf4 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf4(base, new_vl, vl); return vle8ff_v_u8mf4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8mf2( // CHECK-RV64-LABEL: @test_vle8ff_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
// //
vuint8mf2_t test_vle8ff_v_u8mf2 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8mf2_t test_vle8ff_v_u8mf2 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf2(base, new_vl, vl); return vle8ff_v_u8mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8m1( // CHECK-RV64-LABEL: @test_vle8ff_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
// //
vuint8m1_t test_vle8ff_v_u8m1 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8m1_t test_vle8ff_v_u8m1 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m1(base, new_vl, vl); return vle8ff_v_u8m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8m2( // CHECK-RV64-LABEL: @test_vle8ff_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
// //
vuint8m2_t test_vle8ff_v_u8m2 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8m2_t test_vle8ff_v_u8m2 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m2(base, new_vl, vl); return vle8ff_v_u8m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8m4( // CHECK-RV64-LABEL: @test_vle8ff_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
// //
vuint8m4_t test_vle8ff_v_u8m4 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8m4_t test_vle8ff_v_u8m4 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m4(base, new_vl, vl); return vle8ff_v_u8m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle8ff_v_u8m8( // CHECK-RV64-LABEL: @test_vle8ff_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
// //
vuint8m8_t test_vle8ff_v_u8m8 (const uint8_t *base, size_t *new_vl, size_t vl) { vuint8m8_t test_vle8ff_v_u8m8 (const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m8(base, new_vl, vl); return vle8ff_v_u8m8(base, new_vl, vl);
} }
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
// //
vuint8m8_t test_vle8ff_v_u8m8_m (vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { vuint8m8_t test_vle8ff_v_u8m8_m (vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m8_m(mask, maskedoff, base, new_vl, vl); return vle8ff_v_u8m8_m(mask, maskedoff, base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16mf4( // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
// //
vint16mf4_t test_vle16ff_v_i16mf4 (const int16_t *base, size_t *new_vl, size_t vl) { vint16mf4_t test_vle16ff_v_i16mf4 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf4(base, new_vl, vl); return vle16ff_v_i16mf4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16mf2( // CHECK-RV64-LABEL: @test_vle16ff_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
// //
vint16mf2_t test_vle16ff_v_i16mf2 (const int16_t *base, size_t *new_vl, size_t vl) { vint16mf2_t test_vle16ff_v_i16mf2 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf2(base, new_vl, vl); return vle16ff_v_i16mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16m1( // CHECK-RV64-LABEL: @test_vle16ff_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
// //
vint16m1_t test_vle16ff_v_i16m1 (const int16_t *base, size_t *new_vl, size_t vl) { vint16m1_t test_vle16ff_v_i16m1 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m1(base, new_vl, vl); return vle16ff_v_i16m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16m2( // CHECK-RV64-LABEL: @test_vle16ff_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
// //
vint16m2_t test_vle16ff_v_i16m2 (const int16_t *base, size_t *new_vl, size_t vl) { vint16m2_t test_vle16ff_v_i16m2 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m2(base, new_vl, vl); return vle16ff_v_i16m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16m4( // CHECK-RV64-LABEL: @test_vle16ff_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
// //
vint16m4_t test_vle16ff_v_i16m4 (const int16_t *base, size_t *new_vl, size_t vl) { vint16m4_t test_vle16ff_v_i16m4 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m4(base, new_vl, vl); return vle16ff_v_i16m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_i16m8( // CHECK-RV64-LABEL: @test_vle16ff_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
// //
vint16m8_t test_vle16ff_v_i16m8 (const int16_t *base, size_t *new_vl, size_t vl) { vint16m8_t test_vle16ff_v_i16m8 (const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m8(base, new_vl, vl); return vle16ff_v_i16m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16mf4( // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
// //
vuint16mf4_t test_vle16ff_v_u16mf4 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16mf4_t test_vle16ff_v_u16mf4 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf4(base, new_vl, vl); return vle16ff_v_u16mf4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16mf2( // CHECK-RV64-LABEL: @test_vle16ff_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
// //
vuint16mf2_t test_vle16ff_v_u16mf2 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16mf2_t test_vle16ff_v_u16mf2 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf2(base, new_vl, vl); return vle16ff_v_u16mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16m1( // CHECK-RV64-LABEL: @test_vle16ff_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
// //
vuint16m1_t test_vle16ff_v_u16m1 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16m1_t test_vle16ff_v_u16m1 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m1(base, new_vl, vl); return vle16ff_v_u16m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16m2( // CHECK-RV64-LABEL: @test_vle16ff_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
// //
vuint16m2_t test_vle16ff_v_u16m2 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16m2_t test_vle16ff_v_u16m2 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m2(base, new_vl, vl); return vle16ff_v_u16m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16m4( // CHECK-RV64-LABEL: @test_vle16ff_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
// //
vuint16m4_t test_vle16ff_v_u16m4 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16m4_t test_vle16ff_v_u16m4 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m4(base, new_vl, vl); return vle16ff_v_u16m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_u16m8( // CHECK-RV64-LABEL: @test_vle16ff_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
// //
vuint16m8_t test_vle16ff_v_u16m8 (const uint16_t *base, size_t *new_vl, size_t vl) { vuint16m8_t test_vle16ff_v_u16m8 (const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m8(base, new_vl, vl); return vle16ff_v_u16m8(base, new_vl, vl);
} }
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
// //
vuint16m8_t test_vle16ff_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { vuint16m8_t test_vle16ff_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m8_m(mask, maskedoff, base, new_vl, vl); return vle16ff_v_u16m8_m(mask, maskedoff, base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2( // CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
// //
vint32mf2_t test_vle32ff_v_i32mf2 (const int32_t *base, size_t *new_vl, size_t vl) { vint32mf2_t test_vle32ff_v_i32mf2 (const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32mf2(base, new_vl, vl); return vle32ff_v_i32mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_i32m1( // CHECK-RV64-LABEL: @test_vle32ff_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
// //
vint32m1_t test_vle32ff_v_i32m1 (const int32_t *base, size_t *new_vl, size_t vl) { vint32m1_t test_vle32ff_v_i32m1 (const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m1(base, new_vl, vl); return vle32ff_v_i32m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_i32m2( // CHECK-RV64-LABEL: @test_vle32ff_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
// //
vint32m2_t test_vle32ff_v_i32m2 (const int32_t *base, size_t *new_vl, size_t vl) { vint32m2_t test_vle32ff_v_i32m2 (const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m2(base, new_vl, vl); return vle32ff_v_i32m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_i32m4( // CHECK-RV64-LABEL: @test_vle32ff_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
// //
vint32m4_t test_vle32ff_v_i32m4 (const int32_t *base, size_t *new_vl, size_t vl) { vint32m4_t test_vle32ff_v_i32m4 (const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m4(base, new_vl, vl); return vle32ff_v_i32m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_i32m8( // CHECK-RV64-LABEL: @test_vle32ff_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
// //
vint32m8_t test_vle32ff_v_i32m8 (const int32_t *base, size_t *new_vl, size_t vl) { vint32m8_t test_vle32ff_v_i32m8 (const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m8(base, new_vl, vl); return vle32ff_v_i32m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2( // CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
// //
vuint32mf2_t test_vle32ff_v_u32mf2 (const uint32_t *base, size_t *new_vl, size_t vl) { vuint32mf2_t test_vle32ff_v_u32mf2 (const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32mf2(base, new_vl, vl); return vle32ff_v_u32mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_u32m1( // CHECK-RV64-LABEL: @test_vle32ff_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
// //
vuint32m1_t test_vle32ff_v_u32m1 (const uint32_t *base, size_t *new_vl, size_t vl) { vuint32m1_t test_vle32ff_v_u32m1 (const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m1(base, new_vl, vl); return vle32ff_v_u32m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_u32m2( // CHECK-RV64-LABEL: @test_vle32ff_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
// //
vuint32m2_t test_vle32ff_v_u32m2 (const uint32_t *base, size_t *new_vl, size_t vl) { vuint32m2_t test_vle32ff_v_u32m2 (const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m2(base, new_vl, vl); return vle32ff_v_u32m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_u32m4( // CHECK-RV64-LABEL: @test_vle32ff_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
// //
vuint32m4_t test_vle32ff_v_u32m4 (const uint32_t *base, size_t *new_vl, size_t vl) { vuint32m4_t test_vle32ff_v_u32m4 (const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m4(base, new_vl, vl); return vle32ff_v_u32m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_u32m8( // CHECK-RV64-LABEL: @test_vle32ff_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
// //
vuint32m8_t test_vle32ff_v_u32m8 (const uint32_t *base, size_t *new_vl, size_t vl) { vuint32m8_t test_vle32ff_v_u32m8 (const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m8(base, new_vl, vl); return vle32ff_v_u32m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2( // CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64(<vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
// //
vfloat32mf2_t test_vle32ff_v_f32mf2 (const float *base, size_t *new_vl, size_t vl) { vfloat32mf2_t test_vle32ff_v_f32mf2 (const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32mf2(base, new_vl, vl); return vle32ff_v_f32mf2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_f32m1( // CHECK-RV64-LABEL: @test_vle32ff_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64(<vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP2]]
// //
vfloat32m1_t test_vle32ff_v_f32m1 (const float *base, size_t *new_vl, size_t vl) { vfloat32m1_t test_vle32ff_v_f32m1 (const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m1(base, new_vl, vl); return vle32ff_v_f32m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_f32m2( // CHECK-RV64-LABEL: @test_vle32ff_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64(<vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP2]]
// //
vfloat32m2_t test_vle32ff_v_f32m2 (const float *base, size_t *new_vl, size_t vl) { vfloat32m2_t test_vle32ff_v_f32m2 (const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m2(base, new_vl, vl); return vle32ff_v_f32m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_f32m4( // CHECK-RV64-LABEL: @test_vle32ff_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64(<vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP2]]
// //
vfloat32m4_t test_vle32ff_v_f32m4 (const float *base, size_t *new_vl, size_t vl) { vfloat32m4_t test_vle32ff_v_f32m4 (const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m4(base, new_vl, vl); return vle32ff_v_f32m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle32ff_v_f32m8( // CHECK-RV64-LABEL: @test_vle32ff_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64(<vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP2]]
// //
vfloat32m8_t test_vle32ff_v_f32m8 (const float *base, size_t *new_vl, size_t vl) { vfloat32m8_t test_vle32ff_v_f32m8 (const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m8(base, new_vl, vl); return vle32ff_v_f32m8(base, new_vl, vl);
} }
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
// //
vfloat32m8_t test_vle32ff_v_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) { vfloat32m8_t test_vle32ff_v_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m8_m(mask, maskedoff, base, new_vl, vl); return vle32ff_v_f32m8_m(mask, maskedoff, base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_i64m1( // CHECK-RV64-LABEL: @test_vle64ff_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
// //
vint64m1_t test_vle64ff_v_i64m1 (const int64_t *base, size_t *new_vl, size_t vl) { vint64m1_t test_vle64ff_v_i64m1 (const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m1(base, new_vl, vl); return vle64ff_v_i64m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_i64m2( // CHECK-RV64-LABEL: @test_vle64ff_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
// //
vint64m2_t test_vle64ff_v_i64m2 (const int64_t *base, size_t *new_vl, size_t vl) { vint64m2_t test_vle64ff_v_i64m2 (const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m2(base, new_vl, vl); return vle64ff_v_i64m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_i64m4( // CHECK-RV64-LABEL: @test_vle64ff_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
// //
vint64m4_t test_vle64ff_v_i64m4 (const int64_t *base, size_t *new_vl, size_t vl) { vint64m4_t test_vle64ff_v_i64m4 (const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m4(base, new_vl, vl); return vle64ff_v_i64m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_i64m8( // CHECK-RV64-LABEL: @test_vle64ff_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
// //
vint64m8_t test_vle64ff_v_i64m8 (const int64_t *base, size_t *new_vl, size_t vl) { vint64m8_t test_vle64ff_v_i64m8 (const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m8(base, new_vl, vl); return vle64ff_v_i64m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_u64m1( // CHECK-RV64-LABEL: @test_vle64ff_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
// //
vuint64m1_t test_vle64ff_v_u64m1 (const uint64_t *base, size_t *new_vl, size_t vl) { vuint64m1_t test_vle64ff_v_u64m1 (const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m1(base, new_vl, vl); return vle64ff_v_u64m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_u64m2( // CHECK-RV64-LABEL: @test_vle64ff_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
// //
vuint64m2_t test_vle64ff_v_u64m2 (const uint64_t *base, size_t *new_vl, size_t vl) { vuint64m2_t test_vle64ff_v_u64m2 (const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m2(base, new_vl, vl); return vle64ff_v_u64m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_u64m4( // CHECK-RV64-LABEL: @test_vle64ff_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
// //
vuint64m4_t test_vle64ff_v_u64m4 (const uint64_t *base, size_t *new_vl, size_t vl) { vuint64m4_t test_vle64ff_v_u64m4 (const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m4(base, new_vl, vl); return vle64ff_v_u64m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_u64m8( // CHECK-RV64-LABEL: @test_vle64ff_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
// //
vuint64m8_t test_vle64ff_v_u64m8 (const uint64_t *base, size_t *new_vl, size_t vl) { vuint64m8_t test_vle64ff_v_u64m8 (const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m8(base, new_vl, vl); return vle64ff_v_u64m8(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_f64m1( // CHECK-RV64-LABEL: @test_vle64ff_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64(<vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP2]]
// //
vfloat64m1_t test_vle64ff_v_f64m1 (const double *base, size_t *new_vl, size_t vl) { vfloat64m1_t test_vle64ff_v_f64m1 (const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m1(base, new_vl, vl); return vle64ff_v_f64m1(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_f64m2( // CHECK-RV64-LABEL: @test_vle64ff_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64(<vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP2]]
// //
vfloat64m2_t test_vle64ff_v_f64m2 (const double *base, size_t *new_vl, size_t vl) { vfloat64m2_t test_vle64ff_v_f64m2 (const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m2(base, new_vl, vl); return vle64ff_v_f64m2(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_f64m4( // CHECK-RV64-LABEL: @test_vle64ff_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64(<vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP2]]
// //
vfloat64m4_t test_vle64ff_v_f64m4 (const double *base, size_t *new_vl, size_t vl) { vfloat64m4_t test_vle64ff_v_f64m4 (const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m4(base, new_vl, vl); return vle64ff_v_f64m4(base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle64ff_v_f64m8( // CHECK-RV64-LABEL: @test_vle64ff_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64(<vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP2]]
// //
vfloat64m8_t test_vle64ff_v_f64m8 (const double *base, size_t *new_vl, size_t vl) { vfloat64m8_t test_vle64ff_v_f64m8 (const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m8(base, new_vl, vl); return vle64ff_v_f64m8(base, new_vl, vl);
} }
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// //
vfloat64m8_t test_vle64ff_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) { vfloat64m8_t test_vle64ff_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m8_m(mask, maskedoff, base, new_vl, vl); return vle64ff_v_f64m8_m(mask, maskedoff, base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16mf4( // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64(<vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP2]]
// //
vfloat16mf4_t test_vle16ff_v_f16mf4 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16mf4_t test_vle16ff_v_f16mf4 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16mf4 (base, new_vl, vl); return vle16ff_v_f16mf4 (base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2( // CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64(<vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP2]]
// //
vfloat16mf2_t test_vle16ff_v_f16mf2 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16mf2_t test_vle16ff_v_f16mf2 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16mf2 (base, new_vl, vl); return vle16ff_v_f16mf2 (base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m1( // CHECK-RV64-LABEL: @test_vle16ff_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64(<vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP2]]
// //
vfloat16m1_t test_vle16ff_v_f16m1 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16m1_t test_vle16ff_v_f16m1 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16m1 (base, new_vl, vl); return vle16ff_v_f16m1 (base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m2( // CHECK-RV64-LABEL: @test_vle16ff_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64(<vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP2]]
// //
vfloat16m2_t test_vle16ff_v_f16m2 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16m2_t test_vle16ff_v_f16m2 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16m2 (base, new_vl, vl); return vle16ff_v_f16m2 (base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m4( // CHECK-RV64-LABEL: @test_vle16ff_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64(<vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP2]]
// //
vfloat16m4_t test_vle16ff_v_f16m4 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16m4_t test_vle16ff_v_f16m4 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16m4 (base, new_vl, vl); return vle16ff_v_f16m4 (base, new_vl, vl);
} }
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m8( // CHECK-RV64-LABEL: @test_vle16ff_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64(<vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 0 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 0
// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1 // CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP1]], 1
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8 // CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP2]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP2]]
// //
vfloat16m8_t test_vle16ff_v_f16m8 (const _Float16 *base, size_t *new_vl, size_t vl) { vfloat16m8_t test_vle16ff_v_f16m8 (const _Float16 *base, size_t *new_vl, size_t vl) {
return vle16ff_v_f16m8 (base, new_vl, vl); return vle16ff_v_f16m8 (base, new_vl, vl);
} }
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) { vint8mf8_t test_vloxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_i8mf8(base, bindex, vl); return vloxei8_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) { vint8mf4_t test_vloxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_i8mf4(base, bindex, vl); return vloxei8_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) { vint8mf2_t test_vloxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_i8mf2(base, bindex, vl); return vloxei8_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) { vint8m1_t test_vloxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_i8m1(base, bindex, vl); return vloxei8_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) { vint8m2_t test_vloxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_i8m2(base, bindex, vl); return vloxei8_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vloxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) { vint8m4_t test_vloxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8_v_i8m4(base, bindex, vl); return vloxei8_v_i8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vloxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) { vint8m8_t test_vloxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) {
return vloxei8_v_i8m8(base, bindex, vl); return vloxei8_v_i8m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) { vint8mf8_t test_vloxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_i8mf8(base, bindex, vl); return vloxei16_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) { vint8mf4_t test_vloxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_i8mf4(base, bindex, vl); return vloxei16_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) { vint8mf2_t test_vloxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_i8mf2(base, bindex, vl); return vloxei16_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) { vint8m1_t test_vloxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_i8m1(base, bindex, vl); return vloxei16_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) { vint8m2_t test_vloxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_i8m2(base, bindex, vl); return vloxei16_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i8m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vloxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) { vint8m4_t test_vloxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16_v_i8m4(base, bindex, vl); return vloxei16_v_i8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) { vint8mf8_t test_vloxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_i8mf8(base, bindex, vl); return vloxei32_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) { vint8mf4_t test_vloxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_i8mf4(base, bindex, vl); return vloxei32_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) { vint8mf2_t test_vloxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_i8mf2(base, bindex, vl); return vloxei32_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) { vint8m1_t test_vloxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_i8m1(base, bindex, vl); return vloxei32_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i8m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vloxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) { vint8m2_t test_vloxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_i8m2(base, bindex, vl); return vloxei32_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf8( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vloxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) { vint8mf8_t test_vloxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_i8mf8(base, bindex, vl); return vloxei64_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vloxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) { vint8mf4_t test_vloxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_i8mf4(base, bindex, vl); return vloxei64_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vloxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) { vint8mf2_t test_vloxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_i8mf2(base, bindex, vl); return vloxei64_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i8m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_i8m1(base, bindex, vl); return vloxei64_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) { vint16mf4_t test_vloxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_i16mf4(base, bindex, vl); return vloxei8_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) { vint16mf2_t test_vloxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_i16mf2(base, bindex, vl); return vloxei8_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) { vint16m1_t test_vloxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_i16m1(base, bindex, vl); return vloxei8_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) { vint16m2_t test_vloxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_i16m2(base, bindex, vl); return vloxei8_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) { vint16m4_t test_vloxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_i16m4(base, bindex, vl); return vloxei8_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i16m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vloxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) { vint16m8_t test_vloxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8_v_i16m8(base, bindex, vl); return vloxei8_v_i16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) { vint16mf4_t test_vloxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_i16mf4(base, bindex, vl); return vloxei16_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) { vint16mf2_t test_vloxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_i16mf2(base, bindex, vl); return vloxei16_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) { vint16m1_t test_vloxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_i16m1(base, bindex, vl); return vloxei16_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) { vint16m2_t test_vloxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_i16m2(base, bindex, vl); return vloxei16_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) { vint16m4_t test_vloxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_i16m4(base, bindex, vl); return vloxei16_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i16m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vloxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) { vint16m8_t test_vloxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16_v_i16m8(base, bindex, vl); return vloxei16_v_i16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) { vint16mf4_t test_vloxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_i16mf4(base, bindex, vl); return vloxei32_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) { vint16mf2_t test_vloxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_i16mf2(base, bindex, vl); return vloxei32_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) { vint16m1_t test_vloxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_i16m1(base, bindex, vl); return vloxei32_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) { vint16m2_t test_vloxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_i16m2(base, bindex, vl); return vloxei32_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i16m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vloxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) { vint16m4_t test_vloxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_i16m4(base, bindex, vl); return vloxei32_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vloxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) { vint16mf4_t test_vloxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_i16mf4(base, bindex, vl); return vloxei64_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vloxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) { vint16mf2_t test_vloxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_i16mf2(base, bindex, vl); return vloxei64_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vloxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) { vint16m1_t test_vloxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_i16m1(base, bindex, vl); return vloxei64_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i16m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vloxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) { vint16m2_t test_vloxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_i16m2(base, bindex, vl); return vloxei64_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) { vint32mf2_t test_vloxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_i32mf2(base, bindex, vl); return vloxei8_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) { vint32m1_t test_vloxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_i32m1(base, bindex, vl); return vloxei8_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) { vint32m2_t test_vloxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_i32m2(base, bindex, vl); return vloxei8_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) { vint32m4_t test_vloxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_i32m4(base, bindex, vl); return vloxei8_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) { vint32m8_t test_vloxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_i32m8(base, bindex, vl); return vloxei8_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) { vint32mf2_t test_vloxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_i32mf2(base, bindex, vl); return vloxei16_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) { vint32m1_t test_vloxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_i32m1(base, bindex, vl); return vloxei16_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) { vint32m2_t test_vloxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_i32m2(base, bindex, vl); return vloxei16_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) { vint32m4_t test_vloxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_i32m4(base, bindex, vl); return vloxei16_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) { vint32m8_t test_vloxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_i32m8(base, bindex, vl); return vloxei16_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) { vint32mf2_t test_vloxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_i32mf2(base, bindex, vl); return vloxei32_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { vint32m1_t test_vloxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_i32m1(base, bindex, vl); return vloxei32_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) { vint32m2_t test_vloxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_i32m2(base, bindex, vl); return vloxei32_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) { vint32m4_t test_vloxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_i32m4(base, bindex, vl); return vloxei32_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vloxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) { vint32m8_t test_vloxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_i32m8(base, bindex, vl); return vloxei32_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vloxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) { vint32mf2_t test_vloxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_i32mf2(base, bindex, vl); return vloxei64_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vloxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) { vint32m1_t test_vloxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_i32m1(base, bindex, vl); return vloxei64_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vloxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) { vint32m2_t test_vloxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_i32m2(base, bindex, vl); return vloxei64_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vloxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) { vint32m4_t test_vloxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_i32m4(base, bindex, vl); return vloxei64_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) { vint64m1_t test_vloxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_i64m1(base, bindex, vl); return vloxei8_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) { vint64m2_t test_vloxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_i64m2(base, bindex, vl); return vloxei8_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) { vint64m4_t test_vloxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_i64m4(base, bindex, vl); return vloxei8_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) { vint64m8_t test_vloxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_i64m8(base, bindex, vl); return vloxei8_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) { vint64m1_t test_vloxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_i64m1(base, bindex, vl); return vloxei16_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) { vint64m2_t test_vloxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_i64m2(base, bindex, vl); return vloxei16_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) { vint64m4_t test_vloxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_i64m4(base, bindex, vl); return vloxei16_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) { vint64m8_t test_vloxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_i64m8(base, bindex, vl); return vloxei16_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) { vint64m1_t test_vloxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_i64m1(base, bindex, vl); return vloxei32_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) { vint64m2_t test_vloxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_i64m2(base, bindex, vl); return vloxei32_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) { vint64m4_t test_vloxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_i64m4(base, bindex, vl); return vloxei32_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) { vint64m8_t test_vloxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_i64m8(base, bindex, vl); return vloxei32_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vloxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) { vint64m1_t test_vloxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_i64m1(base, bindex, vl); return vloxei64_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vloxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) { vint64m2_t test_vloxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_i64m2(base, bindex, vl); return vloxei64_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vloxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) { vint64m4_t test_vloxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_i64m4(base, bindex, vl); return vloxei64_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_i64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vloxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) { vint64m8_t test_vloxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_i64m8(base, bindex, vl); return vloxei64_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) { vuint8mf8_t test_vloxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_u8mf8(base, bindex, vl); return vloxei8_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) { vuint8mf4_t test_vloxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_u8mf4(base, bindex, vl); return vloxei8_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) { vuint8mf2_t test_vloxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_u8mf2(base, bindex, vl); return vloxei8_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) { vuint8m1_t test_vloxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_u8m1(base, bindex, vl); return vloxei8_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) { vuint8m2_t test_vloxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_u8m2(base, bindex, vl); return vloxei8_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vloxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) { vuint8m4_t test_vloxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8_v_u8m4(base, bindex, vl); return vloxei8_v_u8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u8m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vloxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) { vuint8m8_t test_vloxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) {
return vloxei8_v_u8m8(base, bindex, vl); return vloxei8_v_u8m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) { vuint8mf8_t test_vloxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_u8mf8(base, bindex, vl); return vloxei16_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) { vuint8mf4_t test_vloxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_u8mf4(base, bindex, vl); return vloxei16_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) { vuint8mf2_t test_vloxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_u8mf2(base, bindex, vl); return vloxei16_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) { vuint8m1_t test_vloxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_u8m1(base, bindex, vl); return vloxei16_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) { vuint8m2_t test_vloxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_u8m2(base, bindex, vl); return vloxei16_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u8m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vloxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) { vuint8m4_t test_vloxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16_v_u8m4(base, bindex, vl); return vloxei16_v_u8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) { vuint8mf8_t test_vloxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_u8mf8(base, bindex, vl); return vloxei32_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) { vuint8mf4_t test_vloxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_u8mf4(base, bindex, vl); return vloxei32_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) { vuint8mf2_t test_vloxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_u8mf2(base, bindex, vl); return vloxei32_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) { vuint8m1_t test_vloxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_u8m1(base, bindex, vl); return vloxei32_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u8m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vloxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) { vuint8m2_t test_vloxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_u8m2(base, bindex, vl); return vloxei32_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf8( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vloxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) { vuint8mf8_t test_vloxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_u8mf8(base, bindex, vl); return vloxei64_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vloxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) { vuint8mf4_t test_vloxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_u8mf4(base, bindex, vl); return vloxei64_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vloxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) { vuint8mf2_t test_vloxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_u8mf2(base, bindex, vl); return vloxei64_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u8m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vloxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) { vuint8m1_t test_vloxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_u8m1(base, bindex, vl); return vloxei64_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) { vuint16mf4_t test_vloxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_u16mf4(base, bindex, vl); return vloxei8_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) { vuint16mf2_t test_vloxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_u16mf2(base, bindex, vl); return vloxei8_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) { vuint16m1_t test_vloxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_u16m1(base, bindex, vl); return vloxei8_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) { vuint16m2_t test_vloxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_u16m2(base, bindex, vl); return vloxei8_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) { vuint16m4_t test_vloxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_u16m4(base, bindex, vl); return vloxei8_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u16m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vloxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) { vuint16m8_t test_vloxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) {
return vloxei8_v_u16m8(base, bindex, vl); return vloxei8_v_u16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) { vuint16mf4_t test_vloxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_u16mf4(base, bindex, vl); return vloxei16_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) { vuint16mf2_t test_vloxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_u16mf2(base, bindex, vl); return vloxei16_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) { vuint16m1_t test_vloxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_u16m1(base, bindex, vl); return vloxei16_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) { vuint16m2_t test_vloxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_u16m2(base, bindex, vl); return vloxei16_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) { vuint16m4_t test_vloxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_u16m4(base, bindex, vl); return vloxei16_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u16m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vloxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) { vuint16m8_t test_vloxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) {
return vloxei16_v_u16m8(base, bindex, vl); return vloxei16_v_u16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) { vuint16mf4_t test_vloxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_u16mf4(base, bindex, vl); return vloxei32_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) { vuint16mf2_t test_vloxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_u16mf2(base, bindex, vl); return vloxei32_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) { vuint16m1_t test_vloxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_u16m1(base, bindex, vl); return vloxei32_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) { vuint16m2_t test_vloxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_u16m2(base, bindex, vl); return vloxei32_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u16m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vloxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) { vuint16m4_t test_vloxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_u16m4(base, bindex, vl); return vloxei32_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vloxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) { vuint16mf4_t test_vloxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_u16mf4(base, bindex, vl); return vloxei64_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vloxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) { vuint16mf2_t test_vloxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_u16mf2(base, bindex, vl); return vloxei64_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vloxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) { vuint16m1_t test_vloxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_u16m1(base, bindex, vl); return vloxei64_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u16m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vloxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) { vuint16m2_t test_vloxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_u16m2(base, bindex, vl); return vloxei64_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) { vuint32mf2_t test_vloxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_u32mf2(base, bindex, vl); return vloxei8_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) { vuint32m1_t test_vloxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_u32m1(base, bindex, vl); return vloxei8_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) { vuint32m2_t test_vloxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_u32m2(base, bindex, vl); return vloxei8_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) { vuint32m4_t test_vloxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_u32m4(base, bindex, vl); return vloxei8_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) { vuint32m8_t test_vloxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_u32m8(base, bindex, vl); return vloxei8_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) { vuint32mf2_t test_vloxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_u32mf2(base, bindex, vl); return vloxei16_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) { vuint32m1_t test_vloxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_u32m1(base, bindex, vl); return vloxei16_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) { vuint32m2_t test_vloxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_u32m2(base, bindex, vl); return vloxei16_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) { vuint32m4_t test_vloxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_u32m4(base, bindex, vl); return vloxei16_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) { vuint32m8_t test_vloxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_u32m8(base, bindex, vl); return vloxei16_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) { vuint32mf2_t test_vloxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_u32mf2(base, bindex, vl); return vloxei32_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) { vuint32m1_t test_vloxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_u32m1(base, bindex, vl); return vloxei32_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) { vuint32m2_t test_vloxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_u32m2(base, bindex, vl); return vloxei32_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) { vuint32m4_t test_vloxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_u32m4(base, bindex, vl); return vloxei32_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vloxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) { vuint32m8_t test_vloxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_u32m8(base, bindex, vl); return vloxei32_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vloxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) { vuint32mf2_t test_vloxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_u32mf2(base, bindex, vl); return vloxei64_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vloxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) { vuint32m1_t test_vloxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_u32m1(base, bindex, vl); return vloxei64_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vloxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) { vuint32m2_t test_vloxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_u32m2(base, bindex, vl); return vloxei64_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vloxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) { vuint32m4_t test_vloxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_u32m4(base, bindex, vl); return vloxei64_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) { vuint64m1_t test_vloxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_u64m1(base, bindex, vl); return vloxei8_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) { vuint64m2_t test_vloxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_u64m2(base, bindex, vl); return vloxei8_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) { vuint64m4_t test_vloxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_u64m4(base, bindex, vl); return vloxei8_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) { vuint64m8_t test_vloxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_u64m8(base, bindex, vl); return vloxei8_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) { vuint64m1_t test_vloxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_u64m1(base, bindex, vl); return vloxei16_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) { vuint64m2_t test_vloxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_u64m2(base, bindex, vl); return vloxei16_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) { vuint64m4_t test_vloxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_u64m4(base, bindex, vl); return vloxei16_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) { vuint64m8_t test_vloxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_u64m8(base, bindex, vl); return vloxei16_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) { vuint64m1_t test_vloxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_u64m1(base, bindex, vl); return vloxei32_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) { vuint64m2_t test_vloxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_u64m2(base, bindex, vl); return vloxei32_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) { vuint64m4_t test_vloxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_u64m4(base, bindex, vl); return vloxei32_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) { vuint64m8_t test_vloxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_u64m8(base, bindex, vl); return vloxei32_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vloxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) { vuint64m1_t test_vloxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_u64m1(base, bindex, vl); return vloxei64_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vloxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) { vuint64m2_t test_vloxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_u64m2(base, bindex, vl); return vloxei64_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vloxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) { vuint64m4_t test_vloxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_u64m4(base, bindex, vl); return vloxei64_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_u64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vloxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) { vuint64m8_t test_vloxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_u64m8(base, bindex, vl); return vloxei64_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) { vfloat32mf2_t test_vloxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_f32mf2(base, bindex, vl); return vloxei8_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) { vfloat32m1_t test_vloxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_f32m1(base, bindex, vl); return vloxei8_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) { vfloat32m2_t test_vloxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_f32m2(base, bindex, vl); return vloxei8_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) { vfloat32m4_t test_vloxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_f32m4(base, bindex, vl); return vloxei8_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei8_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) { vfloat32m8_t test_vloxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_f32m8(base, bindex, vl); return vloxei8_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) { vfloat32mf2_t test_vloxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_f32mf2(base, bindex, vl); return vloxei16_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) { vfloat32m1_t test_vloxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_f32m1(base, bindex, vl); return vloxei16_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) { vfloat32m2_t test_vloxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_f32m2(base, bindex, vl); return vloxei16_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) { vfloat32m4_t test_vloxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_f32m4(base, bindex, vl); return vloxei16_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei16_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) { vfloat32m8_t test_vloxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_f32m8(base, bindex, vl); return vloxei16_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) { vfloat32mf2_t test_vloxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_f32mf2(base, bindex, vl); return vloxei32_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) { vfloat32m1_t test_vloxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_f32m1(base, bindex, vl); return vloxei32_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) { vfloat32m2_t test_vloxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_f32m2(base, bindex, vl); return vloxei32_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) { vfloat32m4_t test_vloxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_f32m4(base, bindex, vl); return vloxei32_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f32m8( // CHECK-RV64-LABEL: @test_vloxei32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vloxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) { vfloat32m8_t test_vloxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_f32m8(base, bindex, vl); return vloxei32_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vloxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) { vfloat32mf2_t test_vloxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_f32mf2(base, bindex, vl); return vloxei64_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m1( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vloxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) { vfloat32m1_t test_vloxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_f32m1(base, bindex, vl); return vloxei64_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m2( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vloxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) { vfloat32m2_t test_vloxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_f32m2(base, bindex, vl); return vloxei64_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f32m4( // CHECK-RV64-LABEL: @test_vloxei64_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vloxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) { vfloat32m4_t test_vloxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_f32m4(base, bindex, vl); return vloxei64_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) { vfloat64m1_t test_vloxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_f64m1(base, bindex, vl); return vloxei8_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) { vfloat64m2_t test_vloxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_f64m2(base, bindex, vl); return vloxei8_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) { vfloat64m4_t test_vloxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_f64m4(base, bindex, vl); return vloxei8_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei8_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) { vfloat64m8_t test_vloxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_f64m8(base, bindex, vl); return vloxei8_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) { vfloat64m1_t test_vloxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_f64m1(base, bindex, vl); return vloxei16_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) { vfloat64m2_t test_vloxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_f64m2(base, bindex, vl); return vloxei16_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) { vfloat64m4_t test_vloxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_f64m4(base, bindex, vl); return vloxei16_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei16_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) { vfloat64m8_t test_vloxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_f64m8(base, bindex, vl); return vloxei16_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) { vfloat64m1_t test_vloxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_f64m1(base, bindex, vl); return vloxei32_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) { vfloat64m2_t test_vloxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_f64m2(base, bindex, vl); return vloxei32_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) { vfloat64m4_t test_vloxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_f64m4(base, bindex, vl); return vloxei32_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei32_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) { vfloat64m8_t test_vloxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_f64m8(base, bindex, vl); return vloxei32_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m1( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vloxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) { vfloat64m1_t test_vloxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_f64m1(base, bindex, vl); return vloxei64_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m2( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vloxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) { vfloat64m2_t test_vloxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_f64m2(base, bindex, vl); return vloxei64_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m4( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vloxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) { vfloat64m4_t test_vloxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_f64m4(base, bindex, vl); return vloxei64_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f64m8( // CHECK-RV64-LABEL: @test_vloxei64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vloxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vloxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_f64m8(base, bindex, vl); return vloxei64_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 1,903 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vloxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vloxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_f64m8_m(mask, maskedoff, base, bindex, vl); return vloxei64_v_f64m8_m(mask, maskedoff, base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf4( // CHECK-RV64-LABEL: @test_vloxei8_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vloxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) { vfloat16mf4_t test_vloxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
return vloxei8_v_f16mf4 (base, bindex, vl); return vloxei8_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf2( // CHECK-RV64-LABEL: @test_vloxei8_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vloxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) { vfloat16mf2_t test_vloxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
return vloxei8_v_f16mf2 (base, bindex, vl); return vloxei8_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m1( // CHECK-RV64-LABEL: @test_vloxei8_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vloxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) { vfloat16m1_t test_vloxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
return vloxei8_v_f16m1 (base, bindex, vl); return vloxei8_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m2( // CHECK-RV64-LABEL: @test_vloxei8_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vloxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) { vfloat16m2_t test_vloxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) {
return vloxei8_v_f16m2 (base, bindex, vl); return vloxei8_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m4( // CHECK-RV64-LABEL: @test_vloxei8_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vloxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) { vfloat16m4_t test_vloxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) {
return vloxei8_v_f16m4 (base, bindex, vl); return vloxei8_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m8( // CHECK-RV64-LABEL: @test_vloxei8_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vloxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) { vfloat16m8_t test_vloxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) {
return vloxei8_v_f16m8 (base, bindex, vl); return vloxei8_v_f16m8 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf4( // CHECK-RV64-LABEL: @test_vloxei16_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vloxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) { vfloat16mf4_t test_vloxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
return vloxei16_v_f16mf4 (base, bindex, vl); return vloxei16_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf2( // CHECK-RV64-LABEL: @test_vloxei16_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vloxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) { vfloat16mf2_t test_vloxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
return vloxei16_v_f16mf2 (base, bindex, vl); return vloxei16_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m1( // CHECK-RV64-LABEL: @test_vloxei16_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vloxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) { vfloat16m1_t test_vloxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) {
return vloxei16_v_f16m1 (base, bindex, vl); return vloxei16_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m2( // CHECK-RV64-LABEL: @test_vloxei16_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vloxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) { vfloat16m2_t test_vloxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) {
return vloxei16_v_f16m2 (base, bindex, vl); return vloxei16_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m4( // CHECK-RV64-LABEL: @test_vloxei16_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vloxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) { vfloat16m4_t test_vloxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) {
return vloxei16_v_f16m4 (base, bindex, vl); return vloxei16_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m8( // CHECK-RV64-LABEL: @test_vloxei16_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vloxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) { vfloat16m8_t test_vloxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) {
return vloxei16_v_f16m8 (base, bindex, vl); return vloxei16_v_f16m8 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf4( // CHECK-RV64-LABEL: @test_vloxei32_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vloxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) { vfloat16mf4_t test_vloxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
return vloxei32_v_f16mf4 (base, bindex, vl); return vloxei32_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf2( // CHECK-RV64-LABEL: @test_vloxei32_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vloxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) { vfloat16mf2_t test_vloxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) {
return vloxei32_v_f16mf2 (base, bindex, vl); return vloxei32_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m1( // CHECK-RV64-LABEL: @test_vloxei32_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vloxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) { vfloat16m1_t test_vloxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) {
return vloxei32_v_f16m1 (base, bindex, vl); return vloxei32_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m2( // CHECK-RV64-LABEL: @test_vloxei32_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vloxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) { vfloat16m2_t test_vloxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) {
return vloxei32_v_f16m2 (base, bindex, vl); return vloxei32_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m4( // CHECK-RV64-LABEL: @test_vloxei32_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vloxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) { vfloat16m4_t test_vloxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) {
return vloxei32_v_f16m4 (base, bindex, vl); return vloxei32_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf4( // CHECK-RV64-LABEL: @test_vloxei64_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vloxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) { vfloat16mf4_t test_vloxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) {
return vloxei64_v_f16mf4 (base, bindex, vl); return vloxei64_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf2( // CHECK-RV64-LABEL: @test_vloxei64_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vloxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) { vfloat16mf2_t test_vloxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) {
return vloxei64_v_f16mf2 (base, bindex, vl); return vloxei64_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m1( // CHECK-RV64-LABEL: @test_vloxei64_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vloxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) { vfloat16m1_t test_vloxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) {
return vloxei64_v_f16m1 (base, bindex, vl); return vloxei64_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m2( // CHECK-RV64-LABEL: @test_vloxei64_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vloxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) { vfloat16m2_t test_vloxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) {
return vloxei64_v_f16m2 (base, bindex, vl); return vloxei64_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vloxei8_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8( // CHECK-RV64-LABEL: @test_vlse8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vlse8_v_i8mf8(const int8_t *base, ptrdiff_t bstride, vint8mf8_t test_vlse8_v_i8mf8(const int8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_i8mf8(base, bstride, vl); return vlse8_v_i8mf8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf4( // CHECK-RV64-LABEL: @test_vlse8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vlse8_v_i8mf4(const int8_t *base, ptrdiff_t bstride, vint8mf4_t test_vlse8_v_i8mf4(const int8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_i8mf4(base, bstride, vl); return vlse8_v_i8mf4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf2( // CHECK-RV64-LABEL: @test_vlse8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vlse8_v_i8mf2(const int8_t *base, ptrdiff_t bstride, vint8mf2_t test_vlse8_v_i8mf2(const int8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_i8mf2(base, bstride, vl); return vlse8_v_i8mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8m1( // CHECK-RV64-LABEL: @test_vlse8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vlse8_v_i8m1(const int8_t *base, ptrdiff_t bstride, size_t vl) { vint8m1_t test_vlse8_v_i8m1(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m1(base, bstride, vl); return vlse8_v_i8m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8m2( // CHECK-RV64-LABEL: @test_vlse8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vlse8_v_i8m2(const int8_t *base, ptrdiff_t bstride, size_t vl) { vint8m2_t test_vlse8_v_i8m2(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m2(base, bstride, vl); return vlse8_v_i8m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8m4( // CHECK-RV64-LABEL: @test_vlse8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vlse8_v_i8m4(const int8_t *base, ptrdiff_t bstride, size_t vl) { vint8m4_t test_vlse8_v_i8m4(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m4(base, bstride, vl); return vlse8_v_i8m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8m8( // CHECK-RV64-LABEL: @test_vlse8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vlse8_v_i8m8(const int8_t *base, ptrdiff_t bstride, size_t vl) { vint8m8_t test_vlse8_v_i8m8(const int8_t *base, ptrdiff_t bstride, size_t vl) {
return vlse8_v_i8m8(base, bstride, vl); return vlse8_v_i8m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf4( // CHECK-RV64-LABEL: @test_vlse16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vlse16_v_i16mf4(const int16_t *base, ptrdiff_t bstride, vint16mf4_t test_vlse16_v_i16mf4(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16mf4(base, bstride, vl); return vlse16_v_i16mf4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16mf2( // CHECK-RV64-LABEL: @test_vlse16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vlse16_v_i16mf2(const int16_t *base, ptrdiff_t bstride, vint16mf2_t test_vlse16_v_i16mf2(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16mf2(base, bstride, vl); return vlse16_v_i16mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16m1( // CHECK-RV64-LABEL: @test_vlse16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vlse16_v_i16m1(const int16_t *base, ptrdiff_t bstride, vint16m1_t test_vlse16_v_i16m1(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16m1(base, bstride, vl); return vlse16_v_i16m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16m2( // CHECK-RV64-LABEL: @test_vlse16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vlse16_v_i16m2(const int16_t *base, ptrdiff_t bstride, vint16m2_t test_vlse16_v_i16m2(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16m2(base, bstride, vl); return vlse16_v_i16m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16m4( // CHECK-RV64-LABEL: @test_vlse16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vlse16_v_i16m4(const int16_t *base, ptrdiff_t bstride, vint16m4_t test_vlse16_v_i16m4(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16m4(base, bstride, vl); return vlse16_v_i16m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_i16m8( // CHECK-RV64-LABEL: @test_vlse16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vlse16_v_i16m8(const int16_t *base, ptrdiff_t bstride, vint16m8_t test_vlse16_v_i16m8(const int16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_i16m8(base, bstride, vl); return vlse16_v_i16m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2( // CHECK-RV64-LABEL: @test_vlse32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vlse32_v_i32mf2(const int32_t *base, ptrdiff_t bstride, vint32mf2_t test_vlse32_v_i32mf2(const int32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_i32mf2(base, bstride, vl); return vlse32_v_i32mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_i32m1( // CHECK-RV64-LABEL: @test_vlse32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vlse32_v_i32m1(const int32_t *base, ptrdiff_t bstride, vint32m1_t test_vlse32_v_i32m1(const int32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_i32m1(base, bstride, vl); return vlse32_v_i32m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_i32m2( // CHECK-RV64-LABEL: @test_vlse32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vlse32_v_i32m2(const int32_t *base, ptrdiff_t bstride, vint32m2_t test_vlse32_v_i32m2(const int32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_i32m2(base, bstride, vl); return vlse32_v_i32m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_i32m4( // CHECK-RV64-LABEL: @test_vlse32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vlse32_v_i32m4(const int32_t *base, ptrdiff_t bstride, vint32m4_t test_vlse32_v_i32m4(const int32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_i32m4(base, bstride, vl); return vlse32_v_i32m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_i32m8( // CHECK-RV64-LABEL: @test_vlse32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vlse32_v_i32m8(const int32_t *base, ptrdiff_t bstride, vint32m8_t test_vlse32_v_i32m8(const int32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_i32m8(base, bstride, vl); return vlse32_v_i32m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_i64m1( // CHECK-RV64-LABEL: @test_vlse64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vlse64_v_i64m1(const int64_t *base, ptrdiff_t bstride, vint64m1_t test_vlse64_v_i64m1(const int64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_i64m1(base, bstride, vl); return vlse64_v_i64m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_i64m2( // CHECK-RV64-LABEL: @test_vlse64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vlse64_v_i64m2(const int64_t *base, ptrdiff_t bstride, vint64m2_t test_vlse64_v_i64m2(const int64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_i64m2(base, bstride, vl); return vlse64_v_i64m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_i64m4( // CHECK-RV64-LABEL: @test_vlse64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vlse64_v_i64m4(const int64_t *base, ptrdiff_t bstride, vint64m4_t test_vlse64_v_i64m4(const int64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_i64m4(base, bstride, vl); return vlse64_v_i64m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_i64m8( // CHECK-RV64-LABEL: @test_vlse64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vlse64_v_i64m8(const int64_t *base, ptrdiff_t bstride, vint64m8_t test_vlse64_v_i64m8(const int64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_i64m8(base, bstride, vl); return vlse64_v_i64m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf8( // CHECK-RV64-LABEL: @test_vlse8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vlse8_v_u8mf8(const uint8_t *base, ptrdiff_t bstride, vuint8mf8_t test_vlse8_v_u8mf8(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8mf8(base, bstride, vl); return vlse8_v_u8mf8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf4( // CHECK-RV64-LABEL: @test_vlse8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vlse8_v_u8mf4(const uint8_t *base, ptrdiff_t bstride, vuint8mf4_t test_vlse8_v_u8mf4(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8mf4(base, bstride, vl); return vlse8_v_u8mf4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8mf2( // CHECK-RV64-LABEL: @test_vlse8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vlse8_v_u8mf2(const uint8_t *base, ptrdiff_t bstride, vuint8mf2_t test_vlse8_v_u8mf2(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8mf2(base, bstride, vl); return vlse8_v_u8mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8m1( // CHECK-RV64-LABEL: @test_vlse8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vlse8_v_u8m1(const uint8_t *base, ptrdiff_t bstride, vuint8m1_t test_vlse8_v_u8m1(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8m1(base, bstride, vl); return vlse8_v_u8m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8m2( // CHECK-RV64-LABEL: @test_vlse8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vlse8_v_u8m2(const uint8_t *base, ptrdiff_t bstride, vuint8m2_t test_vlse8_v_u8m2(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8m2(base, bstride, vl); return vlse8_v_u8m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8m4( // CHECK-RV64-LABEL: @test_vlse8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vlse8_v_u8m4(const uint8_t *base, ptrdiff_t bstride, vuint8m4_t test_vlse8_v_u8m4(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8m4(base, bstride, vl); return vlse8_v_u8m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_u8m8( // CHECK-RV64-LABEL: @test_vlse8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vlse8_v_u8m8(const uint8_t *base, ptrdiff_t bstride, vuint8m8_t test_vlse8_v_u8m8(const uint8_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse8_v_u8m8(base, bstride, vl); return vlse8_v_u8m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf4( // CHECK-RV64-LABEL: @test_vlse16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vlse16_v_u16mf4(const uint16_t *base, ptrdiff_t bstride, vuint16mf4_t test_vlse16_v_u16mf4(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16mf4(base, bstride, vl); return vlse16_v_u16mf4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16mf2( // CHECK-RV64-LABEL: @test_vlse16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vlse16_v_u16mf2(const uint16_t *base, ptrdiff_t bstride, vuint16mf2_t test_vlse16_v_u16mf2(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16mf2(base, bstride, vl); return vlse16_v_u16mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16m1( // CHECK-RV64-LABEL: @test_vlse16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vlse16_v_u16m1(const uint16_t *base, ptrdiff_t bstride, vuint16m1_t test_vlse16_v_u16m1(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16m1(base, bstride, vl); return vlse16_v_u16m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16m2( // CHECK-RV64-LABEL: @test_vlse16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vlse16_v_u16m2(const uint16_t *base, ptrdiff_t bstride, vuint16m2_t test_vlse16_v_u16m2(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16m2(base, bstride, vl); return vlse16_v_u16m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16m4( // CHECK-RV64-LABEL: @test_vlse16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vlse16_v_u16m4(const uint16_t *base, ptrdiff_t bstride, vuint16m4_t test_vlse16_v_u16m4(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16m4(base, bstride, vl); return vlse16_v_u16m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_u16m8( // CHECK-RV64-LABEL: @test_vlse16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vlse16_v_u16m8(const uint16_t *base, ptrdiff_t bstride, vuint16m8_t test_vlse16_v_u16m8(const uint16_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse16_v_u16m8(base, bstride, vl); return vlse16_v_u16m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2( // CHECK-RV64-LABEL: @test_vlse32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vlse32_v_u32mf2(const uint32_t *base, ptrdiff_t bstride, vuint32mf2_t test_vlse32_v_u32mf2(const uint32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_u32mf2(base, bstride, vl); return vlse32_v_u32mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_u32m1( // CHECK-RV64-LABEL: @test_vlse32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vlse32_v_u32m1(const uint32_t *base, ptrdiff_t bstride, vuint32m1_t test_vlse32_v_u32m1(const uint32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_u32m1(base, bstride, vl); return vlse32_v_u32m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_u32m2( // CHECK-RV64-LABEL: @test_vlse32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vlse32_v_u32m2(const uint32_t *base, ptrdiff_t bstride, vuint32m2_t test_vlse32_v_u32m2(const uint32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_u32m2(base, bstride, vl); return vlse32_v_u32m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_u32m4( // CHECK-RV64-LABEL: @test_vlse32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vlse32_v_u32m4(const uint32_t *base, ptrdiff_t bstride, vuint32m4_t test_vlse32_v_u32m4(const uint32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_u32m4(base, bstride, vl); return vlse32_v_u32m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_u32m8( // CHECK-RV64-LABEL: @test_vlse32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vlse32_v_u32m8(const uint32_t *base, ptrdiff_t bstride, vuint32m8_t test_vlse32_v_u32m8(const uint32_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_u32m8(base, bstride, vl); return vlse32_v_u32m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_u64m1( // CHECK-RV64-LABEL: @test_vlse64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vlse64_v_u64m1(const uint64_t *base, ptrdiff_t bstride, vuint64m1_t test_vlse64_v_u64m1(const uint64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_u64m1(base, bstride, vl); return vlse64_v_u64m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_u64m2( // CHECK-RV64-LABEL: @test_vlse64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vlse64_v_u64m2(const uint64_t *base, ptrdiff_t bstride, vuint64m2_t test_vlse64_v_u64m2(const uint64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_u64m2(base, bstride, vl); return vlse64_v_u64m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_u64m4( // CHECK-RV64-LABEL: @test_vlse64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vlse64_v_u64m4(const uint64_t *base, ptrdiff_t bstride, vuint64m4_t test_vlse64_v_u64m4(const uint64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_u64m4(base, bstride, vl); return vlse64_v_u64m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_u64m8( // CHECK-RV64-LABEL: @test_vlse64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vlse64_v_u64m8(const uint64_t *base, ptrdiff_t bstride, vuint64m8_t test_vlse64_v_u64m8(const uint64_t *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_u64m8(base, bstride, vl); return vlse64_v_u64m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2( // CHECK-RV64-LABEL: @test_vlse32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vlse32_v_f32mf2(const float *base, ptrdiff_t bstride, vfloat32mf2_t test_vlse32_v_f32mf2(const float *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_f32mf2(base, bstride, vl); return vlse32_v_f32mf2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_f32m1( // CHECK-RV64-LABEL: @test_vlse32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.i64(<vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vlse32_v_f32m1(const float *base, ptrdiff_t bstride, vfloat32m1_t test_vlse32_v_f32m1(const float *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_f32m1(base, bstride, vl); return vlse32_v_f32m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_f32m2( // CHECK-RV64-LABEL: @test_vlse32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.i64(<vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vlse32_v_f32m2(const float *base, ptrdiff_t bstride, vfloat32m2_t test_vlse32_v_f32m2(const float *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_f32m2(base, bstride, vl); return vlse32_v_f32m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_f32m4( // CHECK-RV64-LABEL: @test_vlse32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.i64(<vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vlse32_v_f32m4(const float *base, ptrdiff_t bstride, vfloat32m4_t test_vlse32_v_f32m4(const float *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_f32m4(base, bstride, vl); return vlse32_v_f32m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse32_v_f32m8( // CHECK-RV64-LABEL: @test_vlse32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.i64(<vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vlse32_v_f32m8(const float *base, ptrdiff_t bstride, vfloat32m8_t test_vlse32_v_f32m8(const float *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse32_v_f32m8(base, bstride, vl); return vlse32_v_f32m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_f64m1( // CHECK-RV64-LABEL: @test_vlse64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.i64(<vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vlse64_v_f64m1(const double *base, ptrdiff_t bstride, vfloat64m1_t test_vlse64_v_f64m1(const double *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_f64m1(base, bstride, vl); return vlse64_v_f64m1(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_f64m2( // CHECK-RV64-LABEL: @test_vlse64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.i64(<vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vlse64_v_f64m2(const double *base, ptrdiff_t bstride, vfloat64m2_t test_vlse64_v_f64m2(const double *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_f64m2(base, bstride, vl); return vlse64_v_f64m2(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_f64m4( // CHECK-RV64-LABEL: @test_vlse64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.i64(<vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vlse64_v_f64m4(const double *base, ptrdiff_t bstride, vfloat64m4_t test_vlse64_v_f64m4(const double *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_f64m4(base, bstride, vl); return vlse64_v_f64m4(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse64_v_f64m8( // CHECK-RV64-LABEL: @test_vlse64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.i64(<vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vlse64_v_f64m8(const double *base, ptrdiff_t bstride, vfloat64m8_t test_vlse64_v_f64m8(const double *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_f64m8(base, bstride, vl); return vlse64_v_f64m8(base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m(
▲ Show 20 Lines • Show All 630 Lines • ▼ Show 20 Linesvfloat64m8_t test_vlse64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
const double *base, ptrdiff_t bstride, const double *base, ptrdiff_t bstride,
size_t vl) { size_t vl) {
return vlse64_v_f64m8_m(mask, maskedoff, base, bstride, vl); return vlse64_v_f64m8_m(mask, maskedoff, base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf4( // CHECK-RV64-LABEL: @test_vlse16_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.i64(<vscale x 1 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vlse16_v_f16mf4 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16mf4_t test_vlse16_v_f16mf4 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16mf4 (base, bstride, vl); return vlse16_v_f16mf4 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf2( // CHECK-RV64-LABEL: @test_vlse16_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.i64(<vscale x 2 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vlse16_v_f16mf2 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16mf2_t test_vlse16_v_f16mf2 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16mf2 (base, bstride, vl); return vlse16_v_f16mf2 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16m1( // CHECK-RV64-LABEL: @test_vlse16_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.i64(<vscale x 4 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vlse16_v_f16m1 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16m1_t test_vlse16_v_f16m1 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16m1 (base, bstride, vl); return vlse16_v_f16m1 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16m2( // CHECK-RV64-LABEL: @test_vlse16_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.i64(<vscale x 8 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vlse16_v_f16m2 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16m2_t test_vlse16_v_f16m2 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16m2 (base, bstride, vl); return vlse16_v_f16m2 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16m4( // CHECK-RV64-LABEL: @test_vlse16_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.i64(<vscale x 16 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vlse16_v_f16m4 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16m4_t test_vlse16_v_f16m4 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16m4 (base, bstride, vl); return vlse16_v_f16m4 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16m8( // CHECK-RV64-LABEL: @test_vlse16_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.i64(<vscale x 32 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vlse16_v_f16m8 (const _Float16 *base, ptrdiff_t bstride, size_t vl) { vfloat16m8_t test_vlse16_v_f16m8 (const _Float16 *base, ptrdiff_t bstride, size_t vl) {
return vlse16_v_f16m8 (base, bstride, vl); return vlse16_v_f16m8 (base, bstride, vl);
} }
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vlse16_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) { vint8mf8_t test_vluxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_i8mf8(base, bindex, vl); return vluxei8_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) { vint8mf4_t test_vluxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_i8mf4(base, bindex, vl); return vluxei8_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) { vint8mf2_t test_vluxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_i8mf2(base, bindex, vl); return vluxei8_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) { vint8m1_t test_vluxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_i8m1(base, bindex, vl); return vluxei8_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) { vint8m2_t test_vluxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_i8m2(base, bindex, vl); return vluxei8_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vluxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) { vint8m4_t test_vluxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8_v_i8m4(base, bindex, vl); return vluxei8_v_i8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vint8m8_t test_vluxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) { vint8m8_t test_vluxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) {
return vluxei8_v_i8m8(base, bindex, vl); return vluxei8_v_i8m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) { vint8mf8_t test_vluxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_i8mf8(base, bindex, vl); return vluxei16_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) { vint8mf4_t test_vluxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_i8mf4(base, bindex, vl); return vluxei16_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) { vint8mf2_t test_vluxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_i8mf2(base, bindex, vl); return vluxei16_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) { vint8m1_t test_vluxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_i8m1(base, bindex, vl); return vluxei16_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) { vint8m2_t test_vluxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_i8m2(base, bindex, vl); return vluxei16_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vint8m4_t test_vluxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) { vint8m4_t test_vluxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16_v_i8m4(base, bindex, vl); return vluxei16_v_i8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) { vint8mf8_t test_vluxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_i8mf8(base, bindex, vl); return vluxei32_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) { vint8mf4_t test_vluxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_i8mf4(base, bindex, vl); return vluxei32_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) { vint8mf2_t test_vluxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_i8mf2(base, bindex, vl); return vluxei32_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) { vint8m1_t test_vluxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_i8m1(base, bindex, vl); return vluxei32_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vint8m2_t test_vluxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) { vint8m2_t test_vluxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_i8m2(base, bindex, vl); return vluxei32_v_i8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vint8mf8_t test_vluxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) { vint8mf8_t test_vluxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_i8mf8(base, bindex, vl); return vluxei64_v_i8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vint8mf4_t test_vluxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) { vint8mf4_t test_vluxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_i8mf4(base, bindex, vl); return vluxei64_v_i8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vint8mf2_t test_vluxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) { vint8mf2_t test_vluxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_i8mf2(base, bindex, vl); return vluxei64_v_i8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i8m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vint8m1_t test_vluxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { vint8m1_t test_vluxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_i8m1(base, bindex, vl); return vluxei64_v_i8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) { vint16mf4_t test_vluxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_i16mf4(base, bindex, vl); return vluxei8_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) { vint16mf2_t test_vluxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_i16mf2(base, bindex, vl); return vluxei8_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) { vint16m1_t test_vluxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_i16m1(base, bindex, vl); return vluxei8_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) { vint16m2_t test_vluxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_i16m2(base, bindex, vl); return vluxei8_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) { vint16m4_t test_vluxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_i16m4(base, bindex, vl); return vluxei8_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vluxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) { vint16m8_t test_vluxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8_v_i16m8(base, bindex, vl); return vluxei8_v_i16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) { vint16mf4_t test_vluxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_i16mf4(base, bindex, vl); return vluxei16_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) { vint16mf2_t test_vluxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_i16mf2(base, bindex, vl); return vluxei16_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) { vint16m1_t test_vluxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_i16m1(base, bindex, vl); return vluxei16_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) { vint16m2_t test_vluxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_i16m2(base, bindex, vl); return vluxei16_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) { vint16m4_t test_vluxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_i16m4(base, bindex, vl); return vluxei16_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vint16m8_t test_vluxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) { vint16m8_t test_vluxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16_v_i16m8(base, bindex, vl); return vluxei16_v_i16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) { vint16mf4_t test_vluxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_i16mf4(base, bindex, vl); return vluxei32_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) { vint16mf2_t test_vluxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_i16mf2(base, bindex, vl); return vluxei32_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) { vint16m1_t test_vluxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_i16m1(base, bindex, vl); return vluxei32_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) { vint16m2_t test_vluxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_i16m2(base, bindex, vl); return vluxei32_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vint16m4_t test_vluxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) { vint16m4_t test_vluxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_i16m4(base, bindex, vl); return vluxei32_v_i16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vint16mf4_t test_vluxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) { vint16mf4_t test_vluxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_i16mf4(base, bindex, vl); return vluxei64_v_i16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vint16mf2_t test_vluxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) { vint16mf2_t test_vluxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_i16mf2(base, bindex, vl); return vluxei64_v_i16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vint16m1_t test_vluxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) { vint16m1_t test_vluxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_i16m1(base, bindex, vl); return vluxei64_v_i16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vint16m2_t test_vluxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) { vint16m2_t test_vluxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_i16m2(base, bindex, vl); return vluxei64_v_i16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) { vint32mf2_t test_vluxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_i32mf2(base, bindex, vl); return vluxei8_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) { vint32m1_t test_vluxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_i32m1(base, bindex, vl); return vluxei8_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) { vint32m2_t test_vluxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_i32m2(base, bindex, vl); return vluxei8_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) { vint32m4_t test_vluxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_i32m4(base, bindex, vl); return vluxei8_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) { vint32m8_t test_vluxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_i32m8(base, bindex, vl); return vluxei8_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) { vint32mf2_t test_vluxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_i32mf2(base, bindex, vl); return vluxei16_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) { vint32m1_t test_vluxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_i32m1(base, bindex, vl); return vluxei16_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) { vint32m2_t test_vluxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_i32m2(base, bindex, vl); return vluxei16_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) { vint32m4_t test_vluxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_i32m4(base, bindex, vl); return vluxei16_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) { vint32m8_t test_vluxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_i32m8(base, bindex, vl); return vluxei16_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) { vint32mf2_t test_vluxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_i32mf2(base, bindex, vl); return vluxei32_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { vint32m1_t test_vluxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_i32m1(base, bindex, vl); return vluxei32_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) { vint32m2_t test_vluxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_i32m2(base, bindex, vl); return vluxei32_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) { vint32m4_t test_vluxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_i32m4(base, bindex, vl); return vluxei32_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vint32m8_t test_vluxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) { vint32m8_t test_vluxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_i32m8(base, bindex, vl); return vluxei32_v_i32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vint32mf2_t test_vluxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) { vint32mf2_t test_vluxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_i32mf2(base, bindex, vl); return vluxei64_v_i32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vint32m1_t test_vluxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) { vint32m1_t test_vluxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_i32m1(base, bindex, vl); return vluxei64_v_i32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vint32m2_t test_vluxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) { vint32m2_t test_vluxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_i32m2(base, bindex, vl); return vluxei64_v_i32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vint32m4_t test_vluxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) { vint32m4_t test_vluxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_i32m4(base, bindex, vl); return vluxei64_v_i32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) { vint64m1_t test_vluxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_i64m1(base, bindex, vl); return vluxei8_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) { vint64m2_t test_vluxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_i64m2(base, bindex, vl); return vluxei8_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) { vint64m4_t test_vluxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_i64m4(base, bindex, vl); return vluxei8_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) { vint64m8_t test_vluxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_i64m8(base, bindex, vl); return vluxei8_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) { vint64m1_t test_vluxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_i64m1(base, bindex, vl); return vluxei16_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) { vint64m2_t test_vluxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_i64m2(base, bindex, vl); return vluxei16_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) { vint64m4_t test_vluxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_i64m4(base, bindex, vl); return vluxei16_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) { vint64m8_t test_vluxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_i64m8(base, bindex, vl); return vluxei16_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) { vint64m1_t test_vluxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_i64m1(base, bindex, vl); return vluxei32_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) { vint64m2_t test_vluxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_i64m2(base, bindex, vl); return vluxei32_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) { vint64m4_t test_vluxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_i64m4(base, bindex, vl); return vluxei32_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) { vint64m8_t test_vluxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_i64m8(base, bindex, vl); return vluxei32_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vint64m1_t test_vluxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) { vint64m1_t test_vluxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_i64m1(base, bindex, vl); return vluxei64_v_i64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vint64m2_t test_vluxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) { vint64m2_t test_vluxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_i64m2(base, bindex, vl); return vluxei64_v_i64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vint64m4_t test_vluxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) { vint64m4_t test_vluxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_i64m4(base, bindex, vl); return vluxei64_v_i64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vint64m8_t test_vluxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) { vint64m8_t test_vluxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_i64m8(base, bindex, vl); return vluxei64_v_i64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) { vuint8mf8_t test_vluxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_u8mf8(base, bindex, vl); return vluxei8_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) { vuint8mf4_t test_vluxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_u8mf4(base, bindex, vl); return vluxei8_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) { vuint8mf2_t test_vluxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_u8mf2(base, bindex, vl); return vluxei8_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) { vuint8m1_t test_vluxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_u8m1(base, bindex, vl); return vluxei8_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) { vuint8m2_t test_vluxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_u8m2(base, bindex, vl); return vluxei8_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vluxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) { vuint8m4_t test_vluxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8_v_u8m4(base, bindex, vl); return vluxei8_v_u8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
// //
vuint8m8_t test_vluxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) { vuint8m8_t test_vluxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) {
return vluxei8_v_u8m8(base, bindex, vl); return vluxei8_v_u8m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) { vuint8mf8_t test_vluxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_u8mf8(base, bindex, vl); return vluxei16_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) { vuint8mf4_t test_vluxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_u8mf4(base, bindex, vl); return vluxei16_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) { vuint8mf2_t test_vluxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_u8mf2(base, bindex, vl); return vluxei16_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) { vuint8m1_t test_vluxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_u8m1(base, bindex, vl); return vluxei16_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) { vuint8m2_t test_vluxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_u8m2(base, bindex, vl); return vluxei16_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> undef, <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
// //
vuint8m4_t test_vluxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) { vuint8m4_t test_vluxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16_v_u8m4(base, bindex, vl); return vluxei16_v_u8m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) { vuint8mf8_t test_vluxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_u8mf8(base, bindex, vl); return vluxei32_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) { vuint8mf4_t test_vluxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_u8mf4(base, bindex, vl); return vluxei32_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) { vuint8mf2_t test_vluxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_u8mf2(base, bindex, vl); return vluxei32_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) { vuint8m1_t test_vluxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_u8m1(base, bindex, vl); return vluxei32_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> undef, <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
// //
vuint8m2_t test_vluxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) { vuint8m2_t test_vluxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_u8m2(base, bindex, vl); return vluxei32_v_u8m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
// //
vuint8mf8_t test_vluxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) { vuint8mf8_t test_vluxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_u8mf8(base, bindex, vl); return vluxei64_v_u8mf8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> undef, <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
// //
vuint8mf4_t test_vluxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) { vuint8mf4_t test_vluxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_u8mf4(base, bindex, vl); return vluxei64_v_u8mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> undef, <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
// //
vuint8mf2_t test_vluxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) { vuint8mf2_t test_vluxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_u8mf2(base, bindex, vl); return vluxei64_v_u8mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u8m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
// //
vuint8m1_t test_vluxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) { vuint8m1_t test_vluxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_u8m1(base, bindex, vl); return vluxei64_v_u8m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) { vuint16mf4_t test_vluxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_u16mf4(base, bindex, vl); return vluxei8_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) { vuint16mf2_t test_vluxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_u16mf2(base, bindex, vl); return vluxei8_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) { vuint16m1_t test_vluxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_u16m1(base, bindex, vl); return vluxei8_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) { vuint16m2_t test_vluxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_u16m2(base, bindex, vl); return vluxei8_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) { vuint16m4_t test_vluxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_u16m4(base, bindex, vl); return vluxei8_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vluxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) { vuint16m8_t test_vluxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) {
return vluxei8_v_u16m8(base, bindex, vl); return vluxei8_v_u16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) { vuint16mf4_t test_vluxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_u16mf4(base, bindex, vl); return vluxei16_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) { vuint16mf2_t test_vluxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_u16mf2(base, bindex, vl); return vluxei16_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) { vuint16m1_t test_vluxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_u16m1(base, bindex, vl); return vluxei16_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) { vuint16m2_t test_vluxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_u16m2(base, bindex, vl); return vluxei16_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) { vuint16m4_t test_vluxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_u16m4(base, bindex, vl); return vluxei16_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
// //
vuint16m8_t test_vluxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) { vuint16m8_t test_vluxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) {
return vluxei16_v_u16m8(base, bindex, vl); return vluxei16_v_u16m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) { vuint16mf4_t test_vluxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_u16mf4(base, bindex, vl); return vluxei32_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) { vuint16mf2_t test_vluxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_u16mf2(base, bindex, vl); return vluxei32_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) { vuint16m1_t test_vluxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_u16m1(base, bindex, vl); return vluxei32_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) { vuint16m2_t test_vluxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_u16m2(base, bindex, vl); return vluxei32_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> undef, <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
// //
vuint16m4_t test_vluxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) { vuint16m4_t test_vluxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_u16m4(base, bindex, vl); return vluxei32_v_u16m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> undef, <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
// //
vuint16mf4_t test_vluxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) { vuint16mf4_t test_vluxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_u16mf4(base, bindex, vl); return vluxei64_v_u16mf4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> undef, <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
// //
vuint16mf2_t test_vluxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) { vuint16mf2_t test_vluxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_u16mf2(base, bindex, vl); return vluxei64_v_u16mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> undef, <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
// //
vuint16m1_t test_vluxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) { vuint16m1_t test_vluxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_u16m1(base, bindex, vl); return vluxei64_v_u16m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> undef, <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
// //
vuint16m2_t test_vluxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) { vuint16m2_t test_vluxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_u16m2(base, bindex, vl); return vluxei64_v_u16m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) { vuint32mf2_t test_vluxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_u32mf2(base, bindex, vl); return vluxei8_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) { vuint32m1_t test_vluxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_u32m1(base, bindex, vl); return vluxei8_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) { vuint32m2_t test_vluxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_u32m2(base, bindex, vl); return vluxei8_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) { vuint32m4_t test_vluxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_u32m4(base, bindex, vl); return vluxei8_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) { vuint32m8_t test_vluxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_u32m8(base, bindex, vl); return vluxei8_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) { vuint32mf2_t test_vluxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_u32mf2(base, bindex, vl); return vluxei16_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) { vuint32m1_t test_vluxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_u32m1(base, bindex, vl); return vluxei16_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) { vuint32m2_t test_vluxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_u32m2(base, bindex, vl); return vluxei16_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) { vuint32m4_t test_vluxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_u32m4(base, bindex, vl); return vluxei16_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) { vuint32m8_t test_vluxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_u32m8(base, bindex, vl); return vluxei16_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) { vuint32mf2_t test_vluxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_u32mf2(base, bindex, vl); return vluxei32_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) { vuint32m1_t test_vluxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_u32m1(base, bindex, vl); return vluxei32_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) { vuint32m2_t test_vluxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_u32m2(base, bindex, vl); return vluxei32_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) { vuint32m4_t test_vluxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_u32m4(base, bindex, vl); return vluxei32_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
// //
vuint32m8_t test_vluxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) { vuint32m8_t test_vluxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_u32m8(base, bindex, vl); return vluxei32_v_u32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
// //
vuint32mf2_t test_vluxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) { vuint32mf2_t test_vluxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_u32mf2(base, bindex, vl); return vluxei64_v_u32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
// //
vuint32m1_t test_vluxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) { vuint32m1_t test_vluxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_u32m1(base, bindex, vl); return vluxei64_v_u32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
// //
vuint32m2_t test_vluxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) { vuint32m2_t test_vluxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_u32m2(base, bindex, vl); return vluxei64_v_u32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> undef, <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
// //
vuint32m4_t test_vluxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) { vuint32m4_t test_vluxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_u32m4(base, bindex, vl); return vluxei64_v_u32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) { vuint64m1_t test_vluxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_u64m1(base, bindex, vl); return vluxei8_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) { vuint64m2_t test_vluxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_u64m2(base, bindex, vl); return vluxei8_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) { vuint64m4_t test_vluxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_u64m4(base, bindex, vl); return vluxei8_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) { vuint64m8_t test_vluxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_u64m8(base, bindex, vl); return vluxei8_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) { vuint64m1_t test_vluxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_u64m1(base, bindex, vl); return vluxei16_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) { vuint64m2_t test_vluxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_u64m2(base, bindex, vl); return vluxei16_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) { vuint64m4_t test_vluxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_u64m4(base, bindex, vl); return vluxei16_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) { vuint64m8_t test_vluxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_u64m8(base, bindex, vl); return vluxei16_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) { vuint64m1_t test_vluxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_u64m1(base, bindex, vl); return vluxei32_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) { vuint64m2_t test_vluxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_u64m2(base, bindex, vl); return vluxei32_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) { vuint64m4_t test_vluxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_u64m4(base, bindex, vl); return vluxei32_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) { vuint64m8_t test_vluxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_u64m8(base, bindex, vl); return vluxei32_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
// //
vuint64m1_t test_vluxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) { vuint64m1_t test_vluxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_u64m1(base, bindex, vl); return vluxei64_v_u64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
// //
vuint64m2_t test_vluxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) { vuint64m2_t test_vluxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_u64m2(base, bindex, vl); return vluxei64_v_u64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
// //
vuint64m4_t test_vluxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) { vuint64m4_t test_vluxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_u64m4(base, bindex, vl); return vluxei64_v_u64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
// //
vuint64m8_t test_vluxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) { vuint64m8_t test_vluxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_u64m8(base, bindex, vl); return vluxei64_v_u64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) { vfloat32mf2_t test_vluxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_f32mf2(base, bindex, vl); return vluxei8_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) { vfloat32m1_t test_vluxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_f32m1(base, bindex, vl); return vluxei8_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) { vfloat32m2_t test_vluxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_f32m2(base, bindex, vl); return vluxei8_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) { vfloat32m4_t test_vluxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_f32m4(base, bindex, vl); return vluxei8_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei8_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) { vfloat32m8_t test_vluxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_f32m8(base, bindex, vl); return vluxei8_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) { vfloat32mf2_t test_vluxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_f32mf2(base, bindex, vl); return vluxei16_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) { vfloat32m1_t test_vluxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_f32m1(base, bindex, vl); return vluxei16_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) { vfloat32m2_t test_vluxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_f32m2(base, bindex, vl); return vluxei16_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) { vfloat32m4_t test_vluxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_f32m4(base, bindex, vl); return vluxei16_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei16_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) { vfloat32m8_t test_vluxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_f32m8(base, bindex, vl); return vluxei16_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) { vfloat32mf2_t test_vluxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_f32mf2(base, bindex, vl); return vluxei32_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) { vfloat32m1_t test_vluxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_f32m1(base, bindex, vl); return vluxei32_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) { vfloat32m2_t test_vluxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_f32m2(base, bindex, vl); return vluxei32_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) { vfloat32m4_t test_vluxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_f32m4(base, bindex, vl); return vluxei32_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m8( // CHECK-RV64-LABEL: @test_vluxei32_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
// //
vfloat32m8_t test_vluxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) { vfloat32m8_t test_vluxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_f32m8(base, bindex, vl); return vluxei32_v_f32m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
// //
vfloat32mf2_t test_vluxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) { vfloat32mf2_t test_vluxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_f32mf2(base, bindex, vl); return vluxei64_v_f32mf2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m1( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
// //
vfloat32m1_t test_vluxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) { vfloat32m1_t test_vluxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_f32m1(base, bindex, vl); return vluxei64_v_f32m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m2( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
// //
vfloat32m2_t test_vluxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) { vfloat32m2_t test_vluxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_f32m2(base, bindex, vl); return vluxei64_v_f32m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m4( // CHECK-RV64-LABEL: @test_vluxei64_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
// //
vfloat32m4_t test_vluxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) { vfloat32m4_t test_vluxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_f32m4(base, bindex, vl); return vluxei64_v_f32m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) { vfloat64m1_t test_vluxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_f64m1(base, bindex, vl); return vluxei8_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) { vfloat64m2_t test_vluxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_f64m2(base, bindex, vl); return vluxei8_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) { vfloat64m4_t test_vluxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_f64m4(base, bindex, vl); return vluxei8_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei8_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) { vfloat64m8_t test_vluxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_f64m8(base, bindex, vl); return vluxei8_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) { vfloat64m1_t test_vluxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_f64m1(base, bindex, vl); return vluxei16_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) { vfloat64m2_t test_vluxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_f64m2(base, bindex, vl); return vluxei16_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) { vfloat64m4_t test_vluxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_f64m4(base, bindex, vl); return vluxei16_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei16_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) { vfloat64m8_t test_vluxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_f64m8(base, bindex, vl); return vluxei16_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) { vfloat64m1_t test_vluxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_f64m1(base, bindex, vl); return vluxei32_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) { vfloat64m2_t test_vluxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_f64m2(base, bindex, vl); return vluxei32_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) { vfloat64m4_t test_vluxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_f64m4(base, bindex, vl); return vluxei32_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei32_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) { vfloat64m8_t test_vluxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_f64m8(base, bindex, vl); return vluxei32_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m1( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
// //
vfloat64m1_t test_vluxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) { vfloat64m1_t test_vluxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_f64m1(base, bindex, vl); return vluxei64_v_f64m1(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m2( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
// //
vfloat64m2_t test_vluxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) { vfloat64m2_t test_vluxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_f64m2(base, bindex, vl); return vluxei64_v_f64m2(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m4( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
// //
vfloat64m4_t test_vluxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) { vfloat64m4_t test_vluxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_f64m4(base, bindex, vl); return vluxei64_v_f64m4(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m8( // CHECK-RV64-LABEL: @test_vluxei64_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
// //
vfloat64m8_t test_vluxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vluxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_f64m8(base, bindex, vl); return vluxei64_v_f64m8(base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8_m( // CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 1,903 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vluxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) { vfloat64m8_t test_vluxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_f64m8_m(mask, maskedoff, base, bindex, vl); return vluxei64_v_f64m8_m(mask, maskedoff, base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf4( // CHECK-RV64-LABEL: @test_vluxei8_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vluxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) { vfloat16mf4_t test_vluxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
return vluxei8_v_f16mf4 (base, bindex, vl); return vluxei8_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf2( // CHECK-RV64-LABEL: @test_vluxei8_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vluxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) { vfloat16mf2_t test_vluxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
return vluxei8_v_f16mf2 (base, bindex, vl); return vluxei8_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m1( // CHECK-RV64-LABEL: @test_vluxei8_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vluxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) { vfloat16m1_t test_vluxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
return vluxei8_v_f16m1 (base, bindex, vl); return vluxei8_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m2( // CHECK-RV64-LABEL: @test_vluxei8_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vluxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) { vfloat16m2_t test_vluxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) {
return vluxei8_v_f16m2 (base, bindex, vl); return vluxei8_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m4( // CHECK-RV64-LABEL: @test_vluxei8_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vluxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) { vfloat16m4_t test_vluxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) {
return vluxei8_v_f16m4 (base, bindex, vl); return vluxei8_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m8( // CHECK-RV64-LABEL: @test_vluxei8_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vluxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) { vfloat16m8_t test_vluxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) {
return vluxei8_v_f16m8 (base, bindex, vl); return vluxei8_v_f16m8 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf4( // CHECK-RV64-LABEL: @test_vluxei16_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vluxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) { vfloat16mf4_t test_vluxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
return vluxei16_v_f16mf4 (base, bindex, vl); return vluxei16_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf2( // CHECK-RV64-LABEL: @test_vluxei16_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vluxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) { vfloat16mf2_t test_vluxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
return vluxei16_v_f16mf2 (base, bindex, vl); return vluxei16_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m1( // CHECK-RV64-LABEL: @test_vluxei16_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vluxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) { vfloat16m1_t test_vluxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) {
return vluxei16_v_f16m1 (base, bindex, vl); return vluxei16_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m2( // CHECK-RV64-LABEL: @test_vluxei16_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vluxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) { vfloat16m2_t test_vluxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) {
return vluxei16_v_f16m2 (base, bindex, vl); return vluxei16_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m4( // CHECK-RV64-LABEL: @test_vluxei16_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vluxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) { vfloat16m4_t test_vluxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) {
return vluxei16_v_f16m4 (base, bindex, vl); return vluxei16_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m8( // CHECK-RV64-LABEL: @test_vluxei16_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
// //
vfloat16m8_t test_vluxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) { vfloat16m8_t test_vluxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) {
return vluxei16_v_f16m8 (base, bindex, vl); return vluxei16_v_f16m8 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf4( // CHECK-RV64-LABEL: @test_vluxei32_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vluxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) { vfloat16mf4_t test_vluxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
return vluxei32_v_f16mf4 (base, bindex, vl); return vluxei32_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf2( // CHECK-RV64-LABEL: @test_vluxei32_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vluxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) { vfloat16mf2_t test_vluxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) {
return vluxei32_v_f16mf2 (base, bindex, vl); return vluxei32_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m1( // CHECK-RV64-LABEL: @test_vluxei32_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vluxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) { vfloat16m1_t test_vluxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) {
return vluxei32_v_f16m1 (base, bindex, vl); return vluxei32_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m2( // CHECK-RV64-LABEL: @test_vluxei32_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vluxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) { vfloat16m2_t test_vluxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) {
return vluxei32_v_f16m2 (base, bindex, vl); return vluxei32_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m4( // CHECK-RV64-LABEL: @test_vluxei32_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
// //
vfloat16m4_t test_vluxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) { vfloat16m4_t test_vluxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) {
return vluxei32_v_f16m4 (base, bindex, vl); return vluxei32_v_f16m4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf4( // CHECK-RV64-LABEL: @test_vluxei64_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
// //
vfloat16mf4_t test_vluxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) { vfloat16mf4_t test_vluxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) {
return vluxei64_v_f16mf4 (base, bindex, vl); return vluxei64_v_f16mf4 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf2( // CHECK-RV64-LABEL: @test_vluxei64_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
// //
vfloat16mf2_t test_vluxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) { vfloat16mf2_t test_vluxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) {
return vluxei64_v_f16mf2 (base, bindex, vl); return vluxei64_v_f16mf2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m1( // CHECK-RV64-LABEL: @test_vluxei64_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
// //
vfloat16m1_t test_vluxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) { vfloat16m1_t test_vluxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) {
return vluxei64_v_f16m1 (base, bindex, vl); return vluxei64_v_f16m1 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m2( // CHECK-RV64-LABEL: @test_vluxei64_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>* // CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
// //
vfloat16m2_t test_vluxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) { vfloat16m2_t test_vluxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) {
return vluxei64_v_f16m2 (base, bindex, vl); return vluxei64_v_f16m2 (base, bindex, vl);
} }
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vluxei8_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines def int_riscv_vsetvli_opt : Intrinsic<[llvm_anyint_ty],
ImmArg<ArgIndex<2>>]>; ImmArg<ArgIndex<2>>]>;
def int_riscv_vsetvlimax_opt : Intrinsic<[llvm_anyint_ty], def int_riscv_vsetvlimax_opt : Intrinsic<[llvm_anyint_ty],
/* VSEW */ [LLVMMatchType<0>, /* VSEW */ [LLVMMatchType<0>,
/* VLMUL */ LLVMMatchType<0>], /* VLMUL */ LLVMMatchType<0>],
[IntrNoMem, [IntrNoMem,
ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<0>>,
ImmArg<ArgIndex<1>>]>; ImmArg<ArgIndex<1>>]>;
// For unit stride load // For unit stride mask load
// Input: (pointer, vl) // Input: (pointer, vl)
class RISCVUSLoad class RISCVUSMLoad
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMPointerType<LLVMMatchType<0>>, [LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty], llvm_anyint_ty],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic { [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
// For unit stride load
// Input: (passthru, pointer, vl)
class RISCVUSLoad
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
// For unit stride fault-only-first load // For unit stride fault-only-first load
// Input: (pointer, vl) // Input: (passthru, pointer, vl)
// Output: (data, vl) // Output: (data, vl)
// NOTE: We model this with default memory properties since we model writing // NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work. // VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSLoadFF class RISCVUSLoadFF
: Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty], : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
[LLVMPointerType<LLVMMatchType<0>>, LLVMMatchType<1>], [LLVMMatchType<0>,
[NoCapture<ArgIndex<0>>]>, LLVMPointerType<LLVMMatchType<0>>, LLVMMatchType<1>],
[NoCapture<ArgIndex<1>>]>,
RISCVVIntrinsic { RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// For unit stride load with mask // For unit stride load with mask
// Input: (maskedoff, pointer, mask, vl, ta) // Input: (maskedoff, pointer, mask, vl, ta)
class RISCVUSLoadMask class RISCVUSLoadMask
: Intrinsic<[llvm_anyvector_ty ], : Intrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, LLVMPointerType<LLVMMatchType<0>>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
Show All 11 Lines class RISCVUSLoadFFMask
: Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty], : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, LLVMPointerType<LLVMMatchType<0>>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>, LLVMMatchType<1>], LLVMMatchType<1>, LLVMMatchType<1>],
[NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic { [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// For strided load // For strided load with passthru operand
// Input: (pointer, stride, vl) // Input: (passthru, pointer, stride, vl)
class RISCVSLoad class RISCVSLoad
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMPointerType<LLVMMatchType<0>>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty, LLVMMatchType<1>], llvm_anyint_ty, LLVMMatchType<1>],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic { [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
let VLOperand = 2; let VLOperand = 3;
} }
// For strided load with mask // For strided load with mask
// Input: (maskedoff, pointer, stride, mask, vl, ta) // Input: (maskedoff, pointer, stride, mask, vl, ta)
class RISCVSLoadMask class RISCVSLoadMask
: Intrinsic<[llvm_anyvector_ty ], : Intrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyint_ty, LLVMPointerType<LLVMMatchType<0>>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>,
LLVMMatchType<1>], LLVMMatchType<1>],
[NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem]>, [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem]>,
RISCVVIntrinsic { RISCVVIntrinsic {
let VLOperand = 4; let VLOperand = 4;
} }
// For indexed load // For indexed load with passthru operand
// Input: (pointer, index, vl) // Input: (passthru, pointer, index, vl)
class RISCVILoad class RISCVILoad
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMPointerType<LLVMMatchType<0>>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyvector_ty, llvm_anyint_ty], llvm_anyvector_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic { [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
let VLOperand = 2; let VLOperand = 3;
} }
// For indexed load with mask // For indexed load with mask
// Input: (maskedoff, pointer, index, mask, vl, ta) // Input: (maskedoff, pointer, index, mask, vl, ta)
class RISCVILoadMask class RISCVILoadMask
: Intrinsic<[llvm_anyvector_ty ], : Intrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
▲ Show 20 Lines • Show All 857 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vse : RISCVUSStore; defm vse : RISCVUSStore;
defm vlse: RISCVSLoad; defm vlse: RISCVSLoad;
defm vsse: RISCVSStore; defm vsse: RISCVSStore;
defm vluxei : RISCVILoad; defm vluxei : RISCVILoad;
defm vloxei : RISCVILoad; defm vloxei : RISCVILoad;
defm vsoxei : RISCVIStore; defm vsoxei : RISCVIStore;
defm vsuxei : RISCVIStore; defm vsuxei : RISCVIStore;
def int_riscv_vlm : RISCVUSLoad; def int_riscv_vlm : RISCVUSMLoad;
def int_riscv_vsm : RISCVUSStore; def int_riscv_vsm : RISCVUSStore;
defm vadd : RISCVBinaryAAX; defm vadd : RISCVBinaryAAX;
defm vsub : RISCVBinaryAAX; defm vsub : RISCVBinaryAAX;
defm vrsub : RISCVBinaryAAX; defm vrsub : RISCVBinaryAAX;
defm vwaddu : RISCVBinaryABX; defm vwaddu : RISCVBinaryABX;
defm vwadd : RISCVBinaryABX; defm vwadd : RISCVBinaryABX;
▲ Show 20 Lines • Show All 307 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Linesstruct VSXSEGPseudo {
uint16_t Log2SEW : 3; uint16_t Log2SEW : 3;
uint16_t LMUL : 3; uint16_t LMUL : 3;
uint16_t IndexLMUL : 3; uint16_t IndexLMUL : 3;
uint16_t Pseudo; uint16_t Pseudo;
}; };
struct VLEPseudo { struct VLEPseudo {
uint16_t Masked : 1; uint16_t Masked : 1;
uint16_t IsTU : 1;
uint16_t Strided : 1; uint16_t Strided : 1;
uint16_t FF : 1; uint16_t FF : 1;
uint16_t Log2SEW : 3; uint16_t Log2SEW : 3;
uint16_t LMUL : 3; uint16_t LMUL : 3;
uint16_t Pseudo; uint16_t Pseudo;
}; };
struct VSEPseudo { struct VSEPseudo {
uint16_t Masked :1; uint16_t Masked :1;
uint16_t Strided : 1; uint16_t Strided : 1;
uint16_t Log2SEW : 3; uint16_t Log2SEW : 3;
uint16_t LMUL : 3; uint16_t LMUL : 3;
uint16_t Pseudo; uint16_t Pseudo;
}; };
struct VLX_VSXPseudo { struct VLX_VSXPseudo {
uint16_t Masked : 1; uint16_t Masked : 1;
uint16_t IsTU : 1;
uint16_t Ordered : 1; uint16_t Ordered : 1;
uint16_t Log2SEW : 3; uint16_t Log2SEW : 3;
uint16_t LMUL : 3; uint16_t LMUL : 3;
uint16_t IndexLMUL : 3; uint16_t IndexLMUL : 3;
uint16_t Pseudo; uint16_t Pseudo;
}; };
#define GET_RISCVVSSEGTable_DECL #define GET_RISCVVSSEGTable_DECL
Show All 13 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
Hi = CurDAG->getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4), Hi = CurDAG->getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4),
Align(8)); Align(8));
Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); SDVTList VTs = CurDAG->getVTList({VT, MVT::Other});
SDValue IntID = SDValue IntID =
CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64); CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64);
SDValue Ops[] = {Chain, IntID, StackSlot, SDValue Ops[] = {Chain,
CurDAG->getRegister(RISCV::X0, MVT::i64), VL}; IntID,
CurDAG->getUNDEF(VT),
StackSlot,
CurDAG->getRegister(RISCV::X0, MVT::i64),
VL};
SDValue Result = CurDAG->getMemIntrinsicNode( SDValue Result = CurDAG->getMemIntrinsicNode(
ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64, MPI, Align(8), ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64, MPI, Align(8),
MachineMemOperand::MOLoad); MachineMemOperand::MOLoad);
// We're about to replace all uses of the SPLAT_VECTOR_SPLIT_I64 with the // We're about to replace all uses of the SPLAT_VECTOR_SPLIT_I64 with the
// vlse we created. This will cause general havok on the dag because // vlse we created. This will cause general havok on the dag because
// anything below the conversion could be folded into other existing nodes. // anything below the conversion could be folded into other existing nodes.
▲ Show 20 Lines • Show All 1,106 Lines • ▼ Show 20 Lines case Intrinsic::riscv_vluxei_mask: {
IntNo == Intrinsic::riscv_vluxei_mask; IntNo == Intrinsic::riscv_vluxei_mask;
bool IsOrdered = IntNo == Intrinsic::riscv_vloxei || bool IsOrdered = IntNo == Intrinsic::riscv_vloxei ||
IntNo == Intrinsic::riscv_vloxei_mask; IntNo == Intrinsic::riscv_vloxei_mask;
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// Masked intrinsic only have TU version pseduo instructions.
bool IsTU = IsMasked || (!IsMasked && !Node->getOperand(CurOp).isUndef());
SmallVector<SDValue, 8> Operands; SmallVector<SDValue, 8> Operands;
if (IsMasked) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

If I'm reading this right, isn't it possible that we could have a masked/tu intrinsic, so push back the passthru operand, increment CurOp then check whether the pointer operand is Undef, then wrongly increment CurOp a second time? So basically an undef base pointer has the potential to (presumably) crash the compiler somewhere later?

Don't we unconditionally want to increment CurOp (a single time) since we now always have a passthru operand that we want to skip over?

frasercrmck: If I'm reading this right, isn't it possible that we could have a masked/tu intrinsic, so push…
// Skip the undef passthru operand for nomask TA version pseudo
CurOp++;
MVT IndexVT; MVT IndexVT;
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
/*IsStridedOrIndexed*/ true, Operands, /*IsStridedOrIndexed*/ true, Operands,
/*IsLoad=*/true, &IndexVT); /*IsLoad=*/true, &IndexVT);
assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() && assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
"Element count mismatch"); "Element count mismatch");
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
report_fatal_error("The V extension does not support EEW=64 for index " report_fatal_error("The V extension does not support EEW=64 for index "
"values when XLEN=32"); "values when XLEN=32");
} }
const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo( const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo(
IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), IsMasked, IsTU, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
static_cast<unsigned>(IndexLMUL)); static_cast<unsigned>(IndexLMUL));
MachineSDNode *Load = MachineSDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands); CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
if (auto *MemOp = dyn_cast<MemSDNode>(Node)) if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()}); CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
ReplaceNode(Node, Load); ReplaceNode(Node, Load);
return; return;
} }
case Intrinsic::riscv_vlm: case Intrinsic::riscv_vlm:
case Intrinsic::riscv_vle: case Intrinsic::riscv_vle:
case Intrinsic::riscv_vle_mask: case Intrinsic::riscv_vle_mask:
case Intrinsic::riscv_vlse: case Intrinsic::riscv_vlse:
case Intrinsic::riscv_vlse_mask: { case Intrinsic::riscv_vlse_mask: {
bool IsMasked = IntNo == Intrinsic::riscv_vle_mask || bool IsMasked = IntNo == Intrinsic::riscv_vle_mask ||
IntNo == Intrinsic::riscv_vlse_mask; IntNo == Intrinsic::riscv_vlse_mask;
bool IsStrided = bool IsStrided =
IntNo == Intrinsic::riscv_vlse || IntNo == Intrinsic::riscv_vlse_mask; IntNo == Intrinsic::riscv_vlse || IntNo == Intrinsic::riscv_vlse_mask;
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// The riscv_vlm intrinsic are always tail agnostic and no passthru operand.
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      // The riscv_vlm intrinsic are always tail agnostic and no passthru operand.
+      // The riscv_vlm intrinsic are always tail agnostic and no passthru
+      // operand.
Lint: Pre-merge checks: clang-format: please reformat the code ``` - // The riscv_vlm intrinsic are always tail…
craig.topperUnsubmitted
Not Done
ReplyInline Actions
bool IsTU = IntNo != Intrinsic::riscv_vlm && (!Node->getOperand(CurOp).isUndef() || IsMasked);
NOTE: I changed it so IsMask is also only checked when it's not vlm. That makes the non vlm part of the condition look like the other intrinsic handling earlier.
craig.topper: ``` bool IsTU = IntNo != Intrinsic::riscv_vlm && (!Node->getOperand(CurOp).isUndef() ||…
bool HasPassthruOperand = IntNo != Intrinsic::riscv_vlm;
// Masked intrinsic only have TU version pseduo instructions.
bool IsTU =
HasPassthruOperand &&
((!IsMasked && !Node->getOperand(CurOp).isUndef()) || IsMasked);
SmallVector<SDValue, 8> Operands; SmallVector<SDValue, 8> Operands;
if (IsMasked) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else if (HasPassthruOperand)
// Skip the undef passthru operand for nomask TA version pseudo
CurOp++;
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided, addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
Operands, /*IsLoad=*/true); Operands, /*IsLoad=*/true);
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Why aren't we using the default value for IndexVT now?

craig.topper: Why aren't we using the default value for IndexVT now?
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
const RISCV::VLEPseudo *P = const RISCV::VLEPseudo *P =
RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW, RISCV::getVLEPseudo(IsMasked, IsTU, IsStrided, /*FF*/ false, Log2SEW,
static_cast<unsigned>(LMUL)); static_cast<unsigned>(LMUL));
MachineSDNode *Load = MachineSDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands); CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
if (auto *MemOp = dyn_cast<MemSDNode>(Node)) if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()}); CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
ReplaceNode(Node, Load); ReplaceNode(Node, Load);
return; return;
} }
case Intrinsic::riscv_vleff: case Intrinsic::riscv_vleff:
case Intrinsic::riscv_vleff_mask: { case Intrinsic::riscv_vleff_mask: {
bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask; bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask;
MVT VT = Node->getSimpleValueType(0); MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
unsigned CurOp = 2; unsigned CurOp = 2;
// Masked intrinsic only have TU version pseduo instructions.
bool IsTU = IsMasked || (!IsMasked && !Node->getOperand(CurOp).isUndef());
SmallVector<SDValue, 7> Operands; SmallVector<SDValue, 7> Operands;
if (IsMasked) if (IsTU)
Operands.push_back(Node->getOperand(CurOp++)); Operands.push_back(Node->getOperand(CurOp++));
else
// Skip the undef passthru operand for nomask TA version pseudo
CurOp++;
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
/*IsStridedOrIndexed*/ false, Operands, /*IsStridedOrIndexed*/ false, Operands,
/*IsLoad=*/true); /*IsLoad=*/true);
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
const RISCV::VLEPseudo *P = const RISCV::VLEPseudo *P =
RISCV::getVLEPseudo(IsMasked, /*Strided*/ false, /*FF*/ true, Log2SEW, RISCV::getVLEPseudo(IsMasked, IsTU, /*Strided*/ false, /*FF*/ true,
static_cast<unsigned>(LMUL)); Log2SEW, static_cast<unsigned>(LMUL));
MachineSDNode *Load = MachineSDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0),
MVT::Other, MVT::Glue, Operands); MVT::Other, MVT::Glue, Operands);
SDNode *ReadVL = CurDAG->getMachineNode(RISCV::PseudoReadVL, DL, XLenVT, SDNode *ReadVL = CurDAG->getMachineNode(RISCV::PseudoReadVL, DL, XLenVT,
/*Glue*/ SDValue(Load, 2)); /*Glue*/ SDValue(Load, 2));
if (auto *MemOp = dyn_cast<MemSDNode>(Node)) if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()}); CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines case Intrinsic::riscv_vsuxei_mask: {
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
report_fatal_error("The V extension does not support EEW=64 for index " report_fatal_error("The V extension does not support EEW=64 for index "
"values when XLEN=32"); "values when XLEN=32");
} }
const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo( const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo(
IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), IsMasked, /*TU*/ false, IsOrdered, IndexLog2EEW,
static_cast<unsigned>(IndexLMUL)); static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL));
MachineSDNode *Store = MachineSDNode *Store =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands); CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
if (auto *MemOp = dyn_cast<MemSDNode>(Node)) if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()}); CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()});
ReplaceNode(Node, Store); ReplaceNode(Node, Store);
return; return;
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines case RISCVISD::VFMV_V_F_VL: {
SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT);
SDValue Operands[] = {Ld->getBasePtr(), SDValue Operands[] = {Ld->getBasePtr(),
CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW, CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW,
Ld->getChain()}; Ld->getChain()};
RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
const RISCV::VLEPseudo *P = RISCV::getVLEPseudo( const RISCV::VLEPseudo *P = RISCV::getVLEPseudo(
/*IsMasked*/ false, /*IsStrided*/ true, /*FF*/ false, Log2SEW, /*IsMasked*/ false, /*IsTU*/ false, /*IsStrided*/ true, /*FF*/ false,
static_cast<unsigned>(LMUL)); Log2SEW, static_cast<unsigned>(LMUL));
MachineSDNode *Load = MachineSDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands); CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
if (auto *MemOp = dyn_cast<MemSDNode>(Node)) if (auto *MemOp = dyn_cast<MemSDNode>(Node))
CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()}); CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});
ReplaceNode(Node, Load); ReplaceNode(Node, Load);
return; return;
▲ Show 20 Lines • Show All 489 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,437 Lines • ▼ Show 20 Lines if (Lane >= 0) {
SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(),
TypeSize::Fixed(Offset), DL); TypeSize::Fixed(Offset), DL);
// If this is SEW=64 on RV32, use a strided load with a stride of x0. // If this is SEW=64 on RV32, use a strided load with a stride of x0.
if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { if (SVT.isInteger() && SVT.bitsGT(XLenVT)) {
SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other}); SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
SDValue IntID = SDValue IntID =
DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, XLenVT); DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, XLenVT);
SDValue Ops[] = {Ld->getChain(), IntID, NewAddr, SDValue Ops[] = {Ld->getChain(),
DAG.getRegister(RISCV::X0, XLenVT), VL}; IntID,
DAG.getUNDEF(ContainerVT),
NewAddr,
DAG.getRegister(RISCV::X0, XLenVT),
VL};
SDValue NewLoad = DAG.getMemIntrinsicNode( SDValue NewLoad = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT, ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT,
DAG.getMachineFunction().getMachineMemOperand( DAG.getMachineFunction().getMachineMemOperand(
Ld->getMemOperand(), Offset, SVT.getStoreSize())); Ld->getMemOperand(), Offset, SVT.getStoreSize()));
DAG.makeEquivalentMemoryOrdering(Ld, NewLoad); DAG.makeEquivalentMemoryOrdering(Ld, NewLoad);
return convertFromScalableVector(VT, NewLoad, DAG, Subtarget); return convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
} }
▲ Show 20 Lines • Show All 2,104 Lines • ▼ Show 20 Lines case Intrinsic::riscv_masked_strided_load: {
SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT); SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);
SDValue IntID = DAG.getTargetConstant( SDValue IntID = DAG.getTargetConstant(
IsUnmasked ? Intrinsic::riscv_vlse : Intrinsic::riscv_vlse_mask, DL, IsUnmasked ? Intrinsic::riscv_vlse : Intrinsic::riscv_vlse_mask, DL,
XLenVT); XLenVT);
auto *Load = cast<MemIntrinsicSDNode>(Op); auto *Load = cast<MemIntrinsicSDNode>(Op);
SmallVector<SDValue, 8> Ops{Load->getChain(), IntID}; SmallVector<SDValue, 8> Ops{Load->getChain(), IntID};
if (!IsUnmasked) if (IsUnmasked)
Ops.push_back(DAG.getUNDEF(ContainerVT));
else
Ops.push_back(PassThru); Ops.push_back(PassThru);
Ops.push_back(Op.getOperand(3)); // Ptr Ops.push_back(Op.getOperand(3)); // Ptr
Ops.push_back(Op.getOperand(4)); // Stride Ops.push_back(Op.getOperand(4)); // Stride
if (!IsUnmasked) if (!IsUnmasked)
Ops.push_back(Mask); Ops.push_back(Mask);
Ops.push_back(VL); Ops.push_back(VL);
if (!IsUnmasked) { if (!IsUnmasked) {
SDValue Policy = DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT); SDValue Policy = DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT);
▲ Show 20 Lines • Show All 841 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
} }
if (!VL) if (!VL)
VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
unsigned IntID = unsigned IntID =
IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask; IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
SmallVector<SDValue, 8> Ops{Chain, DAG.getTargetConstant(IntID, DL, XLenVT)}; SmallVector<SDValue, 8> Ops{Chain, DAG.getTargetConstant(IntID, DL, XLenVT)};
if (!IsUnmasked) if (IsUnmasked)
Ops.push_back(DAG.getUNDEF(ContainerVT));
else
Ops.push_back(PassThru); Ops.push_back(PassThru);
Ops.push_back(BasePtr); Ops.push_back(BasePtr);
if (!IsUnmasked) if (!IsUnmasked)
Ops.push_back(Mask); Ops.push_back(Mask);
Ops.push_back(VL); Ops.push_back(VL);
if (!IsUnmasked) if (!IsUnmasked)
Ops.push_back(DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT)); Ops.push_back(DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT));
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
} }
if (!VL) if (!VL)
VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
unsigned IntID = unsigned IntID =
IsUnmasked ? Intrinsic::riscv_vluxei : Intrinsic::riscv_vluxei_mask; IsUnmasked ? Intrinsic::riscv_vluxei : Intrinsic::riscv_vluxei_mask;
SmallVector<SDValue, 8> Ops{Chain, DAG.getTargetConstant(IntID, DL, XLenVT)}; SmallVector<SDValue, 8> Ops{Chain, DAG.getTargetConstant(IntID, DL, XLenVT)};
if (!IsUnmasked) if (IsUnmasked)
Ops.push_back(DAG.getUNDEF(ContainerVT));
else
Ops.push_back(PassThru); Ops.push_back(PassThru);
Ops.push_back(BasePtr); Ops.push_back(BasePtr);
Ops.push_back(Index); Ops.push_back(Index);
if (!IsUnmasked) if (!IsUnmasked)
Ops.push_back(Mask); Ops.push_back(Mask);
Ops.push_back(VL); Ops.push_back(VL);
if (!IsUnmasked) if (!IsUnmasked)
Ops.push_back(DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT)); Ops.push_back(DAG.getTargetConstant(RISCVII::TAIL_AGNOSTIC, DL, XLenVT));
▲ Show 20 Lines • Show All 5,081 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
def RISCVVIntrinsicsTable : GenericTable { def RISCVVIntrinsicsTable : GenericTable {
let FilterClass = "RISCVVIntrinsic"; let FilterClass = "RISCVVIntrinsic";
let CppTypeName = "RISCVVIntrinsicInfo"; let CppTypeName = "RISCVVIntrinsicInfo";
let Fields = ["IntrinsicID", "SplatOperand", "VLOperand"]; let Fields = ["IntrinsicID", "SplatOperand", "VLOperand"];
let PrimaryKey = ["IntrinsicID"]; let PrimaryKey = ["IntrinsicID"];
let PrimaryKeyName = "getRISCVVIntrinsicInfo"; let PrimaryKeyName = "getRISCVVIntrinsicInfo";
} }
class RISCVVLE<bit M, bit Str, bit F, bits<3> S, bits<3> L> { class RISCVVLE<bit M, bit TU, bit Str, bit F, bits<3> S, bits<3> L> {
bits<1> Masked = M; bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Strided = Str; bits<1> Strided = Str;
bits<1> FF = F; bits<1> FF = F;
bits<3> Log2SEW = S; bits<3> Log2SEW = S;
bits<3> LMUL = L; bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME); Pseudo Pseudo = !cast<Pseudo>(NAME);
} }
def RISCVVLETable : GenericTable { def RISCVVLETable : GenericTable {
let FilterClass = "RISCVVLE"; let FilterClass = "RISCVVLE";
let CppTypeName = "VLEPseudo"; let CppTypeName = "VLEPseudo";
let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"]; let Fields = ["Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"]; let PrimaryKey = ["Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVLEPseudo"; let PrimaryKeyName = "getVLEPseudo";
} }
class RISCVVSE<bit M, bit Str, bits<3> S, bits<3> L> { class RISCVVSE<bit M, bit Str, bits<3> S, bits<3> L> {
bits<1> Masked = M; bits<1> Masked = M;
bits<1> Strided = Str; bits<1> Strided = Str;
bits<3> Log2SEW = S; bits<3> Log2SEW = S;
bits<3> LMUL = L; bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME); Pseudo Pseudo = !cast<Pseudo>(NAME);
} }
def RISCVVSETable : GenericTable { def RISCVVSETable : GenericTable {
let FilterClass = "RISCVVSE"; let FilterClass = "RISCVVSE";
let CppTypeName = "VSEPseudo"; let CppTypeName = "VSEPseudo";
let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"]; let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"]; let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVSEPseudo"; let PrimaryKeyName = "getVSEPseudo";
} }
class RISCVVLX_VSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> { class RISCVVLX_VSX<bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> {
bits<1> Masked = M; bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Ordered = O; bits<1> Ordered = O;
bits<3> Log2SEW = S; bits<3> Log2SEW = S;
bits<3> LMUL = L; bits<3> LMUL = L;
bits<3> IndexLMUL = IL; bits<3> IndexLMUL = IL;
Pseudo Pseudo = !cast<Pseudo>(NAME); Pseudo Pseudo = !cast<Pseudo>(NAME);
} }
class RISCVVLX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> : class RISCVVLX<bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> :
RISCVVLX_VSX<M, O, S, L, IL>; RISCVVLX_VSX<M, TU, O, S, L, IL>;
class RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> : class RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> :
RISCVVLX_VSX<M, O, S, L, IL>; RISCVVLX_VSX<M, /*TU*/0, O, S, L, IL>;
class RISCVVLX_VSXTable : GenericTable { class RISCVVLX_VSXTable : GenericTable {
let CppTypeName = "VLX_VSXPseudo"; let CppTypeName = "VLX_VSXPseudo";
let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"]; let Fields = ["Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"]; let PrimaryKey = ["Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
} }
def RISCVVLXTable : RISCVVLX_VSXTable { def RISCVVLXTable : RISCVVLX_VSXTable {
let FilterClass = "RISCVVLX"; let FilterClass = "RISCVVLX";
let PrimaryKeyName = "getVLXPseudo"; let PrimaryKeyName = "getVLXPseudo";
} }
def RISCVVSXTable : RISCVVLX_VSXTable { def RISCVVSXTable : RISCVVLX_VSXTable {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Linesclass VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
let BaseInstr = instr; let BaseInstr = instr;
let VLMul = m.value; let VLMul = m.value;
} }
class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit isFF> : class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit isFF> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>, (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/isFF, log2<EEW>.val, VLMul> { RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/isFF, log2<EEW>.val, VLMul> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW, bit isFF> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/isFF, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUSLoadMask<VReg RetClass, int EEW, bit isFF> : class VPseudoUSLoadMask<VReg RetClass, int EEW, bit isFF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, (ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1, GPR:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/isFF, log2<EEW>.val, VLMul> { RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/isFF, log2<EEW>.val, VLMul> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = "$rd = $merge"; let Constraints = "$rd = $merge";
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoSLoadNoMask<VReg RetClass, int EEW>: class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>, (ins GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> { RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoSLoadMask<VReg RetClass, int EEW>: class VPseudoSLoadMask<VReg RetClass, int EEW>:
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, (ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1, GPR:$rs2, GPR:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> { RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = "$rd = $merge"; let Constraints = "$rd = $merge";
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL, class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>: bit Ordered, bit EarlyClobber>:
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>, (ins GPR:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, log2<EEW>.val, VLMul, LMUL> { RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", ""); let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>:
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL, class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>: bit Ordered, bit EarlyClobber>:
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, (ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1, IdxClass:$rs2, GPR:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, log2<EEW>.val, VLMul, LMUL> { RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge"); let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
▲ Show 20 Lines • Show All 618 Lines • ▼ Show 20 Linesmulticlass VPseudoUSLoad {
foreach eew = EEWList in { foreach eew = EEWList in {
foreach lmul = MxSet<eew>.m in { foreach lmul = MxSet<eew>.m in {
defvar LInfo = lmul.MX; defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass; defvar vreg = lmul.vrclass;
let VLMul = lmul.value in { let VLMul = lmul.value in {
def "E" # eew # "_V_" # LInfo : def "E" # eew # "_V_" # LInfo :
VPseudoUSLoadNoMask<vreg, eew, false>, VPseudoUSLoadNoMask<vreg, eew, false>,
VLESched<eew>; VLESched<eew>;
def "E" # eew # "_V_" # LInfo # "_TU":
VPseudoUSLoadNoMaskTU<vreg, eew, false>,
VLESched<eew>;
def "E" # eew # "_V_" # LInfo # "_MASK" : def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoUSLoadMask<vreg, eew, false>, VPseudoUSLoadMask<vreg, eew, false>,
VLESched<eew>; VLESched<eew>;
} }
} }
} }
} }
multiclass VPseudoFFLoad { multiclass VPseudoFFLoad {
foreach eew = EEWList in { foreach eew = EEWList in {
foreach lmul = MxSet<eew>.m in { foreach lmul = MxSet<eew>.m in {
defvar LInfo = lmul.MX; defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass; defvar vreg = lmul.vrclass;
let VLMul = lmul.value in { let VLMul = lmul.value in {
def "E" # eew # "FF_V_" # LInfo : def "E" # eew # "FF_V_" # LInfo :
VPseudoUSLoadNoMask<vreg, eew, true>, VPseudoUSLoadNoMask<vreg, eew, true>,
VLFSched<eew>; VLFSched<eew>;
def "E" # eew # "FF_V_" # LInfo # "_TU":
VPseudoUSLoadNoMaskTU<vreg, eew, true>,
VLFSched<eew>;
def "E" # eew # "FF_V_" # LInfo # "_MASK" : def "E" # eew # "FF_V_" # LInfo # "_MASK" :
VPseudoUSLoadMask<vreg, eew, true>, VPseudoUSLoadMask<vreg, eew, true>,
VLFSched<eew>; VLFSched<eew>;
} }
} }
} }
} }
multiclass VPseudoLoadMask { multiclass VPseudoLoadMask {
foreach mti = AllMasks in { foreach mti = AllMasks in {
let VLMul = mti.LMul.value in { let VLMul = mti.LMul.value in {
def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1, /*isFF*/0>; def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1, /*isFF*/0>;
} }
} }
} }
multiclass VPseudoSLoad { multiclass VPseudoSLoad {
foreach eew = EEWList in { foreach eew = EEWList in {
foreach lmul = MxSet<eew>.m in { foreach lmul = MxSet<eew>.m in {
defvar LInfo = lmul.MX; defvar LInfo = lmul.MX;
defvar vreg = lmul.vrclass; defvar vreg = lmul.vrclass;
let VLMul = lmul.value in { let VLMul = lmul.value in {
def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>, def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,
VLSSched<eew>; VLSSched<eew>;
def "E" # eew # "_V_" # LInfo # "_TU": VPseudoSLoadNoMaskTU<vreg, eew>,
VLSSched<eew>;
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSLoadMask<vreg, eew>, def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSLoadMask<vreg, eew>,
VLSSched<eew>; VLSSched<eew>;
} }
} }
} }
} }
multiclass VPseudoILoad<bit Ordered> { multiclass VPseudoILoad<bit Ordered> {
Show All 10 Lines foreach sew = EEWList in {
defvar Vreg = lmul.vrclass; defvar Vreg = lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass; defvar IdxVreg = idx_lmul.vrclass;
defvar HasConstraint = !ne(sew, eew); defvar HasConstraint = !ne(sew, eew);
defvar Order = !if(Ordered, "O", "U"); defvar Order = !if(Ordered, "O", "U");
let VLMul = lmul.value in { let VLMul = lmul.value in {
def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo : def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>, VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
VLXSched<eew, Order>; VLXSched<eew, Order>;
def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_TU":
VPseudoILoadNoMaskTU<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
VLXSched<eew, Order>;
def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>, VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
VLXSched<eew, Order>; VLXSched<eew, Order>;
} }
} }
} }
} }
} }
▲ Show 20 Lines • Show All 3,609 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_vsetvlimax_opt_e64m4: ; CHECK-LABEL: test_vsetvlimax_opt_e64m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 3, i32 2) %vl = call i32 @llvm.riscv.vsetvlimax.opt.i32(i32 3, i32 2)
ret i32 %vl ret i32 %vl
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32>*, i32) declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32>, <vscale x 4 x i32>*, i32)
; Check that we remove the redundant vsetvli when followed by another operation ; Check that we remove the redundant vsetvli when followed by another operation
define <vscale x 4 x i32> @redundant_vsetvli(i32 %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @redundant_vsetvli(i32 %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: redundant_vsetvli: ; CHECK-LABEL: redundant_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call i32 @llvm.riscv.vsetvli.i32(i32 %avl, i32 2, i32 1) %vl = call i32 @llvm.riscv.vsetvli.i32(i32 %avl, i32 2, i32 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32>* %ptr, i32 %vl) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, i32 %vl)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
; Check that we remove the repeated/redundant vsetvli when followed by another ; Check that we remove the repeated/redundant vsetvli when followed by another
; operation ; operation
; FIXME: We don't catch the second vsetvli because it has a use of its output. ; FIXME: We don't catch the second vsetvli because it has a use of its output.
; We could replace it with the output of the first vsetvli. ; We could replace it with the output of the first vsetvli.
define <vscale x 4 x i32> @repeated_vsetvli(i32 %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @repeated_vsetvli(i32 %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: repeated_vsetvli: ; CHECK-LABEL: repeated_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl0 = call i32 @llvm.riscv.vsetvli.i32(i32 %avl, i32 2, i32 1) %vl0 = call i32 @llvm.riscv.vsetvli.i32(i32 %avl, i32 2, i32 1)
%vl1 = call i32 @llvm.riscv.vsetvli.i32(i32 %vl0, i32 2, i32 1) %vl1 = call i32 @llvm.riscv.vsetvli.i32(i32 %vl0, i32 2, i32 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32>* %ptr, i32 %vl1) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i32(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, i32 %vl1)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }

llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_vsetvlimax_opt_e64m4: ; CHECK-LABEL: test_vsetvlimax_opt_e64m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 3, i64 2) %vl = call i64 @llvm.riscv.vsetvlimax.opt.i64(i64 3, i64 2)
ret i64 %vl ret i64 %vl
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>*, i64) declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>*, i64)
; Check that we remove the redundant vsetvli when followed by another operation ; Check that we remove the redundant vsetvli when followed by another operation
define <vscale x 4 x i32> @redundant_vsetvli(i64 %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @redundant_vsetvli(i64 %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: redundant_vsetvli: ; CHECK-LABEL: redundant_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 2, i64 1) %vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 2, i64 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>* %ptr, i64 %vl) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, i64 %vl)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
; Check that we remove the repeated/redundant vsetvli when followed by another ; Check that we remove the repeated/redundant vsetvli when followed by another
; operation ; operation
; FIXME: We don't catch the second vsetvli because it has a use of its output. ; FIXME: We don't catch the second vsetvli because it has a use of its output.
; We could replace it with the output of the first vsetvli. ; We could replace it with the output of the first vsetvli.
define <vscale x 4 x i32> @repeated_vsetvli(i64 %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @repeated_vsetvli(i64 %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: repeated_vsetvli: ; CHECK-LABEL: repeated_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl0 = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 2, i64 1) %vl0 = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 2, i64 1)
%vl1 = call i64 @llvm.riscv.vsetvli.i64(i64 %vl0, i64 2, i64 1) %vl1 = call i64 @llvm.riscv.vsetvli.i64(i64 %vl0, i64 2, i64 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32>* %ptr, i64 %vl1) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, i64 %vl1)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Linesentry:
store i32 0, i32* %retval, align 4 store i32 0, i32* %retval, align 4
%0 = bitcast [4 x i32]* %input to i8* %0 = bitcast [4 x i32]* %input to i8*
call void @llvm.memset.p0i8.i64(i8* align 4 %0, i8 0, i64 16, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %0, i8 0, i64 16, i1 false)
%1 = call i64 @llvm.riscv.vsetvli.i64(i64 4, i64 2, i64 3) %1 = call i64 @llvm.riscv.vsetvli.i64(i64 4, i64 2, i64 3)
store i64 %1, i64* %vl, align 8 store i64 %1, i64* %vl, align 8
%arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %input, i64 0, i64 0 %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %input, i64 0, i64 0
%2 = load i64, i64* %vl, align 8 %2 = load i64, i64* %vl, align 8
%3 = bitcast i32* %arraydecay to <vscale x 16 x i32>* %3 = bitcast i32* %arraydecay to <vscale x 16 x i32>*
%4 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>* %3, i64 %2) %4 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i32>* %3, i64 %2)
store <vscale x 16 x i32> %4, <vscale x 16 x i32>* %v0, align 4 store <vscale x 16 x i32> %4, <vscale x 16 x i32>* %v0, align 4
store i32 1, i32* %x0, align 4 store i32 1, i32* %x0, align 4
store i32 1, i32* %x1, align 4 store i32 1, i32* %x1, align 4
store i32 1, i32* %x2, align 4 store i32 1, i32* %x2, align 4
store i32 1, i32* %x3, align 4 store i32 1, i32* %x3, align 4
store i32 1, i32* %x4, align 4 store i32 1, i32* %x4, align 4
store i32 1, i32* %x5, align 4 store i32 1, i32* %x5, align 4
store i32 1, i32* %x6, align 4 store i32 1, i32* %x6, align 4
Show All 26 Linesentry:
call void @lots_args(i32 signext %16, i32 signext %17, <vscale x 16 x i32> %18, i32 signext %19, i32 signext %20, i32 signext %21, i32 signext %22, i32 signext %23, i32 %24, i32 %25, i32 %26) call void @lots_args(i32 signext %16, i32 signext %17, <vscale x 16 x i32> %18, i32 signext %19, i32 signext %20, i32 signext %21, i32 signext %22, i32 signext %23, i32 %24, i32 %25, i32 %26)
ret i32 0 ret i32 0
} }
declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>* nocapture, i64) declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>* nocapture, i64)
attributes #0 = { noinline nounwind optnone "frame-pointer"="all" } attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64
declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*,
iXLen);
define <vscale x 1 x i8> @intrinsic_vle_v_tu_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vle_v_tu_nxv1i8_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vle_v_tu_nxv1i8_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8>* %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vlse(
<vscale x 1 x i8>,
<vscale x 1 x i8>*,
iXLen,
iXLen);
define <vscale x 1 x i8> @intrinsic_vlse_v_tu(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, iXLen %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vlse_v_tu:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a2, e8, mf8, tu, mu
; RV32-NEXT: vlse8.v v8, (a0), a1
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vlse_v_tu:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a2, e8, mf8, tu, mu
; RV64-NEXT: vlse8.v v8, (a0), a1
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vlse(
<vscale x 1 x i8> %0,
<vscale x 1 x i8>* %1,
iXLen %2,
iXLen %3)
ret <vscale x 1 x i8> %a
}
declare { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff(
<vscale x 1 x i8>,
<vscale x 1 x i8>*,
iXLen);
define <vscale x 1 x i8> @intrinsic_vleff_v_tu(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, iXLen %2, iXLen* %3) nounwind {
; RV32-LABEL: intrinsic_vleff_v_tu:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV32-NEXT: vle8ff.v v8, (a0)
; RV32-NEXT: csrr a0, vl
; RV32-NEXT: sw a0, 0(a2)
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vleff_v_tu:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV64-NEXT: vle8ff.v v8, (a0)
; RV64-NEXT: csrr a0, vl
; RV64-NEXT: sd a0, 0(a2)
; RV64-NEXT: ret
entry:
%a = call { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff(
<vscale x 1 x i8> %0,
<vscale x 1 x i8>* %1,
iXLen %2)
%b = extractvalue { <vscale x 1 x i8>, iXLen } %a, 0
%c = extractvalue { <vscale x 1 x i8>, iXLen } %a, 1
store iXLen %c, iXLen* %3
ret <vscale x 1 x i8> %b
}
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vloxei_v_tu_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vloxei_v_tu_nxv1i8_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV32-NEXT: vloxei8.v v8, (a0), v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vloxei_v_tu_nxv1i8_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV64-NEXT: vloxei8.v v8, (a0), v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8>* %1,
<vscale x 1 x i8> %2,
iXLen %3)
ret <vscale x 1 x i8> %a
}

llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+zfh \ ; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+zfh \
; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: -mattr=+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64>* %1, <vscale x 1 x i64>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64(
<vscale x 2 x i64>* %1, <vscale x 2 x i64>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64(
<vscale x 4 x i64>* %1, <vscale x 4 x i64>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64(
<vscale x 8 x i64>* %1, <vscale x 8 x i64>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i32); i32);
define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1) nounwind { define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64(
<vscale x 1 x double>* %1, <vscale x 1 x double>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i32); i32);
define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1) nounwind { define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64(
<vscale x 2 x double>* %1, <vscale x 2 x double>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i32); i32);
define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1) nounwind { define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64(
<vscale x 4 x double>* %1, <vscale x 4 x double>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i32); i32);
define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1) nounwind { define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 14 Lines %a = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64(
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
<vscale x 1 x i32>* %1, <vscale x 1 x i32>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32(
<vscale x 2 x i32>* %1, <vscale x 2 x i32>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32(
<vscale x 4 x i32>* %1, <vscale x 4 x i32>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32(
<vscale x 8 x i32>* %1, <vscale x 8 x i32>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32(
<vscale x 16 x i32>* %1, <vscale x 16 x i32>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i32); i32);
define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1) nounwind { define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32(
<vscale x 1 x float>* %1, <vscale x 1 x float>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i32); i32);
define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1) nounwind { define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32(
<vscale x 2 x float>* %1, <vscale x 2 x float>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i32); i32);
define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1) nounwind { define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32(
<vscale x 4 x float>* %1, <vscale x 4 x float>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i32); i32);
define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1) nounwind { define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32(
<vscale x 8 x float>* %1, <vscale x 8 x float>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i32); i32);
define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1) nounwind { define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i32 %1) i32 %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32(
<vscale x 16 x float>* %1, <vscale x 16 x float>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16(
<vscale x 1 x i16>* %1, <vscale x 1 x i16>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16(
<vscale x 2 x i16>* %1, <vscale x 2 x i16>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16(
<vscale x 4 x i16>* %1, <vscale x 4 x i16>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16(
<vscale x 8 x i16>* %1, <vscale x 8 x i16>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16(
<vscale x 16 x i16>* %1, <vscale x 16 x i16>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16(
<vscale x 32 x i16>* %1, <vscale x 32 x i16>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i32); i32);
define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i32 %1) nounwind { define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16(
<vscale x 1 x half>* %1, <vscale x 1 x half>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i32); i32);
define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i32 %1) nounwind { define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16(
<vscale x 2 x half>* %1, <vscale x 2 x half>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i32); i32);
define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i32 %1) nounwind { define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16(
<vscale x 4 x half>* %1, <vscale x 4 x half>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i32); i32);
define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i32 %1) nounwind { define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16(
<vscale x 8 x half>* %1, <vscale x 8 x half>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i32); i32);
define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i32 %1) nounwind { define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16(
<vscale x 16 x half>* %1, <vscale x 16 x half>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i32); i32);
define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i32 %1) nounwind { define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i32 %1) i32 %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16(
<vscale x 32 x half>* %1, <vscale x 32 x half>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8(
<vscale x 1 x i8>* %1, <vscale x 1 x i8>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8(
<vscale x 2 x i8>* %1, <vscale x 2 x i8>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8(
<vscale x 4 x i8>* %1, <vscale x 4 x i8>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8(
<vscale x 8 x i8>* %1, <vscale x 8 x i8>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8(
<vscale x 16 x i8>* %1, <vscale x 16 x i8>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8(
<vscale x 32 x i8>* %1, <vscale x 32 x i8>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+zfh \
; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: -mattr=+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64>* %1, <vscale x 1 x i64>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64(
<vscale x 2 x i64>* %1, <vscale x 2 x i64>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64(
<vscale x 4 x i64>* %1, <vscale x 4 x i64>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64(
<vscale x 8 x i64>* %1, <vscale x 8 x i64>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i64); i64);
define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1) nounwind { define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64(
<vscale x 1 x double>* %1, <vscale x 1 x double>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i64); i64);
define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1) nounwind { define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64(
<vscale x 2 x double>* %1, <vscale x 2 x double>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i64); i64);
define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1) nounwind { define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64(
<vscale x 4 x double>* %1, <vscale x 4 x double>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i64); i64);
define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1) nounwind { define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 14 Lines %a = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64(
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(
<vscale x 1 x i32>* %1, <vscale x 1 x i32>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32(
<vscale x 2 x i32>* %1, <vscale x 2 x i32>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32(
<vscale x 4 x i32>* %1, <vscale x 4 x i32>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32(
<vscale x 8 x i32>* %1, <vscale x 8 x i32>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32(
<vscale x 16 x i32>* %1, <vscale x 16 x i32>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i64); i64);
define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1) nounwind { define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32(
<vscale x 1 x float>* %1, <vscale x 1 x float>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i64); i64);
define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1) nounwind { define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32(
<vscale x 2 x float>* %1, <vscale x 2 x float>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i64); i64);
define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1) nounwind { define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32(
<vscale x 4 x float>* %1, <vscale x 4 x float>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i64); i64);
define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1) nounwind { define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32(
<vscale x 8 x float>* %1, <vscale x 8 x float>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i64); i64);
define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1) nounwind { define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i64 %1) i64 %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32(
<vscale x 16 x float>* %1, <vscale x 16 x float>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16(
<vscale x 1 x i16>* %1, <vscale x 1 x i16>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16(
<vscale x 2 x i16>* %1, <vscale x 2 x i16>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16(
<vscale x 4 x i16>* %1, <vscale x 4 x i16>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16(
<vscale x 8 x i16>* %1, <vscale x 8 x i16>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16(
<vscale x 16 x i16>* %1, <vscale x 16 x i16>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16(
<vscale x 32 x i16>* %1, <vscale x 32 x i16>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i64); i64);
define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i64 %1) nounwind { define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16(
<vscale x 1 x half>* %1, <vscale x 1 x half>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i64); i64);
define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i64 %1) nounwind { define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16(
<vscale x 2 x half>* %1, <vscale x 2 x half>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i64); i64);
define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i64 %1) nounwind { define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16(
<vscale x 4 x half>* %1, <vscale x 4 x half>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i64); i64);
define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i64 %1) nounwind { define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16(
<vscale x 8 x half>* %1, <vscale x 8 x half>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i64); i64);
define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i64 %1) nounwind { define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16(
<vscale x 16 x half>* %1, <vscale x 16 x half>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i64); i64);
define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i64 %1) nounwind { define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i64 %1) i64 %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16(
<vscale x 32 x half>* %1, <vscale x 32 x half>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8(
<vscale x 1 x i8>* %1, <vscale x 1 x i8>* %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8(
<vscale x 2 x i8>* %1, <vscale x 2 x i8>* %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8(
<vscale x 4 x i8>* %1, <vscale x 4 x i8>* %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8(
<vscale x 8 x i8>* %1, <vscale x 8 x i8>* %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8(
<vscale x 16 x i8>* %1, <vscale x 16 x i8>* %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8(
<vscale x 32 x i8>* %1, <vscale x 32 x i8>* %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare { <vscale x 1 x i64>, i32 } @llvm.riscv.vleff.nxv1i64( declare { <vscale x 1 x i64>, i32 } @llvm.riscv.vleff.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i64>, i32 } @llvm.riscv.vleff.nxv1i64( %a = call { <vscale x 1 x i64>, i32 } @llvm.riscv.vleff.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i64>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i64>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
declare { <vscale x 2 x i64>, i32 } @llvm.riscv.vleff.nxv2i64( declare { <vscale x 2 x i64>, i32 } @llvm.riscv.vleff.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i64>, i32 } @llvm.riscv.vleff.nxv2i64( %a = call { <vscale x 2 x i64>, i32 } @llvm.riscv.vleff.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i64>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x i64> %b ret <vscale x 2 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i64>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x i64> %b ret <vscale x 2 x i64> %b
} }
declare { <vscale x 4 x i64>, i32 } @llvm.riscv.vleff.nxv4i64( declare { <vscale x 4 x i64>, i32 } @llvm.riscv.vleff.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i64>, i32 } @llvm.riscv.vleff.nxv4i64( %a = call { <vscale x 4 x i64>, i32 } @llvm.riscv.vleff.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i64>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x i64> %b ret <vscale x 4 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i64>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x i64> %b ret <vscale x 4 x i64> %b
} }
declare { <vscale x 8 x i64>, i32 } @llvm.riscv.vleff.nxv8i64( declare { <vscale x 8 x i64>, i32 } @llvm.riscv.vleff.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i64>, i32 } @llvm.riscv.vleff.nxv8i64( %a = call { <vscale x 8 x i64>, i32 } @llvm.riscv.vleff.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i64>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x i64> %b ret <vscale x 8 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i64>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i64>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i64>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i64>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x i64> %b ret <vscale x 8 x i64> %b
} }
declare { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64( declare { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i32); i32);
define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x double>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x double>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
declare { <vscale x 2 x double>, i32 } @llvm.riscv.vleff.nxv2f64( declare { <vscale x 2 x double>, i32 } @llvm.riscv.vleff.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i32); i32);
define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x double>, i32 } @llvm.riscv.vleff.nxv2f64( %a = call { <vscale x 2 x double>, i32 } @llvm.riscv.vleff.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x double>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x double> %b ret <vscale x 2 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x double>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x double> %b ret <vscale x 2 x double> %b
} }
declare { <vscale x 4 x double>, i32 } @llvm.riscv.vleff.nxv4f64( declare { <vscale x 4 x double>, i32 } @llvm.riscv.vleff.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i32); i32);
define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x double>, i32 } @llvm.riscv.vleff.nxv4f64( %a = call { <vscale x 4 x double>, i32 } @llvm.riscv.vleff.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x double>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x double> %b ret <vscale x 4 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x double>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x double> %b ret <vscale x 4 x double> %b
} }
declare { <vscale x 8 x double>, i32 } @llvm.riscv.vleff.nxv8f64( declare { <vscale x 8 x double>, i32 } @llvm.riscv.vleff.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i32); i32);
define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x double>, i32 } @llvm.riscv.vleff.nxv8f64( %a = call { <vscale x 8 x double>, i32 } @llvm.riscv.vleff.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x double>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x double> %b ret <vscale x 8 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x double>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x double>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x double>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x double> %b ret <vscale x 8 x double> %b
} }
declare { <vscale x 1 x i32>, i32 } @llvm.riscv.vleff.nxv1i32( declare { <vscale x 1 x i32>, i32 } @llvm.riscv.vleff.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i32>, i32 } @llvm.riscv.vleff.nxv1i32( %a = call { <vscale x 1 x i32>, i32 } @llvm.riscv.vleff.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i32>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x i32> %b ret <vscale x 1 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i32>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x i32> %b ret <vscale x 1 x i32> %b
} }
declare { <vscale x 2 x i32>, i32 } @llvm.riscv.vleff.nxv2i32( declare { <vscale x 2 x i32>, i32 } @llvm.riscv.vleff.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i32>, i32 } @llvm.riscv.vleff.nxv2i32( %a = call { <vscale x 2 x i32>, i32 } @llvm.riscv.vleff.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i32>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x i32> %b ret <vscale x 2 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i32>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x i32> %b ret <vscale x 2 x i32> %b
} }
declare { <vscale x 4 x i32>, i32 } @llvm.riscv.vleff.nxv4i32( declare { <vscale x 4 x i32>, i32 } @llvm.riscv.vleff.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i32>, i32 } @llvm.riscv.vleff.nxv4i32( %a = call { <vscale x 4 x i32>, i32 } @llvm.riscv.vleff.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i32>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x i32> %b ret <vscale x 4 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i32>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x i32> %b ret <vscale x 4 x i32> %b
} }
declare { <vscale x 8 x i32>, i32 } @llvm.riscv.vleff.nxv8i32( declare { <vscale x 8 x i32>, i32 } @llvm.riscv.vleff.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i32>, i32 } @llvm.riscv.vleff.nxv8i32( %a = call { <vscale x 8 x i32>, i32 } @llvm.riscv.vleff.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i32>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x i32> %b ret <vscale x 8 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i32>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x i32> %b ret <vscale x 8 x i32> %b
} }
declare { <vscale x 16 x i32>, i32 } @llvm.riscv.vleff.nxv16i32( declare { <vscale x 16 x i32>, i32 } @llvm.riscv.vleff.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1, i32* %2) nounwind { define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i32>, i32 } @llvm.riscv.vleff.nxv16i32( %a = call { <vscale x 16 x i32>, i32 } @llvm.riscv.vleff.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 16 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i32>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 16 x i32> %b ret <vscale x 16 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i32>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i32>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i32>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i32>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 16 x i32> %b ret <vscale x 16 x i32> %b
} }
declare { <vscale x 1 x float>, i32 } @llvm.riscv.vleff.nxv1f32( declare { <vscale x 1 x float>, i32 } @llvm.riscv.vleff.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i32); i32);
define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x float>, i32 } @llvm.riscv.vleff.nxv1f32( %a = call { <vscale x 1 x float>, i32 } @llvm.riscv.vleff.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x float>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x float>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
declare { <vscale x 2 x float>, i32 } @llvm.riscv.vleff.nxv2f32( declare { <vscale x 2 x float>, i32 } @llvm.riscv.vleff.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i32); i32);
define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x float>, i32 } @llvm.riscv.vleff.nxv2f32( %a = call { <vscale x 2 x float>, i32 } @llvm.riscv.vleff.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x float>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x float> %b ret <vscale x 2 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x float>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x float> %b ret <vscale x 2 x float> %b
} }
declare { <vscale x 4 x float>, i32 } @llvm.riscv.vleff.nxv4f32( declare { <vscale x 4 x float>, i32 } @llvm.riscv.vleff.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i32); i32);
define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x float>, i32 } @llvm.riscv.vleff.nxv4f32( %a = call { <vscale x 4 x float>, i32 } @llvm.riscv.vleff.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x float>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x float> %b ret <vscale x 4 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x float>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x float> %b ret <vscale x 4 x float> %b
} }
declare { <vscale x 8 x float>, i32 } @llvm.riscv.vleff.nxv8f32( declare { <vscale x 8 x float>, i32 } @llvm.riscv.vleff.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i32); i32);
define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x float>, i32 } @llvm.riscv.vleff.nxv8f32( %a = call { <vscale x 8 x float>, i32 } @llvm.riscv.vleff.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x float>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x float> %b ret <vscale x 8 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x float>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x float> %b ret <vscale x 8 x float> %b
} }
declare { <vscale x 16 x float>, i32 } @llvm.riscv.vleff.nxv16f32( declare { <vscale x 16 x float>, i32 } @llvm.riscv.vleff.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i32); i32);
define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1, i32* %2) nounwind { define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x float>, i32 } @llvm.riscv.vleff.nxv16f32( %a = call { <vscale x 16 x float>, i32 } @llvm.riscv.vleff.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 16 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x float>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 16 x float> %b ret <vscale x 16 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x float>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x float>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x float>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x float>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 16 x float> %b ret <vscale x 16 x float> %b
} }
declare { <vscale x 1 x i16>, i32 } @llvm.riscv.vleff.nxv1i16( declare { <vscale x 1 x i16>, i32 } @llvm.riscv.vleff.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i16>, i32 } @llvm.riscv.vleff.nxv1i16( %a = call { <vscale x 1 x i16>, i32 } @llvm.riscv.vleff.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x i16> %b ret <vscale x 1 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x i16> %b ret <vscale x 1 x i16> %b
} }
declare { <vscale x 2 x i16>, i32 } @llvm.riscv.vleff.nxv2i16( declare { <vscale x 2 x i16>, i32 } @llvm.riscv.vleff.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i16>, i32 } @llvm.riscv.vleff.nxv2i16( %a = call { <vscale x 2 x i16>, i32 } @llvm.riscv.vleff.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x i16> %b ret <vscale x 2 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x i16> %b ret <vscale x 2 x i16> %b
} }
declare { <vscale x 4 x i16>, i32 } @llvm.riscv.vleff.nxv4i16( declare { <vscale x 4 x i16>, i32 } @llvm.riscv.vleff.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i16>, i32 } @llvm.riscv.vleff.nxv4i16( %a = call { <vscale x 4 x i16>, i32 } @llvm.riscv.vleff.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x i16> %b ret <vscale x 4 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x i16> %b ret <vscale x 4 x i16> %b
} }
declare { <vscale x 8 x i16>, i32 } @llvm.riscv.vleff.nxv8i16( declare { <vscale x 8 x i16>, i32 } @llvm.riscv.vleff.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i16>, i32 } @llvm.riscv.vleff.nxv8i16( %a = call { <vscale x 8 x i16>, i32 } @llvm.riscv.vleff.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x i16> %b ret <vscale x 8 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x i16> %b ret <vscale x 8 x i16> %b
} }
declare { <vscale x 16 x i16>, i32 } @llvm.riscv.vleff.nxv16i16( declare { <vscale x 16 x i16>, i32 } @llvm.riscv.vleff.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i16>, i32 } @llvm.riscv.vleff.nxv16i16( %a = call { <vscale x 16 x i16>, i32 } @llvm.riscv.vleff.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 16 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 16 x i16> %b ret <vscale x 16 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 16 x i16> %b ret <vscale x 16 x i16> %b
} }
declare { <vscale x 32 x i16>, i32 } @llvm.riscv.vleff.nxv32i16( declare { <vscale x 32 x i16>, i32 } @llvm.riscv.vleff.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1, i32* %2) nounwind { define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x i16>, i32 } @llvm.riscv.vleff.nxv32i16( %a = call { <vscale x 32 x i16>, i32 } @llvm.riscv.vleff.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 32 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x i16>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 32 x i16> %b ret <vscale x 32 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x i16>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x i16>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x i16>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x i16>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 32 x i16> %b ret <vscale x 32 x i16> %b
} }
declare { <vscale x 1 x half>, i32 } @llvm.riscv.vleff.nxv1f16( declare { <vscale x 1 x half>, i32 } @llvm.riscv.vleff.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i32); i32);
define <vscale x 1 x half> @intrinsic_vleff_v_nxv1half_nxv1f16(<vscale x 1 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x half> @intrinsic_vleff_v_nxv1half_nxv1f16(<vscale x 1 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1half_nxv1f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv1half_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x half>, i32 } @llvm.riscv.vleff.nxv1f16( %a = call { <vscale x 1 x half>, i32 } @llvm.riscv.vleff.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
declare { <vscale x 2 x half>, i32 } @llvm.riscv.vleff.nxv2f16( declare { <vscale x 2 x half>, i32 } @llvm.riscv.vleff.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i32); i32);
define <vscale x 2 x half> @intrinsic_vleff_v_nxv2half_nxv2f16(<vscale x 2 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x half> @intrinsic_vleff_v_nxv2half_nxv2f16(<vscale x 2 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2half_nxv2f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv2half_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x half>, i32 } @llvm.riscv.vleff.nxv2f16( %a = call { <vscale x 2 x half>, i32 } @llvm.riscv.vleff.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x half> %b ret <vscale x 2 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x half> %b ret <vscale x 2 x half> %b
} }
declare { <vscale x 4 x half>, i32 } @llvm.riscv.vleff.nxv4f16( declare { <vscale x 4 x half>, i32 } @llvm.riscv.vleff.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i32); i32);
define <vscale x 4 x half> @intrinsic_vleff_v_nxv4half_nxv4f16(<vscale x 4 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x half> @intrinsic_vleff_v_nxv4half_nxv4f16(<vscale x 4 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4half_nxv4f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv4half_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x half>, i32 } @llvm.riscv.vleff.nxv4f16( %a = call { <vscale x 4 x half>, i32 } @llvm.riscv.vleff.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x half> %b ret <vscale x 4 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x half> %b ret <vscale x 4 x half> %b
} }
declare { <vscale x 8 x half>, i32 } @llvm.riscv.vleff.nxv8f16( declare { <vscale x 8 x half>, i32 } @llvm.riscv.vleff.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i32); i32);
define <vscale x 8 x half> @intrinsic_vleff_v_nxv8half_nxv8f16(<vscale x 8 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x half> @intrinsic_vleff_v_nxv8half_nxv8f16(<vscale x 8 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8half_nxv8f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv8half_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x half>, i32 } @llvm.riscv.vleff.nxv8f16( %a = call { <vscale x 8 x half>, i32 } @llvm.riscv.vleff.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x half> %b ret <vscale x 8 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x half> %b ret <vscale x 8 x half> %b
} }
declare { <vscale x 16 x half>, i32 } @llvm.riscv.vleff.nxv16f16( declare { <vscale x 16 x half>, i32 } @llvm.riscv.vleff.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i32); i32);
define <vscale x 16 x half> @intrinsic_vleff_v_nxv16half_nxv16f16(<vscale x 16 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 16 x half> @intrinsic_vleff_v_nxv16half_nxv16f16(<vscale x 16 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16half_nxv16f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv16half_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x half>, i32 } @llvm.riscv.vleff.nxv16f16( %a = call { <vscale x 16 x half>, i32 } @llvm.riscv.vleff.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 16 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 16 x half> %b ret <vscale x 16 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 16 x half> %b ret <vscale x 16 x half> %b
} }
declare { <vscale x 32 x half>, i32 } @llvm.riscv.vleff.nxv32f16( declare { <vscale x 32 x half>, i32 } @llvm.riscv.vleff.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i32); i32);
define <vscale x 32 x half> @intrinsic_vleff_v_nxv32half_nxv32f16(<vscale x 32 x half>* %0, i32 %1, i32* %2) nounwind { define <vscale x 32 x half> @intrinsic_vleff_v_nxv32half_nxv32f16(<vscale x 32 x half>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32half_nxv32f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv32half_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x half>, i32 } @llvm.riscv.vleff.nxv32f16( %a = call { <vscale x 32 x half>, i32 } @llvm.riscv.vleff.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 32 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x half>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 32 x half> %b ret <vscale x 32 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x half>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x half>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x half>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x half>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 32 x half> %b ret <vscale x 32 x half> %b
} }
declare { <vscale x 1 x i8>, i32 } @llvm.riscv.vleff.nxv1i8( declare { <vscale x 1 x i8>, i32 } @llvm.riscv.vleff.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i8>, i32 } @llvm.riscv.vleff.nxv1i8( %a = call { <vscale x 1 x i8>, i32 } @llvm.riscv.vleff.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 1 x i8> %b ret <vscale x 1 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 1 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 1 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 1 x i8> %b ret <vscale x 1 x i8> %b
} }
declare { <vscale x 2 x i8>, i32 } @llvm.riscv.vleff.nxv2i8( declare { <vscale x 2 x i8>, i32 } @llvm.riscv.vleff.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i8>, i32 } @llvm.riscv.vleff.nxv2i8( %a = call { <vscale x 2 x i8>, i32 } @llvm.riscv.vleff.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 2 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 2 x i8> %b ret <vscale x 2 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 2 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 2 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 2 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 2 x i8> %b ret <vscale x 2 x i8> %b
} }
declare { <vscale x 4 x i8>, i32 } @llvm.riscv.vleff.nxv4i8( declare { <vscale x 4 x i8>, i32 } @llvm.riscv.vleff.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i8>, i32 } @llvm.riscv.vleff.nxv4i8( %a = call { <vscale x 4 x i8>, i32 } @llvm.riscv.vleff.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 4 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 4 x i8> %b ret <vscale x 4 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 4 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 4 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 4 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 4 x i8> %b ret <vscale x 4 x i8> %b
} }
declare { <vscale x 8 x i8>, i32 } @llvm.riscv.vleff.nxv8i8( declare { <vscale x 8 x i8>, i32 } @llvm.riscv.vleff.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i8>, i32 } @llvm.riscv.vleff.nxv8i8( %a = call { <vscale x 8 x i8>, i32 } @llvm.riscv.vleff.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 8 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 8 x i8> %b ret <vscale x 8 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 8 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 8 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 8 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 8 x i8> %b ret <vscale x 8 x i8> %b
} }
declare { <vscale x 16 x i8>, i32 } @llvm.riscv.vleff.nxv16i8( declare { <vscale x 16 x i8>, i32 } @llvm.riscv.vleff.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i8>, i32 } @llvm.riscv.vleff.nxv16i8( %a = call { <vscale x 16 x i8>, i32 } @llvm.riscv.vleff.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 16 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 16 x i8> %b ret <vscale x 16 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 16 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 16 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 16 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 16 x i8> %b ret <vscale x 16 x i8> %b
} }
declare { <vscale x 32 x i8>, i32 } @llvm.riscv.vleff.nxv32i8( declare { <vscale x 32 x i8>, i32 } @llvm.riscv.vleff.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x i8>, i32 } @llvm.riscv.vleff.nxv32i8( %a = call { <vscale x 32 x i8>, i32 } @llvm.riscv.vleff.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 32 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 32 x i8> %b ret <vscale x 32 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 32 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 32 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 32 x i8>, i32 } %a, 1
store i32 %c, i32* %4 store i32 %c, i32* %4
ret <vscale x 32 x i8> %b ret <vscale x 32 x i8> %b
} }
declare { <vscale x 64 x i8>, i32 } @llvm.riscv.vleff.nxv64i8( declare { <vscale x 64 x i8>, i32 } @llvm.riscv.vleff.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1, i32* %2) nounwind { define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 64 x i8>, i32 } @llvm.riscv.vleff.nxv64i8( %a = call { <vscale x 64 x i8>, i32 } @llvm.riscv.vleff.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 64 x i8>, i32 } %a, 0 %b = extractvalue { <vscale x 64 x i8>, i32 } %a, 0
%c = extractvalue { <vscale x 64 x i8>, i32 } %a, 1 %c = extractvalue { <vscale x 64 x i8>, i32 } %a, 1
store i32 %c, i32* %2 store i32 %c, i32* %2
ret <vscale x 64 x i8> %b ret <vscale x 64 x i8> %b
} }
Show All 29 Lines
define <vscale x 1 x double> @intrinsic_vleff_dead_vl(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind { define <vscale x 1 x double> @intrinsic_vleff_dead_vl(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_dead_vl: ; CHECK-LABEL: intrinsic_vleff_dead_vl:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x double>, i32 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i32 } %a, 0
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
define <vscale x 1 x double> @intrinsic_vleff_mask_dead_vl(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vleff_mask_dead_vl(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vleff_mask_dead_vl: ; CHECK-LABEL: intrinsic_vleff_mask_dead_vl:
Show All 18 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1) i32 %1)
%b = extractvalue { <vscale x 1 x double>, i32 } %a, 1 %b = extractvalue { <vscale x 1 x double>, i32 } %a, 1
store i32 %b, i32* %2 store i32 %b, i32* %2
ret void ret void
} }
define void @intrinsic_vleff_mask_dead_value(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3, i32* %4) nounwind { define void @intrinsic_vleff_mask_dead_value(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3, i32* %4) nounwind {
Show All 20 Lines
define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind { define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i32 %1, i32* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_dead_all: ; CHECK-LABEL: intrinsic_vleff_dead_all:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1) i32 %1)
ret void ret void
} }
define void @intrinsic_vleff_mask_dead_all(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define void @intrinsic_vleff_mask_dead_all(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vleff_mask_dead_all: ; CHECK-LABEL: intrinsic_vleff_mask_dead_all:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64( declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64( %a = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i64>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i64>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64( declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64( %a = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i64>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x i64> %b ret <vscale x 2 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i64>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x i64> %b ret <vscale x 2 x i64> %b
} }
declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64( declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64( %a = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i64>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x i64> %b ret <vscale x 4 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i64>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x i64> %b ret <vscale x 4 x i64> %b
} }
declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64( declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64( %a = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i64>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x i64> %b ret <vscale x 8 x i64> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i64>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i64>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i64>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i64>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x i64> %b ret <vscale x 8 x i64> %b
} }
declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64( declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i64); i64);
define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x double>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x double>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64( declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i64); i64);
define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64( %a = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x double>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x double> %b ret <vscale x 2 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x double>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x double> %b ret <vscale x 2 x double> %b
} }
declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64( declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i64); i64);
define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64( %a = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x double>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x double> %b ret <vscale x 4 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x double>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x double> %b ret <vscale x 4 x double> %b
} }
declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64( declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i64); i64);
define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64( %a = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x double>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x double> %b ret <vscale x 8 x double> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x double>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x double>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x double>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x double> %b ret <vscale x 8 x double> %b
} }
declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32( declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32( %a = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i32>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x i32> %b ret <vscale x 1 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i32>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x i32> %b ret <vscale x 1 x i32> %b
} }
declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32( declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32( %a = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i32>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x i32> %b ret <vscale x 2 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i32>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x i32> %b ret <vscale x 2 x i32> %b
} }
declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32( declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32( %a = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i32>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x i32> %b ret <vscale x 4 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i32>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x i32> %b ret <vscale x 4 x i32> %b
} }
declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32( declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32( %a = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i32>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x i32> %b ret <vscale x 8 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i32>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x i32> %b ret <vscale x 8 x i32> %b
} }
declare { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32( declare { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1, i64* %2) nounwind { define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32( %a = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 16 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i32>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 16 x i32> %b ret <vscale x 16 x i32> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i32>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i32>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i32>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i32>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 16 x i32> %b ret <vscale x 16 x i32> %b
} }
declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32( declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i64); i64);
define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32( %a = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x float>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x float>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x float> %b ret <vscale x 1 x float> %b
} }
declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32( declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i64); i64);
define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32( %a = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x float>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x float> %b ret <vscale x 2 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x float>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x float> %b ret <vscale x 2 x float> %b
} }
declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32( declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i64); i64);
define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32( %a = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x float>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x float> %b ret <vscale x 4 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x float>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x float> %b ret <vscale x 4 x float> %b
} }
declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32( declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i64); i64);
define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32( %a = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x float>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x float> %b ret <vscale x 8 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x float>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x float> %b ret <vscale x 8 x float> %b
} }
declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32( declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i64); i64);
define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1, i64* %2) nounwind { define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: vle32ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32( %a = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 16 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x float>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 16 x float> %b ret <vscale x 16 x float> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x float>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x float>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x float>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x float>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 16 x float> %b ret <vscale x 16 x float> %b
} }
declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16( declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16( %a = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x i16> %b ret <vscale x 1 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x i16> %b ret <vscale x 1 x i16> %b
} }
declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16( declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16( %a = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x i16> %b ret <vscale x 2 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x i16> %b ret <vscale x 2 x i16> %b
} }
declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16( declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16( %a = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x i16> %b ret <vscale x 4 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x i16> %b ret <vscale x 4 x i16> %b
} }
declare { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16( declare { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16( %a = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x i16> %b ret <vscale x 8 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x i16> %b ret <vscale x 8 x i16> %b
} }
declare { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16( declare { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16( %a = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 16 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 16 x i16> %b ret <vscale x 16 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 16 x i16> %b ret <vscale x 16 x i16> %b
} }
declare { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16( declare { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1, i64* %2) nounwind { define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16( %a = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 32 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x i16>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 32 x i16> %b ret <vscale x 32 x i16> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x i16>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x i16>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x i16>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x i16>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 32 x i16> %b ret <vscale x 32 x i16> %b
} }
declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16( declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i64); i64);
define <vscale x 1 x half> @intrinsic_vleff_v_nxv1half_nxv1f16(<vscale x 1 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x half> @intrinsic_vleff_v_nxv1half_nxv1f16(<vscale x 1 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1half_nxv1f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv1half_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16( %a = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x half> %b ret <vscale x 1 x half> %b
} }
declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16( declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i64); i64);
define <vscale x 2 x half> @intrinsic_vleff_v_nxv2half_nxv2f16(<vscale x 2 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x half> @intrinsic_vleff_v_nxv2half_nxv2f16(<vscale x 2 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2half_nxv2f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv2half_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16( %a = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x half> %b ret <vscale x 2 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x half> %b ret <vscale x 2 x half> %b
} }
declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16( declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i64); i64);
define <vscale x 4 x half> @intrinsic_vleff_v_nxv4half_nxv4f16(<vscale x 4 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x half> @intrinsic_vleff_v_nxv4half_nxv4f16(<vscale x 4 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4half_nxv4f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv4half_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16( %a = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x half> %b ret <vscale x 4 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x half> %b ret <vscale x 4 x half> %b
} }
declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16( declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i64); i64);
define <vscale x 8 x half> @intrinsic_vleff_v_nxv8half_nxv8f16(<vscale x 8 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x half> @intrinsic_vleff_v_nxv8half_nxv8f16(<vscale x 8 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8half_nxv8f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv8half_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16( %a = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x half> %b ret <vscale x 8 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x half> %b ret <vscale x 8 x half> %b
} }
declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16( declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i64); i64);
define <vscale x 16 x half> @intrinsic_vleff_v_nxv16half_nxv16f16(<vscale x 16 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 16 x half> @intrinsic_vleff_v_nxv16half_nxv16f16(<vscale x 16 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16half_nxv16f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv16half_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16( %a = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 16 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 16 x half> %b ret <vscale x 16 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 16 x half> %b ret <vscale x 16 x half> %b
} }
declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16( declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i64); i64);
define <vscale x 32 x half> @intrinsic_vleff_v_nxv32half_nxv32f16(<vscale x 32 x half>* %0, i64 %1, i64* %2) nounwind { define <vscale x 32 x half> @intrinsic_vleff_v_nxv32half_nxv32f16(<vscale x 32 x half>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32half_nxv32f16: ; CHECK-LABEL: intrinsic_vleff_v_nxv32half_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: vle16ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16( %a = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 32 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x half>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 32 x half> %b ret <vscale x 32 x half> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x half>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x half>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x half>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x half>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 32 x half> %b ret <vscale x 32 x half> %b
} }
declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8( declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8( %a = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 1 x i8> %b ret <vscale x 1 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 1 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 1 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 1 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 1 x i8> %b ret <vscale x 1 x i8> %b
} }
declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8( declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8( %a = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 2 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 2 x i8> %b ret <vscale x 2 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 2 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 2 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 2 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 2 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 2 x i8> %b ret <vscale x 2 x i8> %b
} }
declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8( declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8( %a = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 4 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 4 x i8> %b ret <vscale x 4 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 4 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 4 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 4 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 4 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 4 x i8> %b ret <vscale x 4 x i8> %b
} }
declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8( declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8( %a = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 8 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 8 x i8> %b ret <vscale x 8 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 8 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 8 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 8 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 8 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 8 x i8> %b ret <vscale x 8 x i8> %b
} }
declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8( declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8( %a = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 16 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 16 x i8> %b ret <vscale x 16 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 16 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 16 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 16 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 16 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 16 x i8> %b ret <vscale x 16 x i8> %b
} }
declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8( declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8( %a = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 32 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 32 x i8> %b ret <vscale x 32 x i8> %b
} }
Show All 21 Linesentry:
%b = extractvalue { <vscale x 32 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 32 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 32 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 32 x i8>, i64 } %a, 1
store i64 %c, i64* %4 store i64 %c, i64* %4
ret <vscale x 32 x i8> %b ret <vscale x 32 x i8> %b
} }
declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8( declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1, i64* %2) nounwind { define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1, i64* %2) nounwind {
; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: vle8ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8( %a = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 64 x i8>, i64 } %a, 0 %b = extractvalue { <vscale x 64 x i8>, i64 } %a, 0
%c = extractvalue { <vscale x 64 x i8>, i64 } %a, 1 %c = extractvalue { <vscale x 64 x i8>, i64 } %a, 1
store i64 %c, i64* %2 store i64 %c, i64* %2
ret <vscale x 64 x i8> %b ret <vscale x 64 x i8> %b
} }
Show All 29 Lines
define <vscale x 1 x double> @intrinsic_vleff_dead_vl(<vscale x 1 x double>* %0, i64 %1) nounwind { define <vscale x 1 x double> @intrinsic_vleff_dead_vl(<vscale x 1 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vleff_dead_vl: ; CHECK-LABEL: intrinsic_vleff_dead_vl:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x double>, i64 } %a, 0 %b = extractvalue { <vscale x 1 x double>, i64 } %a, 0
ret <vscale x 1 x double> %b ret <vscale x 1 x double> %b
} }
define <vscale x 1 x double> @intrinsic_vleff_mask_dead_vl(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vleff_mask_dead_vl(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vleff_mask_dead_vl: ; CHECK-LABEL: intrinsic_vleff_mask_dead_vl:
Show All 18 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1) i64 %1)
%b = extractvalue { <vscale x 1 x double>, i64 } %a, 1 %b = extractvalue { <vscale x 1 x double>, i64 } %a, 1
store i64 %b, i64* %2 store i64 %b, i64* %2
ret void ret void
} }
define void @intrinsic_vleff_mask_dead_value(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3, i64* %4) nounwind { define void @intrinsic_vleff_mask_dead_value(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3, i64* %4) nounwind {
Show All 20 Lines
define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i64 %1) nounwind { define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vleff_dead_all: ; CHECK-LABEL: intrinsic_vleff_dead_all:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64( %a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1) i64 %1)
ret void ret void
} }
define void @intrinsic_vleff_mask_dead_all(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define void @intrinsic_vleff_mask_dead_all(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vleff_mask_dead_all: ; CHECK-LABEL: intrinsic_vleff_mask_dead_all:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16( %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8(
Show All 17 Lines %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei64.v v9, (a0), v8 ; CHECK-NEXT: vloxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei64.v v10, (a0), v8 ; CHECK-NEXT: vloxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei64.v v12, (a0), v8 ; CHECK-NEXT: vloxei64.v v12, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v12 ; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei64.v v16, (a0), v8 ; CHECK-NEXT: vloxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei64.v v9, (a0), v8 ; CHECK-NEXT: vloxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei64.v v10, (a0), v8 ; CHECK-NEXT: vloxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei64.v v12, (a0), v8 ; CHECK-NEXT: vloxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei64.v v16, (a0), v8 ; CHECK-NEXT: vloxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei64.v v9, (a0), v8 ; CHECK-NEXT: vloxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei64.v v10, (a0), v8 ; CHECK-NEXT: vloxei64.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei64.v v12, (a0), v8 ; CHECK-NEXT: vloxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei64.v v16, (a0), v8 ; CHECK-NEXT: vloxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei64.v v9, (a0), v8 ; CHECK-NEXT: vloxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei64.v v10, (a0), v8 ; CHECK-NEXT: vloxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei64.v v12, (a0), v8 ; CHECK-NEXT: vloxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei64.v v16, (a0), v8 ; CHECK-NEXT: vloxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei64.v v9, (a0), v8 ; CHECK-NEXT: vloxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei64.v v10, (a0), v8 ; CHECK-NEXT: vloxei64.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei64.v v12, (a0), v8 ; CHECK-NEXT: vloxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei64.v v16, (a0), v8 ; CHECK-NEXT: vloxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: vloxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: vloxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei32.v v9, (a0), v8 ; CHECK-NEXT: vloxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei32.v v10, (a0), v8 ; CHECK-NEXT: vloxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei32.v v12, (a0), v8 ; CHECK-NEXT: vloxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei32.v v16, (a0), v8 ; CHECK-NEXT: vloxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16( %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: vloxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei16.v v9, (a0), v8 ; CHECK-NEXT: vloxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei16.v v10, (a0), v8 ; CHECK-NEXT: vloxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei16.v v12, (a0), v8 ; CHECK-NEXT: vloxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei16.v v16, (a0), v8 ; CHECK-NEXT: vloxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: vloxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8(
Show All 17 Lines %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8( %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8( %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8( %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8( %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8( %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei8.v v9, (a0), v8 ; CHECK-NEXT: vloxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8( %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vloxei8.v v10, (a0), v8 ; CHECK-NEXT: vloxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8( %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vloxei8.v v12, (a0), v8 ; CHECK-NEXT: vloxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8( %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vloxei8.v v16, (a0), v8 ; CHECK-NEXT: vloxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8( %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i32, i32,
i32); i32);
define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i32, i32,
i32); i32);
define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i32, i32,
i32); i32);
define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i32, i32,
i32); i32);
define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32(
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i32, i32,
i32); i32);
define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i32, i32,
i32); i32);
define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i32, i32,
i32); i32);
define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i32, i32,
i32); i32);
define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i32, i32,
i32); i32);
define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32(
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i32, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i32, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i32, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i32, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i32, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16(
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i32, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16(
i32 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i32, i32,
i32); i32);
define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i32, i32,
i32); i32);
define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i32, i32,
i32); i32);
define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i32, i32,
i32); i32);
define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i32, i32,
i32); i32);
define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16(
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i32, i32,
i32); i32);
define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i32 %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16(
i32 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i32, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8(
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i32, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8(
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i32, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8(
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i32, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8(
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i32, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8(
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i32, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8(
i32 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i32, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
i64, i64,
i64); i64);
define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
i64, i64,
i64); i64);
define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
i64, i64,
i64); i64);
define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
i64, i64,
i64); i64);
define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: vlse64.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
i64, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
i64, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
i64, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
i64, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
i64, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32(
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
i64, i64,
i64); i64);
define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
i64, i64,
i64); i64);
define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
i64, i64,
i64); i64);
define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
i64, i64,
i64); i64);
define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
i64, i64,
i64); i64);
define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: vlse32.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32(
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
i64, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
i64, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
i64, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
i64, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
i64, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16(
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
i64, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16(
i64 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
i64, i64,
i64); i64);
define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
i64, i64,
i64); i64);
define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
i64, i64,
i64); i64);
define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
i64, i64,
i64); i64);
define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
i64, i64,
i64); i64);
define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16(
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
i64, i64,
i64); i64);
define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i64 %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: vlse16.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16(
i64 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
i64, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8(
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
i64, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8(
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
i64, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8(
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
i64, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8(
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
i64, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8(
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
i64, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8(
i64 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
i64, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: vlse8.v v8, (a0), a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16( %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(
Show All 17 Lines %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+f,+d -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei64.v v9, (a0), v8 ; CHECK-NEXT: vluxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei64.v v10, (a0), v8 ; CHECK-NEXT: vluxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei64.v v12, (a0), v8 ; CHECK-NEXT: vluxei64.v v12, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v12 ; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei64.v v16, (a0), v8 ; CHECK-NEXT: vluxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei64.v v9, (a0), v8 ; CHECK-NEXT: vluxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei64.v v10, (a0), v8 ; CHECK-NEXT: vluxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei64.v v12, (a0), v8 ; CHECK-NEXT: vluxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei64.v v16, (a0), v8 ; CHECK-NEXT: vluxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei64.v v9, (a0), v8 ; CHECK-NEXT: vluxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei64.v v10, (a0), v8 ; CHECK-NEXT: vluxei64.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei64.v v12, (a0), v8 ; CHECK-NEXT: vluxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei64.v v16, (a0), v8 ; CHECK-NEXT: vluxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei64.v v9, (a0), v8 ; CHECK-NEXT: vluxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei64.v v10, (a0), v8 ; CHECK-NEXT: vluxei64.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei64.v v12, (a0), v8 ; CHECK-NEXT: vluxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei64.v v16, (a0), v8 ; CHECK-NEXT: vluxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei64.v v9, (a0), v8 ; CHECK-NEXT: vluxei64.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei64.v v10, (a0), v8 ; CHECK-NEXT: vluxei64.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei64.v v12, (a0), v8 ; CHECK-NEXT: vluxei64.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei64.v v16, (a0), v8 ; CHECK-NEXT: vluxei64.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64(
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64(
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64(
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v8 ; CHECK-NEXT: vluxei64.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v8 ; CHECK-NEXT: vluxei32.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei32.v v9, (a0), v8 ; CHECK-NEXT: vluxei32.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei32.v v10, (a0), v8 ; CHECK-NEXT: vluxei32.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei32.v v12, (a0), v8 ; CHECK-NEXT: vluxei32.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei32.v v16, (a0), v8 ; CHECK-NEXT: vluxei32.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16( %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16( declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei16.v v8, (a0), v8 ; CHECK-NEXT: vluxei16.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei16.v v9, (a0), v8 ; CHECK-NEXT: vluxei16.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei16.v v10, (a0), v8 ; CHECK-NEXT: vluxei16.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei16.v v12, (a0), v8 ; CHECK-NEXT: vluxei16.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei16.v v16, (a0), v8 ; CHECK-NEXT: vluxei16.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(
Show All 17 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>*, <vscale x 1 x i8>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8>* %0, <vscale x 1 x i8>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>*, <vscale x 2 x i8>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8>* %0, <vscale x 2 x i8>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>*, <vscale x 4 x i8>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8>* %0, <vscale x 4 x i8>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>*, <vscale x 8 x i8>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8>* %0, <vscale x 8 x i8>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>*, <vscale x 16 x i8>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8>* %0, <vscale x 16 x i8>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>*, <vscale x 32 x i8>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8>* %0, <vscale x 32 x i8>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>*, <vscale x 64 x i8>*,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vluxei8.v v8, (a0), v8 ; CHECK-NEXT: vluxei8.v v8, (a0), v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8>* %0, <vscale x 64 x i8>* %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(
Show All 17 Lines %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i16>*, <vscale x 1 x i16>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i16>* %0, <vscale x 1 x i16>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i16>*, <vscale x 2 x i16>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i16>* %0, <vscale x 2 x i16>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i16>*, <vscale x 4 x i16>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i16>* %0, <vscale x 4 x i16>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i16>*, <vscale x 8 x i16>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i16>* %0, <vscale x 8 x i16>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i16>*, <vscale x 16 x i16>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i16>* %0, <vscale x 16 x i16>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i16>*, <vscale x 32 x i16>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i16>* %0, <vscale x 32 x i16>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i32>*, <vscale x 1 x i32>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i32>* %0, <vscale x 1 x i32>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i32>*, <vscale x 2 x i32>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i32>* %0, <vscale x 2 x i32>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i32>*, <vscale x 4 x i32>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i32>* %0, <vscale x 4 x i32>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i32>*, <vscale x 8 x i32>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i32>* %0, <vscale x 8 x i32>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i32>*, <vscale x 16 x i32>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i32>* %0, <vscale x 16 x i32>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0, <vscale x 1 x i64>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i64>*, <vscale x 2 x i64>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i64>* %0, <vscale x 2 x i64>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i64>*, <vscale x 4 x i64>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i64>* %0, <vscale x 4 x i64>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i64>*, <vscale x 8 x i64>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i64>* %0, <vscale x 8 x i64>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x half>*, <vscale x 1 x half>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x half>* %0, <vscale x 1 x half>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x half>*, <vscale x 2 x half>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x half>* %0, <vscale x 2 x half>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x half>*, <vscale x 4 x half>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x half>* %0, <vscale x 4 x half>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x half>*, <vscale x 8 x half>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x half>* %0, <vscale x 8 x half>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x half>*, <vscale x 16 x half>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x half>* %0, <vscale x 16 x half>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x half>*, <vscale x 32 x half>*,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x half>* %0, <vscale x 32 x half>* %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(
Show All 17 Lines %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
<vscale x 1 x float>,
<vscale x 1 x float>*, <vscale x 1 x float>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8( %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
<vscale x 1 x float> undef,
<vscale x 1 x float>* %0, <vscale x 1 x float>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8( declare <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
<vscale x 2 x float>,
<vscale x 2 x float>*, <vscale x 2 x float>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8( %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
<vscale x 2 x float> undef,
<vscale x 2 x float>* %0, <vscale x 2 x float>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8( declare <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
<vscale x 4 x float>,
<vscale x 4 x float>*, <vscale x 4 x float>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8( %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
<vscale x 4 x float> undef,
<vscale x 4 x float>* %0, <vscale x 4 x float>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8( declare <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
<vscale x 8 x float>,
<vscale x 8 x float>*, <vscale x 8 x float>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8( %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
<vscale x 8 x float> undef,
<vscale x 8 x float>* %0, <vscale x 8 x float>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8( declare <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(
Show All 17 Lines %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
<vscale x 16 x float>,
<vscale x 16 x float>*, <vscale x 16 x float>*,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8( %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
<vscale x 16 x float> undef,
<vscale x 16 x float>* %0, <vscale x 16 x float>* %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8( declare <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(
Show All 17 Lines %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
<vscale x 1 x double>,
<vscale x 1 x double>*, <vscale x 1 x double>*,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei8.v v9, (a0), v8 ; CHECK-NEXT: vluxei8.v v9, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8( %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
<vscale x 1 x double> undef,
<vscale x 1 x double>* %0, <vscale x 1 x double>* %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8( declare <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(
Show All 17 Lines %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
<vscale x 2 x double>,
<vscale x 2 x double>*, <vscale x 2 x double>*,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vluxei8.v v10, (a0), v8 ; CHECK-NEXT: vluxei8.v v10, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8( %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
<vscale x 2 x double> undef,
<vscale x 2 x double>* %0, <vscale x 2 x double>* %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8( declare <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(
Show All 17 Lines %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
<vscale x 4 x double>,
<vscale x 4 x double>*, <vscale x 4 x double>*,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vluxei8.v v12, (a0), v8 ; CHECK-NEXT: vluxei8.v v12, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8( %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
<vscale x 4 x double> undef,
<vscale x 4 x double>* %0, <vscale x 4 x double>* %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8( declare <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(
Show All 17 Lines %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
<vscale x 8 x double>,
<vscale x 8 x double>*, <vscale x 8 x double>*,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vluxei8.v v16, (a0), v8 ; CHECK-NEXT: vluxei8.v v16, (a0), v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8( %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
<vscale x 8 x double> undef,
<vscale x 8 x double>* %0, <vscale x 8 x double>* %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8( declare <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Show First 20 Lines • Show All 469 Lines • ▼ Show 20 Linesentry:
br i1 %cmp.not13, label %for.end, label %for.body br i1 %cmp.not13, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%1 = phi i64 [ %7, %for.body ], [ %0, %entry ] %1 = phi i64 [ %7, %for.body ], [ %0, %entry ]
%n.addr.016 = phi i64 [ %sub, %for.body ], [ %n, %entry ] %n.addr.016 = phi i64 [ %sub, %for.body ], [ %n, %entry ]
%x.addr.015 = phi float* [ %add.ptr, %for.body ], [ %x, %entry ] %x.addr.015 = phi float* [ %add.ptr, %for.body ], [ %x, %entry ]
%y.addr.014 = phi float* [ %add.ptr1, %for.body ], [ %y, %entry ] %y.addr.014 = phi float* [ %add.ptr1, %for.body ], [ %y, %entry ]
%2 = bitcast float* %x.addr.015 to <vscale x 16 x float>* %2 = bitcast float* %x.addr.015 to <vscale x 16 x float>*
%3 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>* %2, i64 %1) %3 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %2, i64 %1)
%add.ptr = getelementptr inbounds float, float* %x.addr.015, i64 %1 %add.ptr = getelementptr inbounds float, float* %x.addr.015, i64 %1
%4 = bitcast float* %y.addr.014 to <vscale x 16 x float>* %4 = bitcast float* %y.addr.014 to <vscale x 16 x float>*
%5 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>* %4, i64 %1) %5 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %4, i64 %1)
%6 = tail call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> %5, float %a, <vscale x 16 x float> %3, i64 %1) %6 = tail call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> %5, float %a, <vscale x 16 x float> %3, i64 %1)
tail call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %6, <vscale x 16 x float>* %4, i64 %1) tail call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %6, <vscale x 16 x float>* %4, i64 %1)
%add.ptr1 = getelementptr inbounds float, float* %y.addr.014, i64 %1 %add.ptr1 = getelementptr inbounds float, float* %y.addr.014, i64 %1
%sub = sub i64 %n.addr.016, %1 %sub = sub i64 %n.addr.016, %1
%7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %sub, i64 2, i64 3) %7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %sub, i64 2, i64 3)
%cmp.not = icmp eq i64 %7, 0 %cmp.not = icmp eq i64 %7, 0
br i1 %cmp.not, label %for.end, label %for.body br i1 %cmp.not, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>* nocapture, i64) declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64)
declare <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float>, float, <vscale x 16 x float>, i64) declare <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float>, float, <vscale x 16 x float>, i64)
declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64) declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64)
; We need a vsetvli in the last block because the predecessors have different ; We need a vsetvli in the last block because the predecessors have different
; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so ; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so
; we don't need to read AVL and can keep VL unchanged. ; we don't need to read AVL and can keep VL unchanged.
define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x 2 x i16>* %y, <vscale x 2 x i32> %z, i64 %vl, i1 %cond) nounwind { define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x 2 x i16>* %y, <vscale x 2 x i32> %z, i64 %vl, i1 %cond) nounwind {
; CHECK-LABEL: test_vsetvli_x0_x0: ; CHECK-LABEL: test_vsetvli_x0_x0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: andi a0, a3, 1 ; CHECK-NEXT: andi a0, a3, 1
; CHECK-NEXT: beqz a0, .LBB9_2 ; CHECK-NEXT: beqz a0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %if ; CHECK-NEXT: # %bb.1: # %if
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v10, (a1) ; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vwadd.vx v8, v10, zero ; CHECK-NEXT: vwadd.vx v8, v10, zero
; CHECK-NEXT: .LBB9_2: # %if.end ; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>* %x, i64 %vl) %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %x, i64 %vl)
br i1 %cond, label %if, label %if.end br i1 %cond, label %if, label %if.end
if: if:
%b = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16>* %y, i64 %vl) %b = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16>* %y, i64 %vl)
%c = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32(<vscale x 2 x i16> %b, i16 0, i64 %vl) %c = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32(<vscale x 2 x i16> %b, i16 0, i64 %vl)
br label %if.end br label %if.end
if.end: if.end:
%d = phi <vscale x 2 x i32> [ %z, %entry ], [ %c, %if ] %d = phi <vscale x 2 x i32> [ %z, %entry ], [ %c, %if ]
%e = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %d, i64 %vl) %e = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %d, i64 %vl)
ret <vscale x 2 x i32> %e ret <vscale x 2 x i32> %e
} }
declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>*, i64) declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>*, i64)
declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16>*, i64) declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>*, i64)
declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32(<vscale x 2 x i16>, i16, i64) declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32(<vscale x 2 x i16>, i16, i64)
declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i64) declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i64)
; We can use X0, X0 vsetvli in if2 and if2.end. The merge point as if.end will ; We can use X0, X0 vsetvli in if2 and if2.end. The merge point as if.end will
; see two different vtypes with the same SEW/LMUL ratio. At if2.end we will only ; see two different vtypes with the same SEW/LMUL ratio. At if2.end we will only
; know the SEW/LMUL ratio for the if.end predecessor and the full vtype for ; know the SEW/LMUL ratio for the if.end predecessor and the full vtype for
; the if2 predecessor. This makes sure we can merge a SEW/LMUL predecessor with ; the if2 predecessor. This makes sure we can merge a SEW/LMUL predecessor with
; a predecessor we know the vtype for. ; a predecessor we know the vtype for.
Show All 15 Lines
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v10, (a2) ; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: vwadd.wv v9, v9, v10 ; CHECK-NEXT: vwadd.wv v9, v9, v10
; CHECK-NEXT: .LBB10_4: # %if2.end ; CHECK-NEXT: .LBB10_4: # %if2.end
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>* %x, i64 %vl) %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %x, i64 %vl)
br i1 %cond, label %if, label %if.end br i1 %cond, label %if, label %if.end
if: if:
%b = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16>* %y, i64 %vl) %b = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16>* %y, i64 %vl)
%c = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32> %a, <vscale x 2 x i16> %b, i64 %vl) %c = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32> %a, <vscale x 2 x i16> %b, i64 %vl)
br label %if.end br label %if.end
if.end: if.end:
%d = phi <vscale x 2 x i32> [ %a, %entry ], [ %c, %if ] %d = phi <vscale x 2 x i32> [ %a, %entry ], [ %c, %if ]
br i1 %cond2, label %if2, label %if2.end br i1 %cond2, label %if2, label %if2.end
if2: if2:
%e = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16>* %z, i64 %vl) %e = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16>* %z, i64 %vl)
%f = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32> %d, <vscale x 2 x i16> %e, i64 %vl) %f = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32> %d, <vscale x 2 x i16> %e, i64 %vl)
br label %if2.end br label %if2.end
if2.end: if2.end:
%g = phi <vscale x 2 x i32> [ %d, %if.end ], [ %f, %if2 ] %g = phi <vscale x 2 x i32> [ %d, %if.end ], [ %f, %if2 ]
%h = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> %g, <vscale x 2 x i32> %w, i64 %vl) %h = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> %g, <vscale x 2 x i32> %w, i64 %vl)
ret <vscale x 2 x i32> %h ret <vscale x 2 x i32> %h
} }
declare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) declare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32>, <vscale x 2 x i16>, i64)

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=riscv64 -mattr=v \ # RUN: llc %s -o - -mtriple=riscv64 -mattr=v \
# RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s # RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s
--- | --- |
; ModuleID = 'vsetvli-insert.ll' ; ModuleID = 'vsetvli-insert.ll'
source_filename = "vsetvli-insert.ll" source_filename = "vsetvli-insert.ll"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64" target triple = "riscv64"
define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 { define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* %0, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2)
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
%c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2) %c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ] %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
ret <vscale x 1 x i64> %d ret <vscale x 1 x i64> %d
} }
define void @load_zext_or_sext(i8 zeroext %cond, <vscale x 1 x i32>* %0, <vscale x 1 x i64>* %1, i64 %2) #0 { define void @load_zext_or_sext(i8 zeroext %cond, <vscale x 1 x i32>* %0, <vscale x 1 x i64>* %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* %0, i64 %2) %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %2)
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2)
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
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; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* nocapture, i64) #3 declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #3
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* nocapture, i64) #3 declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #3
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4 declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

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for.cond.cleanup: ; preds = %for.body, %entry for.cond.cleanup: ; preds = %for.body, %entry
ret void ret void
for.body: ; preds = %entry, %for.body for.body: ; preds = %entry, %for.body
%1 = phi i64 [ %8, %for.body ], [ %0, %entry ] %1 = phi i64 [ %8, %for.body ], [ %0, %entry ]
%i.012 = phi i64 [ %add, %for.body ], [ 0, %entry ] %i.012 = phi i64 [ %add, %for.body ], [ 0, %entry ]
%add.ptr = getelementptr inbounds i32, i32* %A, i64 %i.012 %add.ptr = getelementptr inbounds i32, i32* %A, i64 %i.012
%2 = bitcast i32* %add.ptr to <vscale x 2 x i32>* %2 = bitcast i32* %add.ptr to <vscale x 2 x i32>*
%3 = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32>* %2, i64 %1) %3 = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %2, i64 %1)
%4 = tail call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32.i64(<vscale x 2 x i32> %3, i32 -2, i64 %1) %4 = tail call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32.i64(<vscale x 2 x i32> %3, i32 -2, i64 %1)
%5 = tail call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32.i64(<vscale x 2 x i32> %3, i32 2, i64 %1) %5 = tail call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32.i64(<vscale x 2 x i32> %3, i32 2, i64 %1)
%6 = tail call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %4, <vscale x 2 x i1> %5, i64 %1) %6 = tail call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %4, <vscale x 2 x i1> %5, i64 %1)
%add.ptr1 = getelementptr inbounds i32, i32* %B, i64 %i.012 %add.ptr1 = getelementptr inbounds i32, i32* %B, i64 %i.012
%7 = bitcast i32* %add.ptr1 to <vscale x 2 x i32>* %7 = bitcast i32* %add.ptr1 to <vscale x 2 x i32>*
tail call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> %3, <vscale x 2 x i32>* %7, <vscale x 2 x i1> %6, i64 %1) tail call void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32> %3, <vscale x 2 x i32>* %7, <vscale x 2 x i1> %6, i64 %1)
%add = add i64 %1, %i.012 %add = add i64 %1, %i.012
%8 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0) %8 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0)
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(
i64); i64);
declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64 declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64
(<vscale x 1 x double>, (<vscale x 1 x double>,
double, double,
i64) i64)
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32>* nocapture, i64) declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>* nocapture, i64)
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32.i64(<vscale x 2 x i32>, i32, i64) declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32.i64(<vscale x 2 x i32>, i32, i64)
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32.i64(<vscale x 2 x i32>, i32, i64) declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32.i64(<vscale x 2 x i32>, i32, i64)
declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64)
declare void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>* nocapture, <vscale x 2 x i1>, i64) declare void @llvm.riscv.vse.mask.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>* nocapture, <vscale x 2 x i1>, i64)

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

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define <vscale x 1 x i64> @add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 { define <vscale x 1 x i64> @add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @load_add(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 { define <vscale x 1 x i64> @load_add(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* %0, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2)
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
define <vscale x 1 x i64> @load_zext(<vscale x 1 x i32>* %0, i64 %1) #0 { define <vscale x 1 x i64> @load_zext(<vscale x 1 x i32>* %0, i64 %1) #0 {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* %0, i64 %1) %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %1)
%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %1) %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %1)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1 declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 { define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {
Show All 26 Lines--- |
entry: entry:
%a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0) %a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %a) %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %a)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
define <vscale x 1 x i64> @load_add_inlineasm(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 { define <vscale x 1 x i64> @load_add_inlineasm(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* %0, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2)
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* nocapture, i64) #4 declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* nocapture, i64) #4 declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #4
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
attributes #0 = { "target-features"="+v" } attributes #0 = { "target-features"="+v" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nofree nosync nounwind readnone willreturn } attributes #2 = { nofree nosync nounwind readnone willreturn }
attributes #3 = { nounwind } attributes #3 = { nounwind }
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