[RISCV] Support I extension version 2.1

[kito-cheng]

I think this makes us need to consider another issue: Should we support I extension with version 2.1? zifencei and zicsr split from I ext. since 2.1.

RISC-V GNU toolchain site are consider to bump the extension version to newer version in next release, which means will default with I 2.1, A 2.1, F 2.2 and D 2.2.

[luismarques]

In D113237#3110778, @kito-cheng wrote:

Should we support I extension with version 2.1? zifencei and zicsr split from I ext. since 2.1.

I think so.

Should we also support fence.i with RVI 2.0, without zifencei?

[luismarques]

In D113237#3124188, @luismarques wrote:

Should we also support fence.i with RVI 2.0, without zifencei?

Here's a proposed path forwards:

• Patch 1: Add support for RVI 2.1 and related changes. Keep RVI 2.0 as the default.
• Patch 2: Add warnings for uses of the removed fence.i, CSRs and counters when using RVI 2.0 (at least when doing so by default; arguably this should error out instead when explicitly specifying version 2.0.)
• Patch 3: Start defaulting to RVI 2.1. IMO this should only be committed after patch 2 being in effect for a while.

[achieveartificialintelligence]

Update I-ext to Version 2.1

[achieveartificialintelligence]

In D113237#3124232, @luismarques wrote:

In D113237#3124188, @luismarques wrote:

Should we also support fence.i with RVI 2.0, without zifencei?

Here's a proposed path forwards:

• Patch 1: Add support for RVI 2.1 and related changes. Keep RVI 2.0 as the default.
• Patch 2: Add warnings for uses of the removed fence.i, CSRs and counters when using RVI 2.0 (at least when doing so by default; arguably this should error out instead when explicitly specifying version 2.0.)
• Patch 3: Start defaulting to RVI 2.1. IMO this should only be committed after patch 2 being in effect for a while.

I tried to make I-ext imply zifencei, zicsr, and zihintpause automatically. BTW zihintpause is implemented in D93019.

[asb]

In D113237#3172492, @achieveartificialintelligence wrote:

In D113237#3124232, @luismarques wrote:

In D113237#3124188, @luismarques wrote:

Should we also support fence.i with RVI 2.0, without zifencei?

Here's a proposed path forwards:

• Patch 1: Add support for RVI 2.1 and related changes. Keep RVI 2.0 as the default.
• Patch 2: Add warnings for uses of the removed fence.i, CSRs and counters when using RVI 2.0 (at least when doing so by default; arguably this should error out instead when explicitly specifying version 2.0.)
• Patch 3: Start defaulting to RVI 2.1. IMO this should only be committed after patch 2 being in effect for a while.

I tried to make I-ext imply zifencei, zicsr, and zihintpause automatically. BTW zihintpause is implemented in D93019.

It's a fairly minor detail, but I think implying zihintpause automatically is semantically different to what Luis proposed (as zihintpause wasn't in RVI 2.0, it shouldn't be implied by default like zifencei and zicsr should).

Luis' proposed series of patches makes a lot of sense to me, but a complicating factor is I'm not sure we have a super clean way to support different versions of an extension at the same time.

For instance, to make this patch match Luis' suggested "patch 1" you'd need to be able to specify rvi2.1 and then have it not automatically included zifencei and zicsr. Ideally the version emitted in build attributes would stay as 2.0 unless you explicitly selected 2.1 as well. This patch would then also not need to update test cases to include +zifencei and +zicsr.

We should discuss this in the RISC-V LLVM call today.

[kito-cheng]

There is several issue around the default extension version stuffs.

• Should we add -misa-spec= option to Clang/LLVM?
• Behavior for zifencei and zicsr with i 2.0?
• How to encode the extension version in LLVM? by attribute or module flags?

---

Should we add -misa-spec= option to Clang/LLVM?

Here is a long discussion[1] at 2019, at that moment I think we all agree -misa-spec is a good solution,

However it's kind of awkward for this scheme is ISA spec changing the version scheme again after 20191213 release,
it's become NO formal release for long time, just bunch of draft release.

That's means NO -misa-spec version can cover vector, crypto and bit manipulation.

So we might consider different scheme on controlling default version,
or change the semantic of -misa-spec to make it no longer just reference version of RISC-V ISA manual,
maybe we could reference RISC-V profile[2], but the spec still under discussion.

For GNU toolchain land, -misa-spec= already implemented in GNU toolchain about ~ 2yrs,
so I prefer change the semantic to reference version other than version of RISC-V ISA manual
rather than adding new command line option to control that.

[1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aZhMG7NIVTk/m/PTZEaTWiAwAJ
[2] https://github.com/riscv/riscv-profiles

---

Behavior for zifencei and zicsr with i 2.0?

I would suggest still accept i 2.0 with zifencei and zicsr for compatibility,
but NO effect and NO ELF attribute for those two extensions if I is 2.0,
however I don't have strong opinion on this issue.

---

How to encode the extension version in LLVM? by attribute or module flags?

It's kind of LLVM specific implementation issue, RISC-V LLVM use target attribute to
enable/disable specific extension, but we didn't encode version info in target attribute or module flags yet,
there is not too much problem on clang side during parsing arch string, but that cause some problem on ELF
attribute emission, +a means 2.0 or 2.1? +f means 2.0, 2.1 or 2.2? and what the version of i?

i has major change between 2.0 and 2.1, so we might consider adding new target attribute (e.g +i2p1?) to identify the version of i.

But f and d is clarification on the NaN behavior, which is related minor for toolchain, so adding new target attribute to that is kind of ... weird?

f/d 2.0

FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and
rs2 to rd.

f/d 2.2

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write,
respectively, the smaller or larger of rs1 and rs2 to rd. For the purposes of these instructions only,
the value −0.0 is considered to be less than the value +0.0. If both inputs are NaNs, the result is
the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling
NaN inputs set the invalid operation exception flag, even when the result is not NaN.

Anyway, I think here is two possible solution, but I didn't have strong opinion here:

• Add new target attribute for each version.
• Encode whole arch string with explicit version into module flag.

Note: Ext. versions in RISC-V ISA spec 20191213: I 2.1, M 2.0, A 2.1, F 2.2, D 2.2, C 2.0, E 1.9, Zicsr 2.0, Zifencei 2.1

[jrtc27]

Outside of the I/F/D special cases, where F/D don't really matter and I2p0 is just I2p1Zicsr2p0_Zifencei2p0,, I thought the new policy was that ratified extensions would never be changed, only new extensions published, and thus version numbers are basically irrelevant other than to distinguish ratified from pre-ratified?

[achieveartificialintelligence]

Support both i2p0 and i2p1

[asb]

@kito-cheng

In D113237#3183969, @kito-cheng wrote:

Here is a long discussion[1] at 2019, at that moment I think we all agree -misa-spec is a good solution,

However it's kind of awkward for this scheme is ISA spec changing the version scheme again after 20191213 release,
it's become NO formal release for long time, just bunch of draft release.

That's means NO -misa-spec version can cover vector, crypto and bit manipulation.

Thanks for writing all of that up Kito.

I just wanted to check my understanding on this point. It's certainly true that there hasn't been a new ISA manual release for a long time. Are you saying that there won't be a new ISA manual release (using whatever naming scheme) that incorporates the ratified versions of bitmanip, crypto, vector etc?

[kito-cheng]

@jrtc27

Outside of the I/F/D special cases, where F/D don't really matter and I2p0 is just I2p1Zicsr2p0_Zifencei2p0,, I thought the new policy was that ratified extensions would never be changed, only new extensions published, and thus version numbers are basically irrelevant other than to distinguish ratified from pre-ratified?

The I2p0 and I2p1 is the most problem now, and new policy seems intend to add new ratified ext. rather than extend or change, but I guess I just be more conservative here, since the I isn't expect to be changed before it change.

And we are trying to support *real* multi-version on clang/LLVM (e.g. try to support v 0.10 and 1.0 and emit right version on ELF attr.), so we are headache on this issue for a while, but this might not issue to upstream LLVM I guess.

[kito-cheng]

@asb

Are you saying that there won't be a new ISA manual release (using whatever naming scheme) that incorporates the ratified versions of bitmanip, crypto, vector etc?

Oh, I guess I using some word too strong there, here should have some newer release in future, but we don't know the time-frame and release version scheme, maybe I should checked that with other foundation folks, and back to post the updated info here.

That already become a practical problem to GNU toolchain side since upstream GNU toolchain support those extensions who already frozen, and could enable that without version and -meanble-experimental-extension, but for Clang/LLVM side, it's still guarded by -meanble-experimental-extension and require explicitly version, so it's not urgent issue for Clang/LLVM

[khchen]

https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4
RISC-V GNU toolchain are going to bump the default ISA spec to 20191213, which means will default with I 2.1, A 2.1, F 2.2 and D 2.2.
I think it will be good if LLVM could supports I 2.1 and have the same default ISA version with gnu...

@achieveartificialintelligence Do you know what is the relation between your patch and D115921?

clang/lib/Basic/Targets/RISCV.cpp

236

auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, /*IsI2p1=*/ false, Features);

clang/test/Driver/riscv-arch.c

3

could we have a check for -march=rv32i2p1?

[achieveartificialintelligence]

@achieveartificialintelligence Do you know what is the relation between your patch and D115921?

This commit doesn't depend on D115921, but if D115921 is merged, it's a good idea to build on it.

clang/lib/Basic/Targets/RISCV.cpp

bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
 
   return false;
 }
 
 /// Perform initialization based on the user configured set of features.
 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
                                            DiagnosticsEngine &Diags) {
   unsigned XLen = getTriple().isArch64Bit() ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, Features);
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, false, Features);
   if (!ParseResult) {
     std::string Buffer;
     llvm::raw_string_ostream OutputErrMsg(Buffer);
     handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
       OutputErrMsg << ErrMsg.getMessage();
     });
     Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
     return false;

clang/test/Driver/riscv-arch.c

 // RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s \

 // RV32-CVER: error: invalid arch name 'rv32imc5', unsupported
 // RV32-CVER: version number 5 for extension 'c'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32i2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR-MISS %s
 // RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p',
 // RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p1 -### %s \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i2p2 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR1 %s
-// RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
-// RV32-IMINOR1: version number 2.1 for extension 'i'
+// RV32-IMINOR1: error: invalid arch name 'rv32i2p2', unsupported
+// RV32-IMINOR1: version number 2.2 for extension 'i'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ixt2p -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
 // RV32-XMINOR-MISS: error: invalid arch name 'rv32ixt2p',
 // RV32-XMINOR-MISS: minor version number missing after 'p' for extension 'xt'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32ist2p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s

clang/test/Driver/riscv-cpus.c

 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
 // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
 
 // march overwrite mcpu's default march
 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
-// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31"
+// MCPU-MARCH: "-target-feature" "+m" "-target-feature" "+c"
 // MCPU-MARCH: "-target-abi" "ilp32"
 
 // Check interaction between mcpu and mtune, mtune won't affect arch related
 // target feature, but mcpu will.
 //
 // In this case, sifive-e31 is rv32imac, sifive-e76 is rv32imafc, so M-extension
 // should not enabled.
 //

llvm/include/llvm/Support/RISCVISAInfo.h

public:
 
   /// Parse RISCV ISA info from arch string.
   static llvm::Expected<std::unique_ptr<RISCVISAInfo>>
   parseArchString(StringRef Arch, bool EnableExperimentalExtension,
                   bool ExperimentalExtensionVersionCheck = true);
 
   /// Parse RISCV ISA info from feature vector.
   static llvm::Expected<std::unique_ptr<RISCVISAInfo>>
-  parseFeatures(unsigned XLen, const std::vector<std::string> &Features);
+  parseFeatures(unsigned XLen, bool IsI2p1,
+                const std::vector<std::string> &Features);
 
   /// Convert RISCV ISA info to a feature vector.
   void toFeatures(std::vector<StringRef> &Features,
                   std::function<StringRef(const Twine &)> StrAlloc) const;
 
   const OrderedExtensionMap &getExtensions() const { return Exts; };
 
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
+  bool getIsI2p1() const { return IsI2p1; };
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext, unsigned MajorVersion,
                                    unsigned MinorVersion);
 
 private:
   RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0) {}
 
   unsigned XLen;
   unsigned FLen;
+  bool IsI2p1;
 
   OrderedExtensionMap Exts;
 
   void addExtension(StringRef ExtName, unsigned MajorVersion,
                     unsigned MinorVersion);
 
   Error checkDependency();
 
   void updateImplication();
   void updateFLen();
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Support/RISCVISAInfo.cpp

 /// Represents the major and version number components of a RISC-V extension
 struct RISCVExtensionVersion {
   unsigned Major;
   unsigned Minor;
 };
 
 struct RISCVSupportedExtension {
   const char *Name;
-  /// Supported version.
-  RISCVExtensionVersion Version;
+  /// Supported versions.
+  std::array<RISCVExtensionVersion, 2> Versions;
 };
 
 } // end anonymous namespace
 
 static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn";
 
-static const RISCVSupportedExtension SupportedExtensions[] = {
-    {"i", RISCVExtensionVersion{2, 0}},
-    {"e", RISCVExtensionVersion{1, 9}},
-    {"m", RISCVExtensionVersion{2, 0}},
-    {"a", RISCVExtensionVersion{2, 0}},
-    {"f", RISCVExtensionVersion{2, 0}},
-    {"d", RISCVExtensionVersion{2, 0}},
-    {"c", RISCVExtensionVersion{2, 0}},
+const RISCVSupportedExtension SupportedExtensions[] = {
+    {"i", {RISCVExtensionVersion{2, 0}, RISCVExtensionVersion{2, 1}}},
+    {"e", {RISCVExtensionVersion{1, 9}}},
+    {"m", {RISCVExtensionVersion{2, 0}}},
+    {"a", {RISCVExtensionVersion{2, 0}}},
+    {"f", {RISCVExtensionVersion{2, 0}}},
+    {"d", {RISCVExtensionVersion{2, 0}}},
+    {"c", {RISCVExtensionVersion{2, 0}}},
+
+    {"zicsr", {RISCVExtensionVersion{2, 0}}},
+    {"zifencei", {RISCVExtensionVersion{2, 0}}},
 };
 
-static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
-    {"v", RISCVExtensionVersion{0, 10}},
-    {"zba", RISCVExtensionVersion{1, 0}},
-    {"zbb", RISCVExtensionVersion{1, 0}},
-    {"zbc", RISCVExtensionVersion{1, 0}},
-    {"zbe", RISCVExtensionVersion{0, 93}},
-    {"zbf", RISCVExtensionVersion{0, 93}},
-    {"zbm", RISCVExtensionVersion{0, 93}},
-    {"zbp", RISCVExtensionVersion{0, 93}},
-    {"zbr", RISCVExtensionVersion{0, 93}},
-    {"zbs", RISCVExtensionVersion{1, 0}},
-    {"zbt", RISCVExtensionVersion{0, 93}},
+const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
+    {"v", {RISCVExtensionVersion{0, 10}}},
+    {"zba", {RISCVExtensionVersion{1, 0}}},
+    {"zbb", {RISCVExtensionVersion{1, 0}}},
+    {"zbc", {RISCVExtensionVersion{1, 0}}},
+    {"zbe", {RISCVExtensionVersion{0, 93}}},
+    {"zbf", {RISCVExtensionVersion{0, 93}}},
+    {"zbm", {RISCVExtensionVersion{0, 93}}},
+    {"zbp", {RISCVExtensionVersion{0, 93}}},
+    {"zbr", {RISCVExtensionVersion{0, 93}}},
+    {"zbs", {RISCVExtensionVersion{1, 0}}},
+    {"zbt", {RISCVExtensionVersion{0, 93}}},
 
-    {"zvamo", RISCVExtensionVersion{0, 10}},
-    {"zvlsseg", RISCVExtensionVersion{0, 10}},
+    {"zvamo", {RISCVExtensionVersion{0, 10}}},
+    {"zvlsseg", {RISCVExtensionVersion{0, 10}}},
 
-    {"zfhmin", RISCVExtensionVersion{0, 1}},
-    {"zfh", RISCVExtensionVersion{0, 1}},
+    {"zfhmin", {RISCVExtensionVersion{0, 1}}},
+    {"zfh", {RISCVExtensionVersion{0, 1}}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
 
 // This function finds the first character that doesn't belong to a version
 // (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
static Optional<RISCVExtensionVersion> findDefaultVersion(StringRef ExtName) {
   // TODO: We might set default version based on profile or ISA spec.
   for (auto &ExtInfo : {makeArrayRef(SupportedExtensions),
                         makeArrayRef(SupportedExperimentalExtensions)}) {
     auto ExtensionInfoIterator = llvm::find_if(ExtInfo, FindByName(ExtName));
 
     if (ExtensionInfoIterator == ExtInfo.end()) {
       continue;
     }
-    return ExtensionInfoIterator->Version;
+    return ExtensionInfoIterator->Versions.front();
   }
   return None;
 }
 
 void RISCVISAInfo::addExtension(StringRef ExtName, unsigned MajorVersion,
                                 unsigned MinorVersion) {
   RISCVExtensionInfo Ext;
   Ext.ExtName = ExtName.str();

 }
 
 static Optional<RISCVExtensionVersion> isExperimentalExtension(StringRef Ext) {
   auto ExtIterator =
       llvm::find_if(SupportedExperimentalExtensions, FindByName(Ext));
   if (ExtIterator == std::end(SupportedExperimentalExtensions))
     return None;
 
-  return ExtIterator->Version;
+  return ExtIterator->Versions.front();
 }
 
 bool RISCVISAInfo::isSupportedExtensionFeature(StringRef Ext) {
   bool IsExperimental = stripExperimentalPrefix(Ext);
 
   if (IsExperimental)
     return llvm::any_of(SupportedExperimentalExtensions, FindByName(Ext));
   else
     return llvm::any_of(SupportedExtensions, FindByName(Ext));
 }
 
 bool RISCVISAInfo::isSupportedExtension(StringRef Ext) {
   return llvm::any_of(SupportedExtensions, FindByName(Ext)) ||
          llvm::any_of(SupportedExperimentalExtensions, FindByName(Ext));
 }
 
 bool RISCVISAInfo::isSupportedExtension(StringRef Ext, unsigned MajorVersion,
                                         unsigned MinorVersion) {
   auto FindByNameAndVersion = [=](const RISCVSupportedExtension &ExtInfo) {
-    return ExtInfo.Name == Ext && (MajorVersion == ExtInfo.Version.Major) &&
-           (MinorVersion == ExtInfo.Version.Minor);
+    for (const auto &Version : ExtInfo.Versions)
+      if (ExtInfo.Name == Ext && (MajorVersion == Version.Major) &&
+          (MinorVersion == Version.Minor))
+        return true;
+    return false;
   };
   return llvm::any_of(SupportedExtensions, FindByNameAndVersion) ||
          llvm::any_of(SupportedExperimentalExtensions, FindByNameAndVersion);
 }
 
 bool RISCVISAInfo::hasExtension(StringRef Ext) const {
   stripExperimentalPrefix(Ext);
 
bool RISCVISAInfo::compareExtension(const std::string &LHS,
   return LHS < RHS;
 }
 
 void RISCVISAInfo::toFeatures(
     std::vector<StringRef> &Features,
     std::function<StringRef(const Twine &)> StrAlloc) const {
   for (auto &Ext : Exts) {
     StringRef ExtName = Ext.first;
+    unsigned Major = Ext.second.MajorVersion;
+    unsigned Minor = Ext.second.MinorVersion;
 
-    if (ExtName == "i")
+    if (ExtName == "i") {
+      if (Major == 2 && Minor == 0) {
+        Features.push_back("+zicsr");
+        Features.push_back("+zifencei");
+      }
       continue;
+    }
 
     if (ExtName == "zvlsseg") {
       Features.push_back("+experimental-v");
       Features.push_back("+experimental-zvlsseg");
     } else if (ExtName == "zvamo") {
       Features.push_back("+experimental-v");
       Features.push_back("+experimental-zvlsseg");
       Features.push_back("+experimental-zvamo");
static Error getExtensionVersion(StringRef Ext, StringRef In, unsigned &Major,
   std::string Error = "unsupported version number " + std::string(MajorStr);
   if (!MinorStr.empty())
     Error += "." + MinorStr.str();
   Error += " for extension '" + Ext.str() + "'";
   return createStringError(errc::invalid_argument, Error);
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
-RISCVISAInfo::parseFeatures(unsigned XLen,
+RISCVISAInfo::parseFeatures(unsigned XLen, bool IsI2p1,
                             const std::vector<std::string> &Features) {
   assert(XLen == 32 || XLen == 64);
   std::unique_ptr<RISCVISAInfo> ISAInfo(new RISCVISAInfo(XLen));
 
   for (auto &Feature : Features) {
     StringRef ExtName = Feature;
     bool Experimental = false;
     assert(ExtName.size() > 1 && (ExtName[0] == '+' || ExtName[0] == '-'));
     bool Add = ExtName[0] == '+';
     ExtName = ExtName.drop_front(1); // Drop '+' or '-'
     Experimental = stripExperimentalPrefix(ExtName);
     auto ExtensionInfos = Experimental
                               ? makeArrayRef(SupportedExperimentalExtensions)
                               : makeArrayRef(SupportedExtensions);
     auto ExtensionInfoIterator =
         llvm::find_if(ExtensionInfos, FindByName(ExtName));
 
     // Not all features is related to ISA extension, like `relax` or
     // `save-restore`, skip those feature.
     if (ExtensionInfoIterator == ExtensionInfos.end())
       continue;
 
     if (Add)
-      ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
-                            ExtensionInfoIterator->Version.Minor);
+      ISAInfo->addExtension(ExtName,
+                            ExtensionInfoIterator->Versions.front().Major,
+                            ExtensionInfoIterator->Versions.front().Minor);
     else
       ISAInfo->Exts.erase(ExtName.str());
   }
 
+  if (IsI2p1)
+    ISAInfo->addExtension("i", 2, 1);
+
   ISAInfo->updateImplication();
   ISAInfo->updateFLen();
 
   if (Error Result = ISAInfo->checkDependency())
     return std::move(Result);
 
   return std::move(ISAInfo);
 }
if (Baseline == 'g') {
     // No matter which version is given to `g`, we always set imafd to default
     // version since the we don't have clear version scheme for that on
     // ISA spec.
     for (auto Ext : {"i", "m", "a", "f", "d"})
       if (auto Version = findDefaultVersion(Ext))
         ISAInfo->addExtension(Ext, Version->Major, Version->Minor);
       else
         llvm_unreachable("Default extension version not found?");
-  } else
+  } else {
     // Baseline is `i` or `e`
     ISAInfo->addExtension(std::string(1, Baseline), Major, Minor);
+    if (Baseline == 'i' && Major == 2 && Minor == 1)
+      ISAInfo->IsI2p1 = true;
+  }
 
   // Consume the base ISA version number and any '_' between rvxxx and the
   // first extension
   Exts = Exts.drop_front(ConsumeLength);
   Exts.consume_front("_");
 
   // TODO: Use version number when setting target features
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (!ParseResult) {
       return Error(ValueExprLoc, OutputErrMsg.str());
     }
     auto &ISAInfo = *ParseResult;
 
     for (auto Feature : RISCVFeatureKV)
       if (ISAInfo->hasExtension(Feature.Key))
         setFeatureBits(Feature.Value, Feature.Key);
 
+    if (ISAInfo->getIsI2p1())
+      setFeatureBits(RISCV::FeatureI2p1, "i2p1");
+
     if (ISAInfo->getXLen() == 32)
       clearFeatureBits(RISCV::Feature64Bit, "64bit");
     else if (ISAInfo->getXLen() == 64)
       setFeatureBits(RISCV::Feature64Bit, "64bit");
     else
       return Error(ValueExprLoc, "bad arch string " + Arch);
 
     // Then emit the arch string.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

if (STI.hasFeature(RISCV::FeatureRV32E))
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
   else
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
   unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
   std::vector<std::string> FeatureVector;
   RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
 
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+  bool IsI2p1 = STI.hasFeature(RISCV::FeatureI2p1);
+  auto ParseResult =
+      llvm::RISCVISAInfo::parseFeatures(XLen, false, FeatureVector);
   if (!ParseResult) {
     /* Assume any error about features should handled earlier.  */
     consumeError(ParseResult.takeError());
     llvm_unreachable("Parsing feature error when emitTargetAttributes?");
   } else {
     auto &ISAInfo = *ParseResult;
     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
   }

llvm/lib/Target/RISCV/RISCV.td

 def FeatureStdExtZvamo
     : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                        "'Zvamo' (Vector AMO Operations)",
                        [FeatureStdExtV]>;
 def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
                                AssemblerPredicate<(all_of FeatureStdExtZvamo),
                                "'Zvamo' (Vector AMO Operations)">;
 
+def FeatureI2p1
+    : SubtargetFeature<"i2p1", "IsI2p1", "true", "Implements I 2.1">;
+
+def FeatureStdExtZicsr
+    : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+                       "'Zicsr' (Control and Status Register)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+                               AssemblerPredicate<(all_of FeatureStdExtZicsr),
+                               "'Zicsr' (Control and Status Register)">;
+
+def FeatureStdExtZifencei
+    : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+                       "'Zifencei' (Instruction-Fetch Fence)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+                                  AssemblerPredicate<(all_of FeatureStdExtZifencei),
+                                  "'Zifencei' (Instruction-Fetch Fence)">;
+
+def HasI2p0OrZicsr       : Predicate<"Subtarget->HasI2p0OrZicsr()">;
+def HasI2p0OrZifencei    : Predicate<"Subtarget->HasI2p0OrZifencei()">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                        "RV32I Base Instruction Set">;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 }
 
 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = {0b1000,0b0011,0b0011};
 }
 
+let Predicates = [HasI2p0OrZifencei] in
 def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = 0;
 }
 
 def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> {
   let rs1 = 0;

 def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
             Sched<[]> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = 0b110000000000;
 }
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
+let Predicates = [HasI2p0OrZicsr] in {
 def CSRRW : CSR_ir<0b001, "csrrw">;
 def CSRRS : CSR_ir<0b010, "csrrs">;
 def CSRRC : CSR_ir<0b011, "csrrc">;
 
 def CSRRWI : CSR_ii<0b101, "csrrwi">;
 def CSRRSI : CSR_ii<0b110, "csrrsi">;
 def CSRRCI : CSR_ii<0b111, "csrrci">;
+} // Predicates = [HasI2p0OrZicsr]
 
 /// RV64I instructions
 
 let Predicates = [IsRV64] in {
 def LWU   : Load_ri<0b110, "lwu">, Sched<[WriteLDWU, ReadMemBase]>;
 def LD    : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
 def SD    : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
 

 def : InstAlias<"rdtime $rd",    (CSRRS GPR:$rd, TIME.Encoding, X0)>;
 
 let Predicates = [IsRV32] in {
 def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>;
 def : InstAlias<"rdcycleh $rd",   (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>;
 def : InstAlias<"rdtimeh $rd",    (CSRRS GPR:$rd, TIMEH.Encoding, X0)>;
 } // Predicates = [IsRV32]
 
+let Predicates = [HasI2p0OrZicsr] in {
 def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr,      X0)>;
 def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, csr_sysreg:$csr, GPR:$rs)>;
 def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, csr_sysreg:$csr, GPR:$rs)>;
 def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, csr_sysreg:$csr, GPR:$rs)>;
 
 def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
 let EmitPriority = 0 in {
 def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 }
+} // Predicates = [HasI2p0OrZicsr]
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
 let EmitPriority = 0 in {
 def : InstAlias<"lb $rd, (${rs1})",
                 (LB  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lh $rd, (${rs1})",

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
+  bool IsI2p1 = false;
+  bool HasStdExtZicsr = false;
+  bool HasStdExtZifencei = false;
   bool HasStdExtZfhmin = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
public:
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
+  bool hasStdExtZicsr() const { return HasStdExtZicsr; }
+  bool hasStdExtZifencei() const { return HasStdExtZifencei; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
public:
   bool hasVInstructionsF32() const { return HasStdExtV && hasStdExtF(); }
   bool hasVInstructionsF64() const { return HasStdExtV && hasStdExtD(); }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
   unsigned getMaxInterleaveFactor() const {
     return hasVInstructions() ? MaxInterleaveFactor : 1;
   }
 
+  bool HasI2p0OrZicsr() {
+    return (IsI2p1 && HasStdExtZicsr) || (!IsI2p1 && !HasStdExtZicsr);
+  }
+  bool HasI2p0OrZifencei() {
+    return (IsI2p1 && HasStdExtZifencei) || (!IsI2p1 && !HasStdExtZifencei);
+  }
+
 protected:
   // GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 
 public:

llvm/test/MC/RISCV/attribute-arch.s

 ## Arch string without version.
 
 # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
 # RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
 
 .attribute arch, "rv32i"
 # CHECK: attribute      5, "rv32i2p0"
 
 .attribute arch, "rv32i2"
 # CHECK: attribute      5, "rv32i2p0"
 
 .attribute arch, "rv32i2p0"
 # CHECK: attribute      5, "rv32i2p0"
 
+.attribute arch, "rv32i2p1"
+# CHECK: attribute      5, "rv32i2p1"
+
 .attribute arch, "rv32i2_m2"
 # CHECK: attribute      5, "rv32i2p0_m2p0"
 
 .attribute arch, "rv32i2_ma"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0"
 
 .attribute arch, "rv32g"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0"

llvm/test/MC/RISCV/rv32zicsr-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+zicsr < %s 2>&1 | FileCheck %s
+
+# Out of range immediates
+## uimm5
+csrrwi a1, 0x1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+csrrsi t1, 999, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+csrrci x0, 43, -90 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+
+## uimm12
+csrrw a0, -1, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrs a0, 4096, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrs a0, -0xf, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrc a0, 0x1000, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrwi a0, -50, 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+csrrsi a0, 4097, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+csrrci a0, 0xffff, a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+
+# Illegal operand modifier
+## uimm5
+csrrwi a1, 0x1, %hi(b) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+csrrsi t1, 999, %pcrel_hi(3) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+csrrci x0, 43, %pcrel_hi(c) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+csrrsi t1, 999, %pcrel_lo(4) # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+csrrci x0, 43, %pcrel_lo(d) # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+
+## uimm12
+csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrs a0, %lo(a), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrs a0, %hi(2), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrc a0, %hi(b), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
+csrrwi a0, %pcrel_hi(3), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+csrrsi a0, %pcrel_hi(c), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+csrrwi a0, %pcrel_lo(4), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+csrrsi a0, %pcrel_lo(d), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
+
+## named csr in place of uimm12
+csrrw a0, foos, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrs a0, mstatusx, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrs a0, xmstatus, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrc a0, m12status, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrwi a0, mstatus12, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrsi a0, mhpm12counter, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrwi a0, mhpmcounter32, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrsi a0, A, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]

llvm/test/MC/RISCV/rv32zicsr-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
+# CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
+csrrw t0, 0xfff, t1
+# CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1
+# CHECK-ASM: encoding: [0x73,0x94,0xf4,0xff]
+csrrw s0, ~(-4096), s1
+# CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1
+# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00]
+csrrw s0, !0, s1
+# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
+# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
+csrrs s0, 0xc00, x0
+# CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
+# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
+csrrs s3, 0x001, s5
+# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
+# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
+csrrc sp, 0x000, ra
+# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
+# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
+csrrwi a5, 0x000, 0
+# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
+# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff]
+csrrsi t2, 0xfff, 31
+# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
+# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14]
+csrrci t1, 0x140, 5

llvm/test/MC/RISCV/rv32zifencei-valid.s

+# RUN: llvm-mc %s -triple=riscv32  -mattr=+zifencei -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+zifencei -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fence.i
+# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00]
+fence.i