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[RISCV] [1/2] Add IR intrinsic for Zbp extension
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Authored by LevyHsu on Apr 20 2021, 2:15 AM.

Details

Summary

RV32/64:

grev
grevi
gorc
gorci
shfl
shfli
unshfl
unshfli
xperm.n
xperm.b
xperm.h

RV64 ONLY:

grevw
greviw
gorcw
gorciw
shflw
shfli     (For non-existing shfliw)
unshfli   (For non-existing unshfliw)
xperm.w

Diff Detail

Event Timeline

LevyHsu created this revision.Apr 20 2021, 2:15 AM
LevyHsu requested review of this revision.Apr 20 2021, 2:15 AM
craig.topper added inline comments.Apr 20 2021, 12:25 PM
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
33

Line the colons up

742

Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together

938

Put these in the same block that has PatGprImm<riscv_grev

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
93

This immediate is too large to make shfli. It needs to b 4 bits for i32.

127

Same here

llvm/test/MC/RISCV/rv32b-aliases-valid.s
256

This test fails check-llvm because 29 isn't a shfl_uimm on RV32

LevyHsu updated this revision to Diff 339086.EditedApr 20 2021, 7:59 PM

Change Log:

  1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    • Aligned SDNode def for shflw/unshfl/unshflw
    • Reordered def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
    • Merged Pat def when Predicates = [HasStdExtZbp]
  1. llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll llvm/test/MC/RISCV/rv32b-aliases-valid.s llvm/test/MC/RISCV/rv64b-aliases-valid.s clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
    • Replaced all imm from 29 to 4
LevyHsu updated this revision to Diff 339105.EditedApr 20 2021, 11:22 PM
LevyHsu marked 6 inline comments as done.
  • clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  • clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  • llvm/test/MC/RISCV/rv32b-aliases-valid.s
  • llvm/test/MC/RISCV/rv64b-aliases-valid.s
  • llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  • llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

Changed imm in the test cases to 13 so it's 4bit 1101 and won't be lower to other instructions.

LevyHsu updated this revision to Diff 339138.Apr 21 2021, 1:45 AM
  1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    • Fix format issue with clang-format
LevyHsu updated this revision to Diff 339150.Apr 21 2021, 2:33 AM

Fix format in RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN

This revision is now accepted and ready to land.Apr 21 2021, 7:28 PM
This revision was automatically updated to reflect the committed changes.
LevyHsu edited the summary of this revision. (Show Details)Thu, Jun 10, 8:38 PM