[RISCV] [1/2] Add IR intrinsic for Zbp extension

[LevyHsu]

Summary

RV32/64:

grev
grevi
gorc
gorci
shfl
shfli
unshfl
unshfli
xperm.n
xperm.b
xperm.h

RV64 ONLY:

grevw
greviw
gorcw
gorciw
shflw
shfli     (For non-existing shfliw)
unshfli   (For non-existing unshfliw)
xperm.w

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

33

Line the colons up

758

Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together

954

Put these in the same block that has PatGprImm<riscv_grev

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

93

This immediate is too large to make shfli. It needs to b 4 bits for i32.

127

Same here

llvm/test/MC/RISCV/rv32b-aliases-valid.s

256

This test fails check-llvm because 29 isn't a shfl_uimm on RV32

[LevyHsu]

Change Log:

1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
   • Aligned SDNode def for shflw/unshfl/unshflw
   • Reordered def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
   • Merged Pat def when Predicates = [HasStdExtZbp]

2. llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll llvm/test/MC/RISCV/rv32b-aliases-valid.s llvm/test/MC/RISCV/rv64b-aliases-valid.s clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
   • Replaced all imm from 29 to 4

[LevyHsu]

• clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
• clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
• llvm/test/MC/RISCV/rv32b-aliases-valid.s
• llvm/test/MC/RISCV/rv64b-aliases-valid.s
• llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
• llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

Changed imm in the test cases to 13 so it's 4bit 1101 and won't be lower to other instructions.

[LevyHsu]

1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
   • Fix format issue with clang-format

[LevyHsu]

Fix format in RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN

[craig.topper]

LGTM

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
 
 // Zbc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
 
+// Zbp extension
+TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
+TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
+TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
+TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_unshfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
+TARGET_BUILTIN(__builtin_riscv_xperm_n, "LiLiLi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_xperm_b, "LiLiLi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_xperm_h, "LiLiLi", "nc", "experimental-zbp")
+TARGET_BUILTIN(__builtin_riscv_xperm_w, "WiWiWi", "nc", "experimental-zbp,64bit")
+
 // Zbr extension
 TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
+  case RISCV::BI__builtin_riscv_grev_32:
+  case RISCV::BI__builtin_riscv_grev_64:
+  case RISCV::BI__builtin_riscv_gorc_32:
+  case RISCV::BI__builtin_riscv_gorc_64:
+  case RISCV::BI__builtin_riscv_shfl_32:
+  case RISCV::BI__builtin_riscv_shfl_64:
+  case RISCV::BI__builtin_riscv_unshfl_32:
+  case RISCV::BI__builtin_riscv_unshfl_64:
+  case RISCV::BI__builtin_riscv_xperm_n:
+  case RISCV::BI__builtin_riscv_xperm_b:
+  case RISCV::BI__builtin_riscv_xperm_h:
+  case RISCV::BI__builtin_riscv_xperm_w:
   case RISCV::BI__builtin_riscv_crc32_b:
   case RISCV::BI__builtin_riscv_crc32_h:
   case RISCV::BI__builtin_riscv_crc32_w:
   case RISCV::BI__builtin_riscv_crc32_d:
   case RISCV::BI__builtin_riscv_crc32c_b:
   case RISCV::BI__builtin_riscv_crc32c_h:
   case RISCV::BI__builtin_riscv_crc32c_w:
   case RISCV::BI__builtin_riscv_crc32c_d: {
case RISCV::BI__builtin_riscv_clmul:
       break;
     case RISCV::BI__builtin_riscv_clmulh:
       ID = Intrinsic::riscv_clmulh;
       break;
     case RISCV::BI__builtin_riscv_clmulr:
       ID = Intrinsic::riscv_clmulr;
       break;
 
+    // Zbp
+    case RISCV::BI__builtin_riscv_grev_32:
+    case RISCV::BI__builtin_riscv_grev_64:
+      ID = Intrinsic::riscv_grev;
+      break;
+    case RISCV::BI__builtin_riscv_gorc_32:
+    case RISCV::BI__builtin_riscv_gorc_64:
+      ID = Intrinsic::riscv_gorc;
+      break;
+    case RISCV::BI__builtin_riscv_shfl_32:
+    case RISCV::BI__builtin_riscv_shfl_64:
+      ID = Intrinsic::riscv_shfl;
+      break;
+    case RISCV::BI__builtin_riscv_unshfl_32:
+    case RISCV::BI__builtin_riscv_unshfl_64:
+      ID = Intrinsic::riscv_unshfl;
+      break;
+    case RISCV::BI__builtin_riscv_xperm_n:
+      ID = Intrinsic::riscv_xperm_n;
+      break;
+    case RISCV::BI__builtin_riscv_xperm_b:
+      ID = Intrinsic::riscv_xperm_b;
+      break;
+    case RISCV::BI__builtin_riscv_xperm_h:
+      ID = Intrinsic::riscv_xperm_h;
+      break;
+    case RISCV::BI__builtin_riscv_xperm_w:
+      ID = Intrinsic::riscv_xperm_w;
+      break;
+
     // Zbr
     case RISCV::BI__builtin_riscv_crc32_b:
       ID = Intrinsic::riscv_crc32_b;
       break;
     case RISCV::BI__builtin_riscv_crc32_h:
       ID = Intrinsic::riscv_crc32_h;
       break;
     case RISCV::BI__builtin_riscv_crc32_w:

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbp -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBP
+
+// RV32ZBP-LABEL: @grev(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long grev(long rs1, long rs2)
+{
+  return __builtin_riscv_grev_32(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @grevi(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 4)
+// RV32ZBP-NEXT:    ret i32 [[TMP1]]
+//
+long grevi(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_grev_32(rs1, i);
+}
+
+// RV32ZBP-LABEL: @gorc(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long gorc(long rs1, long rs2)
+{
+  return __builtin_riscv_gorc_32(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @gorci(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 4)
+// RV32ZBP-NEXT:    ret i32 [[TMP1]]
+//
+long gorci(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_gorc_32(rs1, i);
+}
+
+// RV32ZBP-LABEL: @shfl(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long shfl(long rs1, long rs2)
+{
+  return __builtin_riscv_shfl_32(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @shfli(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 4)
+// RV32ZBP-NEXT:    ret i32 [[TMP1]]
+//
+long shfli(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_shfl_32(rs1, i);
+}
+
+// RV32ZBP-LABEL: @unshfl(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long unshfl(long rs1, long rs2)
+{
+  return __builtin_riscv_unshfl_32(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @unshfli(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 4)
+// RV32ZBP-NEXT:    ret i32 [[TMP1]]
+//
+long unshfli(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_unshfl_32(rs1, i);
+}
+
+// RV32ZBP-LABEL: @xperm_n(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.n.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long xperm_n(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_n(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @xperm_b(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.b.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long xperm_b(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_b(rs1, rs2);
+}
+
+// RV32ZBP-LABEL: @xperm_h(
+// RV32ZBP-NEXT:  entry:
+// RV32ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.h.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBP-NEXT:    ret i32 [[TMP2]]
+//
+long xperm_h(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_h(rs1, rs2);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbp -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBP
+
+// RV64ZBP-LABEL: @grev(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.grev.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long grev(long rs1, long rs2)
+{
+  return __builtin_riscv_grev_64(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @grevi(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.grev.i64(i64 [[TMP0]], i64 4)
+// RV64ZBP-NEXT:    ret i64 [[TMP1]]
+//
+long grevi(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_grev_64(rs1, i);
+}
+
+// RV64ZBP-LABEL: @grevw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBP-NEXT:    ret i32 [[TMP2]]
+//
+int grevw(int rs1, int rs2)
+{
+  return __builtin_riscv_grev_32(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @greviw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 4)
+// RV64ZBP-NEXT:    ret i32 [[TMP1]]
+//
+int greviw(int rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_grev_32(rs1, i);
+}
+
+// RV64ZBP-LABEL: @gorc(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.gorc.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long gorc(long rs1, long rs2)
+{
+  return __builtin_riscv_gorc_64(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @gorci(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.gorc.i64(i64 [[TMP0]], i64 4)
+// RV64ZBP-NEXT:    ret i64 [[TMP1]]
+//
+long gorci(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_gorc_64(rs1, i);
+}
+
+// RV64ZBP-LABEL: @gorcw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBP-NEXT:    ret i32 [[TMP2]]
+//
+int gorcw(int rs1, int rs2)
+{
+  return __builtin_riscv_gorc_32(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @gorciw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 4)
+// RV64ZBP-NEXT:    ret i32 [[TMP1]]
+//
+int gorciw(int rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_gorc_32(rs1, i);
+}
+
+// RV64ZBP-LABEL: @shfl(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.shfl.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long shfl(long rs1, long rs2)
+{
+  return __builtin_riscv_shfl_64(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @shfli(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.shfl.i64(i64 [[TMP0]], i64 4)
+// RV64ZBP-NEXT:    ret i64 [[TMP1]]
+//
+long shfli(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_shfl_64(rs1, i);
+}
+
+// RV64ZBP-LABEL: @shflw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBP-NEXT:    ret i32 [[TMP2]]
+//
+int shflw(int rs1, int rs2)
+{
+  return __builtin_riscv_shfl_32(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @shfli_NOw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 4)
+// RV64ZBP-NEXT:    ret i32 [[TMP1]]
+//
+int shfli_NOw(int rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_shfl_32(rs1, i);
+}
+
+// RV64ZBP-LABEL: @unshfl(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.unshfl.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long unshfl(long rs1, long rs2)
+{
+  return __builtin_riscv_unshfl_64(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @unshfli(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.unshfl.i64(i64 [[TMP0]], i64 4)
+// RV64ZBP-NEXT:    ret i64 [[TMP1]]
+//
+long unshfli(long rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_unshfl_64(rs1, i);
+}
+
+// RV64ZBP-LABEL: @unshflw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBP-NEXT:    ret i32 [[TMP2]]
+//
+int unshflw(int rs1, int rs2)
+{
+  return __builtin_riscv_unshfl_32(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @unshfli_NOw(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    [[I:%.*]] = alloca i32, align 4
+// RV64ZBP-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    store i32 4, i32* [[I]], align 4
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 4)
+// RV64ZBP-NEXT:    ret i32 [[TMP1]]
+//
+int unshfli_NOw(int rs1)
+{
+  const int i = 4;
+  return __builtin_riscv_unshfl_32(rs1, i);
+}
+
+// RV64ZBP-LABEL: @xperm_n(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.n.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long xperm_n(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_n(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @xperm_b(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.b.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long xperm_b(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_b(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @xperm_h(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.h.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long xperm_h(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_h(rs1, rs2);
+}
+
+// RV64ZBP-LABEL: @xperm_w(
+// RV64ZBP-NEXT:  entry:
+// RV64ZBP-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBP-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBP-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.w.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBP-NEXT:    ret i64 [[TMP2]]
+//
+long xperm_w(long rs1, long rs2)
+{
+  return __builtin_riscv_xperm_w(rs1, rs2);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
 
   // Zbc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbp
+  def int_riscv_grev  : BitManipGPRGPRIntrinsics;
+  def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
+  def int_riscv_shfl  : BitManipGPRGPRIntrinsics;
+  def int_riscv_unshfl  : BitManipGPRGPRIntrinsics;
+  def int_riscv_xperm_n  : BitManipGPRGPRIntrinsics;
+  def int_riscv_xperm_b  : BitManipGPRGPRIntrinsics;
+  def int_riscv_xperm_h  : BitManipGPRGPRIntrinsics;
+  def int_riscv_xperm_w  : BitManipGPRGPRIntrinsics;
+
   // Zbr
   def int_riscv_crc32_b : BitManipGPRIntrinsics;
   def int_riscv_crc32_h : BitManipGPRIntrinsics;
   def int_riscv_crc32_w : BitManipGPRIntrinsics;
   def int_riscv_crc32_d : BitManipGPRIntrinsics;
   def int_riscv_crc32c_b : BitManipGPRIntrinsics;
   def int_riscv_crc32c_h : BitManipGPRIntrinsics;
   def int_riscv_crc32c_w : BitManipGPRIntrinsics;

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   // TableGen chokes when faced with commutative permutations in deeply-nested
   // DAGs. Each node takes an input operand and a control operand and outputs a
   // bit-manipulated version of input. All operands are i32 or XLenVT.
   GREV,
   GREVW,
   GORC,
   GORCW,
   SHFL,
+  SHFLW,
+  UNSHFL,
+  UNSHFLW,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
   VMV_V_X_VL,
   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
   // for the VL value to be used for the operation.
   VFMV_V_F_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtZbp()) {
     // Custom lower bswap/bitreverse so we can convert them to GREVI to enable
     // more combining.
     setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
     setOperationAction(ISD::BSWAP, XLenVT, Custom);
 
     if (Subtarget.is64Bit()) {
       setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
       setOperationAction(ISD::BSWAP, MVT::i32, Custom);
+      setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
     }
   } else {
     // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
     // pattern match it directly in isel.
     setOperationAction(ISD::BSWAP, XLenVT,
                        Subtarget.hasStdExtZbb() ? Legal : Expand);
   }
 
SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
   case Intrinsic::riscv_orc_b:
     // Lower to the GORCI encoding for orc.b.
     return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
                        DAG.getConstant(7, DL, XLenVT));
+  case Intrinsic::riscv_grev:
+  case Intrinsic::riscv_gorc: {
+    unsigned Opc = 
+        IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
+    return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
+  }
+  case Intrinsic::riscv_shfl:
+  case Intrinsic::riscv_unshfl: {
+    unsigned Opc = 
+        IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
+    return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
+  }
   case Intrinsic::riscv_vmv_x_s:
     assert(Op.getValueType() == XLenVT && "Unexpected VT!");
     return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
                        Op.getOperand(1));
   case Intrinsic::riscv_vmv_v_x: {
     SDValue Scalar = Op.getOperand(1);
     if (Scalar.getValueType().bitsLE(XLenVT)) {
       unsigned ExtOpc =
case Intrinsic::riscv_vslide1down_mask: {
     SDValue ScalarLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
                                    DAG.getConstant(0, DL, XLenVT));
     SDValue ScalarHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
                                    DAG.getConstant(1, DL, XLenVT));
 
     // Double the VL since we halved SEW.
     SDValue VL = Op.getOperand(NumOps - 1);
     SDValue I32VL =
         DAG.getNode(ISD::SHL, DL, XLenVT, VL, DAG.getConstant(1, DL, XLenVT));
 
     MVT I32MaskVT = MVT::getVectorVT(MVT::i1, I32VT.getVectorElementCount());
     SDValue I32Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, I32MaskVT, VL);
 
     // Shift the two scalar parts in using SEW=32 slide1up/slide1down
     // instructions.
     if (IntNo == Intrinsic::riscv_vslide1up ||
         IntNo == Intrinsic::riscv_vslide1up_mask) {
       Vec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32VT, Vec, ScalarHi,
                         I32Mask, I32VL);
       Vec = DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, I32VT, Vec, ScalarLo,
                         I32Mask, I32VL);
     } else {
       Vec = DAG.getNode(RISCVISD::VSLIDE1DOWN_VL, DL, I32VT, Vec, ScalarLo,
case Intrinsic::riscv_orc_b: {
       // If Zbp is enabled, use GORCIW which will sign extend the result.
       unsigned Opc =
           Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC;
       SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
                                 DAG.getConstant(7, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }
+    case Intrinsic::riscv_grev:
+    case Intrinsic::riscv_gorc: {
+      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+          Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+      SDValue NewOp1 =
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue NewOp2 =
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
+      unsigned Opc =
+          IntNo == Intrinsic::riscv_grev ? RISCVISD::GREVW : RISCVISD::GORCW;
+      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      break;
+    }
+    case Intrinsic::riscv_shfl:
+    case Intrinsic::riscv_unshfl: {
+      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+          Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+      SDValue NewOp1 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue NewOp2 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
+      unsigned Opc =
+            IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFLW : RISCVISD::UNSHFLW;
+      if (isa<ConstantSDNode>(N->getOperand(2))) {
+        NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2,
+                             DAG.getConstant(0xf, DL, MVT::i64));
+        Opc = IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
+      }
+      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      break;
+    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
       if (VT.bitsLT(XLenVT)) {
         // Simple case just extract using vmv.x.s and truncate.
         SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                       Subtarget.getXLenVT(), N->getOperand(1));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));

 // Matches patterns of the form
 //   (and (shl x, C2), (C1 << C2))
 //   (and (srl x, C2), C1)
 //   (shl (and x, C1), C2)
 //   (srl (and x, (C1 << C2)), C2)
 // Where C2 is a power of 2 and C1 has at least that many leading zeroes.
 // The expected masks for each shift amount are specified in BitmanipMasks where
 // BitmanipMasks[log2(C2)] specifies the expected C1 value.
 // The max allowed shift amount is either XLen/2 or XLen/4 determined by whether
 // BitmanipMasks contains 6 or 5 entries assuming that the maximum possible
 // XLen is 64.
 static Optional<RISCVBitmanipPat>
 matchRISCVBitmanipPat(SDValue Op, ArrayRef<uint64_t> BitmanipMasks) {
   assert((BitmanipMasks.size() == 5 || BitmanipMasks.size() == 6) &&
          "Unexpected number of masks");
   Optional<uint64_t> Mask;
   // Optionally consume a mask around the shift operation.
   if (Op.getOpcode() == ISD::AND && isa<ConstantSDNode>(Op.getOperand(1))) {
     Mask = Op.getConstantOperandVal(1);
     Op = Op.getOperand(0);
   }
   if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL)
     return None;
   bool IsSHL = Op.getOpcode() == ISD::SHL;
 
   if (!isa<ConstantSDNode>(Op.getOperand(1)))
     return None;
   uint64_t ShAmt = Op.getConstantOperandVal(1);
 
   unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32;
   if (ShAmt >= Width && !isPowerOf2_64(ShAmt))
     return None;
   // If we don't have enough masks for 64 bit, then we must be trying to
   // match SHFL so we're only allowed to shift 1/4 of the width.
   if (BitmanipMasks.size() == 5 && ShAmt >= (Width / 2))
     return None;
 
   SDValue Src = Op.getOperand(0);
 
   // The expected mask is shifted left when the AND is found around SHL
   // patterns.
unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::DIVUW:
   case RISCVISD::REMUW:
   case RISCVISD::ROLW:
   case RISCVISD::RORW:
   case RISCVISD::GREVW:
   case RISCVISD::GORCW:
   case RISCVISD::FSLW:
   case RISCVISD::FSRW:
+  case RISCVISD::SHFLW:
+  case RISCVISD::UNSHFLW:
     // TODO: As the result is sign-extended, this is conservatively correct. A
     // more precise answer could be calculated for SRAW depending on known
     // bits in the shift amount.
     return 33;
-  case RISCVISD::SHFL: {
+  case RISCVISD::SHFL:
+  case RISCVISD::UNSHFL: {
     // There is no SHFLIW, but a i64 SHFLI with bit 4 of the control word
     // cleared doesn't affect bit 31. The upper 32 bits will be shuffled, but
     // will stay within the upper 32 bits. If there were more than 32 sign bits
     // before there will be at least 33 sign bits after.
     if (Op.getValueType() == MVT::i64 &&
         isa<ConstantSDNode>(Op.getOperand(1)) &&
         (Op.getConstantOperandVal(1) & 0x10) == 0) {
       unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(FMV_W_X_RV64)
   NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
   NODE_NAME_CASE(READ_CYCLE_WIDE)
   NODE_NAME_CASE(GREV)
   NODE_NAME_CASE(GREVW)
   NODE_NAME_CASE(GORC)
   NODE_NAME_CASE(GORCW)
   NODE_NAME_CASE(SHFL)
+  NODE_NAME_CASE(SHFLW)
+  NODE_NAME_CASE(UNSHFL)
+  NODE_NAME_CASE(UNSHFLW)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)
   NODE_NAME_CASE(VFMV_S_F_VL)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
   NODE_NAME_CASE(READ_VLENB)
   NODE_NAME_CASE(TRUNCATE_VECTOR_VL)

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def riscv_fsrw   : SDNode<"RISCVISD::FSRW",   SDT_RISCVIntShiftDOpW>;
 def riscv_fsl    : SDNode<"RISCVISD::FSL",    SDTIntShiftDOp>;
 def riscv_fsr    : SDNode<"RISCVISD::FSR",    SDTIntShiftDOp>;
 def riscv_grev   : SDNode<"RISCVISD::GREV",   SDTIntBinOp>;
 def riscv_grevw  : SDNode<"RISCVISD::GREVW",  SDT_RISCVIntBinOpW>;
 def riscv_gorc   : SDNode<"RISCVISD::GORC",   SDTIntBinOp>;
 def riscv_gorcw  : SDNode<"RISCVISD::GORCW",  SDT_RISCVIntBinOpW>;
 def riscv_shfl   : SDNode<"RISCVISD::SHFL",   SDTIntBinOp>;
+def riscv_shflw  : SDNode<"RISCVISD::SHFLW",   SDT_RISCVIntBinOpW>;
+def riscv_unshfl : SDNode<"RISCVISD::UNSHFL",   SDTIntBinOp>;
+def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",   SDT_RISCVIntBinOpW>;
 
 def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenHalf";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidUImmLog2XLenHalf";
 }
 
 def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
def : InstAlias<"ror $rd, $rs1, $shamt",
                 (RORI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : InstAlias<"rorw $rd, $rs1, $shamt",
                 (RORIW  GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
+let Predicates = [HasStdExtZbp] in {
+def : InstAlias<"grev $rd, $rs1, $shamt",
+                (GREVI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"gorc $rd, $rs1, $shamt",
+                (GORCI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"shfl $rd, $rs1, $shamt",
+                (SHFLI  GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
+def : InstAlias<"unshfl $rd, $rs1, $shamt",
+                (UNSHFLI  GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : InstAlias<"grevw $rd, $rs1, $shamt",
+                (GREVIW  GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
+def : InstAlias<"gorcw $rd, $rs1, $shamt",
+                (GORCIW  GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
 let Predicates = [HasStdExtZbs] in {
 def : InstAlias<"bset $rd, $rs1, $shamt",
                 (BSETI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 def : InstAlias<"bclr $rd, $rs1, $shamt",
                 (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 def : InstAlias<"binv $rd, $rs1, $shamt",
                 (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 def : InstAlias<"bext $rd, $rs1, $shamt",
def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
 
 // We treat orc.b as a separate instruction, so match it directly. We also
 // lower the Zbb orc.b intrinsic to this.
 def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
 }
 
 let Predicates = [HasStdExtZbp] in {
+def : PatGprGpr<riscv_grev, GREV>;
+def : PatGprGpr<riscv_gorc, GORC>;
+def : PatGprGpr<riscv_shfl, SHFL>;
+def : PatGprGpr<riscv_unshfl, UNSHFL>;
+def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
+def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
+def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
+def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
 def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
+def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
 def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
 def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp, IsRV32] in {
 def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
 def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
 
 // We treat rev8 as a separate instruction, so match it directly.
 def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
 } // Predicates = [HasStdExtZbp, IsRV32]

 def : PatGprImm<riscv_rorw, RORIW, uimm5>;
 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
 def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
+def : PatGprGpr<riscv_grevw, GREVW>;
+def : PatGprGpr<riscv_gorcw, GORCW>;
+def : PatGprGpr<riscv_shflw, SHFLW>;
+def : PatGprGpr<riscv_unshflw, UNSHFLW>;
 def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
 def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),

 
 let Predicates = [HasStdExtZbc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;
 def : PatGprGpr<int_riscv_clmulr, CLMULR>;
 } // Predicates = [HasStdExtZbc]
 
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr<int_riscv_crc32_b, CRC32B>;
 def : PatGpr<int_riscv_crc32_h, CRC32H>;
 def : PatGpr<int_riscv_crc32_w, CRC32W>;
 def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
 def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
 def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def : PatGpr<int_riscv_crc32_d, CRC32D>;
 def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
 } // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define i32 @grev32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: grev32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    grev a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: grev32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    grev a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define i32 @grevi32(i32 %a) nounwind {
+; RV32IB-LABEL: grevi32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    rev4.b a0, a0
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: grevi32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    rev4.b a0, a0
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define i32 @gorc32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: gorc32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    gorc a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: gorc32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    gorc a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define i32 @gorci32(i32 %a) nounwind {
+; RV32IB-LABEL: gorci32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    orc4.b a0, a0
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: gorci32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    orc4.b a0, a0
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+
+define i32 @shfl32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: shfl32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    shfl a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: shfl32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    shfl a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfli.i32(i32 %a)
+
+define i32 @shfli32(i32 %a) nounwind {
+; RV32IB-LABEL: shfli32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    zip4.h a0, a0
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: shfli32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    zip4.h a0, a0
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
+
+define i32 @unshfl32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: unshfl32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    unshfl a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: unshfl32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    unshfl a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.unshfli.i32(i32 %a)
+
+define i32 @unshfli32(i32 %a) nounwind {
+; RV32IB-LABEL: unshfli32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    unzip4.h a0, a0
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: unshfli32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    unzip4.h a0, a0
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
+
+define i32 @xpermn32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: xpermn32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    xperm.n a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: xpermn32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    xperm.n a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
+
+define i32 @xpermb32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: xpermb32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    xperm.b a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: xpermb32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    xperm.b a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
+
+define i32 @xpermh32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: xpermh32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    xperm.h a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBP-LABEL: xpermh32:
+; RV32IBP:       # %bb.0:
+; RV32IBP-NEXT:    xperm.h a0, a0, a1
+; RV32IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBP
+
+declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+
+define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: grev32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    grevw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: grev32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    grevw a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.grevi.i32(i32 %a)
+
+define signext i32 @grevi32(i32 signext %a) nounwind {
+; RV64IB-LABEL: grevi32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    greviw a0, a0, 4
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: grevi32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    greviw a0, a0, 4
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+
+define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: gorc32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    gorcw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: gorc32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    gorcw a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.gorci.i32(i32 %a)
+
+define signext i32 @gorci32(i32 signext %a) nounwind {
+; RV64IB-LABEL: gorci32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    gorciw a0, a0, 4
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: gorci32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    gorciw a0, a0, 4
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+
+define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: shfl32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    shflw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: shfl32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    shflw a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.shfli.i32(i32 %a)
+
+define signext i32 @shfli32(i32 signext %a) nounwind {
+; RV64IB-LABEL: shfli32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    zip4.h a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: shfli32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    zip4.h a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
+
+define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: unshfl32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    unshflw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: unshfl32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    unshflw a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.unshfli.i32(i32 %a)
+
+define signext i32 @unshfli32(i32 signext %a) nounwind {
+; RV64IB-LABEL: unshfli32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    unzip4.h a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: unshfli32:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    unzip4.h a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 4)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
+
+define i64 @grev64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: grev64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    grev a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: grev64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    grev a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.grevi.i64(i64 %a)
+
+define i64 @grevi64(i64 %a) nounwind {
+; RV64IB-LABEL: grevi64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    rev4.b a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: grevi64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    rev4.b a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 4)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
+
+define i64 @gorc64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: gorc64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    gorc a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: gorc64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    gorc a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.gorci.i64(i64 %a)
+
+define i64 @gorci64(i64 %a) nounwind {
+; RV64IB-LABEL: gorci64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    orc4.b a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: gorci64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    orc4.b a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 4)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
+
+define i64 @shfl64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: shfl64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    shfl a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: shfl64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    shfl a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.shfli.i64(i64 %a)
+
+define i64 @shfli64(i64 %a) nounwind {
+; RV64IB-LABEL: shfli64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    zip4.h a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: shfli64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    zip4.h a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 4)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
+
+define i64 @unshfl64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: unshfl64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    unshfl a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: unshfl64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    unshfl a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.unshfli.i64(i64 %a)
+
+define i64 @unshfli64(i64 %a) nounwind {
+; RV64IB-LABEL: unshfli64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    unzip4.h a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: unshfli64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    unzip4.h a0, a0
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 4)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
+
+define i64 @xpermn64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: xpermn64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    xperm.n a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: xpermn64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    xperm.n a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
+
+define i64 @xpermb64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: xpermb64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    xperm.b a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: xpermb64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    xperm.b a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
+
+define i64 @xpermh64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: xpermh64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    xperm.h a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: xpermh64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    xperm.h a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
+
+define i64 @xpermw64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: xpermw64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    xperm.w a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBP-LABEL: xpermw64:
+; RV64IBP:       # %bb.0:
+; RV64IBP-NEXT:    xperm.w a0, a0, a1
+; RV64IBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}

llvm/test/MC/RISCV/rv32b-aliases-valid.s

 
 # CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
 # CHECK-S-OBJ: binvi t0, t1, 8
 binv x5, x6, 8
 
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: grevi t0, t1, 4
+grev x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: gorci t0, t1, 4
+gorc x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: shfli t0, t1, 4
+shfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unshfli t0, t1, 4
+unshfl x5, x6, 4

llvm/test/MC/RISCV/rv64b-aliases-valid.s

 
 # CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
 # CHECK-S-OBJ: binvi t0, t1, 8
 binv x5, x6, 8
 
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: grevi t0, t1, 4
+grev x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: gorci t0, t1, 4
+gorc x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: shfli t0, t1, 4
+shfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unshfli t0, t1, 4
+unshfl x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 4
+# CHECK-S-OBJ: greviw t0, t1, 4
+grevw x5, x6, 4
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 4
+# CHECK-S-OBJ: gorciw t0, t1, 4
+gorcw x5, x6, 4