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Differential D100830

[RISCV] [1/2] Add IR intrinsic for Zbp extension
ClosedPublic

Authored by LevyHsu on Apr 20 2021, 2:15 AM.

Details

Reviewers
craig.topper
jrtc27
kito-cheng
asb
Jim
Commits
rGb49337bbb9de: [RISCV] [1/2] Add IR intrinsic for Zbp extension
Summary

RV32/64:

grev
grevi
gorc
gorci
shfl
shfli
unshfl
unshfli
xperm.n
xperm.b
xperm.h

RV64 ONLY:

grevw
greviw
gorcw
gorciw
shflw
shfli     (For non-existing shfliw)
unshfli   (For non-existing unshfliw)
xperm.w

Diff Detail

Event Timeline

LevyHsu created this revision.Apr 20 2021, 2:15 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 21 others. · View Herald TranscriptApr 20 2021, 2:15 AM
LevyHsu requested review of this revision.Apr 20 2021, 2:15 AM
Herald added subscribers: llvm-commits, cfe-commits, MaskRay. · View Herald TranscriptApr 20 2021, 2:15 AM
Harbormaster completed remote builds in B99655: Diff 338777.Apr 20 2021, 3:41 AM
craig.topper added inline comments.Apr 20 2021, 12:25 PM
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
33

Line the colons up

742

Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together

938

Put these in the same block that has PatGprImm<riscv_grev

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
93

This immediate is too large to make shfli. It needs to b 4 bits for i32.

127

Same here

llvm/test/MC/RISCV/rv32b-aliases-valid.s
256

This test fails check-llvm because 29 isn't a shfl_uimm on RV32

LevyHsu updated this revision to Diff 339086.EditedApr 20 2021, 7:59 PM

Change Log:

  1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    • Aligned SDNode def for shflw/unshfl/unshflw
    • Reordered def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
    • Merged Pat def when Predicates = [HasStdExtZbp]
  1. llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll llvm/test/MC/RISCV/rv32b-aliases-valid.s llvm/test/MC/RISCV/rv64b-aliases-valid.s clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
    • Replaced all imm from 29 to 4
Harbormaster completed remote builds in B99879: Diff 339086.Apr 20 2021, 8:37 PM
LevyHsu updated this revision to Diff 339105.EditedApr 20 2021, 11:22 PM
LevyHsu marked 6 inline comments as done.
  • clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c
  • clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c
  • llvm/test/MC/RISCV/rv32b-aliases-valid.s
  • llvm/test/MC/RISCV/rv64b-aliases-valid.s
  • llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
  • llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

Changed imm in the test cases to 13 so it's 4bit 1101 and won't be lower to other instructions.

Harbormaster completed remote builds in B99892: Diff 339105.Apr 21 2021, 12:35 AM
LevyHsu updated this revision to Diff 339138.Apr 21 2021, 1:45 AM
  1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    • Fix format issue with clang-format
LevyHsu updated this revision to Diff 339150.Apr 21 2021, 2:33 AM

Fix format in RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN

Harbormaster completed remote builds in B99915: Diff 339138.Apr 21 2021, 2:39 AM
Harbormaster completed remote builds in B99923: Diff 339150.Apr 21 2021, 3:27 AM
craig.topper accepted this revision.Apr 21 2021, 7:28 PM

LGTM

This revision is now accepted and ready to land.Apr 21 2021, 7:28 PM
Closed by commit rGb49337bbb9de: [RISCV] [1/2] Add IR intrinsic for Zbp extension (authored by LevyHsu, committed by craig.topper). · Explain WhyApr 22 2021, 4:35 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGb49337bbb9de: [RISCV] [1/2] Add IR intrinsic for Zbp extension.
LevyHsu edited the summary of this revision. (Show Details)Jun 10 2021, 8:38 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
14 lines
lib/
CodeGen/
42 lines
test/
CodeGen/
RISCV/
rvb-intrinsics/
179 lines
323 lines
llvm/
include/
llvm/
IR/
10 lines
lib/
Target/
RISCV/
3 lines
53 lines
34 lines
test/
CodeGen/
RISCV/
181 lines
325 lines
MC/
RISCV/
16 lines
24 lines

Diff 339138

clang/include/clang/Basic/BuiltinsRISCV.def

Show All 20 Lines
TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb") TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit") TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
// Zbc extension // Zbc extension
TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc") TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc") TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc") TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
// Zbp extension
TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_unshfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
TARGET_BUILTIN(__builtin_riscv_xperm_n, "LiLiLi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_xperm_b, "LiLiLi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_xperm_h, "LiLiLi", "nc", "experimental-zbp")
TARGET_BUILTIN(__builtin_riscv_xperm_w, "WiWiWi", "nc", "experimental-zbp,64bit")
// Zbr extension // Zbr extension
TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
#undef BUILTIN #undef BUILTIN
#undef TARGET_BUILTIN #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 17,843 Lines • ▼ Show 20 LinesValue *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes; llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
switch (BuiltinID) { switch (BuiltinID) {
default: llvm_unreachable("unexpected builtin ID"); default: llvm_unreachable("unexpected builtin ID");
case RISCV::BI__builtin_riscv_orc_b_32: case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64: case RISCV::BI__builtin_riscv_orc_b_64:
case RISCV::BI__builtin_riscv_clmul: case RISCV::BI__builtin_riscv_clmul:
case RISCV::BI__builtin_riscv_clmulh: case RISCV::BI__builtin_riscv_clmulh:
case RISCV::BI__builtin_riscv_clmulr: case RISCV::BI__builtin_riscv_clmulr:
case RISCV::BI__builtin_riscv_grev_32:
case RISCV::BI__builtin_riscv_grev_64:
case RISCV::BI__builtin_riscv_gorc_32:
case RISCV::BI__builtin_riscv_gorc_64:
case RISCV::BI__builtin_riscv_shfl_32:
case RISCV::BI__builtin_riscv_shfl_64:
case RISCV::BI__builtin_riscv_unshfl_32:
case RISCV::BI__builtin_riscv_unshfl_64:
case RISCV::BI__builtin_riscv_xperm_n:
case RISCV::BI__builtin_riscv_xperm_b:
case RISCV::BI__builtin_riscv_xperm_h:
case RISCV::BI__builtin_riscv_xperm_w:
case RISCV::BI__builtin_riscv_crc32_b: case RISCV::BI__builtin_riscv_crc32_b:
case RISCV::BI__builtin_riscv_crc32_h: case RISCV::BI__builtin_riscv_crc32_h:
case RISCV::BI__builtin_riscv_crc32_w: case RISCV::BI__builtin_riscv_crc32_w:
case RISCV::BI__builtin_riscv_crc32_d: case RISCV::BI__builtin_riscv_crc32_d:
case RISCV::BI__builtin_riscv_crc32c_b: case RISCV::BI__builtin_riscv_crc32c_b:
case RISCV::BI__builtin_riscv_crc32c_h: case RISCV::BI__builtin_riscv_crc32c_h:
case RISCV::BI__builtin_riscv_crc32c_w: case RISCV::BI__builtin_riscv_crc32c_w:
case RISCV::BI__builtin_riscv_crc32c_d: { case RISCV::BI__builtin_riscv_crc32c_d: {
Show All 11 Lines case RISCV::BI__builtin_riscv_clmul:
break; break;
case RISCV::BI__builtin_riscv_clmulh: case RISCV::BI__builtin_riscv_clmulh:
ID = Intrinsic::riscv_clmulh; ID = Intrinsic::riscv_clmulh;
break; break;
case RISCV::BI__builtin_riscv_clmulr: case RISCV::BI__builtin_riscv_clmulr:
ID = Intrinsic::riscv_clmulr; ID = Intrinsic::riscv_clmulr;
break; break;
// Zbp
case RISCV::BI__builtin_riscv_grev_32:
case RISCV::BI__builtin_riscv_grev_64:
ID = Intrinsic::riscv_grev;
break;
case RISCV::BI__builtin_riscv_gorc_32:
case RISCV::BI__builtin_riscv_gorc_64:
ID = Intrinsic::riscv_gorc;
break;
case RISCV::BI__builtin_riscv_shfl_32:
case RISCV::BI__builtin_riscv_shfl_64:
ID = Intrinsic::riscv_shfl;
break;
case RISCV::BI__builtin_riscv_unshfl_32:
case RISCV::BI__builtin_riscv_unshfl_64:
ID = Intrinsic::riscv_unshfl;
break;
case RISCV::BI__builtin_riscv_xperm_n:
ID = Intrinsic::riscv_xperm_n;
break;
case RISCV::BI__builtin_riscv_xperm_b:
ID = Intrinsic::riscv_xperm_b;
break;
case RISCV::BI__builtin_riscv_xperm_h:
ID = Intrinsic::riscv_xperm_h;
break;
case RISCV::BI__builtin_riscv_xperm_w:
ID = Intrinsic::riscv_xperm_w;
break;
// Zbr // Zbr
case RISCV::BI__builtin_riscv_crc32_b: case RISCV::BI__builtin_riscv_crc32_b:
ID = Intrinsic::riscv_crc32_b; ID = Intrinsic::riscv_crc32_b;
break; break;
case RISCV::BI__builtin_riscv_crc32_h: case RISCV::BI__builtin_riscv_crc32_h:
ID = Intrinsic::riscv_crc32_h; ID = Intrinsic::riscv_crc32_h;
break; break;
case RISCV::BI__builtin_riscv_crc32_w: case RISCV::BI__builtin_riscv_crc32_w:
Show All 31 Lines

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbp.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbp -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32ZBP
// RV32ZBP-LABEL: @grev(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long grev(long rs1, long rs2)
{
return __builtin_riscv_grev_32(rs1, rs2);
}
// RV32ZBP-LABEL: @grevi(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 13)
// RV32ZBP-NEXT: ret i32 [[TMP1]]
//
long grevi(long rs1)
{
const int i = 13;
return __builtin_riscv_grev_32(rs1, i);
}
// RV32ZBP-LABEL: @gorc(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long gorc(long rs1, long rs2)
{
return __builtin_riscv_gorc_32(rs1, rs2);
}
// RV32ZBP-LABEL: @gorci(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 13)
// RV32ZBP-NEXT: ret i32 [[TMP1]]
//
long gorci(long rs1)
{
const int i = 13;
return __builtin_riscv_gorc_32(rs1, i);
}
// RV32ZBP-LABEL: @shfl(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long shfl(long rs1, long rs2)
{
return __builtin_riscv_shfl_32(rs1, rs2);
}
// RV32ZBP-LABEL: @shfli(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 13)
// RV32ZBP-NEXT: ret i32 [[TMP1]]
//
long shfli(long rs1)
{
const int i = 13;
return __builtin_riscv_shfl_32(rs1, i);
}
// RV32ZBP-LABEL: @unshfl(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long unshfl(long rs1, long rs2)
{
return __builtin_riscv_unshfl_32(rs1, rs2);
}
// RV32ZBP-LABEL: @unshfli(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 13)
// RV32ZBP-NEXT: ret i32 [[TMP1]]
//
long unshfli(long rs1)
{
const int i = 13;
return __builtin_riscv_unshfl_32(rs1, i);
}
// RV32ZBP-LABEL: @xperm_n(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.n.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long xperm_n(long rs1, long rs2)
{
return __builtin_riscv_xperm_n(rs1, rs2);
}
// RV32ZBP-LABEL: @xperm_b(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.b.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long xperm_b(long rs1, long rs2)
{
return __builtin_riscv_xperm_b(rs1, rs2);
}
// RV32ZBP-LABEL: @xperm_h(
// RV32ZBP-NEXT: entry:
// RV32ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV32ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.xperm.h.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBP-NEXT: ret i32 [[TMP2]]
//
long xperm_h(long rs1, long rs2)
{
return __builtin_riscv_xperm_h(rs1, rs2);
}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbp.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbp -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBP
// RV64ZBP-LABEL: @grev(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.grev.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long grev(long rs1, long rs2)
{
return __builtin_riscv_grev_64(rs1, rs2);
}
// RV64ZBP-LABEL: @grevi(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.grev.i64(i64 [[TMP0]], i64 13)
// RV64ZBP-NEXT: ret i64 [[TMP1]]
//
long grevi(long rs1)
{
const int i = 13;
return __builtin_riscv_grev_64(rs1, i);
}
// RV64ZBP-LABEL: @grevw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV64ZBP-NEXT: ret i32 [[TMP2]]
//
int grevw(int rs1, int rs2)
{
return __builtin_riscv_grev_32(rs1, rs2);
}
// RV64ZBP-LABEL: @greviw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 13)
// RV64ZBP-NEXT: ret i32 [[TMP1]]
//
int greviw(int rs1)
{
const int i = 13;
return __builtin_riscv_grev_32(rs1, i);
}
// RV64ZBP-LABEL: @gorc(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.gorc.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long gorc(long rs1, long rs2)
{
return __builtin_riscv_gorc_64(rs1, rs2);
}
// RV64ZBP-LABEL: @gorci(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.gorc.i64(i64 [[TMP0]], i64 13)
// RV64ZBP-NEXT: ret i64 [[TMP1]]
//
long gorci(long rs1)
{
const int i = 13;
return __builtin_riscv_gorc_64(rs1, i);
}
// RV64ZBP-LABEL: @gorcw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV64ZBP-NEXT: ret i32 [[TMP2]]
//
int gorcw(int rs1, int rs2)
{
return __builtin_riscv_gorc_32(rs1, rs2);
}
// RV64ZBP-LABEL: @gorciw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.gorc.i32(i32 [[TMP0]], i32 13)
// RV64ZBP-NEXT: ret i32 [[TMP1]]
//
int gorciw(int rs1)
{
const int i = 13;
return __builtin_riscv_gorc_32(rs1, i);
}
// RV64ZBP-LABEL: @shfl(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.shfl.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long shfl(long rs1, long rs2)
{
return __builtin_riscv_shfl_64(rs1, rs2);
}
// RV64ZBP-LABEL: @shfli(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.shfl.i64(i64 [[TMP0]], i64 13)
// RV64ZBP-NEXT: ret i64 [[TMP1]]
//
long shfli(long rs1)
{
const int i = 13;
return __builtin_riscv_shfl_64(rs1, i);
}
// RV64ZBP-LABEL: @shflw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV64ZBP-NEXT: ret i32 [[TMP2]]
//
int shflw(int rs1, int rs2)
{
return __builtin_riscv_shfl_32(rs1, rs2);
}
// RV64ZBP-LABEL: @shfli_NOw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.shfl.i32(i32 [[TMP0]], i32 13)
// RV64ZBP-NEXT: ret i32 [[TMP1]]
//
int shfli_NOw(int rs1)
{
const int i = 13;
return __builtin_riscv_shfl_32(rs1, i);
}
// RV64ZBP-LABEL: @unshfl(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.unshfl.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long unshfl(long rs1, long rs2)
{
return __builtin_riscv_unshfl_64(rs1, rs2);
}
// RV64ZBP-LABEL: @unshfli(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.unshfl.i64(i64 [[TMP0]], i64 13)
// RV64ZBP-NEXT: ret i64 [[TMP1]]
//
long unshfli(long rs1)
{
const int i = 13;
return __builtin_riscv_unshfl_64(rs1, i);
}
// RV64ZBP-LABEL: @unshflw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV64ZBP-NEXT: ret i32 [[TMP2]]
//
int unshflw(int rs1, int rs2)
{
return __builtin_riscv_unshfl_32(rs1, rs2);
}
// RV64ZBP-LABEL: @unshfli_NOw(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: [[I:%.*]] = alloca i32, align 4
// RV64ZBP-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: store i32 13, i32* [[I]], align 4
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV64ZBP-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.unshfl.i32(i32 [[TMP0]], i32 13)
// RV64ZBP-NEXT: ret i32 [[TMP1]]
//
int unshfli_NOw(int rs1)
{
const int i = 13;
return __builtin_riscv_unshfl_32(rs1, i);
}
// RV64ZBP-LABEL: @xperm_n(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.n.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long xperm_n(long rs1, long rs2)
{
return __builtin_riscv_xperm_n(rs1, rs2);
}
// RV64ZBP-LABEL: @xperm_b(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.b.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long xperm_b(long rs1, long rs2)
{
return __builtin_riscv_xperm_b(rs1, rs2);
}
// RV64ZBP-LABEL: @xperm_h(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.h.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long xperm_h(long rs1, long rs2)
{
return __builtin_riscv_xperm_h(rs1, rs2);
}
// RV64ZBP-LABEL: @xperm_w(
// RV64ZBP-NEXT: entry:
// RV64ZBP-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBP-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBP-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.xperm.w.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBP-NEXT: ret i64 [[TMP2]]
//
long xperm_w(long rs1, long rs2)
{
return __builtin_riscv_xperm_w(rs1, rs2);
}

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
// Zbb // Zbb
def int_riscv_orc_b : BitManipGPRIntrinsics; def int_riscv_orc_b : BitManipGPRIntrinsics;
// Zbc // Zbc
def int_riscv_clmul : BitManipGPRGPRIntrinsics; def int_riscv_clmul : BitManipGPRGPRIntrinsics;
def int_riscv_clmulh : BitManipGPRGPRIntrinsics; def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
def int_riscv_clmulr : BitManipGPRGPRIntrinsics; def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
// Zbp
def int_riscv_grev : BitManipGPRGPRIntrinsics;
def int_riscv_gorc : BitManipGPRGPRIntrinsics;
def int_riscv_shfl : BitManipGPRGPRIntrinsics;
def int_riscv_unshfl : BitManipGPRGPRIntrinsics;
def int_riscv_xperm_n : BitManipGPRGPRIntrinsics;
def int_riscv_xperm_b : BitManipGPRGPRIntrinsics;
def int_riscv_xperm_h : BitManipGPRGPRIntrinsics;
def int_riscv_xperm_w : BitManipGPRGPRIntrinsics;
// Zbr // Zbr
def int_riscv_crc32_b : BitManipGPRIntrinsics; def int_riscv_crc32_b : BitManipGPRIntrinsics;
def int_riscv_crc32_h : BitManipGPRIntrinsics; def int_riscv_crc32_h : BitManipGPRIntrinsics;
def int_riscv_crc32_w : BitManipGPRIntrinsics; def int_riscv_crc32_w : BitManipGPRIntrinsics;
def int_riscv_crc32_d : BitManipGPRIntrinsics; def int_riscv_crc32_d : BitManipGPRIntrinsics;
def int_riscv_crc32c_b : BitManipGPRIntrinsics; def int_riscv_crc32c_b : BitManipGPRIntrinsics;
def int_riscv_crc32c_h : BitManipGPRIntrinsics; def int_riscv_crc32c_h : BitManipGPRIntrinsics;
def int_riscv_crc32c_w : BitManipGPRIntrinsics; def int_riscv_crc32c_w : BitManipGPRIntrinsics;
▲ Show 20 Lines • Show All 1,133 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
// TableGen chokes when faced with commutative permutations in deeply-nested // TableGen chokes when faced with commutative permutations in deeply-nested
// DAGs. Each node takes an input operand and a control operand and outputs a // DAGs. Each node takes an input operand and a control operand and outputs a
// bit-manipulated version of input. All operands are i32 or XLenVT. // bit-manipulated version of input. All operands are i32 or XLenVT.
GREV, GREV,
GREVW, GREVW,
GORC, GORC,
GORCW, GORCW,
SHFL, SHFL,
SHFLW,
UNSHFL,
UNSHFLW,
// Vector Extension // Vector Extension
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
// for the VL value to be used for the operation. // for the VL value to be used for the operation.
VMV_V_X_VL, VMV_V_X_VL,
// VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
// for the VL value to be used for the operation. // for the VL value to be used for the operation.
VFMV_V_F_VL, VFMV_V_F_VL,
// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
▲ Show 20 Lines • Show All 465 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines if (Subtarget.hasStdExtZbp()) {
// Custom lower bswap/bitreverse so we can convert them to GREVI to enable // Custom lower bswap/bitreverse so we can convert them to GREVI to enable
// more combining. // more combining.
setOperationAction(ISD::BITREVERSE, XLenVT, Custom); setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
setOperationAction(ISD::BSWAP, XLenVT, Custom); setOperationAction(ISD::BSWAP, XLenVT, Custom);
if (Subtarget.is64Bit()) { if (Subtarget.is64Bit()) {
setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
setOperationAction(ISD::BSWAP, MVT::i32, Custom); setOperationAction(ISD::BSWAP, MVT::i32, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
} }
} else { } else {
// With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
// pattern match it directly in isel. // pattern match it directly in isel.
setOperationAction(ISD::BSWAP, XLenVT, setOperationAction(ISD::BSWAP, XLenVT,
Subtarget.hasStdExtZbb() ? Legal : Expand); Subtarget.hasStdExtZbb() ? Legal : Expand);
} }
▲ Show 20 Lines • Show All 2,736 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::thread_pointer: { case Intrinsic::thread_pointer: {
EVT PtrVT = getPointerTy(DAG.getDataLayout()); EVT PtrVT = getPointerTy(DAG.getDataLayout());
return DAG.getRegister(RISCV::X4, PtrVT); return DAG.getRegister(RISCV::X4, PtrVT);
} }
case Intrinsic::riscv_orc_b: case Intrinsic::riscv_orc_b:
// Lower to the GORCI encoding for orc.b. // Lower to the GORCI encoding for orc.b.
return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1), return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
DAG.getConstant(7, DL, XLenVT)); DAG.getConstant(7, DL, XLenVT));
case Intrinsic::riscv_grev:
case Intrinsic::riscv_gorc: {
unsigned Opc = IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    unsigned Opc = IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
+    unsigned Opc =
+        IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
Lint: Pre-merge checks: clang-format: please reformat the code ``` - unsigned Opc = IntNo == Intrinsic::riscv_grev ?
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
}
case Intrinsic::riscv_shfl:
case Intrinsic::riscv_unshfl: {
unsigned Opc = IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    unsigned Opc = IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
+    unsigned Opc =
+        IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
Lint: Pre-merge checks: clang-format: please reformat the code ``` - unsigned Opc = IntNo == Intrinsic::riscv_shfl ?
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
}
case Intrinsic::riscv_vmv_x_s: case Intrinsic::riscv_vmv_x_s:
assert(Op.getValueType() == XLenVT && "Unexpected VT!"); assert(Op.getValueType() == XLenVT && "Unexpected VT!");
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
Op.getOperand(1)); Op.getOperand(1));
case Intrinsic::riscv_vmv_v_x: case Intrinsic::riscv_vmv_v_x:
return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2), return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),
Op.getSimpleValueType(), DL, DAG, Subtarget); Op.getSimpleValueType(), DL, DAG, Subtarget);
case Intrinsic::riscv_vfmv_v_f: case Intrinsic::riscv_vfmv_v_f:
▲ Show 20 Lines • Show All 1,491 Lines • ▼ Show 20 Lines case Intrinsic::riscv_orc_b: {
// If Zbp is enabled, use GORCIW which will sign extend the result. // If Zbp is enabled, use GORCIW which will sign extend the result.
unsigned Opc = unsigned Opc =
Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC; Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC;
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp, SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
DAG.getConstant(7, DL, MVT::i64)); DAG.getConstant(7, DL, MVT::i64));
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res)); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
return; return;
} }
case Intrinsic::riscv_grev:
case Intrinsic::riscv_gorc: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
SDValue NewOp1 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
SDValue NewOp2 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
unsigned Opc =
IntNo == Intrinsic::riscv_grev ? RISCVISD::GREVW : RISCVISD::GORCW;
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
break;
}
case Intrinsic::riscv_shfl:
case Intrinsic::riscv_unshfl: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
SDValue NewOp1 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
SDValue NewOp2 =
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
unsigned Opc =
IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFLW : RISCVISD::UNSHFLW;
if (isa<ConstantSDNode>(N->getOperand(2))) {
NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2,
DAG.getConstant(0xf, DL, MVT::i64));
Opc =
IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
}
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
break;
}
case Intrinsic::riscv_vmv_x_s: { case Intrinsic::riscv_vmv_x_s: {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
if (VT.bitsLT(XLenVT)) { if (VT.bitsLT(XLenVT)) {
// Simple case just extract using vmv.x.s and truncate. // Simple case just extract using vmv.x.s and truncate.
SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL, SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
Subtarget.getXLenVT(), N->getOperand(1)); Subtarget.getXLenVT(), N->getOperand(1));
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract)); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));
▲ Show 20 Lines • Show All 928 Lines • ▼ Show 20 Linesunsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
case RISCVISD::DIVUW: case RISCVISD::DIVUW:
case RISCVISD::REMUW: case RISCVISD::REMUW:
case RISCVISD::ROLW: case RISCVISD::ROLW:
case RISCVISD::RORW: case RISCVISD::RORW:
case RISCVISD::GREVW: case RISCVISD::GREVW:
case RISCVISD::GORCW: case RISCVISD::GORCW:
case RISCVISD::FSLW: case RISCVISD::FSLW:
case RISCVISD::FSRW: case RISCVISD::FSRW:
case RISCVISD::SHFLW:
case RISCVISD::UNSHFLW:
// TODO: As the result is sign-extended, this is conservatively correct. A // TODO: As the result is sign-extended, this is conservatively correct. A
// more precise answer could be calculated for SRAW depending on known // more precise answer could be calculated for SRAW depending on known
// bits in the shift amount. // bits in the shift amount.
return 33; return 33;
case RISCVISD::SHFL: { case RISCVISD::SHFL:
case RISCVISD::UNSHFL: {
// There is no SHFLIW, but a i64 SHFLI with bit 4 of the control word // There is no SHFLIW, but a i64 SHFLI with bit 4 of the control word
// cleared doesn't affect bit 31. The upper 32 bits will be shuffled, but // cleared doesn't affect bit 31. The upper 32 bits will be shuffled, but
// will stay within the upper 32 bits. If there were more than 32 sign bits // will stay within the upper 32 bits. If there were more than 32 sign bits
// before there will be at least 33 sign bits after. // before there will be at least 33 sign bits after.
if (Op.getValueType() == MVT::i64 && if (Op.getValueType() == MVT::i64 &&
isa<ConstantSDNode>(Op.getOperand(1)) && isa<ConstantSDNode>(Op.getOperand(1)) &&
(Op.getConstantOperandVal(1) & 0x10) == 0) { (Op.getConstantOperandVal(1) & 0x10) == 0) {
unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1); unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
▲ Show 20 Lines • Show All 1,725 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(FMV_W_X_RV64) NODE_NAME_CASE(FMV_W_X_RV64)
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64) NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
NODE_NAME_CASE(READ_CYCLE_WIDE) NODE_NAME_CASE(READ_CYCLE_WIDE)
NODE_NAME_CASE(GREV) NODE_NAME_CASE(GREV)
NODE_NAME_CASE(GREVW) NODE_NAME_CASE(GREVW)
NODE_NAME_CASE(GORC) NODE_NAME_CASE(GORC)
NODE_NAME_CASE(GORCW) NODE_NAME_CASE(GORCW)
NODE_NAME_CASE(SHFL) NODE_NAME_CASE(SHFL)
NODE_NAME_CASE(SHFLW)
NODE_NAME_CASE(UNSHFL)
NODE_NAME_CASE(UNSHFLW)
NODE_NAME_CASE(VMV_V_X_VL) NODE_NAME_CASE(VMV_V_X_VL)
NODE_NAME_CASE(VFMV_V_F_VL) NODE_NAME_CASE(VFMV_V_F_VL)
NODE_NAME_CASE(VMV_X_S) NODE_NAME_CASE(VMV_X_S)
NODE_NAME_CASE(VMV_S_X_VL) NODE_NAME_CASE(VMV_S_X_VL)
NODE_NAME_CASE(VFMV_S_F_VL) NODE_NAME_CASE(VFMV_S_F_VL)
NODE_NAME_CASE(SPLAT_VECTOR_I64) NODE_NAME_CASE(SPLAT_VECTOR_I64)
NODE_NAME_CASE(READ_VLENB) NODE_NAME_CASE(READ_VLENB)
NODE_NAME_CASE(TRUNCATE_VECTOR_VL) NODE_NAME_CASE(TRUNCATE_VECTOR_VL)
▲ Show 20 Lines • Show All 746 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Show All 24 Lines
def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>; def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>; def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>;
def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>; def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>; def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>; def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>; def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>; def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>; def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
craig.topperUnsubmitted
Done
ReplyInline Actions

Line the colons up

craig.topper: Line the colons up
def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW", SDT_RISCVIntBinOpW>;
def UImmLog2XLenHalfAsmOperand : AsmOperandClass { def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
let Name = "UImmLog2XLenHalf"; let Name = "UImmLog2XLenHalf";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
let DiagnosticType = "InvalidUImmLog2XLenHalf"; let DiagnosticType = "InvalidUImmLog2XLenHalf";
} }
def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{ def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Linesdef : InstAlias<"ror $rd, $rs1, $shamt",
(RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>; (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
} // Predicates = [HasStdExtZbbOrZbp] } // Predicates = [HasStdExtZbbOrZbp]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
def : InstAlias<"rorw $rd, $rs1, $shamt", def : InstAlias<"rorw $rd, $rs1, $shamt",
(RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>; (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
} // Predicates = [HasStdExtZbbOrZbp, IsRV64] } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
let Predicates = [HasStdExtZbp] in {
def : InstAlias<"grev $rd, $rs1, $shamt",
(GREVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
def : InstAlias<"gorc $rd, $rs1, $shamt",
(GORCI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
def : InstAlias<"shfl $rd, $rs1, $shamt",
(SHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
def : InstAlias<"unshfl $rd, $rs1, $shamt",
(UNSHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbp, IsRV64] in {
def : InstAlias<"grevw $rd, $rs1, $shamt",
(GREVIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
def : InstAlias<"gorcw $rd, $rs1, $shamt",
(GORCIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbs] in { let Predicates = [HasStdExtZbs] in {
def : InstAlias<"bset $rd, $rs1, $shamt", def : InstAlias<"bset $rd, $rs1, $shamt",
(BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>; (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
def : InstAlias<"bclr $rd, $rs1, $shamt", def : InstAlias<"bclr $rd, $rs1, $shamt",
(BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>; (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
def : InstAlias<"binv $rd, $rs1, $shamt", def : InstAlias<"binv $rd, $rs1, $shamt",
(BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>; (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
def : InstAlias<"bext $rd, $rs1, $shamt", def : InstAlias<"bext $rd, $rs1, $shamt",
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesdef : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
(RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>; (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
// We treat orc.b as a separate instruction, so match it directly. We also // We treat orc.b as a separate instruction, so match it directly. We also
// lower the Zbb orc.b intrinsic to this. // lower the Zbb orc.b intrinsic to this.
def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>; def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
} }
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
def : PatGprGpr<riscv_grev, GREV>;
def : PatGprGpr<riscv_gorc, GORC>;
def : PatGprGpr<riscv_shfl, SHFL>;
def : PatGprGpr<riscv_unshfl, UNSHFL>;
def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>; def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>; def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>; def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
} // Predicates = [HasStdExtZbp] } // Predicates = [HasStdExtZbp]
craig.topperUnsubmitted
Done
ReplyInline Actions

Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together

craig.topper: Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together
let Predicates = [HasStdExtZbp, IsRV32] in { let Predicates = [HasStdExtZbp, IsRV32] in {
def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>; def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>; def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
// We treat rev8 as a separate instruction, so match it directly. // We treat rev8 as a separate instruction, so match it directly.
def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>; def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
} // Predicates = [HasStdExtZbp, IsRV32] } // Predicates = [HasStdExtZbp, IsRV32]
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
def : PatGprImm<riscv_rorw, RORIW, uimm5>; def : PatGprImm<riscv_rorw, RORIW, uimm5>;
def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2), def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>; (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
} // Predicates = [HasStdExtZbbOrZbp, IsRV64] } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
let Predicates = [HasStdExtZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>; def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>; def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
def : PatGprGpr<riscv_grevw, GREVW>;
def : PatGprGpr<riscv_gorcw, GORCW>;
def : PatGprGpr<riscv_shflw, SHFLW>;
def : PatGprGpr<riscv_unshflw, UNSHFLW>;
def : PatGprImm<riscv_grevw, GREVIW, uimm5>; def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
def : PatGprImm<riscv_gorcw, GORCIW, uimm5>; def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbt, IsRV64] in { let Predicates = [HasStdExtZbt, IsRV64] in {
def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2), def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
(FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2), def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),
Show All 22 Lines
let Predicates = [HasStdExtZbc] in { let Predicates = [HasStdExtZbc] in {
def : PatGprGpr<int_riscv_clmul, CLMUL>; def : PatGprGpr<int_riscv_clmul, CLMUL>;
def : PatGprGpr<int_riscv_clmulh, CLMULH>; def : PatGprGpr<int_riscv_clmulh, CLMULH>;
def : PatGprGpr<int_riscv_clmulr, CLMULR>; def : PatGprGpr<int_riscv_clmulr, CLMULR>;
} // Predicates = [HasStdExtZbc] } // Predicates = [HasStdExtZbc]
let Predicates = [HasStdExtZbr] in { let Predicates = [HasStdExtZbr] in {
def : PatGpr<int_riscv_crc32_b, CRC32B>; def : PatGpr<int_riscv_crc32_b, CRC32B>;
craig.topperUnsubmitted
Done
ReplyInline Actions

Put these in the same block that has PatGprImm<riscv_grev

craig.topper: Put these in the same block that has PatGprImm<riscv_grev
def : PatGpr<int_riscv_crc32_h, CRC32H>; def : PatGpr<int_riscv_crc32_h, CRC32H>;
def : PatGpr<int_riscv_crc32_w, CRC32W>; def : PatGpr<int_riscv_crc32_w, CRC32W>;
def : PatGpr<int_riscv_crc32c_b, CRC32CB>; def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
def : PatGpr<int_riscv_crc32c_h, CRC32CH>; def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
def : PatGpr<int_riscv_crc32c_w, CRC32CW>; def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
} // Predicates = [HasStdExtZbr] } // Predicates = [HasStdExtZbr]
let Predicates = [HasStdExtZbr, IsRV64] in { let Predicates = [HasStdExtZbr, IsRV64] in {
def : PatGpr<int_riscv_crc32_d, CRC32D>; def : PatGpr<int_riscv_crc32_d, CRC32D>;
def : PatGpr<int_riscv_crc32c_d, CRC32CD>; def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
} // Predicates = [HasStdExtZbr, IsRV64] } // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IB
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define i32 @grev32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: grev32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: grev a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: grev32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: grev a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.grevi.i32(i32 %a)
define i32 @grevi32(i32 %a) nounwind {
; RV32IB-LABEL: grevi32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: grevi a0, a0, 13
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: grevi32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: grevi a0, a0, 13
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define i32 @gorc32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: gorc32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: gorc a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: gorc32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: gorc a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.gorci.i32(i32 %a)
define i32 @gorci32(i32 %a) nounwind {
; RV32IB-LABEL: gorci32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: gorci a0, a0, 13
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: gorci32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: gorci a0, a0, 13
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define i32 @shfl32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: shfl32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: shfl a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: shfl32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: shfl a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.shfli.i32(i32 %a)
define i32 @shfli32(i32 %a) nounwind {
; RV32IB-LABEL: shfli32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: shfli a0, a0, 13
; RV32IB-NEXT: ret
craig.topperUnsubmitted
Done
ReplyInline Actions

This immediate is too large to make shfli. It needs to b 4 bits for i32.

craig.topper: This immediate is too large to make shfli. It needs to b 4 bits for i32.
;
; RV32IBP-LABEL: shfli32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: shfli a0, a0, 13
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define i32 @unshfl32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: unshfl32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: unshfl a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: unshfl32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: unshfl a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.unshfli.i32(i32 %a)
define i32 @unshfli32(i32 %a) nounwind {
; RV32IB-LABEL: unshfli32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: unshfli a0, a0, 13
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: unshfli32:
craig.topperUnsubmitted
Done
ReplyInline Actions

Same here

craig.topper: Same here
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: unshfli a0, a0, 13
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
define i32 @xpermn32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: xpermn32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: xperm.n a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: xpermn32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: xperm.n a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
define i32 @xpermb32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: xpermb32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: xperm.b a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: xpermb32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: xperm.b a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
define i32 @xpermh32(i32 %a, i32 %b) nounwind {
; RV32IB-LABEL: xpermh32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: xperm.h a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: xpermh32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: xperm.h a0, a0, a1
; RV32IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
ret i32 %tmp
}

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IB
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: grev32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: grevw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: grev32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: grevw a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.grevi.i32(i32 %a)
define signext i32 @grevi32(i32 signext %a) nounwind {
; RV64IB-LABEL: grevi32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: greviw a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: grevi32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: greviw a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: gorc32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: gorcw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: gorc32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: gorcw a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.gorci.i32(i32 %a)
define signext i32 @gorci32(i32 signext %a) nounwind {
; RV64IB-LABEL: gorci32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: gorciw a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: gorci32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: gorciw a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: shfl32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: shflw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: shfl32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: shflw a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.shfli.i32(i32 %a)
define signext i32 @shfli32(i32 signext %a) nounwind {
; RV64IB-LABEL: shfli32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: shfli a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: shfli32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: shfli a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: unshfl32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: unshflw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: unshfl32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: unshflw a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.unshfli.i32(i32 %a)
define signext i32 @unshfli32(i32 signext %a) nounwind {
; RV64IB-LABEL: unshfli32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: unshfli a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: unshfli32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: unshfli a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
ret i32 %tmp
}
declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
define i64 @grev64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: grev64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: grev a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: grev64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: grev a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.grevi.i64(i64 %a)
define i64 @grevi64(i64 %a) nounwind {
; RV64IB-LABEL: grevi64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: grevi a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: grevi64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: grevi a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 13)
ret i64 %tmp
}
declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
define i64 @gorc64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: gorc64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: gorc a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: gorc64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: gorc a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.gorci.i64(i64 %a)
define i64 @gorci64(i64 %a) nounwind {
; RV64IB-LABEL: gorci64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: gorci a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: gorci64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: gorci a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.gorc.i64(i64 %a, i64 13)
ret i64 %tmp
}
declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
define i64 @shfl64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: shfl64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: shfl a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: shfl64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: shfl a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.shfli.i64(i64 %a)
define i64 @shfli64(i64 %a) nounwind {
; RV64IB-LABEL: shfli64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: shfli a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: shfli64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: shfli a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 13)
ret i64 %tmp
}
declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
define i64 @unshfl64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: unshfl64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: unshfl a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: unshfl64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: unshfl a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.unshfli.i64(i64 %a)
define i64 @unshfli64(i64 %a) nounwind {
; RV64IB-LABEL: unshfli64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: unshfli a0, a0, 13
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: unshfli64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: unshfli a0, a0, 13
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 13)
ret i64 %tmp
}
declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
define i64 @xpermn64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: xpermn64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: xperm.n a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: xpermn64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: xperm.n a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
define i64 @xpermb64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: xpermb64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: xperm.b a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: xpermb64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: xperm.b a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
define i64 @xpermh64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: xpermh64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: xperm.h a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: xpermh64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: xperm.h a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
define i64 @xpermw64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: xpermw64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: xperm.w a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: xpermw64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: xperm.w a0, a0, a1
; RV64IBP-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
ret i64 %tmp
}

llvm/test/MC/RISCV/rv32b-aliases-valid.s

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Lines
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 # CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8 # CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8 binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8 # CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8 bext x5, x6, 8
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
# CHECK-S-OBJ: grevi t0, t1, 13
grev x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
# CHECK-S-OBJ: gorci t0, t1, 13
gorc x5, x6, 13
# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
# CHECK-S-OBJ: shfli t0, t1, 13
shfl x5, x6, 13
craig.topperUnsubmitted
Done
ReplyInline Actions

This test fails check-llvm because 29 isn't a shfl_uimm on RV32

craig.topper: This test fails check-llvm because 29 isn't a shfl_uimm on RV32
# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
# CHECK-S-OBJ: unshfli t0, t1, 13
unshfl x5, x6, 13

llvm/test/MC/RISCV/rv64b-aliases-valid.s

Show First 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8 # CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
# CHECK-S-OBJ: binvi t0, t1, 8 # CHECK-S-OBJ: binvi t0, t1, 8
binv x5, x6, 8 binv x5, x6, 8
# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
# CHECK-S-OBJ: bexti t0, t1, 8 # CHECK-S-OBJ: bexti t0, t1, 8
bext x5, x6, 8 bext x5, x6, 8
# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
# CHECK-S-OBJ: grevi t0, t1, 13
grev x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
# CHECK-S-OBJ: gorci t0, t1, 13
gorc x5, x6, 13
# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
# CHECK-S-OBJ: shfli t0, t1, 13
shfl x5, x6, 13
# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
# CHECK-S-OBJ: unshfli t0, t1, 13
unshfl x5, x6, 13
# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
# CHECK-S-OBJ: greviw t0, t1, 13
grevw x5, x6, 13
# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
# CHECK-S-OBJ: gorciw t0, t1, 13
gorcw x5, x6, 13