[RISCV] Initially support the K-extension instructions on the LLVM MC layer

[VincentWu]

Summary

This commit is currently implementing supports for scalar cryptography extension for LLVM according to version v1.0.0 of K Ext specification(scala crypto has been ratified already). Currently, we are implementing the MC (Machine Code) layer of his extension and the majority of work is done under llvm/lib/Target/RISCV directory. There are also some test files in llvm/test/MC/RISCV directory.

Remove the subfeature of Zbk* which conflict with b extensions to reduce the size of the patch.
(Zbk* will be resubmit after this patch has been merged)

Co-author：@ksyx & @VincentWu & @lihongliang & @achieveartificialintelligence

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

14

Blank line before

21

Blank line after

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

45 ↗

(On Diff #328842)

Isn't this the round, which is then used to derive the 8-bit round constant, not the round constant itself?

58 ↗

(On Diff #328842)

If you don't have scheduling defined yet just don't add Sched<[]> at all?

74 ↗

(On Diff #328842)

Assembler Pseudo Instructions

to distinguish from LLVM Pseudos.

75 ↗

(On Diff #328842)

Naming aliases is pointless

133 ↗

(On Diff #328842)

Should be fixed

llvm/lib/Target/RISCV/RISCVSubtarget.h

17

Be consistent whether it's "V K Zv*" or "V Zv* K" (latter being what you've done in TableGen). I think I prefer grouping all the V stuff together even if technically Z* extensions sort after all the single-letter ones.

Also, you will need to get the canonical order updated to include K at some point, though it seems relatively safe to assume it'll just be tacked on the end, i.e. after V (and N).

llvm/lib/Target/RISCV/RISCVSystemOperands.td

4

Machine Scalar Cryptography CSRs

? I think these headings come from the ISA manual, but K should be consistent both here and in its spec.

llvm/test/MC/RISCV/rvk/rv32k.s

1 ↗

(On Diff #328842)

You should have 3 files:

rv32k-valid.s - Tests the instructions common between RV32K and RV64K, with RUN lines for both

rv32k-only-valid.s - Tests the instructions only present in RV32K

rv64k-valid.s - Tests the additional instructions in RV64K

12 ↗

(On Diff #328842)

CHECK lines come before not after

144 ↗

(On Diff #328842)

Fix

llvm/test/MC/RISCV/rvk/rv64k.s

126 ↗

(On Diff #328842)

Fix

llvm/test/MC/RISCV/rvk/rvk-invalid.s

1 ↗

(On Diff #328842)

Needs to be testing both RV32 and RV64 including instructions specific to each, similar to what I said for the tests above.

[VincentWu]

style: formate the whitespace, annotation&code style

[VincentWu]

fix: submit wrong patch

[VincentWu]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

9 ↗

(On Diff #328840)

yes, it is a typo, my fault

45 ↗

(On Diff #328842)

I'm a little confused about that. So do you mean number rcon is a kind of offset or something？and we need an extra base address?

58 ↗

(On Diff #328842)

yes, but there will be something wrong whing building if I just remove the Sched<[]>. and we found that the RISCVInstrInfoB.td which is already merged also put an empty Sched<[]> there. So we put it there too.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

45 ↗

(On Diff #328842)

No. Wikipedia has details (https://en.wikipedia.org/wiki/AES_key_schedule#Round_constants), but basically the the round number counts up 1 by 1, but the actual round constant is a function of the round number (either implemented with a simple table or the slightly more general formula). I've filed https://github.com/riscv/riscv-crypto/issues/82 about this, but given that's what the spec currently calls it I think it's fine to call it rcon in LLVM.

58 ↗

(On Diff #328842)

That shouldn't be the case if you add HasStdExtK to UnsupportedFeatures for the models

18–19 ↗

(On Diff #328955)

Indenting is still off:

• 2 spaces not 4
• we don't typically indent inside lets

58 ↗

(On Diff #328955)

Only one space after the colon

66–69 ↗

(On Diff #328955)

I think it'd be neater to make this a separate "group" (i.e. add a blank line between SHA256SIG1 and SM3P0, and then not align the new group with the sha256 ones), as that'll cut down on the number of spaces

97–104 ↗

(On Diff #328955)

Line things up properly if you're going to go to the trouble of doing it

llvm/test/MC/RISCV/rvk/rv32k-valid.s

1 ↗

(On Diff #328955)

These files probably don't need to be in their own subdirectory. RVV has one, but that's only because it's such a huge extension, whereas this is a much smaller extension so can be like how we're testing all the others.

llvm/test/MC/RISCV/rvk/rvk32-invalid.s

1 ↗

(On Diff #328955)

File should be rv32k- not rvk32 (same for the file below)

2 ↗

(On Diff #328955)

Need a riscv64 RUN line

[VincentWu]

llvm/test/MC/RISCV/rvk/rv32k-valid.s

67 ↗

(On Diff #328955)

need fix

[VincentWu]

• style: formate the code
• refactor: use rcon class to limit the imm range
• Test: add 64bit test case
• move test cases
• fix: fix wrong CHECK-INST

[VincentWu]

fix: submit the wrong patch file

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

9 ↗

(On Diff #330449)

I'd base this comment on the one in RISCVInstrInfoB.td, better documenting this is a not-yet-ratified extension.

[VincentWu]

Classifies instructions into their corresponding functional subset
add more test case for Zkg&Zkg which share instructions from B ext

[VincentWu]

llvm/lib/Target/RISCV/RISCVSchedRocket.td

2–1

it seems too long, but we haven't found a good way to shorten them. have any ideas?

[Jim]

llvm/lib/Target/RISCV/RISCV.td

74–1

Add blank line

76

and others

106

Alignment

135

Alignment

152

Add blank line

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

20

This line has undefined behavior if the user tries to pass a value near INT64_MAX since the +5 would wrap around which isn't undefined.

But I'm not sure it does what you want. This would accept -5, -4, -3, -2, and -1.

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

23 ↗

(On Diff #335205)

This isUint<4>(Imm) doesn't match what's in the asm parser.

[VincentWu]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

20

right it's my fault. I forgot the numbers -5~-1, the spec defines the range of number is [0,10], I limit the upper bound is (1 << 4) -5 but forget it also causes the wrong lower bound. I will fix it soon.

[Jim]

Revision Contents look weired. Does this patch upload by git diff -U99999?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

15

Just write 10. I don't think subtracting 6 from 16 makes this very readability. The other places, the name of the error has the number of bits in its name, so using that bit width(or 1 less than it) in the creation of the constants makes sense.

20

Space after the first "Imm"

[VincentWu]

In D98136#2691388, @Jim wrote:

Revision Contents look weired. Does this patch upload by git diff -U99999?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

I checked history and made sure I did use the parameter -U99999, so I don't know where the strange part is, I'll upload a new version.

[VincentWu]

[RISCV][MC][K-ext] Fix wrong input DAG for ByteSelect cls

[kito-cheng]

Could you handle k* extension for ELF attribute?

RISCVAsmParser::parseDirectiveAttribute@lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
RISCVTargetStreamer::emitTargetAttributes@MCTargetDesc/RISCVTargetStreamer.cpp

[VincentWu]

handle k* extension for ELF attribute

[VincentWu]

update the implemention to adopt the spec v1.0.0-rc1
co-worker @lihongliang

[VincentWu]

• [RISCV] style: formate the code of RISCVAsmParser.cpp

[VincentWu]

This comment was removed by VincentWu.

[VincentWu]

update the code to adopt the spec v1.0.0-rc4
co-worker @achieveartificialintelligence

[achieveartificialintelligence]

Ping

[achieveartificialintelligence]

Rebase and Ping.

[liaolucy]

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

83

ROR_K instruction is the same as the B-ext.
./RISCVInstrInfoZb.td: def ROR : ALU_rr<0b0110000, 0b101, "ror">,

Do we need to redefine this instruction? Does anyone have any Suggestions?

[VincentWu]

add Entropy Source CSR

Remove the subfeature of Zbk* which conflict with b extensions to reduce the size of the patch.
(Zbk* will be resubmit after this patch has been merged)

Co-author：@nannan1025

[liaolucy]

llvm/lib/Support/RISCVISAInfo.cpp

80

Should zbkb extension be removed?

[liaolucy]

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

11

Is version 1.0-rc4? The latest version is 1.0.0-rc6.

[VincentWu]

fix issues mentioned on comment

[VincentWu]

PING

The latest spec (rc-6) of the scalar crypto extension has been released for almost two months. That means that the scalar crypto extensions have become stable.
Also the GCC seems to have merged the patch for scalar crypto extensions into the upstream
So I think it is time to decide whether this patch should be merged or not.

Although I understand that this patch may be a bit large, I would still like someone to review it again and tell me if this patch can be merged or still needs to be modified

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

54

This needs to be rebased. Zba/b/c/s were all moved to non-experimental recently

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

430 ↗

(On Diff #397446)

This looks unrelated to the rest of the patch.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

54

line this up with funct3 on the previous line

62

Indent ths two more spaces

70

indent this 2 more spaces to line up with funct3

llvm/lib/Target/RISCV/RISCVSystemOperands.td

363

Space after the comma like the rest of the file

[eopXD]

llvm/lib/Support/RISCVISAInfo.cpp

89

Regarding zkn, zks, zk, D112359 added extension implication as a separate function. I think you may need to rebase and do some modifications.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

430 ↗

(On Diff #397446)

Cleanup?

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

202

Is this Predicate needed? Zkn is just a convenience to enable multiple extensions. No instructions belong to it right?

211

Is this Predicate needed? Zks is just a convenience to enable multiple extensions. No instructions belong to it right?

218

This Predicate doesn't appear to be used on any instructions. Just the scheduler model

228

Is this Predicate needed? Zk is just a convenience to enable multiple extensions. No instructions belong to it right?

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

38

Is this class used?

45

Is this class used?

54

I don't think we should put Sched<[]> inside the generic classes. We'll need to be able to add per instruction information in the future.

72

This line is over indented

[VincentWu]

fix comment

scala crypto has been ratified already, remove description "-rc6"

[VincentWu]

add new line at end of file

[VincentWu]

emove ext verision number

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1254

(1 << 4) - 6 -> 10. There's no reason to write a more complex expression. It makes more sense for things like Match_InvalidUImm2 to show the connection between the name of the error and the integer values. That doesn't apply here.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

1

K -> Zk in both places

9

K -> Zk

24

This ImmLeaf should check 0-10. Alternatively it can be removed until CodeGen support is added.

28

It's not a UIMM4. It should have its own OPERAND type and the range check for it in X86InstrInfo.cpp should check 0-10.

llvm/lib/Target/RISCV/RISCVSchedRocket.td

20

This line needs to rebased I think. I'll also be removed Zvlsseg later today.

[VincentWu]

rebase and fix comments

[VincentWu]

updete

[VincentWu]

rebase and update

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1150 ↗

(On Diff #402163)

Missing "break;" This will be a problem the next time someone adds a case after this one.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

2

Scala -> Scalar

10

ZK -> Zk

[craig.topper]

Please remove [RFC] from the review name. We shouldn't have that in the commit message.

[VincentWu]

address comment & remove [RFC] from title

[craig.topper]

LGTM

[VincentWu]

rebase

[VincentWu]

In D98136#3265096, @craig.topper wrote:

LGTM

Thanks -)

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1150 ↗

(On Diff #402163)

oops, sorry my bad, fixed

[RKSimon]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1149 ↗

(On Diff #402402)

@VincentWu Coverity is warning that this is dead code as RISCVOp::OPERAND_RVKRNU > RISCVOp::OPERAND_LAST_RISCV_IMM

[VincentWu]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1149 ↗

(On Diff #402402)

I am very sorry for this error, how do I fix it?
i mean, should I create a new Differential Revision? Or modify the commit in some way?

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"a", RISCVExtensionVersion{2, 0}},
     {"f", RISCVExtensionVersion{2, 0}},
     {"d", RISCVExtensionVersion{2, 0}},
     {"c", RISCVExtensionVersion{2, 0}},
 
     {"zfhmin", RISCVExtensionVersion{1, 0}},
     {"zfh", RISCVExtensionVersion{1, 0}},
 
     {"zba", RISCVExtensionVersion{1, 0}},
     {"zbb", RISCVExtensionVersion{1, 0}},
     {"zbc", RISCVExtensionVersion{1, 0}},
     {"zbs", RISCVExtensionVersion{1, 0}},
+
+    {"zknd", RISCVExtensionVersion{1, 0}},
+    {"zkne", RISCVExtensionVersion{1, 0}},
+    {"zknh", RISCVExtensionVersion{1, 0}},
+    {"zksed", RISCVExtensionVersion{1, 0}},
+    {"zksh", RISCVExtensionVersion{1, 0}},
+    {"zkr", RISCVExtensionVersion{1, 0}},
+    {"zkn", RISCVExtensionVersion{1, 0}},
+    {"zks", RISCVExtensionVersion{1, 0}},
+    {"zkt", RISCVExtensionVersion{1, 0}},
+    {"zk", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"v", RISCVExtensionVersion{0, 10}},
     {"zbe", RISCVExtensionVersion{0, 93}},
     {"zbf", RISCVExtensionVersion{0, 93}},
     {"zbm", RISCVExtensionVersion{0, 93}},
     {"zbp", RISCVExtensionVersion{0, 93}},
     {"zbr", RISCVExtensionVersion{0, 93}},
     {"zbt", RISCVExtensionVersion{0, 93}},
 
     {"zvlsseg", RISCVExtensionVersion{0, 10}},
     {"zvl32b", RISCVExtensionVersion{0, 10}},
     {"zvl64b", RISCVExtensionVersion{0, 10}},
     {"zvl128b", RISCVExtensionVersion{0, 10}},
     {"zvl256b", RISCVExtensionVersion{0, 10}},
     {"zvl512b", RISCVExtensionVersion{0, 10}},
     {"zvl1024b", RISCVExtensionVersion{0, 10}},
     {"zvl2048b", RISCVExtensionVersion{0, 10}},
     {"zvl4096b", RISCVExtensionVersion{0, 10}},
     {"zvl8192b", RISCVExtensionVersion{0, 10}},
     {"zvl16384b", RISCVExtensionVersion{0, 10}},
     {"zvl32768b", RISCVExtensionVersion{0, 10}},
     {"zvl65536b", RISCVExtensionVersion{0, 10}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }

 static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"};
 static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"};
 static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"};
 static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
 static const char *ImpliedExtsZvl512b[] = {"zvl256b"};
 static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
+static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
+static const char *ImpliedExtsZkn[] = {"zkne", "zknd", "zknh"};
+static const char *ImpliedExtsZks[] = {"zksed", "zksh"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
     {{"zfh"}, {ImpliedExtsZfh}},
+    {{"zk"}, {ImpliedExtsZk}},
+    {{"zkn"}, {ImpliedExtsZkn}},
+    {{"zks"}, {ImpliedExtsZks}},
     {{"zvl1024b"}, {ImpliedExtsZvl1024b}},
     {{"zvl128b"}, {ImpliedExtsZvl128b}},
     {{"zvl16384b"}, {ImpliedExtsZvl16384b}},
     {{"zvl2048b"}, {ImpliedExtsZvl2048b}},
     {{"zvl256b"}, {ImpliedExtsZvl256b}},
     {{"zvl32768b"}, {ImpliedExtsZvl32768b}},
     {{"zvl4096b"}, {ImpliedExtsZvl4096b}},
     {{"zvl512b"}, {ImpliedExtsZvl512b}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVAsmBackend.h"
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVMatInt.h"
 #include "MCTargetDesc/RISCVTargetStreamer.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
bool isUImm7() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<7>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isRnumArg() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(10) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isSImm5() const {
     if (!isImm())
       return false;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     int64_t Imm;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
case Match_InvalidVMaskRegister: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be v0.t");
   }
   case Match_InvalidSImm5Plus1: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
                                       (1 << 4),
                                       "immediate must be in the range");
   }
+  case Match_InvalidRnumArg: {
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 6);
+  }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns true and sets RegNo to 0. If IsRV32E then registers

llvm/lib/Target/RISCV/RISCV.td

def FeatureStdExtZba
     : SubtargetFeature<"zba", "HasStdExtZba", "true",
                        "'Zba' (Address calculation 'B' Instructions)">;
 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
                              AssemblerPredicate<(all_of FeatureStdExtZba),
                              "'Zba' (Address calculation 'B' Instructions)">;
 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 
 def FeatureStdExtZbb
     : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
                        "'Zbb' (Base 'B' Instructions)">;
 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbb),
                              "'Zbb' (Base 'B' Instructions)">;
 
 def FeatureStdExtZbc
     : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
                        "'Zbc' (Carry-Less 'B' Instructions)">;
 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbc),
                              "'Zbc' (Carry-Less 'B' Instructions)">;
 
: SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
                        "'Zbf' (Bit-Field 'B' Instructions)">;
 def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbf),
                              "'Zbf' (Bit-Field 'B' Instructions)">;
 
 def FeatureStdExtZbm
     : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
                        "'Zbm' (Matrix 'B' Instructions)">;
 def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbm),
                              "'Zbm' (Matrix 'B' Instructions)">;
 
 def FeatureStdExtZbp
     : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
                        "'Zbp' (Permutation 'B' Instructions)">;
 def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbp),

 def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbs),
                              "'Zbs' (Single-Bit 'B' Instructions)">;
 
 def FeatureStdExtZbt
     : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
                        "'Zbt' (Ternary 'B' Instructions)">;
 def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
                              AssemblerPredicate<(all_of FeatureStdExtZbt),
                              "'Zbt' (Ternary 'B' Instructions)">;
 
 // Some instructions belong to both the basic and the permutation
 // subextensions. They should be enabled if either has been specified.
 def HasStdExtZbbOrZbp
     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
                                    "'Zbb' (Base 'B' Instructions) or "
                                    "'Zbp' (Permutation 'B' Instructions)">;
 
+def FeatureStdExtZknd
+    : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
+                       "'Zknd' (NIST Suite: AES Decryption)">;
+def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZknd),
+                             "'Zknd' (NIST Suite: AES Decryption)">;
+
+def FeatureStdExtZkne
+    : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
+                       "'Zkne' (NIST Suite: AES Encryption)">;
+def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZkne),
+                             "'Zkne' (NIST Suite: AES Encryption)">;
+
+// Some instructions belong to both Zknd and Zkne subextensions.
+// They should be enabled if either has been specified.
+def HasStdExtZkndOrZkne
+    : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
+                AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
+                                   "'Zknd' (NIST Suite: AES Decryption) or "
+                                   "'Zkne' (NIST Suite: AES Encryption)">;
+
+def FeatureStdExtZknh
+    : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
+                       "'Zknh' (NIST Suite: Hash Function Instructions)">;
+def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZknh),
+                             "'Zknh' (NIST Suite: Hash Function Instructions)">;
+
+def FeatureStdExtZksed
+    : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
+                       "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZksed),
+                             "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+
+def FeatureStdExtZksh
+    : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
+                       "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZksh),
+                             "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+
+def FeatureStdExtZkr
+    : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
+                       "'Zkr' (Entropy Source Extension)">;
+def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZkr),
+                             "'Zkr' (Entropy Source Extension)">;
+
+def FeatureStdExtZkn
+    : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
+                       "'Zkn' (NIST Algorithm Suite)",
+                       [FeatureStdExtZkne,
+                        FeatureStdExtZknd,
+                        FeatureStdExtZknh]>;
+
+def FeatureStdExtZks
+    : SubtargetFeature<"zks", "HasStdExtZks", "true",
+                       "'Zks' (ShangMi Algorithm Suite)",
+                       [FeatureStdExtZksed,
+                        FeatureStdExtZksh]>;
+
+def FeatureStdExtZkt
+    : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
+                       "'Zkt' (Data Independent Execution Latency)">;
+
+def FeatureStdExtZk
+    : SubtargetFeature<"zk", "HasStdExtZk", "true",
+                       "'Zk' (Standard scalar cryptography extension)",
+                       [FeatureStdExtZkn,
+                        FeatureStdExtZkr,
+                        FeatureStdExtZkt]>;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtZvl32b : SubtargetFeature<"experimental-zvl32b", "ZvlLen", "ExtZvl::Zvl32b",
                        "'Zvl' (Minimum Vector Length) 32">;
 
 foreach i = { 6-15 } in {
     defvar I = !shl(1, i);
     def FeatureStdExtZvl#I#b :
         SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
                         "'Zvl' (Minimum Vector Length) "#I,
                         [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
 }

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

+//===-- RISCVInstrInfoK.td - RISC-V 'K' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'K',
+// Cryptography Instructions extension, version 1.0.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RnumArg : AsmOperandClass {
+  let Name = "RnumArg";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidRnumArg";
+}
+
+def rnum : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<4>(Imm);}]> {
+  let ParserMatchClass = RnumArg;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<4>";
+  let OperandType = "OPERAND_UIMM4";
+  let OperandNamespace = "RISCVOp";
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVKUnary<bits<12> imm12_in, bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+              opcodestr, "$rd, $rs1">{
+  let imm12 = imm12_in;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVKByteSelect<bits<5> funct5, string opcodestr>
+    : RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2, uimm2:$bs),
+              opcodestr, "$rd, $rs1, $rs2, $bs">{
+  bits<2> bs;
+  let Inst{31-30} = bs;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVKUnary_rnum<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, rnum:$rnum),
+              opcodestr, "$rd, $rs1, $rnum">{
+    bits<4> rnum;
+    let Inst{31-25} = funct7;
+    let Inst{24} = 1;
+    let Inst{23-20} = rnum;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtZknd, IsRV32] in {
+def AES32DSI  : RVKByteSelect<0b10101, "aes32dsi">;
+def AES32DSMI : RVKByteSelect<0b10111, "aes32dsmi">;
+} // Predicates = [HasStdExtZknd, IsRV32]
+
+let Predicates = [HasStdExtZknd, IsRV64] in {
+def AES64DS  : ALU_rr<0b0011101, 0b000, "aes64ds">;
+def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">;
+
+def AES64IM  : RVKUnary<0b001100000000, 0b001, "aes64im">;
+} // Predicates = [HasStdExtZknd, IsRV64]
+
+let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
+def AES64KS2  : ALU_rr<0b0111111, 0b000, "aes64ks2">;
+
+def AES64KS1I : RVKUnary_rnum<0b0011000, 0b001, "aes64ks1i">;
+} // Predicates = [HasStdExtZkndOrZkne, IsRV64]
+
+let Predicates = [HasStdExtZkne, IsRV32] in {
+def AES32ESI  : RVKByteSelect<0b10001, "aes32esi">;
+def AES32ESMI : RVKByteSelect<0b10011, "aes32esmi">;
+} // Predicates = [HasStdExtZkne, IsRV32]
+
+let Predicates = [HasStdExtZkne, IsRV64] in {
+def AES64ES   : ALU_rr<0b0011001, 0b000, "aes64es">;
+def AES64ESM  : ALU_rr<0b0011011, 0b000, "aes64esm">;
+} // Predicates = [HasStdExtZkne, IsRV64]
+
+let Predicates = [HasStdExtZknh] in {
+def SHA256SIG0 : RVKUnary<0b000100000010, 0b001, "sha256sig0">;
+def SHA256SIG1 : RVKUnary<0b000100000011, 0b001, "sha256sig1">;
+def SHA256SUM0 : RVKUnary<0b000100000000, 0b001, "sha256sum0">;
+def SHA256SUM1 : RVKUnary<0b000100000001, 0b001, "sha256sum1">;
+} // Predicates = [HasStdExtZknh]
+
+let Predicates = [HasStdExtZknh, IsRV32] in {
+def SHA512SIG0H : ALU_rr<0b0101110, 0b000, "sha512sig0h">;
+def SHA512SIG0L : ALU_rr<0b0101010, 0b000, "sha512sig0l">;
+def SHA512SIG1H : ALU_rr<0b0101111, 0b000, "sha512sig1h">;
+def SHA512SIG1L : ALU_rr<0b0101011, 0b000, "sha512sig1l">;
+def SHA512SUM0R : ALU_rr<0b0101000, 0b000, "sha512sum0r">;
+def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">;
+} // [HasStdExtZknh, IsRV32]
+
+let Predicates = [HasStdExtZknh, IsRV64] in {
+def SHA512SIG0 : RVKUnary<0b000100000110, 0b001, "sha512sig0">;
+def SHA512SIG1 : RVKUnary<0b000100000111, 0b001, "sha512sig1">;
+def SHA512SUM0 : RVKUnary<0b000100000100, 0b001, "sha512sum0">;
+def SHA512SUM1 : RVKUnary<0b000100000101, 0b001, "sha512sum1">;
+} // Predicates = [HasStdExtZknh, IsRV64]
+
+let Predicates = [HasStdExtZksed] in {
+def SM4ED : RVKByteSelect<0b11000, "sm4ed">;
+def SM4KS : RVKByteSelect<0b11010, "sm4ks">;
+} // Predicates = [HasStdExtZksed]
+
+let Predicates = [HasStdExtZksh] in {
+def SM3P0 : RVKUnary<0b000100001000, 0b001, "sm3p0">;
+def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">;
+} // Predicates = [HasStdExtZksh]

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 //==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 // ===---------------------------------------------------------------------===//
 // The following definitions describe the simpler per-operand machine model.
 // This works with MachineScheduler. See MCSchedule.h for details.
 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def RocketModel : SchedMachineModel {
   let MicroOpBufferSize = 0; // Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = false;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+                             HasStdExtV, HasStdExtZvlsseg];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 
 // SiFive7 machine model for scheduling and other instruction cost heuristics.
 def SiFive7Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+                             HasStdExtV, HasStdExtZvlsseg];
 }
 
 // The SiFive7 microarchitecture has two pipelines: A and B.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.
 let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {

llvm/lib/Target/RISCV/RISCVSubtarget.h

 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "RISCVFrameLowering.h"
 #include "RISCVISelLowering.h"
 #include "RISCVInstrInfo.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
private:
   bool HasStdExtZbc = false;
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
+  bool HasStdExtZknd = false;
+  bool HasStdExtZkne = false;
+  bool HasStdExtZknh = false;
+  bool HasStdExtZksed = false;
+  bool HasStdExtZksh = false;
+  bool HasStdExtZkr = false;
+  bool HasStdExtZkn = false;
+  bool HasStdExtZks = false;
+  bool HasStdExtZkt = false;
+  bool HasStdExtZk = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZfhmin = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
public:
   bool hasStdExtZbc() const { return HasStdExtZbc; }
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
+  bool hasStdExtZknd() const { return HasStdExtZknd; }
+  bool hasStdExtZkne() const { return HasStdExtZkne; }
+  bool hasStdExtZknh() const { return HasStdExtZknh; }
+  bool hasStdExtZksed() const { return HasStdExtZksed; }
+  bool hasStdExtZksh() const { return HasStdExtZksh; }
+  bool hasStdExtZkr() const { return HasStdExtZkr; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 //===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the symbolic operands permitted for various kinds of
 // RISC-V system instruction.
 //
 //===----------------------------------------------------------------------===//

 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def SysRegVLENB: SysReg<"vlenb", 0xC22>;
 
 //===----------------------------------------------------------------------===//
 // State Enable Extension (Smstateen)
 //===----------------------------------------------------------------------===//
 
 // sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
 // mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
 // and hstateen0h-hstateen3h at 0x61C-0x61F.
 foreach i = 0...3 in {
   def : SysReg<"sstateen"#i, !add(0x10C, i)>;
   def : SysReg<"mstateen"#i, !add(0x30C, i)>;
   let isRV32Only = 1 in
   def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
   def : SysReg<"hstateen"#i, !add(0x60C, i)>;
   let isRV32Only = 1 in
   def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
 }
+
+//===-----------------------------------------------
+// Entropy Source CSR
+//===-----------------------------------------------
+
+def SEED : SysReg<"seed", 0x015>;

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
+; RUN: llc -mtriple=riscv32 -mattr=+zknd %s -o - | FileCheck --check-prefix=RV32ZKND %s
+; RUN: llc -mtriple=riscv32 -mattr=+zkne %s -o - | FileCheck --check-prefix=RV32ZKNE %s
+; RUN: llc -mtriple=riscv32 -mattr=+zknh %s -o - | FileCheck --check-prefix=RV32ZKNH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zksed %s -o - | FileCheck --check-prefix=RV32ZKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zksh %s -o - | FileCheck --check-prefix=RV32ZKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zkr %s -o - | FileCheck --check-prefix=RV32ZKR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zkn %s -o - | FileCheck --check-prefix=RV32ZKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zks %s -o - | FileCheck --check-prefix=RV32ZKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV32ZKT %s
+; RUN: llc -mtriple=riscv32 -mattr=+zk %s -o - | FileCheck --check-prefix=RV32ZK %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
+; RUN: llc -mtriple=riscv64 -mattr=+zknd %s -o - | FileCheck --check-prefix=RV64ZKND %s
+; RUN: llc -mtriple=riscv64 -mattr=+zkne %s -o - | FileCheck --check-prefix=RV64ZKNE %s
+; RUN: llc -mtriple=riscv64 -mattr=+zknh %s -o - | FileCheck --check-prefix=RV64ZKNH %s
+; RUN: llc -mtriple=riscv64 -mattr=+zksed %s -o - | FileCheck --check-prefix=RV64ZKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zksh %s -o - | FileCheck --check-prefix=RV64ZKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+zkr %s -o - | FileCheck --check-prefix=RV64ZKR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zkn %s -o - | FileCheck --check-prefix=RV64ZKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zks %s -o - | FileCheck --check-prefix=RV64ZKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV64ZKT %s
+; RUN: llc -mtriple=riscv64 -mattr=+zk %s -o - | FileCheck --check-prefix=RV64ZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
+; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
+; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
+; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
+; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0"
+; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0"
+; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0"
+; RV32ZKN: .attribute 5, "rv32i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV32ZKS: .attribute 5, "rv32i2p0_zks1p0_zksed1p0_zksh1p0"
+; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
+; RV32ZK: .attribute 5, "rv32i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0_zfhmin1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
+; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
+; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
+; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
+; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0"
+; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0"
+; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0"
+; RV64ZKN: .attribute 5, "rv64i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV64ZKS: .attribute 5, "rv64i2p0_zks1p0_zksed1p0_zksh1p0"
+; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
+; RV64ZK: .attribute 5, "rv64i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32iv0p10zvl16384b0p10"
 # CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv0p10zvl32768b0p10"
 # CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv0p10zvl65536b0p10"
 # CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32i_zknd"
+# CHECK: attribute      5, "rv32i2p0_zknd1p0"
+
+.attribute arch, "rv32i_zkne"
+# CHECK: attribute      5, "rv32i2p0_zkne1p0"
+
+.attribute arch, "rv32i_zknh"
+# CHECK: attribute      5, "rv32i2p0_zknh1p0"
+
+.attribute arch, "rv32i_zksed"
+# CHECK: attribute      5, "rv32i2p0_zksed1p0"
+
+.attribute arch, "rv32i_zksh"
+# CHECK: attribute      5, "rv32i2p0_zksh1p0"
+
+.attribute arch, "rv32i_zkr"
+# CHECK: attribute      5, "rv32i2p0_zkr1p0"
+
+.attribute arch, "rv32i_zkn"
+# CHECK: attribute      5, "rv32i2p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+
+.attribute arch, "rv32i_zks"
+# CHECK: attribute      5, "rv32i2p0_zks1p0_zksed1p0_zksh1p0"
+
+.attribute arch, "rv32i_zkt"
+# CHECK: attribute      5, "rv32i2p0_zkt1p0"
+
+.attribute arch, "rv32i_zk"
+# CHECK: attribute      5, "rv32i2p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"

llvm/test/MC/RISCV/rv32zknd-only-invalid.s

+# With Zk extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zk < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zkn extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zkn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zknd extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zknd < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+aes32dsmi a0, a1, a2, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+aes32dsi a0, a1, a2, 8

llvm/test/MC/RISCV/rv32zknd-only-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zknd -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zknd < %s \
+# RUN:     | llvm-objdump --mattr=+zknd -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: aes32dsi a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xea]
+aes32dsi a0, a1, a2, 3
+
+# CHECK-ASM-AND-OBJ: aes32dsmi a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xee]
+aes32dsmi a0, a1, a2, 3

llvm/test/MC/RISCV/rv32zkne-only-invalid.s

+# With Zk extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zk < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zkn extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zkn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zkne extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zkne < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+aes32esmi a0, a1, a2, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+aes32esi a0, a1, a2, 8

llvm/test/MC/RISCV/rv32zkne-only-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zkne -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zkne < %s \
+# RUN:     | llvm-objdump --mattr=+zkne -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: aes32esi a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xe2]
+aes32esi a0, a1, a2, 3
+
+# CHECK-ASM-AND-OBJ: aes32esmi a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xe6]
+aes32esmi a0, a1, a2, 3

llvm/test/MC/RISCV/rv32zknh-only-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zknh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zknh < %s \
+# RUN:     | llvm-objdump --mattr=+zknh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sha512sig0h a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x5c]
+sha512sig0h a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: sha512sig1h a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x5e]
+sha512sig1h a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: sha512sig0l a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x54]
+sha512sig0l a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: sha512sig1l a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x56]
+sha512sig1l a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: sha512sum0r a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x50]
+sha512sum0r a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: sha512sum1r a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x52]
+sha512sum1r a0, a1, a2

llvm/test/MC/RISCV/rv32zknh-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zknh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zknh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zknh < %s \
+# RUN:     | llvm-objdump --mattr=+zknh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zknh < %s \
+# RUN:     | llvm-objdump --mattr=+zknh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sha256sig0 a0, a1
+# CHECK-ASM: [0x13,0x95,0x25,0x10]
+sha256sig0 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha256sig1 a0, a1
+# CHECK-ASM: [0x13,0x95,0x35,0x10]
+sha256sig1 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha256sum0 a0, a1
+# CHECK-ASM: [0x13,0x95,0x05,0x10]
+sha256sum0 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha256sum1 a0, a1
+# CHECK-ASM: [0x13,0x95,0x15,0x10]
+sha256sum1 a0, a1

llvm/test/MC/RISCV/rv32zksed-invalid.s

+# With Zks extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zks < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zksed extension:
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zksed < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+sm4ed a0, a1, a2, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+sm4ks a0, a1, a2, 8

llvm/test/MC/RISCV/rv32zksed-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zksed -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zksed -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zksed < %s \
+# RUN:     | llvm-objdump --mattr=+zksed -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zksed < %s \
+# RUN:     | llvm-objdump --mattr=+zksed -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sm4ed a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xf0]
+sm4ed a0, a1, a2, 3
+
+# CHECK-ASM-AND-OBJ: sm4ks a0, a1, a2, 3
+# CHECK-ASM: [0x33,0x85,0xc5,0xf4]
+sm4ks a0, a1, a2, 3

llvm/test/MC/RISCV/rv32zksh-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zksh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zksh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zksh < %s \
+# RUN:     | llvm-objdump --mattr=+zksh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zksh < %s \
+# RUN:     | llvm-objdump --mattr=+zksh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sm3p0 a0, a1
+# CHECK-ASM: [0x13,0x95,0x85,0x10]
+sm3p0 a0, a1
+
+# CHECK-ASM-AND-OBJ: sm3p1 a0, a1
+# CHECK-ASM: [0x13,0x95,0x95,0x10]
+sm3p1 a0, a1

llvm/test/MC/RISCV/rv64zknd-only-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zknd -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zknd < %s \
+# RUN:     | llvm-objdump --mattr=+zknd -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: aes64ds a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x3a]
+aes64ds a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: aes64dsm a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x3e]
+aes64dsm a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: aes64im a0, a1
+# CHECK-ASM: [0x13,0x95,0x05,0x30]
+aes64im a0, a1
+
+# CHECK-ASM-AND-OBJ: aes64ks1i a0, a1, 5
+# CHECK-ASM: [0x13,0x95,0x55,0x31]
+aes64ks1i a0, a1, 5
+
+# CHECK-ASM-AND-OBJ: aes64ks2 a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x7e]
+aes64ks2 a0, a1, a2

llvm/test/MC/RISCV/rv64zkne-only-invalid.s

+# With Zk extension:
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zk < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zkn extension:
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zkn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zkne extension:
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zkne < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 10]
+aes64ks1i a0, a1, 11
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 10]
+aes64ks1i a0, a1, -1

llvm/test/MC/RISCV/rv64zkne-only-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zkne -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zkne < %s \
+# RUN:     | llvm-objdump --mattr=+zkne -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: aes64es a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x32]
+aes64es a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: aes64esm a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x36]
+aes64esm a0, a1, a2
+
+# CHECK-ASM-AND-OBJ: aes64ks1i a0, a1, 5
+# CHECK-ASM: [0x13,0x95,0x55,0x31]
+aes64ks1i a0, a1, 5
+
+# CHECK-ASM-AND-OBJ: aes64ks2 a0, a1, a2
+# CHECK-ASM: [0x33,0x85,0xc5,0x7e]
+aes64ks2 a0, a1, a2

llvm/test/MC/RISCV/rv64zknh-only-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zknh -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zknh < %s \
+# RUN:     | llvm-objdump --mattr=+zknh -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sha512sig0 a0, a1
+# CHECK-ASM: [0x13,0x95,0x65,0x10]
+sha512sig0 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha512sig1 a0, a1
+# CHECK-ASM: [0x13,0x95,0x75,0x10]
+sha512sig1 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha512sum0 a0, a1
+# CHECK-ASM: [0x13,0x95,0x45,0x10]
+sha512sum0 a0, a1
+
+# CHECK-ASM-AND-OBJ: sha512sum1 a0, a1
+# CHECK-ASM: [0x13,0x95,0x55,0x10]
+sha512sum1 a0, a1

llvm/test/MC/RISCV/rv64zksed-invalid.s

+# With Zks extension:
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zks < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# With Zksed extension:
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zksed < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+sm4ed a0, a1, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+sm4ks a0, a1, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]

llvm/test/MC/RISCV/rvk-user-csr-name.s

+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zkr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zkr - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zkr < %s \
+# RUN:     | llvm-objdump -d --mattr=+zkr - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Entropy Source CSR
+##################################
+
+# seed
+# name
+# CHECK-INST: csrrs t1, seed, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x50,0x01]
+# CHECK-INST-ALIAS: csrr t1, seed
+# uimm12
+# CHECK-INST: csrrs t2, seed, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0x01]
+# CHECK-INST-ALIAS: csrr t2, seed
+# name
+csrrs t1, seed, zero
+# uimm12
+csrrs t2, 0x015, zero