[RISCV] Initially support the K-extension instructions on the LLVM MC layer

[VincentWu]

Summary

This commit is currently implementing supports for scalar cryptography extension for LLVM according to version v1.0.0 of K Ext specification(scala crypto has been ratified already). Currently, we are implementing the MC (Machine Code) layer of his extension and the majority of work is done under llvm/lib/Target/RISCV directory. There are also some test files in llvm/test/MC/RISCV directory.

Remove the subfeature of Zbk* which conflict with b extensions to reduce the size of the patch.
(Zbk* will be resubmit after this patch has been merged)

Co-author：@ksyx & @VincentWu & @lihongliang & @achieveartificialintelligence

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

23

Blank line before

30

Blank line after

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

46

Isn't this the round, which is then used to derive the 8-bit round constant, not the round constant itself?

59

If you don't have scheduling defined yet just don't add Sched<[]> at all?

75

Assembler Pseudo Instructions

to distinguish from LLVM Pseudos.

76

Naming aliases is pointless

103

Should be fixed

llvm/lib/Target/RISCV/RISCVSubtarget.h

3

Be consistent whether it's "V K Zv*" or "V Zv* K" (latter being what you've done in TableGen). I think I prefer grouping all the V stuff together even if technically Z* extensions sort after all the single-letter ones.

Also, you will need to get the canonical order updated to include K at some point, though it seems relatively safe to assume it'll just be tacked on the end, i.e. after V (and N).

llvm/lib/Target/RISCV/RISCVSystemOperands.td

4

Machine Scalar Cryptography CSRs

? I think these headings come from the ISA manual, but K should be consistent both here and in its spec.

llvm/test/MC/RISCV/rvk/rv32k.s

1 ↗

(On Diff #328842)

You should have 3 files:

rv32k-valid.s - Tests the instructions common between RV32K and RV64K, with RUN lines for both

rv32k-only-valid.s - Tests the instructions only present in RV32K

rv64k-valid.s - Tests the additional instructions in RV64K

12 ↗

(On Diff #328842)

CHECK lines come before not after

144 ↗

(On Diff #328842)

Fix

llvm/test/MC/RISCV/rvk/rv64k.s

126 ↗

(On Diff #328842)

Fix

llvm/test/MC/RISCV/rvk/rvk-invalid.s

1 ↗

(On Diff #328842)

Needs to be testing both RV32 and RV64 including instructions specific to each, similar to what I said for the tests above.

[VincentWu]

style: formate the whitespace, annotation&code style

[VincentWu]

fix: submit wrong patch

[VincentWu]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

10

yes, it is a typo, my fault

46

I'm a little confused about that. So do you mean number rcon is a kind of offset or something？and we need an extra base address?

59

yes, but there will be something wrong whing building if I just remove the Sched<[]>. and we found that the RISCVInstrInfoB.td which is already merged also put an empty Sched<[]> there. So we put it there too.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

19–20

Indenting is still off:

• 2 spaces not 4
• we don't typically indent inside lets

46

No. Wikipedia has details (https://en.wikipedia.org/wiki/AES_key_schedule#Round_constants), but basically the the round number counts up 1 by 1, but the actual round constant is a function of the round number (either implemented with a simple table or the slightly more general formula). I've filed https://github.com/riscv/riscv-crypto/issues/82 about this, but given that's what the spec currently calls it I think it's fine to call it rcon in LLVM.

59

That shouldn't be the case if you add HasStdExtK to UnsupportedFeatures for the models

59

Only one space after the colon

67–70

I think it'd be neater to make this a separate "group" (i.e. add a blank line between SHA256SIG1 and SM3P0, and then not align the new group with the sha256 ones), as that'll cut down on the number of spaces

98–105

Line things up properly if you're going to go to the trouble of doing it

llvm/test/MC/RISCV/rvk/rv32k-valid.s

2

These files probably don't need to be in their own subdirectory. RVV has one, but that's only because it's such a huge extension, whereas this is a much smaller extension so can be like how we're testing all the others.

llvm/test/MC/RISCV/rvk/rvk32-invalid.s

2

File should be rv32k- not rvk32 (same for the file below)

3

Need a riscv64 RUN line

[VincentWu]

llvm/test/MC/RISCV/rvk/rv32k-valid.s

67

need fix

[VincentWu]

• style: formate the code
• refactor: use rcon class to limit the imm range
• Test: add 64bit test case
• move test cases
• fix: fix wrong CHECK-INST

[VincentWu]

fix: submit the wrong patch file

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

10

I'd base this comment on the one in RISCVInstrInfoB.td, better documenting this is a not-yet-ratified extension.

[VincentWu]

Classifies instructions into their corresponding functional subset
add more test case for Zkg&Zkg which share instructions from B ext

[VincentWu]

llvm/lib/Target/RISCV/RISCVSchedRocket.td

0–1

it seems too long, but we haven't found a good way to shorten them. have any ideas?

[Jim]

llvm/lib/Target/RISCV/RISCV.td

5–1

Add blank line

7

and others

37

Alignment

66

Alignment

83

Add blank line

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

29

This line has undefined behavior if the user tries to pass a value near INT64_MAX since the +5 would wrap around which isn't undefined.

But I'm not sure it does what you want. This would accept -5, -4, -3, -2, and -1.

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

24

This isUint<4>(Imm) doesn't match what's in the asm parser.

[VincentWu]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

29

right it's my fault. I forgot the numbers -5~-1, the spec defines the range of number is [0,10], I limit the upper bound is (1 << 4) -5 but forget it also causes the wrong lower bound. I will fix it soon.

[Jim]

Revision Contents look weired. Does this patch upload by git diff -U99999?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

24

Just write 10. I don't think subtracting 6 from 16 makes this very readability. The other places, the name of the error has the number of bits in its name, so using that bit width(or 1 less than it) in the creation of the constants makes sense.

29

Space after the first "Imm"

[VincentWu]

In D98136#2691388, @Jim wrote:

Revision Contents look weired. Does this patch upload by git diff -U99999?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

I checked history and made sure I did use the parameter -U99999, so I don't know where the strange part is, I'll upload a new version.

[VincentWu]

[RISCV][MC][K-ext] Fix wrong input DAG for ByteSelect cls

[kito-cheng]

Could you handle k* extension for ELF attribute?

RISCVAsmParser::parseDirectiveAttribute@lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
RISCVTargetStreamer::emitTargetAttributes@MCTargetDesc/RISCVTargetStreamer.cpp

[VincentWu]

handle k* extension for ELF attribute

[VincentWu]

update the implemention to adopt the spec v1.0.0-rc1
co-worker @lihongliang

[VincentWu]

• [RISCV] style: formate the code of RISCVAsmParser.cpp

[VincentWu]

This comment was removed by VincentWu.

[VincentWu]

update the code to adopt the spec v1.0.0-rc4
co-worker @achieveartificialintelligence

[achieveartificialintelligence]

Ping

[achieveartificialintelligence]

Rebase and Ping.

[liaolucy]

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

82 ↗

(On Diff #388783)

ROR_K instruction is the same as the B-ext.
./RISCVInstrInfoZb.td: def ROR : ALU_rr<0b0110000, 0b101, "ror">,

Do we need to redefine this instruction? Does anyone have any Suggestions?

[VincentWu]

add Entropy Source CSR

Remove the subfeature of Zbk* which conflict with b extensions to reduce the size of the patch.
(Zbk* will be resubmit after this patch has been merged)

Co-author：@nannan1025

[liaolucy]

llvm/lib/Support/RISCVISAInfo.cpp

64 ↗

(On Diff #397218)

Should zbkb extension be removed?

[liaolucy]

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

10 ↗

(On Diff #397218)

Is version 1.0-rc4? The latest version is 1.0.0-rc6.

[VincentWu]

fix issues mentioned on comment

[VincentWu]

PING

The latest spec (rc-6) of the scalar crypto extension has been released for almost two months. That means that the scalar crypto extensions have become stable.
Also the GCC seems to have merged the patch for scalar crypto extensions into the upstream
So I think it is time to decide whether this patch should be merged or not.

Although I understand that this patch may be a bit large, I would still like someone to review it again and tell me if this patch can be merged or still needs to be modified

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

53 ↗

(On Diff #397446)

This needs to be rebased. Zba/b/c/s were all moved to non-experimental recently

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

430 ↗

(On Diff #397446)

This looks unrelated to the rest of the patch.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

53 ↗

(On Diff #397446)

line this up with funct3 on the previous line

61 ↗

(On Diff #397446)

Indent ths two more spaces

69 ↗

(On Diff #397446)

indent this 2 more spaces to line up with funct3

llvm/lib/Target/RISCV/RISCVSystemOperands.td

380

Space after the comma like the rest of the file

[eopXD]

llvm/lib/Support/RISCVISAInfo.cpp

73 ↗

(On Diff #397446)

Regarding zkn, zks, zk, D112359 added extension implication as a separate function. I think you may need to rebase and do some modifications.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

430 ↗

(On Diff #397446)

Cleanup?

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

194

Is this Predicate needed? Zkn is just a convenience to enable multiple extensions. No instructions belong to it right?

203

Is this Predicate needed? Zks is just a convenience to enable multiple extensions. No instructions belong to it right?

210

This Predicate doesn't appear to be used on any instructions. Just the scheduler model

220

Is this Predicate needed? Zk is just a convenience to enable multiple extensions. No instructions belong to it right?

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

37 ↗

(On Diff #397446)

Is this class used?

44 ↗

(On Diff #397446)

Is this class used?

53 ↗

(On Diff #397446)

I don't think we should put Sched<[]> inside the generic classes. We'll need to be able to add per instruction information in the future.

71 ↗

(On Diff #397446)

This line is over indented

[VincentWu]

fix comment

scala crypto has been ratified already, remove description "-rc6"

[VincentWu]

add new line at end of file

[VincentWu]

emove ext verision number

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1191

(1 << 4) - 6 -> 10. There's no reason to write a more complex expression. It makes more sense for things like Match_InvalidUImm2 to show the connection between the name of the error and the integer values. That doesn't apply here.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

1 ↗

(On Diff #400832)

K -> Zk in both places

9 ↗

(On Diff #400832)

K -> Zk

24 ↗

(On Diff #400832)

This ImmLeaf should check 0-10. Alternatively it can be removed until CodeGen support is added.

28 ↗

(On Diff #400832)

It's not a UIMM4. It should have its own OPERAND type and the range check for it in X86InstrInfo.cpp should check 0-10.

llvm/lib/Target/RISCV/RISCVSchedRocket.td

19

This line needs to rebased I think. I'll also be removed Zvlsseg later today.

[VincentWu]

rebase and fix comments

[VincentWu]

updete

[VincentWu]

rebase and update

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1150 ↗

(On Diff #402163)

Missing "break;" This will be a problem the next time someone adds a case after this one.

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

1 ↗

(On Diff #402163)

Scala -> Scalar

9 ↗

(On Diff #402163)

ZK -> Zk

[craig.topper]

Please remove [RFC] from the review name. We shouldn't have that in the commit message.

[VincentWu]

address comment & remove [RFC] from title

[craig.topper]

LGTM

[VincentWu]

rebase

[VincentWu]

In D98136#3265096, @craig.topper wrote:

LGTM

Thanks -)

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1150 ↗

(On Diff #402163)

oops, sorry my bad, fixed

[RKSimon]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1149 ↗

(On Diff #402402)

@VincentWu Coverity is warning that this is dead code as RISCVOp::OPERAND_RVKRNU > RISCVOp::OPERAND_LAST_RISCV_IMM

[VincentWu]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1149 ↗

(On Diff #402402)

I am very sorry for this error, how do I fix it?
i mean, should I create a new Differential Revision? Or modify the commit in some way?

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 #include "MCTargetDesc/RISCVTargetStreamer.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/RISCVAttributes.h"
 #include "llvm/Support/TargetRegistry.h"
bool isUImmLog2XLenHalf() const {
     if (!isImm())
       return false;
     if (!evaluateConstantImm(getImm(), Imm, VK) ||
         VK != RISCVMCExpr::VK_RISCV_None)
       return false;
     return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm);
   }
 
+  bool isUImm2() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm4() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+  
   bool isUImm5() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidUImmLog2XLenNonZero:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenHalf:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
+  case Match_InvalidUImm2:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+  case Match_InvalidUImm4:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidSImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4),
                                       (1 << 4) - 1);
   case Match_InvalidSImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
                                       (1 << 5) - 1);
case Match_InvalidVMaskRegister: {
     return Error(ErrorLoc, "operand must be v0.t");
   }
   case Match_InvalidSImm5Plus1: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
                                       (1 << 4),
                                       "immediate must be in the range");
   }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns true and sets RegNo to 0. If IsRV32E then registers
 // x16-x31 will be rejected.
 static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

enum {
   // multiple "bitmask" flags.
   MO_DIRECT_FLAG_MASK = 15
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM12,
   OPERAND_SIMM12,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
 };
 } // namespace RISCVOp

llvm/lib/Target/RISCV/RISCV.td

 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V subtarget features and instruction predicates.
 //===----------------------------------------------------------------------===//
 
 def FeatureStdExtM
     : SubtargetFeature<"m", "HasStdExtM", "true",
                        "'M' (Integer Multiplication and Division)">;
 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
                            AssemblerPredicate<(all_of FeatureStdExtM),

 def FeatureStdExtF
     : SubtargetFeature<"f", "HasStdExtF", "true",
                        "'F' (Single-Precision Floating-Point)">;
 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
                            AssemblerPredicate<(all_of FeatureStdExtF),
                            "'F' (Single-Precision Floating-Point)">;
 
 def FeatureStdExtD
     : SubtargetFeature<"d", "HasStdExtD", "true",
                        "'D' (Double-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
                            AssemblerPredicate<(all_of FeatureStdExtD),
                            "'D' (Double-Precision Floating-Point)">;
 
 def FeatureExtZfh
     : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",

 
 def FeatureExtZba
     : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
                        "'Zba' (Address calculation 'B' Instructions)">;
 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
                              AssemblerPredicate<(all_of FeatureExtZba),
                              "'Zba' (Address calculation 'B' Instructions)">;
 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 
 def FeatureExtZbb
     : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
                        "'Zbb' (Base 'B' Instructions)">;
 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
                              AssemblerPredicate<(all_of FeatureExtZbb),
                              "'Zbb' (Base 'B' Instructions)">;
 
 def FeatureExtZbc
     : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true",
                        "'Zbc' (Carry-Less 'B' Instructions)">;
 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
                              AssemblerPredicate<(all_of FeatureExtZbc),
                              "'Zbc' (Carry-Less 'B' Instructions)">;
 
 def FeatureExtZbe
     : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
                        "'Zbe' (Extract-Deposit 'B' Instructions)">;
 def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
                              AssemblerPredicate<(all_of FeatureExtZbe),
                              "'Zbe' (Extract-Deposit 'B' Instructions)">;
 
 def FeatureExtZbf
     : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
                        "'Zbf' (Bit-Field 'B' Instructions)">;
 def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
                         "'Zvlsseg' (Vector segment load/store instructions)">;
 def FeatureExtZvamo
     : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                        "'Zvamo'(Vector AMO Operations)",
                        [FeatureStdExtV]>;
 def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
                               AssemblerPredicate<(all_of FeatureExtZvamo),
                               "'Zvamo'(Vector AMO Operations)">;
-
+def FeatureStdExtK
+    : SubtargetFeature<"experimental-k", "HasStdExtK", "true",
+                       "'K' (Scalar Cryptography Instructions)">;
+def HasStdExtK : Predicate<"Subtarget->hasStdExtK()">,
+                           AssemblerPredicate<(all_of FeatureStdExtK),
+                           "'K' (Scalar Cryptography Instructions)">;
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                        "RV32I Base Instruction Set">;
 
 defvar RV32 = DefaultMode;
 def RV64           : HwMode<"+64bit">;
 
 def FeatureRV32E
     : SubtargetFeature<"e", "IsRV32E", "true",
                        "Implements RV32E (provides 16 rather than 32 GPRs)">;
 def IsRV32E : Predicate<"Subtarget->isRV32E()">,
                         AssemblerPredicate<(all_of FeatureRV32E)>;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;
 
 foreach i = {1-31} in
     def FeatureReserveX#i :
         SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
                          "true", "Reserve X"#i>;
 
 def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
                                           "true", "Enable save/restore.">;
 
 //===----------------------------------------------------------------------===//
 // Named operands for CSR instructions.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<2>;
+  let DecoderMethod = "decodeUImmOperand<2>";
+  let OperandType = "OPERAND_UIMM2";
+  let OperandNamespace = "RISCVOp";
+}
+
+def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<4>;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<4>";
+  let OperandType = "OPERAND_UIMM4";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5>;
   let DecoderMethod = "decodeUImmOperand<5>";
   let OperandType = "OPERAND_UIMM5";
   let OperandNamespace = "RISCVOp";
 }
 
 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {

 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
+include "RISCVInstrInfoK.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoK.td

+//===-- RISCVInstrInfoK.td - RISC-V 'K' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the standard 'K' 
+/// scalar cryptography extension, version 0.8.1. 
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    class RVKUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3, string opcodestr>
+        : RVInstR<funct7, funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">{
+            let Inst{24-20} = funct5;
+        }
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    class RVKBinary<bits<7> funct7, bits<3> funct3, string opcodestr>
+        : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    class RVKByteSelect<bits<5> funct5, string opcodestr>
+        : RVInstS<0b000, OPC_OP, (outs GPR:$rt), (ins GPR:$rs2, uimm2:$bs), 
+                opcodestr, "$rt, $rs2, $bs">{
+            bits<2> bs;
+            bits<5> rt;
+
+            let Inst{31-30}=bs;
+            let Inst{29-25}=funct5;
+            let Inst{19-15}=rt;
+            let Inst{11-7}=0b00000;
+        }
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    class RVKUnary_rcon<bits<7> funct7, bits<3> funct3, string opcodestr>
+        : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, uimm4:$rcon),
+                opcodestr, "$rd, $rs1, $rcon"> {
+        bits<4> rcon;
+        
+        let Inst{31-25} = funct7;
+        let Inst{24} = 1;
+        let Inst{23-20} = rcon;
+    }
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtK] in {
+    def SHA256SUM0 : RVKUnary<0b0001000, 0b00000, 0b001, "sha256sum0">;
+    def SHA256SUM1 : RVKUnary<0b0001000, 0b00001, 0b001, "sha256sum1">;
+    def SHA256SIG0 : RVKUnary<0b0001000, 0b00010, 0b001, "sha256sig0">;
+    def SHA256SIG1 : RVKUnary<0b0001000, 0b00011, 0b001, "sha256sig1">;
+
+    def SM3P0 : RVKUnary<0b0001000, 0b01000, 0b001, "sm3p0">;
+    def SM3P1 : RVKUnary<0b0001000, 0b01001, 0b001, "sm3p1">;
+    def SM4ED : RVKByteSelect<0b11000, "sm4ed">;
+    def SM4KS : RVKByteSelect<0b11010, "sm4ks">;
+
+    // Assembler Pseudo Instructions
+    def : InstAlias<"getnoise $rd", (CSRRS GPR:$rd, MNOISE.Encoding, X0)>;
+    def : InstAlias<"pollentropy $rd", (CSRRS GPR:$rd, MENTROPY.Encoding, X0)>;
+} // Predicates = [HasStdExtK]
+
+let Predicates = [HasStdExtK, IsRV32] in {
+    def SHA512SUM0R : RVKBinary<0b0101000, 0b000, "sha512sum0r">;
+    def SHA512SUM1R : RVKBinary<0b0101001, 0b000, "sha512sum1r">;
+    def SHA512SIG0L : RVKBinary<0b0101010, 0b000, "sha512sig0l">;
+    def SHA512SIG0H : RVKBinary<0b0101110, 0b000, "sha512sig0h">;
+    def SHA512SIG1L : RVKBinary<0b0101011, 0b000, "sha512sig1l">;
+    def SHA512SIG1H : RVKBinary<0b0101111, 0b000, "sha512sig1h">;
+
+    def AES32ESMI : RVKByteSelect<0b11011, "aes32esmi">;
+    def AES32DSMI : RVKByteSelect<0b11111, "aes32dsmi">;
+    def AES32ESI : RVKByteSelect<0b11001, "aes32esi">;
+    def AES32DSI : RVKByteSelect<0b11101, "aes32dsi">;
+} // Predicates = [HasStdExtK, IsRV32]
+
+let Predicates = [HasStdExtK, IsRV64] in {
+    def SHA512SUM0 : RVKUnary<0b0001000, 0b00100, 0b001, "sha512sum0">;
+    def SHA512SUM1 : RVKUnary<0b0001000, 0b00101, 0b001, "sha512sum1">;
+    def SHA512SIG0 : RVKUnary<0b0001000, 0b00110, 0b001, "sha512sig0">;
+    def SHA512SIG1 : RVKUnary<0b0001000, 0b00111, 0b001, "sha512sig1">;
+    
+    def AES64IM  : RVKUnary<0b0011000, 0b00000, 0b001, "aes64im">;
+    def AES64KS2 : RVKBinary<0b0111111, 0b000, "aes64ks2">;
+    def AES64ESM : RVKBinary<0b0011011, 0b000, "aes64esm">;
+    def AES64DSM : RVKBinary<0b0011111, 0b000, "aes64dsm">;
+    
+    def AES64ES : RVKBinary<0b0011001, 0b000, "aes64es">;
+    def AES64DS : RVKBinary<0b0011101, 0b000, "aes64ds">;
+
+    def AES64KS1I : RVKUnary_rcon<0b0011000, 0b001, "aes64ks1i">;
+} // Predicates = [HasStdExtK, IsRV64]

llvm/lib/Target/RISCV/RISCVSchedRocket.td

 //==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 // ===---------------------------------------------------------------------===//
 // The following definitions describe the simpler per-operand machine model.
 // This works with MachineScheduler. See MCSchedule.h for details.
 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def RocketModel : SchedMachineModel {
   let MicroOpBufferSize = 0; // Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg, HasStdExtK];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 
 // SiFive7 machine model for scheduling and other instruction cost heuristics.
 def SiFive7Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg, HasStdExtK];
 }
 
 // The SiFive7 microarchitecure has two pipelines: A and B.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.
 let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {

llvm/lib/Target/RISCV/RISCVSubtarget.h

 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
+  bool HasStdExtK = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
public:
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasStdExtK() const { return HasStdExtK; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 //===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the symbolic operands permitted for various kinds of
 // RISC-V system instruction.
 //
 //===----------------------------------------------------------------------===//

 // User Vector CSRs
 //===-----------------------------------------------
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;
 def : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def : SysReg<"vlenb", 0xC22>;
+
+//===-----------------------------------------------
+// Machine Scalar Cryptography CSRs
+//===-----------------------------------------------
+def MENTROPY : SysReg<"mentropy", 0xF15>;
+def MNOISE   : SysReg<"mnoise", 0x7A9>;

llvm/test/MC/RISCV/rvk/rv32k-only-valid.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-k %s \
+# RUN:      | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:      | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d --mattr=+experimental-k - \
+# RUN:      | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: sha512sum0r a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x50]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 50 <unknown>
+sha512sum0r a0, a1, a2
+
+# CHECK-INST: sha512sum1r a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x52]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 52 <unknown>
+sha512sum1r a0, a1, a2
+
+# CHECK-INST: sha512sig0l a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x54]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 54 <unknown>
+sha512sig0l a0, a1, a2
+
+# CHECK-INST: sha512sig0h a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x5c]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 5c <unknown>
+sha512sig0h a0, a1, a2
+
+# CHECK-INST: sha512sig1l a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x56]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 56 <unknown>
+sha512sig1l a0, a1, a2
+
+# CHECK-INST: sha512sig1h a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x5e]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 5e <unknown>
+sha512sig1h a0, a1, a2
+
+# CHECK-INST: csrr a0, mnoise 
+# CHECK-ENCODING: [0x73,0x25,0x90,0x7a]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 73 25 90 7a csrr a0, mnoise
+getnoise a0
+
+# CHECK-INST: csrr a0, mentropy
+# CHECK-ENCODING: [0x73,0x25,0x50,0xf1]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 73 25 50 f1 csrr a0, mentropy
+pollentropy a0
+
+# CHECK-INST: sm4ed t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xf0]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 f0 <unknown>
+sm4ed t0, a2, 3
+
+# CHECK-INST: sm4ks t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xf4]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 f4 <unknown>
+sm4ks t0, a2, 3
+
+# CHECK-INST: aes32esmi t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xf6]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 f6 <unknown>
+aes32esmi t0, a2, 3
+
+# CHECK-INST: aes32esi t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xf2]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 f2 <unknown>
+aes32esi t0, a2, 3
+
+# CHECK-INST: aes32dsmi t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xfe]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 fe <unknown>
+aes32dsmi t0, a2, 3
+
+# CHECK-INST: aes32dsi t0, a2, 3
+# CHECK-ENCODING: [0x33,0x80,0xc2,0xfa]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 80 c2 fa <unknown>
+aes32dsi t0, a2, 3

llvm/test/MC/RISCV/rvk/rv32k-valid.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-k %s \
+# RUN:      | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:      | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d --mattr=+experimental-k - \
+# RUN:      | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-k %s \
+# RUN:      | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:      | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d --mattr=+experimental-k - \
+# RUN:      | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: sha256sum0 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 05 10 <unknown>
+sha256sum0 a0, a1
+
+# CHECK-INST: sha256sum1 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x15,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 15 10 <unknown>
+sha256sum1 a0, a1
+
+# CHECK-INST: sha256sig0 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x25,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 25 10 <unknown>
+sha256sig0 a0, a1
+
+# CHECK-INST: sha256sig1 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x35,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 35 10 <unknown>
+sha256sig1 a0, a1
+
+# CHECK-INST: sm3p0 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x85,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 85 10 <unknown>
+sm3p0 a0, a1
+
+# CHECK-INST: sm3p1 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x95,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 95 10 <unknown>
+sm3p1 a0, a1
+
+# CHECK-INST: csrr a0, mnoise 
+# CHECK-ENCODING: [0x73,0x25,0x90,0x7a]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 73 25 90 7a
+getnoise a0
+
+# CHECK-INST: csrr a0, mentropy
+# CHECK-ENCODING: [0x73,0x25,0x50,0xf1]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 73 25 50 f1
+pollentropy a0
 No newline at end of file

llvm/test/MC/RISCV/rvk/rv64k-valid.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-k %s \
+# RUN:      | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:      | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d --mattr=+experimental-k - \
+# RUN:      | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-k %s \
+# RUN:      | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: sha512sum0 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 45 10 <unknown>
+sha512sum0 a0, a1
+
+# CHECK-INST: sha512sum1 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x55,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 55 10 <unknown>
+sha512sum1 a0, a1
+
+# CHECK-INST: sha512sig0 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x65,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 65 10 <unknown>
+sha512sig0 a0, a1
+
+# CHECK-INST: sha512sig1 a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x75,0x10]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 75 10 <unknown>
+sha512sig1 a0, a1
+
+# CHECK-INST: aes64im a0, a1
+# CHECK-ENCODING: [0x13,0x95,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 05 30 <unknown>
+aes64im a0, a1
+
+# CHECK-INST: aes64ks2 a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x7e]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 7e <unknown>
+aes64ks2 a0, a1, a2
+
+# CHECK-INST: aes64esm a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x36]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 36 <unknown>
+aes64esm a0, a1, a2
+
+# CHECK-INST: aes64es a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x32]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 32 <unknown>
+aes64es a0, a1, a2
+
+# CHECK-INST: aes64dsm a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x3e]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 3e <unknown>
+aes64dsm a0, a1, a2
+
+# CHECK-INST: aes64es a0, a1, a2
+# CHECK-ENCODING: [0x33,0x85,0xc5,0x32]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 33 85 c5 32 <unknown>
+aes64es a0, a1, a2
+
+# CHECK-INST: aes64ks1i a0, a1, 5
+# CHECK-ENCODING: [0x13,0x95,0x55,0x31]
+# CHECK-ERROR: instruction requires the following: 'K' (Scalar Cryptography Instructions)
+# CHECK-UNKNOWN: 13 95 55 31 <unknown>
+aes64ks1i a0, a1, 5

llvm/test/MC/RISCV/rvk/rvk32-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-k < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+sm4ed t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+sm4ks t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]

llvm/test/MC/RISCV/rvk/rvk32-only-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-k < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+aes32esmi t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+aes32esi t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+aes32dsmi t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+aes32dsi t0, a2, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]