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Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines	enum OperandType : unsigned {
OPERAND_UIMM3,		OPERAND_UIMM3,
OPERAND_UIMM4,		OPERAND_UIMM4,
OPERAND_UIMM5,		OPERAND_UIMM5,
OPERAND_UIMM7,		OPERAND_UIMM7,
OPERAND_UIMM12,		OPERAND_UIMM12,
OPERAND_SIMM12,		OPERAND_SIMM12,
OPERAND_UIMM20,		OPERAND_UIMM20,
OPERAND_UIMMLOG2XLEN,		OPERAND_UIMMLOG2XLEN,
OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
OPERAND_RVKRNUM,		OPERAND_RVKRNUM,
		OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
// Operand is either a register or uimm5, this is used by V extension pseudo		// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli		// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.		// or vsetivli.
OPERAND_AVL,		OPERAND_AVL,
};		};
} // namespace RISCVOp		} // namespace RISCVOp

// Describes the predecessor/successor bits used in the FENCE instruction.		// Describes the predecessor/successor bits used in the FENCE instruction.
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[RISCV] fix dead codeClosedPublic