[RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions.

[HsiangKai]

Summary

Demonstrate how to model RISC-V V intrinsics and lower them to V instructions.

The CodeGen strategy is designed by @rogfer01 from BSC.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

17

Documenting this and why it's necessary (X0 != ADD X0, 0 for vsetvli) would be good

81

Documenting this helper class would be helpful

llvm/test/CodeGen/RISCV/rvv/vadd.ll

3

Having +m,+f,+d,+a,+c all seem unnecessary here

7

The formatting of this IR function declaration looks a little weird to me - is this the usual style?

19

It would be good to have a test without undef inputs.

[HsiangKai]

Add more test cases and extend scalar operand to the legal type.

[HsiangKai]

Address @frasercrmck's comments.

[HsiangKai]

llvm/test/CodeGen/RISCV/rvv/vadd.ll

7

It is generated by our internal test generator.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2295

I would suggest add a new assert here, the assertion message seems not fit for the extra checking.

[HsiangKai]

• Remove unnecessary swap function in this patch. Add it if we need it afterward.
• Address @kito-cheng's comments.

[rogfer01]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2066

Thanks a lot for the patch @HsiangKai !

I would add a comment here, to avoid confusion, stating that this is an interim calling convention and it may be changed in the future.

[HsiangKai]

Address @rogfer01's comments.

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

26

The comment block above this is about atomics which should stay with the atomic intrinsics. Can we start a new section for vectors after closing the "let TargetPrefix = "riscv" in {" portion for atomics. Same as what I did in D92973.

81

The vl parameter is going to need to be llvm_anyint_ty to support RV32

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2120

Can you pass TLI by reference since its never null? Just need to change the callers to pass *this instead of this

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

73

Why do we need to do this? The vector instructions for that use a FPR64 or FPR32 should only be supported when the scalar type is supported. Why can't we use the proper register class directly?

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

17

This feels like a library layering violation. This file belongs to the MC layer and shouldn't be pulling in files in the IR directory.

llvm/test/CodeGen/RISCV/rvv/vadd.ll

19

Agreed. Can we just avoid undef inputs in all tests?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2255

Will RC ever be a subclass? Can we just check RC == &RISCV::VRRegClass?

2394

Would getRegClassFor work for the scalar case too?

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

24

Put this inside the if since its only needed if we create nodes.

26

This can be simplified slightly to

auto *C = dyn_cast<ConstantSDNode(N);
if (C && C->isNullValue()

Then you don't need two levels of indentation

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

26

I forget whether C++17 is allowed; if so you can do

if (auto *C = dyn_cast<ConstantSDNode>(N); C->isNullValue())

to get the benefits both of reduced scope and of reduced indentation.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

73

Answering my own question. SEW is part of the pseudo operands. So we don't have separate pseudos for FPR16/FPR32/FPR64. That's why we have this

I'm not completely sure about extracting FPR64 values to FPR32 when we really care about the full 64-bit value. Inserting FPR16 to FPR32 seems more ok. How many instructions does this affect?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1017

Use SmallVector with the expected number of operands.

1022

MVT::i64 here should be Subtarget->XLenVT() I think.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

26

I think we're only allowed to use C++14.

[HsiangKai]

Combine D93048 into this patch.

[evandro]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

20

s/~0/VLMAX/

21

"Keep current vl, just change vtype"

28

Subtarget->XLenVT() instead of MVT::i64, here and below, yes?

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

73

@rogfer01, could you help to give a more detail explanation here, thanks.

[HsiangKai]

The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., comparisons) or the scalar result of a reduction.

[HsiangKai]

Rebase on master.

[HsiangKai]

Update test cases.

[HsiangKai]

Gather the class attributes.

[HsiangKai]

Encode the destination type into pattern classes.

[HsiangKai]

Refine the class name in IntrinsicsRISCV.td.

[HsiangKai]

clang format.

[HsiangKai]

Avoid a library layering violation.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

337

Is MVT::i1 needed here? The custom lowering only checks i8/i16/i32.

Should we only have i32 as custom with RV64?

2386

Pass by reference?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

129 ↗

(On Diff #311189)

lowerest->lowest

131 ↗

(On Diff #311189)

This will fail for VMV1R_V won't it?

133 ↗

(On Diff #311189)

I'm not sure I'm comfortable with losing the tracking of the full register write before all machine IR passes run. Can we have a Pseudo instructions for VMV2/4/8_V with the right register classes and let RISCVMCInstLower.cpp expand them?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

214

It's weird that we have a multiclass and a class both named VPseudoBinary. It works because they are considered difference namespaces by tablegen. But it makes the file hard to navigate for a human.

[evandro]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

337

Good question...

[HsiangKai]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

337

MVT::i1 is not needed. We need i8/i16. In vadd.vx, the SEW of scalar argument may be 8 or 16.

[HsiangKai]

Address @craig.topper's comments. I will create pseudo instructions for vector register move later.

[HsiangKai]

Define pseudo instructions for vector whole register move.

[craig.topper]

This looks good to me other than that one comment.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

101 ↗

(On Diff #311587)

Comment needs to be updated to mention vectors

[evandro]

LGTM, but, please, see if any of the lint notices can be addressed before committing.

[evandro]

RV32 tests are also needed, please.

[HsiangKai]

Address @craig.topper and @evandro's comments.

[craig.topper]

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td

 // they require). We carefully instantiate only specific versions of these for
 // specific integer widths, rather than using `llvm_anyint_ty`.
 //
 // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the
 // canonical names, and the intrinsics used in the code will have a name
 // suffixed with the pointer type they are specialised for (denoted `<p>` in the
 // names below), in order to avoid type conflicts.
 
+class RISCVVIntrinsic {
+  // These intrinsics may accept illegal integer values in their llvm_any_ty
+  // operand, so they have to be extended. If set to zero then the intrinsic
+  // does not have any operand that must be extended.
+  Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
+  bits<4> ExtendOperand = 0;
+}
+
 let TargetPrefix = "riscv" in {
 
   // T @llvm.<name>.T.<p>(any*, T, T, T imm);
   class MaskedAtomicRMWFourArg<LLVMType itype>
       : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype],
                   [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
   // T @llvm.<name>.T.<p>(any*, T, T, T, T imm);
   class MaskedAtomicRMWFiveArg<LLVMType itype>
let TargetPrefix = "riscv" in {
   defm int_riscv_masked_atomicrmw_min : MaskedAtomicRMWFiveArgIntrinsics;
   // Unsigned min and max don't need the extra operand.
   defm int_riscv_masked_atomicrmw_umax : MaskedAtomicRMWFourArgIntrinsics;
   defm int_riscv_masked_atomicrmw_umin : MaskedAtomicRMWFourArgIntrinsics;
 
   // @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
   defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
 
+  // RISC-V V extension
+  // For (vector, vector) and (vector, scalar) binary arithmetic.
+  // Input: (vector_in, vector_in/scalar_in, vl)
+  class RVVBinaryCommon
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_any_ty, llvm_i64_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  // For (vector, vector) and (vector, scalar) bianry arithmetic with mask.
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+  class RVVBinaryCommonMask
+       : Intrinsic<[llvm_anyvector_ty],
+                   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
+                    llvm_anyvector_ty, llvm_i64_ty],
+                   [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 3;
+  }
+
+  multiclass riscv_binary {
+    def "int_riscv_" # NAME : RVVBinaryCommon;
+    def "int_riscv_" # NAME # "_mask" : RVVBinaryCommonMask;
+  }
+
+  defm vadd : riscv_binary;
+
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVISelLowering.h

 
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
                                const RISCVSubtarget &STI);
 
+  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
+
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                           MachineFunction &MF,
                           unsigned Intrinsic) const override;
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
-  if (Subtarget.hasStdExtV())
+  if (Subtarget.hasStdExtV()) {
     setBooleanVectorContents(ZeroOrOneBooleanContent);
+    // RVV intrinsics may have illegal operands.
+    for (auto VT : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
+      setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
+  }
 
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
   SDValue Parts[2] = {Lo, Hi};
   return DAG.getMergeValues(Parts, DL);
 }
 
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc DL(Op);
+
+  if (Subtarget.hasStdExtV()) {
+    // Some RVV intrinsics may claim that they want an integer operand to be
+    // extended.
+    if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
+            RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) {
+      if (II->ExtendedOperand) {
+        assert(II->ExtendedOperand < Op.getNumOperands());
+        std::vector<SDValue> Operands(Op->op_begin(), Op->op_end());
+        SDValue &ScalarOp = Operands[II->ExtendedOperand];
+        if (ScalarOp.getValueType() == MVT::i8 ||
+            ScalarOp.getValueType() == MVT::i16 ||
+            ScalarOp.getValueType() == MVT::i32) {
+          ScalarOp = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, ScalarOp);
+          return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
+                             Operands);
+        }
+      }
+    }
+  }
+
   switch (IntNo) {
   default:
     return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getRegister(RISCV::X4, PtrVT);
   }
   }

 static const MCPhysReg ArgFPR32s[] = {
   RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
   RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
 };
 static const MCPhysReg ArgFPR64s[] = {
   RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
   RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
 };
+// This is an interim calling convention and it may be changed in the future.
+static const MCPhysReg ArgVRs[] = {
+  RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20,
+  RISCV::V21, RISCV::V22, RISCV::V23
+};
+static const MCPhysReg ArgVRM2s[] = {
+  RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2
+};
+static const MCPhysReg ArgVRM4s[] = {RISCV::V16M4, RISCV::V20M4};
+static const MCPhysReg ArgVRM8s[] = {RISCV::V16M8};
 
 // Pass a 2*XLEN argument that has been split into two XLEN values through
 // registers or the stack as necessary.
 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
                                 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
                                 MVT ValVT2, MVT LocVT2,
                                 ISD::ArgFlagsTy ArgFlags2) {
   unsigned XLenInBytes = XLen / 8;
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
 
   return false;
 }
 
 // Implements the RISC-V calling convention. Returns true upon failure.
 static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
                      MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
                      ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
-                     bool IsRet, Type *OrigTy) {
+                     bool IsRet, Type *OrigTy, const RISCVTargetLowering *TLI) {
   unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
   assert(XLen == 32 || XLen == 64);
   MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
 
   // Any return value split in to more than two values can't be returned
   // directly.
   if (IsRet && ValNo > 1)
     return true;
static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // Allocate to a register if possible, or else a stack slot.
   Register Reg;
   if (ValVT == MVT::f16 && !UseGPRForF16_F32)
     Reg = State.AllocateReg(ArgFPR16s);
   else if (ValVT == MVT::f32 && !UseGPRForF16_F32)
     Reg = State.AllocateReg(ArgFPR32s);
   else if (ValVT == MVT::f64 && !UseGPRForF64)
     Reg = State.AllocateReg(ArgFPR64s);
-  else
+  else if (ValVT.isScalableVector()) {
+    const TargetRegisterClass *RC = TLI->getRegClassFor(ValVT);
+    if (RC->hasSuperClassEq(&RISCV::VRRegClass)) {
+      Reg = State.AllocateReg(ArgVRs);
+    } else if (RC->hasSuperClassEq(&RISCV::VRM2RegClass)) {
+      Reg = State.AllocateReg(ArgVRM2s);
+    } else if (RC->hasSuperClassEq(&RISCV::VRM4RegClass)) {
+      Reg = State.AllocateReg(ArgVRM4s);
+    } else if (RC->hasSuperClassEq(&RISCV::VRM8RegClass)) {
+      Reg = State.AllocateReg(ArgVRM8s);
+    } else {
+      llvm_unreachable("Unhandled class register for ValueType");
+    }
+    if (!Reg) {
+      LocInfo = CCValAssign::Indirect;
+      // Try using a GPR to pass the address
+      Reg = State.AllocateReg(ArgGPRs);
+      LocVT = XLenVT;
+    }
+  } else
     Reg = State.AllocateReg(ArgGPRs);
   unsigned StackOffset =
       Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8));
 
   // If we reach this point and PendingLocs is non-empty, we must be at the
   // end of a split argument that must be passed indirectly.
   if (!PendingLocs.empty()) {
     assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
     assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
 
     for (auto &It : PendingLocs) {
       if (Reg)
         It.convertToReg(Reg);
       else
         It.convertToMem(StackOffset);
       State.addLoc(It);
     }
     PendingLocs.clear();
     PendingArgFlags.clear();
     return false;
   }
 
-  assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT) &&
-         "Expected an XLenVT at this stage");
+  assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
+          (TLI->getSubtarget().hasStdExtV() && ValVT.isScalableVector())) &&
+         "Expected an XLenVT or scalable vector types at this stage");
 
   if (Reg) {
     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     return false;
   }
 
   // When a floating-point value is passed on the stack, no bit-conversion is
   // needed.
for (unsigned i = 0; i != NumArgs; ++i) {
     Type *ArgTy = nullptr;
     if (IsRet)
       ArgTy = FType->getReturnType();
     else if (Ins[i].isOrigArg())
       ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
 
     RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
     if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
-                 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) {
+                 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, this)) {
       LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
                         << EVT(ArgVT).getEVTString() << '\n');
       llvm_unreachable(nullptr);
     }
   }
 }
 
 void RISCVTargetLowering::analyzeOutputArgs(
     MachineFunction &MF, CCState &CCInfo,
     const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
     CallLoweringInfo *CLI) const {
   unsigned NumArgs = Outs.size();
 
   for (unsigned i = 0; i != NumArgs; i++) {
     MVT ArgVT = Outs[i].VT;
     ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
     Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
 
     RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
     if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
-                 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
+                 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, this)) {
       LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
                         << EVT(ArgVT).getEVTString() << "\n");
       llvm_unreachable(nullptr);
     }
   }
 }
 
 // Convert Val to a ValVT. Should not be called for CCValAssign::Indirect
case CCValAssign::BCvt:
     break;
   }
   return Val;
 }
 
 // The caller is responsible for loading the full value if the argument is
 // passed with CCValAssign::Indirect.
 static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
-                                const CCValAssign &VA, const SDLoc &DL) {
+                                const CCValAssign &VA, const SDLoc &DL,
+                                const RISCVTargetLowering *TLI) {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   EVT LocVT = VA.getLocVT();
   SDValue Val;
   const TargetRegisterClass *RC;
 
+  if (LocVT.getSimpleVT().isScalableVector()) {
+    RC = TLI->getRegClassFor(LocVT.getSimpleVT());
+  } else {
     switch (LocVT.getSimpleVT().SimpleTy) {
     default:
       llvm_unreachable("Unexpected register type");
     case MVT::i32:
     case MVT::i64:
       RC = &RISCV::GPRRegClass;
       break;
     case MVT::f16:
       RC = &RISCV::FPR16RegClass;
       break;
     case MVT::f32:
       RC = &RISCV::FPR32RegClass;
       break;
     case MVT::f64:
       RC = &RISCV::FPR64RegClass;
       break;
     }
+  }
 
   Register VReg = RegInfo.createVirtualRegister(RC);
   RegInfo.addLiveIn(VA.getLocReg(), VReg);
   Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
 
   if (VA.getLocInfo() == CCValAssign::Indirect)
     return Val;
 
SDValue RISCVTargetLowering::LowerFormalArguments(
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
     SDValue ArgValue;
     // Passing f64 on RV32D with a soft float ABI must be handled as a special
     // case.
     if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
       ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
     else if (VA.isRegLoc())
-      ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);
+      ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, this);
     else
       ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
 
     if (VA.getLocInfo() == CCValAssign::Indirect) {
       // If the original argument was split and passed by reference (e.g. i128
       // on RV32), we need to load all parts of it here (using the same
       // address).
       InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
bool RISCVTargetLowering::CanLowerReturn(
     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
     MVT VT = Outs[i].VT;
     ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
     RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
     if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
-                 ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
+                 ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr,
+                 this))
       return false;
   }
   return true;
 }
 
 SDValue
 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 //===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// This file contains the required infrastructure to support code generation
 /// for the standard 'V' (Vector) extension, version 0.9.  This version is still
 /// experimental as the 'V' extension hasn't been ratified yet.
 ///
 /// This file is included from RISCVInstrInfoV.td
 ///
 //===----------------------------------------------------------------------===//
 
+// X0 has special meaning for vsetvl/vsetvli.
+//  rd | rs1 |   AVL value | Effect on vl
+//--------------------------------------------
+// !X0 |  X0 |          ~0 | Set vl to VLMAX
+//  X0 |  X0 | Value in vl | Keep existing vl
+def NoX0 : SDNodeXForm<undef,
+[{
+    SDLoc DL(N);
+
+    if (auto *C = dyn_cast<ConstantSDNode>(N)) {
+      if (C->isNullValue()) {
+        return SDValue(CurDAG->getMachineNode(RISCV::ADDI, DL, MVT::i64,
+                       CurDAG->getRegister(RISCV::X0, MVT::i64),
+                       CurDAG->getTargetConstant(0, DL, MVT::i64)), 0);
+      }
+    }
+
+    return SDValue(N, 0);
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Utilities.
 //===----------------------------------------------------------------------===//
 
 // This class describes information associated to the LMUL.
 class LMULInfo<int lmul, VReg regclass, string mx> {
   bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
   VReg vrclass = regclass;

 }
 
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
 def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
 
 // List of EEW.
 defvar EEWList = [8, 16, 32, 64];
 
+// We only model FPR32 for V instructions in RISCVInstrInfoV.td.
+// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
+// to FPR32 for V instructions is enough.
+class ToFPR32<ValueType type, DAGOperand operand, string name> {
+  dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
+                      (EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32),
+                  !eq(!cast<string>(operand), !cast<string>(FPR16)):
+                      (SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16),
+                  !eq(1, 1):
+                      !dag(type, [operand], [name]));
+}
+
 //===----------------------------------------------------------------------===//
 // Vector register and vector group type information.
 //===----------------------------------------------------------------------===//
 
 class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M>
 {
   ValueType Vector = Vec;
   ValueType Mask = Mas;
def RISCVVPseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
   let Fields = [ "Pseudo", "BaseInstr", "VLIndex", "SEWIndex", "MergeOpIndex",
                  "VLMul" ];
   let PrimaryKey = [ "Pseudo" ];
   let PrimaryKeyName = "getPseudoInfo";
 }
 
+def RISCVVIntrinsicsTable : GenericTable {
+  let FilterClass = "RISCVVIntrinsic";
+  let CppTypeName = "RISCVVIntrinsicInfo";
+  let Fields = ["IntrinsicID", "ExtendOperand"];
+  let PrimaryKey = ["IntrinsicID"];
+  let PrimaryKeyName = "getRISCVVIntrinsicInfo";
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the different pseudo instructions.
 //===----------------------------------------------------------------------===//
 
 class PseudoToVInst<string PseudoInst> {
   string VInst = !subst("_M8", "",
                  !subst("_M4", "",
                  !subst("_M2", "",
class VPseudoBinaryMask<VReg RetClass,
   let MergeOpIndex = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 multiclass VPseudoBinary<VReg RetClass,
                          VReg Op1Class,
                          DAGOperand Op2Class,
                          LMULInfo MInfo> {
   def "_" # MInfo.MX : VPseudoBinary<RetClass, Op1Class, Op2Class>;
   def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class>;
 }
 
 multiclass VPseudoBinaryV_VV {
   let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in
   foreach m = MxList.m in
   {
     let VLMul = m.value in

 multiclass pat_vop_binary<SDNode vop,
                           string instruction_name,
                           ValueType result_type,
                           ValueType op_type,
                           ValueType mask_type,
                           int sew,
                           LMULInfo vlmul,
                           VReg RetClass,
-                          VReg op_reg_class,
-                          bit swap = 0>
+                          VReg op_reg_class>
 {
   defvar instruction = !cast<Instruction>(instruction_name#"_VV_"# vlmul.MX);
   def : Pat<(result_type (vop
                           (op_type op_reg_class:$rs1),
                           (op_type op_reg_class:$rs2))),
-            (instruction (result_type (IMPLICIT_DEF)),
-                         op_reg_class:$rs1,
+            (instruction op_reg_class:$rs1,
                          op_reg_class:$rs2,
-                         (mask_type zero_reg),
                          VLMax, sew)>;
 }
 
 multiclass pat_vop_binary_common<SDNode vop,
                                  string instruction_name,
                                  list<VTypeInfo> vtilist>
 {
   foreach vti = vtilist in
   defm : pat_vop_binary<vop, instruction_name,
                         vti.Vector, vti.Vector, vti.Mask, vti.SEW,
                         vti.LMul, vti.RegClass, vti.RegClass>;
 }
 
+multiclass pat_intrinsic_binary<string intrinsic_name,
+                                string instruction_name,
+                                string kind,
+                                ValueType result_type,
+                                ValueType op1_type,
+                                ValueType op2_type,
+                                ValueType mask_type,
+                                int sew,
+                                LMULInfo vlmul,
+                                VReg result_reg_class,
+                                VReg op1_reg_class,
+                                DAGOperand op2_kind>
+{
+  defvar inst = !cast<Instruction>(instruction_name#_#kind#"_"# vlmul.MX);
+  defvar inst_mask = !cast<Instruction>(instruction_name#_#kind#"_"# vlmul.MX#"_MASK");
+
+  def : Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                          (op1_type op1_reg_class:$rs1),
+                          (op2_type op2_kind:$rs2),
+                          (i64 GPR:$vl))),
+            (inst (op1_type op1_reg_class:$rs1),
+                  ToFPR32<op2_type, op2_kind, "rs2">.ret,
+                  (NoX0 GPR:$vl), sew)>;
+
+  def : Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
+                          (result_type result_reg_class:$merge),
+                          (op1_type op1_reg_class:$rs1),
+                          (op2_type op2_kind:$rs2),
+                          (mask_type V0),
+                          (i64 GPR:$vl))),
+            (inst_mask (result_type result_reg_class:$merge),
+                       (op1_type op1_reg_class:$rs1),
+                       ToFPR32<op2_type, op2_kind, "rs2">.ret,
+                       (mask_type V0), (NoX0 GPR:$vl), sew)>;
+}
+
+multiclass pat_intrinsic_binary_int_v_vv_vx_vi<string intrinsic_name,
+                                               string instruction_name,
+                                               Operand imm_type = simm5>
+{
+  foreach vti = AllIntegerVectors in
+  {
+    defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VV",
+                                vti.Vector, vti.Vector, vti.Vector, vti.Mask,
+                                vti.SEW, vti.LMul, vti.RegClass,
+                                vti.RegClass, vti.RegClass>;
+    defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VX",
+                                vti.Vector, vti.Vector, XLenVT, vti.Mask,
+                                vti.SEW, vti.LMul, vti.RegClass,
+                                vti.RegClass, GPR>;
+    defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VI",
+                                vti.Vector, vti.Vector, XLenVT, vti.Mask,
+                                vti.SEW, vti.LMul, vti.RegClass,
+                                vti.RegClass, imm_type>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo instructions and patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 
 //===----------------------------------------------------------------------===//
 // 6. Configuration-Setting Instructions

 
 //===----------------------------------------------------------------------===//
 // 12.1. Vector Single-Width Integer Add and Subtract
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
 defm PseudoVADD        : VPseudoBinary_VV_VX_VI;
 
+//===----------------------------------------------------------------------===//
+// Patterns.
+//===----------------------------------------------------------------------===//
+
 // Whole-register vector patterns.
 defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>;
 
+defm "" : pat_intrinsic_binary_int_v_vv_vx_vi<"int_riscv_vadd", "PseudoVADD">;
+
 } // Predicates = [HasStdExtV]

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

 
 using namespace RISCV;
 
 #define GET_RISCVVPseudosTable_DECL
 #include "RISCVGenSearchableTables.inc"
 
 } // end namespace RISCVVPseudosTable
 
+namespace RISCVVIntrinsicsTable {
+
+struct RISCVVIntrinsicInfo {
+  unsigned int IntrinsicID;
+  unsigned int ExtendedOperand;
+};
+
+using namespace RISCV;
+
+#define GET_RISCVVIntrinsicsTable_DECL
+#include "RISCVGenSearchableTables.inc"
+
+} // end namespace RISCVVIntrinsicsTable
+
 } // namespace llvm
 
 #endif

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains small standalone enum definitions for the RISCV target
 // useful for the compiler back-end and the MC libraries.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCVSysReg
 

 
 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
     report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
 } // namespace RISCVFeatures
 
+namespace RISCVVIntrinsicsTable {
+
+#define GET_RISCVVIntrinsicsTable_IMPL
+#include "RISCVGenSearchableTables.inc"
+
+} // namespace RISCVVIntrinsicsTable
+
 namespace RISCVVPseudosTable {
 
 #define GET_RISCVVPseudosTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 
 } // namespace RISCVVPseudosTable
 
 } // namespace llvm

llvm/test/CodeGen/RISCV/rvv/vadd.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8> @test(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: test
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vv v16, v16, v17
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i8> undef,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i16> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i32> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i32> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i32> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i32> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i32> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i64> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i64> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i64> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i64> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
+    <vscale x 1 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> undef,
+    i8 undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
+    <vscale x 2 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i8> undef,
+    i8 undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
+    <vscale x 4 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i8> undef,
+    i8 undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
+    <vscale x 8 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i8> undef,
+    i8 undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
+    <vscale x 16 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i8> undef,
+    i8 undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
+    <vscale x 32 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i8> undef,
+    i8 undef,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
+    <vscale x 64 x i8> undef,
+    i8 undef,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i8> undef,
+    i8 undef,
+    <vscale x 64 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
+    <vscale x 1 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i16> undef,
+    i16 undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
+    <vscale x 2 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i16> undef,
+    i16 undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
+    <vscale x 4 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i16> undef,
+    i16 undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
+    <vscale x 8 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i16> undef,
+    i16 undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
+    <vscale x 16 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i16> undef,
+    i16 undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
+    <vscale x 32 x i16> undef,
+    i16 undef,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i16> undef,
+    i16 undef,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
+    <vscale x 1 x i32> undef,
+    i32 undef,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i32> undef,
+    i32 undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
+    <vscale x 2 x i32> undef,
+    i32 undef,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i32> undef,
+    i32 undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
+    <vscale x 4 x i32> undef,
+    i32 undef,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i32> undef,
+    i32 undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
+    <vscale x 8 x i32> undef,
+    i32 undef,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i32> undef,
+    i32 undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
+    <vscale x 16 x i32> undef,
+    i32 undef,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i32> undef,
+    i32 undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
+    <vscale x 1 x i64> undef,
+    i64 undef,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i64> undef,
+    i64 undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
+    <vscale x 2 x i64> undef,
+    i64 undef,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i64> undef,
+    i64 undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
+    <vscale x 4 x i64> undef,
+    i64 undef,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i64> undef,
+    i64 undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
+    <vscale x 8 x i64> undef,
+    i64 undef,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i64> undef,
+    i64 undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
+    <vscale x 1 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i8> undef,
+    i8 9,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
+    <vscale x 2 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
+    <vscale x 2 x i8> undef,
+    <vscale x 2 x i8> undef,
+    i8 9,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
+    <vscale x 4 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
+    <vscale x 4 x i8> undef,
+    <vscale x 4 x i8> undef,
+    i8 9,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
+    <vscale x 8 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
+    <vscale x 8 x i8> undef,
+    <vscale x 8 x i8> undef,
+    i8 9,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
+    <vscale x 16 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
+    <vscale x 16 x i8> undef,
+    <vscale x 16 x i8> undef,
+    i8 9,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
+    <vscale x 32 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
+    <vscale x 32 x i8> undef,
+    <vscale x 32 x i8> undef,
+    i8 9,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
+    <vscale x 64 x i8> undef,
+    i8 9,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
+    <vscale x 64 x i8> undef,
+    <vscale x 64 x i8> undef,
+    i8 9,
+    <vscale x 64 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
+    <vscale x 1 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
+    <vscale x 1 x i16> undef,
+    <vscale x 1 x i16> undef,
+    i16 9,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
+    <vscale x 2 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
+    <vscale x 2 x i16> undef,
+    <vscale x 2 x i16> undef,
+    i16 9,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
+    <vscale x 4 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
+    <vscale x 4 x i16> undef,
+    <vscale x 4 x i16> undef,
+    i16 9,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
+    <vscale x 8 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
+    <vscale x 8 x i16> undef,
+    <vscale x 8 x i16> undef,
+    i16 9,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
+    <vscale x 16 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
+    <vscale x 16 x i16> undef,
+    <vscale x 16 x i16> undef,
+    i16 9,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
+    <vscale x 32 x i16> undef,
+    i16 9,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
+    <vscale x 32 x i16> undef,
+    <vscale x 32 x i16> undef,
+    i16 9,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
+    <vscale x 1 x i32> undef,
+    i32 9,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
+    <vscale x 1 x i32> undef,
+    <vscale x 1 x i32> undef,
+    i32 9,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
+    <vscale x 2 x i32> undef,
+    i32 9,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
+    <vscale x 2 x i32> undef,
+    <vscale x 2 x i32> undef,
+    i32 9,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
+    <vscale x 4 x i32> undef,
+    i32 9,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
+    <vscale x 4 x i32> undef,
+    <vscale x 4 x i32> undef,
+    i32 9,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
+    <vscale x 8 x i32> undef,
+    i32 9,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
+    <vscale x 8 x i32> undef,
+    <vscale x 8 x i32> undef,
+    i32 9,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
+    <vscale x 16 x i32> undef,
+    i32 9,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
+    <vscale x 16 x i32> undef,
+    <vscale x 16 x i32> undef,
+    i32 9,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
+    <vscale x 1 x i64> undef,
+    i64 9,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
+    <vscale x 1 x i64> undef,
+    <vscale x 1 x i64> undef,
+    i64 9,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
+    <vscale x 2 x i64> undef,
+    i64 9,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
+    <vscale x 2 x i64> undef,
+    <vscale x 2 x i64> undef,
+    i64 9,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
+    <vscale x 4 x i64> undef,
+    i64 9,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
+    <vscale x 4 x i64> undef,
+    <vscale x 4 x i64> undef,
+    i64 9,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
+    <vscale x 8 x i64> undef,
+    i64 9,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
+    <vscale x 8 x i64> undef,
+    <vscale x 8 x i64> undef,
+    i64 9,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x i64> %a
+}