[RISCV] Separate masked and unmasked definitions for pseudo instructions.

[HsiangKai]

Summary

As discussed in D92228, it is beneficial to separate the definitions for masked and unmasked instructions.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

def RISCVVPseudosTable : GenericTable {
   let PrimaryKey = [ "Pseudo" ];
   let PrimaryKeyName = "getPseudoInfo";
 }
 
 //===----------------------------------------------------------------------===//
 // Helpers to define the different pseudo instructions.
 //===----------------------------------------------------------------------===//
 
-multiclass pseudo_binary<VReg result_reg_class,
-                         VReg op1_reg_class,
-                         DAGOperand op2_kind,
-                         LMULInfo vlmul > {
-  let Constraints = "$rd = $merge",
-      Uses = [VL, VTYPE], VLIndex = 5, SEWIndex = 6, MergeOpIndex = 1,
-      BaseInstr = !cast<Instruction>(!subst("Pseudo", "", NAME)) in
-    def "_"# vlmul.MX : Pseudo<(outs result_reg_class:$rd),
-                            (ins result_reg_class:$merge,
-                                 op1_reg_class:$rs2, op2_kind:$rs1,
-                                 VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),
-                            []>,
-                     RISCVVPseudo;
+class PseudoToVInst<string PseudoInst> {
+  string VInst = !subst("_M8", "",
+                 !subst("_M4", "",
+                 !subst("_M2", "",
+                 !subst("_M1", "",
+                 !subst("_MF2", "",
+                 !subst("_MF4", "",
+                 !subst("_MF8", "",
+                 !subst("_MASK", "",
+                 !subst("Pseudo", "", PseudoInst)))))))));
+}
+
+class VPseudoBinary<VReg RetClass,
+                    VReg Op1Class,
+                    DAGOperand Op2Class> :
+        Pseudo<(outs RetClass:$rd),
+               (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let Uses = [VL, VTYPE];
+  let VLIndex = 3;
+  let SEWIndex = 4;
+  let MergeOpIndex = -1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoBinaryMask<VReg RetClass,
+                        VReg Op1Class,
+                        DAGOperand Op2Class> :
+        Pseudo<(outs RetClass:$rd),
+                (ins RetClass:$merge,
+                     Op1Class:$rs2, Op2Class:$rs1,
+                     VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let Constraints = "$rd = $merge";
+  let Uses = [VL, VTYPE];
+  let VLIndex = 5;
+  let SEWIndex = 6;
+  let MergeOpIndex = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+multiclass VPseudoBinary<VReg RetClass,
+                         VReg Op1Class,
+                         DAGOperand Op2Class,
+                         LMULInfo MInfo> {
+  def "_" # MInfo.MX : VPseudoBinary<RetClass, Op1Class, Op2Class>;
+  def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class>;
 }
 
-multiclass pseudo_binary_v_vv_vx_vi<Operand imm_type = simm5,
-                                    bit force_earlyclobber = 0> {
+multiclass VPseudoBinaryV_VV {
   let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in
   foreach m = MxList.m in
   {
     let VLMul = m.value in
-    {
-      defvar evr = m.vrclass;
-      defm _VV : pseudo_binary<evr, evr, evr, m>;
-      defm _VX : pseudo_binary<evr, evr, GPR, m>;
-      defm _VI : pseudo_binary<evr, evr, imm_type, m>;
-    }
-  }
+    defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>;
+  }
+}
+
+multiclass VPseudoBinaryV_VX {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in
+  foreach m = MxList.m in
+    let VLMul = m.value in
+    defm _VX : VPseudoBinary<m.vrclass, m.vrclass, GPR, m>;
+
+multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
+  let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1 in
+  foreach m = MxList.m in
+  {
+    let VLMul = m.value in
+    defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>;
+  }
+}
+
+multiclass VPseudoBinary_VV_VX_VI<Operand ImmType = simm5> {
+  defm "" : VPseudoBinaryV_VV;
+  defm "" : VPseudoBinaryV_VX;
+  defm "" : VPseudoBinaryV_VI<ImmType>;
 }
 
 //===----------------------------------------------------------------------===//
 // Helpers to define the different patterns.
 //===----------------------------------------------------------------------===//
 
 multiclass pat_vop_binary<SDNode vop,
                           string instruction_name,
                           ValueType result_type,
                           ValueType op_type,
                           ValueType mask_type,
                           int sew,
                           LMULInfo vlmul,
-                          VReg result_reg_class,
+                          VReg RetClass,
                           VReg op_reg_class,
                           bit swap = 0>
 {
   defvar instruction = !cast<Instruction>(instruction_name#"_VV_"# vlmul.MX);
   def : Pat<(result_type (vop
                           (op_type op_reg_class:$rs1),
                           (op_type op_reg_class:$rs2))),
-            (instruction (result_type (IMPLICIT_DEF)),
-                         op_reg_class:$rs1,
+            (instruction op_reg_class:$rs1,
                          op_reg_class:$rs2,
-                         (mask_type zero_reg),
                          VLMax, sew)>;
 }
 
 multiclass pat_vop_binary_common<SDNode vop,
                                  string instruction_name,
                                  list<VTypeInfo> vtilist>
 {
   foreach vti = vtilist in

 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // 12.1. Vector Single-Width Integer Add and Subtract
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
-defm PseudoVADD        : pseudo_binary_v_vv_vx_vi;
+defm PseudoVADD        : VPseudoBinary_VV_VX_VI;
 
 // Whole-register vector patterns.
 defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>;
 
 } // Predicates = [HasStdExtV]

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

case MachineOperand::MO_Register: {
       break;
     }
     case MachineOperand::MO_Immediate:
       MCOp = MCOperand::createImm(MO.getImm());
       break;
     }
     OutMI.addOperand(MCOp);
   }
+
+  // Unmasked pseudo instructions define MergeOpIndex to -1.
+  // Append dummy mask operand to V instructions.
+  if (RVV->getMergeOpIndex() == -1)
+    OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
+
   return true;
 }
 
 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                           const AsmPrinter &AP) {
   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
     return;
 
   OutMI.setOpcode(MI->getOpcode());
 
   for (const MachineOperand &MO : MI->operands()) {
     MCOperand MCOp;
     if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
       OutMI.addOperand(MCOp);
   }
 }

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir

bb.0 (%ir-block.0):
     %3:gpr = COPY $x13
     %2:gpr = COPY $x12
     %1:gpr = COPY $x11
     %0:gpr = COPY $x10
     %5:vr = IMPLICIT_DEF
     %4:vr = PseudoVLE64_V_M1 %5, %1, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
     %7:vr = IMPLICIT_DEF
     %6:vr = PseudoVLE64_V_M1 %7, %2, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-    %9:vr = IMPLICIT_DEF
-    %8:vr = PseudoVADD_VV_M1 %9, killed %4, killed %6, $noreg, %3, 64, implicit $vl, implicit $vtype
+    %8:vr = PseudoVADD_VV_M1 killed %4, killed %6, %3, 64, implicit $vl, implicit $vtype
     PseudoVSE64_V_M1 killed %8, %0, $noreg, %3, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
     PseudoRET
 
 ...
 
 # POST-INSERTER: %0:gpr = COPY $x13
 # POST-INSERTER: %4:vr = IMPLICIT_DEF
-# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %4, %2, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
 # POST-INSERTER: %6:vr = IMPLICIT_DEF
-# POST-INSERTER: dead %11:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: %7:vr = PseudoVLE64_V_M1 %6, %1, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-# POST-INSERTER: %8:vr = IMPLICIT_DEF
+# POST-INSERTER: dead %11:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, $noreg, -1, implicit $vl, implicit $vtype
 # POST-INSERTER: dead %12:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %9:vr = PseudoVADD_VV_M1 %8, killed %5, killed %7, $noreg, $noreg, -1, implicit $vl, implicit $vtype
-# POST-INSERTER: dead %13:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: PseudoVSE64_V_M1 killed %9, %3, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
+# POST-INSERTER: PseudoVSE64_V_M1 killed %8, %3, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
 
 # CODEGEN: vsetvli  a4, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vle64.v v25, (a1)
 # CODEGEN-NEXT: vsetvli a1, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vle64.v v26, (a2)
 # CODEGEN-NEXT: vsetvli a1, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vadd.vv v25, v25, v26
 # CODEGEN-NEXT: vsetvli a1, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vse64.v v25, (a0)
 # CODEGEN-NEXT: ret

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

define void @vadd_vint64m1(
   store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc
   ret void
 }
 
 ; PRE-INSERTER: %4:vr = IMPLICIT_DEF
 ; PRE-INSERTER: %3:vr = PseudoVLE64_V_M1 %4, %1, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
 ; PRE-INSERTER: %6:vr = IMPLICIT_DEF
 ; PRE-INSERTER: %5:vr = PseudoVLE64_V_M1 %6, %2, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-; PRE-INSERTER: %8:vr = IMPLICIT_DEF
-; PRE-INSERTER: %7:vr = PseudoVADD_VV_M1 %8, killed %3, killed %5, $noreg, $x0, 64, implicit $vl, implicit $vtype
+; PRE-INSERTER: %7:vr = PseudoVADD_VV_M1 killed %3, killed %5, $x0, 64, implicit $vl, implicit $vtype
 ; PRE-INSERTER: PseudoVSE64_V_M1 killed %7, %0, $noreg, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
 
 ; POST-INSERTER: %4:vr = IMPLICIT_DEF
-; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %4, %1, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
 ; POST-INSERTER: %6:vr = IMPLICIT_DEF
-; POST-INSERTER: dead %10:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %6, %2, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-; POST-INSERTER: %8:vr = IMPLICIT_DEF
+; POST-INSERTER: dead %10:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: %7:vr = PseudoVADD_VV_M1 killed %3, killed %5, $noreg, -1, implicit $vl, implicit $vtype
 ; POST-INSERTER: dead %11:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
-; POST-INSERTER: %7:vr = PseudoVADD_VV_M1 %8, killed %3, killed %5, $noreg, $noreg, -1, implicit $vl, implicit $vtype
-; POST-INSERTER: dead %12:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: PseudoVSE64_V_M1 killed %7, %0, $noreg, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)