[RISCV] Define the vfsqrt RVV intrinsics

[evandro]

Summary

Define the vfsqrt IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez <[e-mail]>
Co-Authored-by: Evandro Menezes <[e-mail]>

[HsiangKai]

llvm/include/llvm/IR/IntrinsicsRISCV.td

346

There is no .vx form for vfsqrt. There should be no need to specify ExtendOperand.

352

vector_in should only be vector type in this case. We could replace llvm_any_ty with LLVMMatchType<0>.

355

There is no .vx form for vfsqrt. There should be no need to specify ExtendOperand.

[evandro]

Address @HsiangKai's comments.

[khchen]

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

14

please update tests without undef input.
https://reviews.llvm.org/D93013?id=310804#inline-868720

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

342

Is this class unused?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

513

We're missing tests for double in the rv32 file.

[evandro]

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

513

Ain't it the case for virtually all other RVV intrinsics so far?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

513

Yes. I didn’t catch it until after a bunch of patches had been committed. Some of the most recent patches have it right.

Would you rather fix this patch now or wait and fix all the tests together?

[evandro]

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

513

I'd rather do it later, if at all possible.

[craig.topper]

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   // For indexed store with mask
   // Input: (vector_in, pointer, index, mask, vl)
   class RISCVIStoreMask
         : Intrinsic<[],
                     [llvm_anyvector_ty,
                      LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic;
+  // For destination vector type is the same as source vector.
+  // Input: (vector_in, vl)
+  class RISCVUnaryAANoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For destination vector type is the same as first source vector (with mask).
+  // Input: (vector_in, mask, vl)
+  class RISCVUnaryAAMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
   class RISCVBinaryAAANoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
   class RISCVBinaryAAAMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first source vector.
   // Input: (vector_in, vector_in/scalar_in, vl)
   class RISCVBinaryAAXNoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
   }
-
   // For destination vector type is the same as first source vector (with mask).
   // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
   class RISCVBinaryAAXMask
        : Intrinsic<[llvm_anyvector_ty],
                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                    [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 3;
let TargetPrefix = "riscv" in {
   // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
   class RISCVSaturatingBinaryABXMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
     let ExtendOperand = 3;
   }
-
   class RISCVTernaryAAAXNoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
                      LLVMMatchType<1>],
                     [IntrNoMem]>, RISCVVIntrinsic;
   class RISCVTernaryAAAXMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>],
                     [IntrNoMem]>, RISCVVIntrinsic;
   class RISCVTernaryAAXANoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
                      llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
   }
   class RISCVTernaryAAXAMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
multiclass RISCVSStore {
     def "int_riscv_" # NAME : RISCVSStore;
     def "int_riscv_" # NAME # "_mask" : RISCVSStoreMask;
   }
 
   multiclass RISCVIStore {
     def "int_riscv_" # NAME : RISCVIStore;
     def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask;
   }
-
+  multiclass RISCVUnaryAA {
+    def "int_riscv_" # NAME : RISCVUnaryAANoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask;
+  }
   // AAX means the destination type(A) is the same as the first source
   // type(A). X means any type for the second source operand.
   multiclass RISCVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXNoMask;
     def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask;
   }
   // ABX means the destination type(A) is different from the first source
   // type(B). X means any type for the second source operand.
let TargetPrefix = "riscv" in {
   defm vfmsub : RISCVTernaryAAXA;
   defm vfnmsub : RISCVTernaryAAXA;
 
   defm vfwmacc : RISCVTernaryWide;
   defm vfwnmacc : RISCVTernaryWide;
   defm vfwmsac : RISCVTernaryWide;
   defm vfwnmsac : RISCVTernaryWide;
 
+  defm vfsqrt : RISCVUnaryAA;
+
   defm vfmin : RISCVBinaryAAX;
   defm vfmax : RISCVBinaryAAX;
 
   defm vfsgnj : RISCVBinaryAAX;
   defm vfsgnjn : RISCVBinaryAAX;
   defm vfsgnjx : RISCVBinaryAAX;
 
   defm vfmerge : RISCVBinaryWithV0;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 multiclass VPseudoUnaryV_F_NoDummyMask {
   foreach m = MxList.m in {
     let VLMul = m.value in {
       def "_F_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, FPR32>;
     }
   }
 }
 
+multiclass VPseudoUnaryV_V {
+  foreach m = MxList.m in {
+    let VLMul = m.value in {
+      def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>;
+      def "_V_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>;
+    }
+  }
+}
+
 multiclass PseudoUnaryV_VF2 {
   defvar constraints = "@earlyclobber $rd";
   foreach m = MxList.m[1-6] in
   {
     let VLMul = m.value in {
       def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>;
       def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, m.f2vrclass,
                                                   constraints>;
foreach vtiTofti = fractionList in
                             vti.Vector, fti.Vector,
                             vti.SEW, vti.LMul, fti.RegClass>;
       def : VPatUnaryMask<intrinsic, instruction, suffix,
                           vti.Vector, fti.Vector, vti.Mask,
                           vti.SEW, vti.LMul, vti.RegClass, fti.RegClass>;
    }
 }
 
+multiclass VPatUnaryV_V<string intrinsic, string instruction,
+                        list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in {
+    def : VPatUnaryNoMask<intrinsic, instruction, "V",
+                          vti.Vector, vti.Vector,
+                          vti.SEW, vti.LMul, vti.RegClass>;
+    def : VPatUnaryMask<intrinsic, instruction, "V",
+                        vti.Vector, vti.Vector, vti.Mask,
+                        vti.SEW, vti.LMul, vti.RegClass, vti.RegClass>;
+  }
+}
+
 multiclass VPatNullaryV<string intrinsic, string instruction>
 {
   foreach vti = AllIntegerVectors in {
     def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                           (XLenVT GPR:$vl))),
                           (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
                           (NoX0 GPR:$vl), vti.SEW)>;
     def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
                           (vti.Vector vti.RegClass:$merge),
                           (vti.Mask V0), (XLenVT GPR:$vl))),
                           (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
                           vti.RegClass:$merge, (vti.Mask V0),
                           (NoX0 GPR:$vl), vti.SEW)>;
   }
 }
 
 multiclass VPatNullaryM<string intrinsic, string inst> {
   foreach mti = AllMasks in
     def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic)
                         (XLenVT GPR:$vl))),
                         (!cast<Instruction>(inst#"_M_"#mti.BX)
                         (NoX0 GPR:$vl), mti.SEW)>;
 }
 
-
 multiclass VPatBinary<string intrinsic,
                       string inst,
                       string kind,
                       ValueType result_type,
                       ValueType op1_type,
                       ValueType op2_type,
                       ValueType mask_type,
                       int sew,

 //===----------------------------------------------------------------------===//
 // 12.15. Vector Integer Merge Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVMERGE      : VPseudoBinaryV_VM_XM_IM;
 
 //===----------------------------------------------------------------------===//
 // 12.17. Vector Integer Move Instructions
 //===----------------------------------------------------------------------===//
-
 defm PseudoVMV_V       : VPseudoUnaryV_V_X_I_NoDummyMask;
 
 //===----------------------------------------------------------------------===//
 // 13.1. Vector Single-Width Saturating Add and Subtract
 //===----------------------------------------------------------------------===//
 let Defs = [VXSAT], hasSideEffects = 1 in {
   defm PseudoVSADDU      : VPseudoBinaryV_VV_VX_VI;
   defm PseudoVSADD       : VPseudoBinaryV_VV_VX_VI;

 // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVFWMACC     : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
 defm PseudoVFWNMACC    : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
 defm PseudoVFWMSAC     : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
 defm PseudoVFWNMSAC    : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
 
 //===----------------------------------------------------------------------===//
+// 14.8. Vector Floating-Point Square-Root Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVFSQRT      : VPseudoUnaryV_V;
+
+//===----------------------------------------------------------------------===//
 // 14.11. Vector Floating-Point Min/Max Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVFMIN       : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
 defm PseudoVFMAX       : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
 
 //===----------------------------------------------------------------------===//
 // 14.12. Vector Floating-Point Sign-Injection Instructions
 //===----------------------------------------------------------------------===//

 // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 //===----------------------------------------------------------------------===//
 defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>;
 defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>;
 defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>;
 defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>;
 
 //===----------------------------------------------------------------------===//
+// 14.8. Vector Floating-Point Square-Root Instruction
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>;
+
+//===----------------------------------------------------------------------===//
 // 14.11. Vector Floating-Point Min/Max Instructions
 //===----------------------------------------------------------------------===//
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>;
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>;
 
 //===----------------------------------------------------------------------===//
 // 14.12. Vector Floating-Point Sign-Injection Instructions
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+    <vscale x 1 x half> %0,
+    i32 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x half> %0,
+  <vscale x 1 x half> %1,
+  <vscale x 1 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+    <vscale x 2 x half> %0,
+    i32 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x half> %0,
+  <vscale x 2 x half> %1,
+  <vscale x 2 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+    <vscale x 4 x half> %0,
+    i32 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x half> %0,
+  <vscale x 4 x half> %1,
+  <vscale x 4 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+    <vscale x 8 x half> %0,
+    i32 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x half> %0,
+  <vscale x 8 x half> %1,
+  <vscale x 8 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+    <vscale x 16 x half> %0,
+    i32 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x half> %0,
+  <vscale x 16 x half> %1,
+  <vscale x 16 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+  <vscale x 32 x half>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 32 x half> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+    <vscale x 32 x half> %0,
+    i32 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 32 x half> %0,
+  <vscale x 32 x half> %1,
+  <vscale x 32 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x float> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+    <vscale x 1 x float> %0,
+    i32 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x float> %0,
+  <vscale x 1 x float> %1,
+  <vscale x 1 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x float> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+    <vscale x 2 x float> %0,
+    i32 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x float> %0,
+  <vscale x 2 x float> %1,
+  <vscale x 2 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x float> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+    <vscale x 4 x float> %0,
+    i32 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x float> %0,
+  <vscale x 4 x float> %1,
+  <vscale x 4 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x float> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+    <vscale x 8 x float> %0,
+    i32 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x float> %0,
+  <vscale x 8 x float> %1,
+  <vscale x 8 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x float> %0,
+  i32 %1) nounwind {
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+    <vscale x 16 x float> %0,
+    i32 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x float> %0,
+  <vscale x 16 x float> %1,
+  <vscale x 16 x i1> %2,
+  i32 %3) nounwind {
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+    <vscale x 1 x half> %0,
+    i64 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x half> %0,
+  <vscale x 1 x half> %1,
+  <vscale x 1 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+    <vscale x 2 x half> %0,
+    i64 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x half> %0,
+  <vscale x 2 x half> %1,
+  <vscale x 2 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+    <vscale x 4 x half> %0,
+    i64 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x half> %0,
+  <vscale x 4 x half> %1,
+  <vscale x 4 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+    <vscale x 8 x half> %0,
+    i64 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x half> %0,
+  <vscale x 8 x half> %1,
+  <vscale x 8 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+    <vscale x 16 x half> %0,
+    i64 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x half> %0,
+  <vscale x 16 x half> %1,
+  <vscale x 16 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+  <vscale x 32 x half>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 32 x half> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+    <vscale x 32 x half> %0,
+    i64 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 32 x half> %0,
+  <vscale x 32 x half> %1,
+  <vscale x 32 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x float> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+    <vscale x 1 x float> %0,
+    i64 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x float> %0,
+  <vscale x 1 x float> %1,
+  <vscale x 1 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x float> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+    <vscale x 2 x float> %0,
+    i64 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x float> %0,
+  <vscale x 2 x float> %1,
+  <vscale x 2 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x float> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+    <vscale x 4 x float> %0,
+    i64 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x float> %0,
+  <vscale x 4 x float> %1,
+  <vscale x 4 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x float> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+    <vscale x 8 x float> %0,
+    i64 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x float> %0,
+  <vscale x 8 x float> %1,
+  <vscale x 8 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x float> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+    <vscale x 16 x float> %0,
+    i64 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 16 x float> %0,
+  <vscale x 16 x float> %1,
+  <vscale x 16 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfsqrt_v_nxv1f64_nxv1f64(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x double> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
+    <vscale x 1 x double> %0,
+    i64 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 1 x double> %0,
+  <vscale x 1 x double> %1,
+  <vscale x 1 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfsqrt_v_nxv2f64_nxv2f64(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x double> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
+    <vscale x 2 x double> %0,
+    i64 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 2 x double> %0,
+  <vscale x 2 x double> %1,
+  <vscale x 2 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfsqrt_v_nxv4f64_nxv4f64(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x double> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
+    <vscale x 4 x double> %0,
+    i64 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 4 x double> %0,
+  <vscale x 4 x double> %1,
+  <vscale x 4 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfsqrt_v_nxv8f64_nxv8f64(
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    vfsqrt.v v16, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x double> %0,
+  i64 %1) nounwind {
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
+    <vscale x 8 x double> %0,
+    i64 %1)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64(
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,tu,mu
+; CHECK-NEXT:    vfsqrt.v v16, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+  <vscale x 8 x double> %0,
+  <vscale x 8 x double> %1,
+  <vscale x 8 x i1> %2,
+  i64 %3) nounwind {
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}