[RISCV] Add intrinsics for vsetvli instruction

[craig.topper]

Summary

This patch adds two IR intrinsics for vsetvli instruction. One to set the vector length to a user specified value and one to set it to vlmax. The vlmax uses the X0 source register encoding.

Clang builtins will follow in a separate patch

[craig.topper]

Disabling isel if V extension isn't enabled.

[NickHung]

llvm/include/llvm/IR/IntrinsicsRISCV.td

76

typo? AVL?

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

76

Oops. Thanks. I think my hands are used to typing AVX after years in X86.

[craig.topper]

Fix typo

[NickHung]

llvm/include/llvm/IR/IntrinsicsRISCV.td

83

vsetvlimax? Why not vsetvlmax defined in rvv intrinsic doc.

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

83

Mainly wanted to match the instruction name that it selects. It would also avoid a conflict if a C intrinsic is ever proposed that takes the vtype in a register. The current C intrinsics all have a SEW and LMUL suffix to their name so a "vsetvlmax(size_t vtype)" could be added without a conflict.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

168

This doesn't look tested below

[craig.topper]

Add tests for zero avl

[evandro]

The default should be ta and mu. The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.

[craig.topper]

Use tail agnostic.

[craig.topper]

Rebase on top of the tail agnostic change

[craig.topper]

Looks like I uploaded the wrong file when I rebased this. Will fix

[craig.topper]

Restore the correct diff

[HsiangKai]

LGTM.

[frasercrmck]

LGTM

[Origami404]

In D92973#2447416, @evandro wrote:

The default should be ta and mu. The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.

Hello! Sorry to bother everyone, but I want to know what should one use to set ta/tu/ma/mu if the intrinsic just make ta and mu as default?

[craig.topper]

In D92973#4218408, @Origami404 wrote:

In D92973#2447416, @evandro wrote:

The default should be ta and mu. The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.

Hello! Sorry to bother everyone, but I want to know what should one use to set ta/tu/ma/mu if the intrinsic just make ta and mu as default?

ta ma is now the default.

The compiler will try to change it automatically based on the requirements of the intrinsics that use it.

In some regards the intrinsic shouldn’t be thought of as creating a vsetvli instruction directly. It’s an intrinsic to get the VL that a vsetvli would produce for the given AVL, SEW, and LMUL.

llvm/include/llvm/IR/IntrinsicsRISCV.td

 } // TargetPrefix = "riscv"
 
 //===----------------------------------------------------------------------===//
 // Vectors
 
 class RISCVVIntrinsic {
   // These intrinsics may accept illegal integer values in their llvm_any_ty
   // operand, so they have to be extended. If set to zero then the intrinsic
   // does not have any operand that must be extended.
   Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
   bits<4> ExtendOperand = 0;
 }
 
 let TargetPrefix = "riscv" in {
+  // We use anyint here but we only support XLen.
+  def int_riscv_vsetvli   : Intrinsic<[llvm_anyint_ty],
+                           /* AVL */  [LLVMMatchType<0>,
+                           /* VSEW */  LLVMMatchType<0>,
+                           /* VLMUL */ LLVMMatchType<0>],
+                                      [IntrNoMem, IntrHasSideEffects,
+                                       ImmArg<ArgIndex<1>>,
+                                       ImmArg<ArgIndex<2>>]>;
+  def int_riscv_vsetvlimax : Intrinsic<[llvm_anyint_ty],
+                            /* VSEW */ [LLVMMatchType<0>,
+                            /* VLMUL */ LLVMMatchType<0>],
+                                      [IntrNoMem, IntrHasSideEffects,
+                                       ImmArg<ArgIndex<0>>,
+                                       ImmArg<ArgIndex<1>>]>;
+
   // For unit stride load
   // Input: (pointer, vl)
   class RISCVUSLoad
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMPointerType<LLVMMatchType<0>>,
                      llvm_anyint_ty],
                     [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
   // For unit stride load with mask

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines an instruction selector for the RISCV target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVISelDAGToDAG.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "Utils/RISCVMatInt.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-isel"
if (isa<ConstantSDNode>(Node->getOperand(1)) && isConstantMask(Op0, Mask)) {
         SDValue ShAmtVal = CurDAG->getTargetConstant(ShAmt, DL, XLenVT);
         CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0),
                              ShAmtVal);
         return;
       }
     }
     break;
   }
+  case ISD::INTRINSIC_W_CHAIN: {
+    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    switch (IntNo) {
+      // By default we do not custom select any intrinsic.
+    default:
+      break;
+
+    case Intrinsic::riscv_vsetvli: {
+      if (!Subtarget->hasStdExtV())
+        break;
+
+      assert(Node->getNumOperands() == 5);
+
+      RISCVVSEW VSEW =
+          static_cast<RISCVVSEW>(Node->getConstantOperandVal(3) & 0x7);
+      RISCVVLMUL VLMul =
+          static_cast<RISCVVLMUL>(Node->getConstantOperandVal(4) & 0x7);
+
+      unsigned VTypeI = RISCVVType::encodeVTYPE(
+          VLMul, VSEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
+      SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
+
+      SDValue VLOperand = Node->getOperand(2);
+      if (auto *C = dyn_cast<ConstantSDNode>(VLOperand)) {
+        if (C->isNullValue()) {
+          VLOperand = SDValue(
+              CurDAG->getMachineNode(RISCV::ADDI, DL, XLenVT,
+                                     CurDAG->getRegister(RISCV::X0, XLenVT),
+                                     CurDAG->getTargetConstant(0, DL, XLenVT)),
+              0);
+        }
+      }
+
+      ReplaceNode(Node,
+                  CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT,
+                                         MVT::Other, VLOperand, VTypeIOp,
+                                         /* Chain */ Node->getOperand(0)));
+      return;
+    }
+    case Intrinsic::riscv_vsetvlimax: {
+      if (!Subtarget->hasStdExtV())
+        break;
+
+      assert(Node->getNumOperands() == 4);
+
+      RISCVVSEW VSEW =
+          static_cast<RISCVVSEW>(Node->getConstantOperandVal(2) & 0x7);
+      RISCVVLMUL VLMul =
+          static_cast<RISCVVLMUL>(Node->getConstantOperandVal(3) & 0x7);
+
+      unsigned VTypeI = RISCVVType::encodeVTYPE(
+          VLMul, VSEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
+      SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
+
+      SDValue VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
+      ReplaceNode(Node,
+                  CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT,
+                                         MVT::Other, VLOperand, VTypeIOp,
+                                         /* Chain */ Node->getOperand(0)));
+      return;
+    }
+    }
+    break;
+  }
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 
 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

enum class RISCVVSEW {
   SEW_1024,
 };
 
 enum class RISCVVLMUL {
   LMUL_1 = 0,
   LMUL_2,
   LMUL_4,
   LMUL_8,
-  LMUL_F8 = 5,
+  LMUL_RESERVED,
+  LMUL_F8,
   LMUL_F4,
   LMUL_F2
 };
 
 namespace RISCVVType {
 // Is this a SEW value that can be encoded into the VTYPE format.
 inline static bool isValidSEW(unsigned SEW) {
   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
   RISCVVSEW VSEW = getVSEW(VType);
   RISCVVLMUL VLMUL = getVLMUL(VType);
 
   unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3);
   OS << "e" << Sew;
 
   switch (VLMUL) {
+  case RISCVVLMUL::LMUL_RESERVED:
+    llvm_unreachable("Unexpected LMUL value!");
   case RISCVVLMUL::LMUL_1:
   case RISCVVLMUL::LMUL_2:
   case RISCVVLMUL::LMUL_4:
   case RISCVVLMUL::LMUL_8: {
     unsigned LMul = 1 << static_cast<unsigned>(VLMUL);
     OS << ",m" << LMul;
     break;
   }

llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare i32 @llvm.riscv.vsetvli.i32(i32, i32, i32)
+declare i32 @llvm.riscv.vsetvlimax.i32(i32, i32)
+
+define void @test_vsetvli_e64mf8(i32 %avl) nounwind {
+; CHECK-LABEL: test_vsetvli_e64mf8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, a0, e64,mf8,ta,mu
+; CHECK-NEXT:    ret
+  call i32 @llvm.riscv.vsetvli.i32(i32 %avl, i32 3, i32 5)
+  ret void
+}
+
+define void @test_vsetvli_e8mf2_zero_avl() nounwind {
+; CHECK-LABEL: test_vsetvli_e8mf2_zero_avl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    ret
+  call i32 @llvm.riscv.vsetvli.i32(i32 0, i32 0, i32 7)
+  ret void
+}
+
+define void @test_vsetvlimax_e64m8() nounwind {
+; CHECK-LABEL: test_vsetvlimax_e64m8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    ret
+  call i32 @llvm.riscv.vsetvlimax.i32(i32 3, i32 3)
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare i64 @llvm.riscv.vsetvli.i64(i64, i64, i64)
+declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64)
+
+define void @test_vsetvli_e8m1(i64 %avl) nounwind {
+; CHECK-LABEL: test_vsetvli_e8m1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    ret
+  call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 0, i64 0)
+  ret void
+}
+
+define void @test_vsetvli_e16mf4(i64 %avl) nounwind {
+; CHECK-LABEL: test_vsetvli_e16mf4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    ret
+  call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 1, i64 6)
+  ret void
+}
+
+define void @test_vsetvli_e32mf8_zero_avl() nounwind {
+; CHECK-LABEL: test_vsetvli_e32mf8_zero_avl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    ret
+  call i64 @llvm.riscv.vsetvli.i64(i64 0, i64 1, i64 6)
+  ret void
+}
+
+define void @test_vsetvlimax_e32m2() nounwind {
+; CHECK-LABEL: test_vsetvlimax_e32m2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    ret
+  call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+  ret void
+}
+
+define void @test_vsetvlimax_e64m4() nounwind {
+; CHECK-LABEL: test_vsetvlimax_e64m4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    ret
+  call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
+  ret void
+}