[RISCV] Add support for XCVbi extension in CV32E40P

[melonedo]

Summary

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

[melonedo]

Fix type

[melonedo]

Rename RVInst* to CVInst*

[craig.topper]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

566

This seems to be a different line wrap style than all the others. Is this clang-format being weird?

llvm/lib/Target/RISCV/RISCVFeatures.td

774

This line is indented 1 space too far

775

I probably should have flagged this in the previous reviews, but shouldn't this string say Core-V in it?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

14

I just commited this rename once I noticed the inconsistency.

184

RV -> CV

[melonedo]

Adopt suggestions

Rename CV to RV; fix indentation and line wrapping; add CORE-V to feature description.

[melonedo]

Change version of spec to 1.0.0

[melonedo]

Add tests for +xcvbi option; add extension to RISCVISAInfo; fix spelling

[melonedo]

Amend RISCVUsage.rst

[craig.topper]

LGTM

[thakis]

Looks like you checked in a merge conflict marker,http://45.33.8.238/linux/113808/step_12.txt

Please take a look and revert for now if it takes a while to fix. And please run tests locally as last step before committing.

llvm/docs/RISCVUsage.rst

 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XCVbitmanip``
   LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
 
 ``XCVmac``
   LLVM implements `version 1.3.1 of the Core-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.mac.` as described in the specification. These instructions are only available for riscv32 at this time.
+
+``XCVbi``
+  LLVM implements `version 1.3.1 of the Core-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableTHeadV32,
                           "XTHeadVdot custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
                           "CORE-V MAC custom opcode table");
+    TRY_TO_DECODE_FEATURE(
+        RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
+        "CORE-V Immediate Branching extensions custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
     return MCDisassembler::Fail;
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXCVmac
     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
                        "'XCVmac' (Multiply-Accumulate)">;
 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
                                 "'XCVmac' (Multiply-Accumulate)">;
 
+def FeatureVendorXCVbi
+    : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
+                       "'XCVbi' (Immediate Branching)">;
+def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
+                                AssemblerPredicate<(all_of FeatureVendorXCVbi),
+                                "'XCVbi' (Immediate Branching)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

 //===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the vendor extensions defined by Core-V extensions.
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "XCVbitmanip" in {
-  class RVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
+  class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
       : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
     bits<5> is3;
     bits<5> is2;
     let imm12 = {funct2, is3, is2};
   }
 
   class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
                       Operand i3type = uimm5>
-      : RVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
+      : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
                           (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
                           opcodestr, "$rd, $rs1, $is3, $is2">;
 
   class CVBitManipRR<bits<7> funct7, string opcodestr>
       : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
                 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVBitManipR<bits<7> funct7, string opcodestr>
let Predicates = [HasVendorXCVbitmanip, IsRV32],
   def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
   def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
   def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
 
   def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
   def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
 
   let Constraints = "$rd = $rd_wb" in {
-    def CV_INSERT : RVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
+    def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
                              (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
                              "cv.insert", "$rd, $rs1, $is3, $is2">;
     def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
                              (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
                              "cv.insertr", "$rd, $rs1, $rs2">;
   }
 
   def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
let Predicates = [HasVendorXCVmac, IsRV32] in {
   // Signed 16x16 bit muls
   def : InstAlias<"cv.muls $rd1, $rs1, $rs2",   (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2", (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 
   // Unsigned 16x16 bit muls
   def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2", (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 } // Predicates = [HasVendorXCVmac, IsRV32]
+
+class RVInstImmBranch<bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+    : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
+  bits<5> imm5;
+  let rs2 = imm5;
+  let DecoderNamespace = "XCVbi";
+}
+
+let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0, isBranch = 1, isTerminator = 1 in {
+  // Immediate branching operations
+  def CV_BEQIMM : RVInstImmBranch<0b110, (outs),
+        (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+        "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
+  def CV_BNEIMM : RVInstImmBranch<0b111, (outs),
+        (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+        "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
+}

llvm/test/MC/RISCV/corev/XCVbi-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbi %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+//===----------------------------------------------------------------------===//
+// cv.beqimm
+//===----------------------------------------------------------------------===//
+
+cv.beqimm 0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.beqimm t0, t1, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, 0, t1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 16, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, -17, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, 0, 1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 0, 4096
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 0, -4098
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+//===----------------------------------------------------------------------===//
+// cv.bneimm
+//===----------------------------------------------------------------------===//
+
+cv.bneimm 0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bneimm t0, t1, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, 0, t1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 16, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, -17, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, 0, 1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 0, 4096
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 0, -4098
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
 No newline at end of file

llvm/test/MC/RISCV/corev/XCVbi.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbi -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+//===----------------------------------------------------------------------===//
+// cv.beqimm
+//===----------------------------------------------------------------------===//
+
+label1:
+
+cv.beqimm t0, 0, 0
+# CHECK-INSTR: cv.beqimm t0, 0, 0
+# CHECK-ENCODING: [0x0b,0xe0,0x02,0x00]
+
+cv.beqimm a0, 5, 42
+# CHECK-INSTR: cv.beqimm a0, 5, 42
+# CHECK-ENCODING: [0x0b,0x65,0x55,0x02]
+
+cv.beqimm a0, -5, label1
+# CHECK-INSTR: cv.beqimm a0, -5, label1
+# CHECK-ENCODING: [0x0b'A',0x60'A',0xb5'A',0x01'A']
+# CHECK-ENCODING: fixup A - offset: 0, value: label1, kind: fixup_riscv_branch
+
+//===----------------------------------------------------------------------===//
+// cv.bneimm
+//===----------------------------------------------------------------------===//
+
+label2:
+
+cv.bneimm t0, 0, 0
+# CHECK-INSTR: cv.bneimm t0, 0, 0
+# CHECK-ENCODING: [0x0b,0xf0,0x02,0x00]
+
+cv.bneimm a0, 5, 42
+# CHECK-INSTR: cv.bneimm a0, 5, 42
+# CHECK-ENCODING: [0x0b,0x75,0x55,0x02]
+
+cv.bneimm a0, -5, label2
+# CHECK-INSTR: cv.bneimm a0, -5, label2
+# CHECK-ENCODING: [0x0b'A',0x70'A',0xb5'A',0x01'A']
+# CHECK-ENCODING: fixup A - offset: 0, value: label2, kind: fixup_riscv_branch