[RISCV] Add support for XCVbi extension in CV32E40P

[melonedo]

Summary

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

[melonedo]

Fix type

[melonedo]

Rename RVInst* to CVInst*

[craig.topper]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

568

This seems to be a different line wrap style than all the others. Is this clang-format being weird?

llvm/lib/Target/RISCV/RISCVFeatures.td

823

This line is indented 1 space too far

824

I probably should have flagged this in the previous reviews, but shouldn't this string say Core-V in it?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

14

I just commited this rename once I noticed the inconsistency.

170

RV -> CV

[melonedo]

Adopt suggestions

Rename CV to RV; fix indentation and line wrapping; add CORE-V to feature description.

[melonedo]

Change version of spec to 1.0.0

[melonedo]

Add tests for +xcvbi option; add extension to RISCVISAInfo; fix spelling

[melonedo]

Amend RISCVUsage.rst

[craig.topper]

LGTM

[thakis]

Looks like you checked in a merge conflict marker,http://45.33.8.238/linux/113808/step_12.txt

Please take a look and revert for now if it takes a while to fix. And please run tests locally as last step before committing.

llvm/docs/RISCVUsage.rst

``XCVmac``
   LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XCValu``
   LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
 
 ``XCVsimd``
   LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification.
 
+``XCVbi``
+  LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
 ``XSfcie``
   LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.  All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"svinval", RISCVExtensionVersion{1, 0}},
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svpbmt", RISCVExtensionVersion{1, 0}},
 
     {"v", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
     {"xcvalu", RISCVExtensionVersion{1, 0}},
+    {"xcvbi", RISCVExtensionVersion{1, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
     {"xcvmac", RISCVExtensionVersion{1, 0}},
     {"xcvsimd", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
                           "Sifive CIE custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
                           DecoderTableXCVbitmanip32,
                           "CORE-V Bit Manipulation custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
                           "CORE-V MAC custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
                           "CORE-V ALU custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32,
                           "CORE-V SIMD extensions custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
+                          "CORE-V Immediate Branching custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
     return MCDisassembler::Fail;
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

 def FeatureVendorXCVsimd
     : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true",
                        "'XCVsimd' (CORE-V SIMD ALU)">;
 def HasVendorXCVsimd
     : Predicate<"Subtarget->hasVendorXCVsimd()">,
                 AssemblerPredicate<(any_of FeatureVendorXCVsimd),
                 "'XCVsimd' (CORE-V SIMD ALU)">;
 
+def FeatureVendorXCVbi
+    : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
+                       "'XCVbi' (CORE-V Immediate Branching)">;
+def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
+                               AssemblerPredicate<(all_of FeatureVendorXCVbi),
+                               "'XCVbi' (CORE-V Immediate Branching)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

 //===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the vendor extensions defined by Core-V extensions.
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "XCVbitmanip" in {
   class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
       : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
     bits<5> is3;
     bits<5> is2;
     let imm12 = {funct2, is3, is2};
   }
 
   class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
let Predicates = [HasVendorXCVmac, IsRV32] in {
 
   // Unsigned 16x16 bit muls
   def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
                   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
                   (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 } // Predicates = [HasVendorXCVmac, IsRV32]
 
 let DecoderNamespace = "XCValu" in {
   class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
       : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
                 opcodestr, "$rd, $rs1, $rs2, $imm5", [], InstFormatOther> {
     bits<5> imm5;
     bits<5> rs2;
     bits<5> rs1;
     bits<5> rd;
 
let Predicates = [HasVendorXCVsimd, IsRV32],
   def CV_ADD_DIV2 :    CVSIMDRR<0b01101, 1, 0, 0b010, "cv.add.div2">;
   def CV_ADD_DIV4 :    CVSIMDRR<0b01101, 1, 0, 0b100, "cv.add.div4">;
   def CV_ADD_DIV8 :    CVSIMDRR<0b01101, 1, 0, 0b110, "cv.add.div8">;
 
   def CV_SUB_DIV2 :    CVSIMDRR<0b01110, 1, 0, 0b010, "cv.sub.div2">;
   def CV_SUB_DIV4 :    CVSIMDRR<0b01110, 1, 0, 0b100, "cv.sub.div4">;
   def CV_SUB_DIV8 :    CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;
 }
+
+class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+    : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
+  bits<5> imm5;
+  let rs2 = imm5;
+  let DecoderNamespace = "XCVbi";
+}
+
+let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0, isBranch = 1, isTerminator = 1 in {
+  // Immediate branching operations
+  def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
+        (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+        "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
+  def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
+        (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+        "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
+<<<<<<< HEAD
 ; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
+=======
+; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
+>>>>>>> 0d564dd452ae ([RISCV] Add support for XCVbi extension in CV32E40P)
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADMEMIDX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s

 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
 ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
 ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
 ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
 ; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
+; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32i_xcvbitmanip"
 # CHECK: attribute      5, "rv32i2p1_xcvbitmanip1p0"
 
 .attribute arch, "rv32i_xcvmac"
 # CHECK: attribute      5, "rv32i2p1_xcvmac1p0"
 
 .attribute arch, "rv32i_xcvsimd"
 # CHECK: attribute      5, "rv32i2p1_xcvsimd1p0"
+
+.attribute arch, "rv32i_xcvbi"
+# CHECK: attribute      5, "rv32i2p1_xcvbi1p0"

llvm/test/MC/RISCV/corev/XCVbi-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbi %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+//===----------------------------------------------------------------------===//
+// cv.beqimm
+//===----------------------------------------------------------------------===//
+
+cv.beqimm 0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.beqimm t0, t1, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, 0, t1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 16, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, -17, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.beqimm t0, 0, 1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 0, 4096
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.beqimm t0, 0, -4098
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+//===----------------------------------------------------------------------===//
+// cv.bneimm
+//===----------------------------------------------------------------------===//
+
+cv.bneimm 0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bneimm t0, t1, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, 0, t1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 16, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, -17, 0
+# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
+
+cv.bneimm t0, 0, 1
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 0, 4096
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
+
+cv.bneimm t0, 0, -4098
+# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
 No newline at end of file

llvm/test/MC/RISCV/corev/XCVbi.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbi -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvbi < %s \
+# RUN:     | llvm-objdump --mattr=+xcvbi -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+//===----------------------------------------------------------------------===//
+// cv.beqimm
+//===----------------------------------------------------------------------===//
+
+label1:
+
+cv.beqimm t0, 0, 0
+# CHECK-INSTR: cv.beqimm t0, 0, 0
+# CHECK-OBJDUMP: cv.beqimm t0, 0, 0x0 <label1>
+# CHECK-ENCODING: [0x0b,0xe0,0x02,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
+
+cv.beqimm a0, 5, 42
+# CHECK-INSTR: cv.beqimm a0, 5, 42
+# CHECK-OBJDUMP: cv.beqimm a0, 5, 0x2e <label2+0x22>
+# CHECK-ENCODING: [0x0b,0x65,0x55,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
+
+cv.beqimm a0, -5, label1
+# CHECK-INSTR: cv.beqimm a0, -5, label1
+# CHECK-OBJDUMP: cv.beqimm a0, -5, 0x0 <label1>
+# CHECK-ENCODING: [0x0b'A',0x60'A',0xb5'A',0x01'A']
+# CHECK-ENCODING: fixup A - offset: 0, value: label1, kind: fixup_riscv_branch
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
+
+//===----------------------------------------------------------------------===//
+// cv.bneimm
+//===----------------------------------------------------------------------===//
+
+label2:
+
+cv.bneimm t0, 0, 0
+# CHECK-INSTR: cv.bneimm t0, 0, 0
+# CHECK-OBJDUMP: cv.bneimm t0, 0, 0xc <label2>
+# CHECK-ENCODING: [0x0b,0xf0,0x02,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
+
+cv.bneimm a0, 5, 42
+# CHECK-INSTR: cv.bneimm a0, 5, 42
+# CHECK-OBJDUMP: cv.bneimm a0, 5, 0x3a <label2+0x2e>
+# CHECK-ENCODING: [0x0b,0x75,0x55,0x02]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
+
+cv.bneimm a0, -5, label2
+# CHECK-INSTR: cv.bneimm a0, -5, label2
+# CHECK-OBJDUMP: cv.bneimm a0, -5, 0xc <label2>
+# CHECK-ENCODING: [0x0b'A',0x70'A',0xb5'A',0x01'A']
+# CHECK-ENCODING: fixup A - offset: 0, value: label2, kind: fixup_riscv_branch
+# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}