[RISCV] Add Zvfhmin extension support for llvm RISCV backend

[jacquesguan]

Summary

This patch supports Zvfhmin for RISCV codegen.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

189

Isn't the clang patch have dependent on this?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

189

I ran the zvfhmin.c from the clang patch through CodeGen and got

fatal error: error in backend: Scalarization of scalable vectors is not supported.

The clang patch should be reverted until the CodeGen patch is in.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1096

This needs to be after By default everything must be expanded.

[jacquesguan]

Address comment and turn over dependency.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

189

Yes, I made a mistake on the dependent relationship. Thanks for reverting it.

1096

Done.

[eopXD]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

7205

Nit: My mind is thinking of the sentence "this variable collects widen-able floating-point vectors that is widened from f16". I think the naming here didn't help me understand the code and I have actually read the RHS to understand the code here. Maybe we can improve this naming a nit.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

7205

Yes, and any suggestion about naming?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vfadd.ll

15

Is there a plan to support this via promotion in a future patch?

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVFeatures.td

502

nit: Mininal -> Minimal

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

915

Need an isTypeLegal check?

From the v-spec:

When LMUL < SEW/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEWMIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.

Consider the scenario when VT is <vscale x 1 x 16>. Then LMUL=MF4. If VLEN=ELEN=32 then LMUL=MF4 would only provide 8 bits of storage in a vector register when 16 is needed.

llvm/lib/Target/RISCV/RISCVSubtarget.h

169

nit: Mininal -> Minimal

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

917

Need to make other fp arithmetic operations not available? We're just relying on isel to not select the instructions, but should we should not give ISel the freedom to do this.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

915

Done, thanks.

llvm/test/CodeGen/RISCV/rvv/vfadd.ll

15

Yes, I am working on a patch to do this.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

175

This needs to be rebased, this list has been alphabetized.

[jacquesguan]

rebase main

[michaelmaitland]

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

919

What is the reason not to use SetCommonVFPActions and SetCommonVFPExtLoadTruncStoreActions? I think we should be able to do all of these common VFP actions if we promote to f32 first.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

919

Here is my patch for promoting f16 vector op zvfhmin https://reviews.llvm.org/D153848. As you say we can do all of these common VFP actions if we promote to f32 first, but then we have a f32 vector op and the action of it should be set under the f32 vector op scope which already used SetCommonVFPActions and SetCommonVFPExtLoadTruncStoreActions.

[jacquesguan]

Address comment.

[jacquesguan]

In D151414#4552130, @michaelmaitland wrote:

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

Thanks to point it. I add a check to prevent the combination to widen op when we have only zvfhmin. But these test can not pass with RUN line zvfhmin because the vf form need promotion of splat, when implement in https://reviews.llvm.org/D153848.

[michaelmaitland]

In D151414#4552577, @jacquesguan wrote:

In D151414#4552130, @michaelmaitland wrote:

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

Thanks to point it. I add a check to prevent the combination to widen op when we have only zvfhmin. But these test can not pass with RUN line zvfhmin because the vf form need promotion of splat, when implement in https://reviews.llvm.org/D153848.

Should this patch depend on the type promotion patch then?

[jacquesguan]

In D151414#4552579, @michaelmaitland wrote:

In D151414#4552577, @jacquesguan wrote:

In D151414#4552130, @michaelmaitland wrote:

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

Thanks to point it. I add a check to prevent the combination to widen op when we have only zvfhmin. But these test can not pass with RUN line zvfhmin because the vf form need promotion of splat, when implement in https://reviews.llvm.org/D153848.

Should this patch depend on the type promotion patch then?

No, actually the type promotion patch depends on this one. This patch added the basic support of zvfhmin which can only select to the several supported type convert instruction. https://reviews.llvm.org/D153848 uses promotion to support other ops.

[jacquesguan]

ping.

[michaelmaitland]

I think that this patch and https://reviews.llvm.org/D153848 need to be committed at the same time. This will ensure that if the zvfhmin option is enabled, then we can codegen all LLVM IR.

I applied this patch and https://reviews.llvm.org/D153848, and then updated all instances of +zvfh to be +zvfhmin and re-ran the update_llc_test script for all of the files that were impacted. I found the following crash:

llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfwsub.w
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: build/bin/llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfhmin -riscv-enable-subreg-liveness=false
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@last_chance_recoloring_failure'
 #0 0x000000000178f197 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (build/bin/llc+0x178f197)
 #1 0x000000000178cebe llvm::sys::RunSignalHandlers() (build/bin/llc+0x178cebe)
 #2 0x000000000178f9af SignalHandler(int) Signals.cpp:0:0
 #3 0x00007f612c0b6cf0 __restore_rt (/lib64/libpthread.so.0+0x12cf0)
 #4 0x00007f612ab2aaff raise (/lib64/libc.so.6+0x4eaff)
 #5 0x00007f612aafdea5 abort (/lib64/libc.so.6+0x21ea5)
 #6 0x000000000170cad3 llvm::report_fatal_error(llvm::Twine const&, bool) (build/bin/llc+0x170cad3)
 #7 0x00000000015b1e3d llvm::SelectionDAGISel::CannotYetSelect(llvm::SDNode*) (build/bin/llc+0x15b1e3d)
 #8 0x00000000015b0cfb llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int) (build/bin/llc+0x15b0cfb)
 #9 0x000000000072465f llvm::RISCVDAGToDAGISel::Select(llvm::SDNode*) (build/bin/llc+0x72465f)
#10 0x00000000015a60f5 llvm::SelectionDAGISel::DoInstructionSelection() (build/bin/llc+0x15a60f5)
#11 0x00000000015a4fe2 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (build/bin/llc+0x15a4fe2)
#12 0x00000000015a2b71 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (build/bin/llc+0x15a2b71)
#13 0x000000000159f69c llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (build/bin/llc+0x159f69c)
#14 0x0000000000be8e2c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (build/bin/llc+0xbe8e2c)
#15 0x0000000001102e23 llvm::FPPassManager::runOnFunction(llvm::Function&) (build/bin/llc+0x1102e23)
#16 0x000000000110aaa1 llvm::FPPassManager::runOnModule(llvm::Module&) (build/bin/llc+0x110aaa1)
#17 0x0000000001103626 llvm::legacy::PassManagerImpl::run(llvm::Module&) (build/bin/llc+0x1103626)
#18 0x00000000006987e8 compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#19 0x00000000006962bd main (build/bin/llc+0x6962bd)
#20 0x00007f612ab16d85 __libc_start_main (/lib64/libc.so.6+0x3ad85)
#21 0x0000000000692c6e _start (build/bin/llc+0x692c6e)

I think we need to be able to update this patch or the type promotion patch to make sure we don't get any crashes like this when we run the experiment I describe above.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

919

Do we need this TODO still?

1108

Do we need this TODO still?

[jacquesguan]

In D151414#4585812, @michaelmaitland wrote:

I think that this patch and https://reviews.llvm.org/D153848 need to be committed at the same time. This will ensure that if the zvfhmin option is enabled, then we can codegen all LLVM IR.

I applied this patch and https://reviews.llvm.org/D153848, and then updated all instances of +zvfh to be +zvfhmin and re-ran the update_llc_test script for all of the files that were impacted. I found the following crash:

llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfwsub.w
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: build/bin/llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfhmin -riscv-enable-subreg-liveness=false
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@last_chance_recoloring_failure'
 #0 0x000000000178f197 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (build/bin/llc+0x178f197)
 #1 0x000000000178cebe llvm::sys::RunSignalHandlers() (build/bin/llc+0x178cebe)
 #2 0x000000000178f9af SignalHandler(int) Signals.cpp:0:0
 #3 0x00007f612c0b6cf0 __restore_rt (/lib64/libpthread.so.0+0x12cf0)
 #4 0x00007f612ab2aaff raise (/lib64/libc.so.6+0x4eaff)
 #5 0x00007f612aafdea5 abort (/lib64/libc.so.6+0x21ea5)
 #6 0x000000000170cad3 llvm::report_fatal_error(llvm::Twine const&, bool) (build/bin/llc+0x170cad3)
 #7 0x00000000015b1e3d llvm::SelectionDAGISel::CannotYetSelect(llvm::SDNode*) (build/bin/llc+0x15b1e3d)
 #8 0x00000000015b0cfb llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char const*, unsigned int) (build/bin/llc+0x15b0cfb)
 #9 0x000000000072465f llvm::RISCVDAGToDAGISel::Select(llvm::SDNode*) (build/bin/llc+0x72465f)
#10 0x00000000015a60f5 llvm::SelectionDAGISel::DoInstructionSelection() (build/bin/llc+0x15a60f5)
#11 0x00000000015a4fe2 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (build/bin/llc+0x15a4fe2)
#12 0x00000000015a2b71 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (build/bin/llc+0x15a2b71)
#13 0x000000000159f69c llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (build/bin/llc+0x159f69c)
#14 0x0000000000be8e2c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (build/bin/llc+0xbe8e2c)
#15 0x0000000001102e23 llvm::FPPassManager::runOnFunction(llvm::Function&) (build/bin/llc+0x1102e23)
#16 0x000000000110aaa1 llvm::FPPassManager::runOnModule(llvm::Module&) (build/bin/llc+0x110aaa1)
#17 0x0000000001103626 llvm::legacy::PassManagerImpl::run(llvm::Module&) (build/bin/llc+0x1103626)
#18 0x00000000006987e8 compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#19 0x00000000006962bd main (build/bin/llc+0x6962bd)
#20 0x00007f612ab16d85 __libc_start_main (/lib64/libc.so.6+0x3ad85)
#21 0x0000000000692c6e _start (build/bin/llc+0x692c6e)

I think we need to be able to update this patch or the type promotion patch to make sure we don't get any crashes like this when we run the experiment I describe above.

Yes, I agree with merging these patches at the same time.

But for the case regalloc-last-chance-recoloring-failure.ll, it uses the intirinsic @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64, this intrinsic is not supported in zvfhmin, so cannot selected is the excepted action. By example we also cannot select @llvm.riscv.vmulh.nxv1i64.i64 for ZVE64D, and any vector intrinsic for no V enable. I don't think we should do promotion for intrinsic too.
Actually target specific intrinsics basiclly comes from clang rvv-builtin. In https://reviews.llvm.org/D150253, any use of unsuportted builtin would cause a clang error. So there is no actual case will generate unsupportted intrinsic.

[jacquesguan]

rebase main

[michaelmaitland]

Yes, I agree with merging these patches at the same time.

But for the case regalloc-last-chance-recoloring-failure.ll, it uses the intirinsic @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64, this intrinsic is not supported in zvfhmin, so cannot selected is the excepted action. By example we also cannot select @llvm.riscv.vmulh.nxv1i64.i64 for ZVE64D, and any vector intrinsic for no V enable. I don't think we should do promotion for intrinsic too.
Actually target specific intrinsics basiclly comes from clang rvv-builtin. In https://reviews.llvm.org/D150253, any use of unsuportted builtin would cause a clang error. So there is no actual case will generate unsupportted intrinsic.

Thanks for the clarification. I agree with you now.

[michaelmaitland]

LGTM. Please wait to merge this and the type promotion patch together.

[jacquesguan]

Rebase main.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
 
     {"zve32f", RISCVExtensionVersion{1, 0}},
     {"zve32x", RISCVExtensionVersion{1, 0}},
     {"zve64d", RISCVExtensionVersion{1, 0}},
     {"zve64f", RISCVExtensionVersion{1, 0}},
     {"zve64x", RISCVExtensionVersion{1, 0}},
 
     {"zvfh", RISCVExtensionVersion{1, 0}},
+    {"zvfhmin", RISCVExtensionVersion{1, 0}},
 
     {"zvl1024b", RISCVExtensionVersion{1, 0}},
     {"zvl128b", RISCVExtensionVersion{1, 0}},
     {"zvl16384b", RISCVExtensionVersion{1, 0}},
     {"zvl2048b", RISCVExtensionVersion{1, 0}},
     {"zvl256b", RISCVExtensionVersion{1, 0}},
     {"zvl32768b", RISCVExtensionVersion{1, 0}},
     {"zvl32b", RISCVExtensionVersion{1, 0}},
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zacas", RISCVExtensionVersion{1, 0}},
 
     {"zfa", RISCVExtensionVersion{0, 2}},
     {"zfbfmin", RISCVExtensionVersion{0, 8}},
 
     {"zicfilp", RISCVExtensionVersion{0, 2}},
     {"zicond", RISCVExtensionVersion{1, 0}},
 
     {"ztso", RISCVExtensionVersion{0, 1}},
 
     {"zvbb", RISCVExtensionVersion{1, 0}},
     {"zvbc", RISCVExtensionVersion{1, 0}},
 
     {"zvfbfmin", RISCVExtensionVersion{0, 8}},
     {"zvfbfwma", RISCVExtensionVersion{0, 8}},
 
     // vector crypto

 static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
 static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
 static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
 static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
 static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
 static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
 static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
 static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
 static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
 static const char *ImpliedExtsZvknhb[] = {"zvknha"};
 static const char *ImpliedExtsZvks[] = {"zvkb", "zvksed", "zvksh", "zvkt"};
 static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
 static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
 static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"zve32f"}, {ImpliedExtsZve32f}},
     {{"zve32x"}, {ImpliedExtsZve32x}},
     {{"zve64d"}, {ImpliedExtsZve64d}},
     {{"zve64f"}, {ImpliedExtsZve64f}},
     {{"zve64x"}, {ImpliedExtsZve64x}},
     {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
     {{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
     {{"zvfh"}, {ImpliedExtsZvfh}},
+    {{"zvfhmin"}, {ImpliedExtsZvfhmin}},
     {{"zvkn"}, {ImpliedExtsZvkn}},
     {{"zvknc"}, {ImpliedExtsZvknc}},
     {{"zvkng"}, {ImpliedExtsZvkng}},
     {{"zvknhb"}, {ImpliedExtsZvknhb}},
     {{"zvks"}, {ImpliedExtsZvks}},
     {{"zvksc"}, {ImpliedExtsZvksc}},
     {{"zvksg"}, {ImpliedExtsZvksg}},
     {{"zvl1024b"}, {ImpliedExtsZvl1024b}},

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
 
 def FeatureStdExtZvfh
     : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
                        "'Zvfh' (Vector Half-Precision Floating-Point)",
                        [FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
 
+def FeatureStdExtZvfhmin
+    : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
+                       "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+                       [FeatureStdExtZve32f]>;
+
 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 
+def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
+      AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
+                         "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
+                         "'Zvfh' (Vector Half-Precision Floating-Point)">;
+
 def HasStdExtZfhOrZvfh
     : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
                                    "'Zfh' (Half-Precision Floating-Point) or "
                                    "'Zvfh' (Vector Half-Precision Floating-Point)">;
 
 def FeatureStdExtZicbom
     : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

for (MVT VT : BoolVecVTs)
       addRegClassForRVV(VT);
     for (MVT VT : IntVecVTs) {
       if (VT.getVectorElementType() == MVT::i64 &&
           !Subtarget.hasVInstructionsI64())
         continue;
       addRegClassForRVV(VT);
     }
 
-    if (Subtarget.hasVInstructionsF16())
+    if (Subtarget.hasVInstructionsF16Minimal())
       for (MVT VT : F16VecVTs)
         addRegClassForRVV(VT);
 
     if (Subtarget.hasVInstructionsBF16())
       for (MVT VT : BF16VecVTs)
         addRegClassForRVV(VT);
 
     if (Subtarget.hasVInstructionsF32())
const auto SetCommonVFPExtLoadTruncStoreActions =
         };
 
     if (Subtarget.hasVInstructionsF16()) {
       for (MVT VT : F16VecVTs) {
         if (!isTypeLegal(VT))
           continue;
         SetCommonVFPActions(VT);
       }
+    } else if (Subtarget.hasVInstructionsF16Minimal()) {
+      for (MVT VT : F16VecVTs) {
+        if (!isTypeLegal(VT))
+          continue;
+        setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+        setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+        // TODO: make others promote?
+      }
     }
 
     if (Subtarget.hasVInstructionsF32()) {
       for (MVT VT : F32VecVTs) {
         if (!isTypeLegal(VT))
           continue;
         SetCommonVFPActions(VT);
         SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs);
if (Subtarget.useRVVForFixedLengthVectors()) {
         for (MVT InnerVT : MVT::fp_fixedlen_vector_valuetypes()) {
           setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
           setTruncStoreAction(VT, InnerVT, Expand);
         }
 
         if (!useRVVForFixedLengthVectorVT(VT))
           continue;
 
         // By default everything must be expanded.
         for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
           setOperationAction(Op, VT, Expand);
 
         // Custom lower fixed vector undefs to scalable vector undefs to avoid
         // expansion to a build_vector of 0s.
         setOperationAction(ISD::UNDEF, VT, Custom);
 
+        if (VT.getVectorElementType() == MVT::f16 &&
+            !Subtarget.hasVInstructionsF16()) {
+          setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+          setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+          // TODO: make others promote?
+          continue;
+        }
+
         // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
         setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT,
                            Custom);
 
         setOperationAction({ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS,
                             ISD::VECTOR_SHUFFLE, ISD::INSERT_VECTOR_ELT,
                             ISD::EXTRACT_VECTOR_ELT},
                            VT, Custom);
static bool useRVVForFixedLengthVectorVT(MVT VT,
   case MVT::i16:
   case MVT::i32:
     break;
   case MVT::i64:
     if (!Subtarget.hasVInstructionsI64())
       return false;
     break;
   case MVT::f16:
-    if (!Subtarget.hasVInstructionsF16())
+    if (!Subtarget.hasVInstructionsF16Minimal())
       return false;
     break;
   case MVT::f32:
     if (!Subtarget.hasVInstructionsF32())
       return false;
     break;
   case MVT::f64:
     if (!Subtarget.hasVInstructionsF64())
static SDValue combineVFMADD_VLWithVFNEG_VL(SDNode *N, SelectionDAG &DAG) {
   unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
   if (N->isTargetStrictFPOpcode())
     return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
                        {N->getOperand(0), A, B, C, Mask, VL});
   return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
                      VL);
 }
 
-static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG,
+                                       const RISCVSubtarget &Subtarget) {
   if (SDValue V = combineVFMADD_VLWithVFNEG_VL(N, DAG))
     return V;
 
+  if (N->getValueType(0).isScalableVector() &&
+      N->getValueType(0).getVectorElementType() == MVT::f32 &&
+      (Subtarget.hasVInstructionsF16Minimal() &&
+       !Subtarget.hasVInstructionsF16())) {
+    return SDValue();
+  }
+
   // FIXME: Ignore strict opcodes for now.
   if (N->isTargetStrictFPOpcode())
     return SDValue();
 
   // Try to form widening FMA.
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
   SDValue Mask = N->getOperand(3);
static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG,
 
   Op0 = Op0.getOperand(0);
   Op1 = Op1.getOperand(0);
 
   return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), Op0, Op1,
                      N->getOperand(2), Mask, VL);
 }
 
-static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG,
+                                      const RISCVSubtarget &Subtarget) {
+  if (N->getValueType(0).isScalableVector() &&
+      N->getValueType(0).getVectorElementType() == MVT::f32 &&
+      (Subtarget.hasVInstructionsF16Minimal() &&
+       !Subtarget.hasVInstructionsF16())) {
+    return SDValue();
+  }
+
   // FIXME: Ignore strict opcodes for now.
   assert(!N->isTargetStrictFPOpcode() && "Unexpected opcode");
 
   // Try to form widening multiply.
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
   SDValue Merge = N->getOperand(2);
   SDValue Mask = N->getOperand(3);
static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG,
 
   Op0 = Op0.getOperand(0);
   Op1 = Op1.getOperand(0);
 
   return DAG.getNode(RISCVISD::VFWMUL_VL, SDLoc(N), N->getValueType(0), Op0,
                      Op1, Merge, Mask, VL);
 }
 
-static SDValue performFADDSUB_VLCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue performFADDSUB_VLCombine(SDNode *N, SelectionDAG &DAG,
+                                        const RISCVSubtarget &Subtarget) {
+  if (N->getValueType(0).isScalableVector() &&
+      N->getValueType(0).getVectorElementType() == MVT::f32 &&
+      (Subtarget.hasVInstructionsF16Minimal() &&
+       !Subtarget.hasVInstructionsF16())) {
+    return SDValue();
+  }
+
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
   SDValue Merge = N->getOperand(2);
   SDValue Mask = N->getOperand(3);
   SDValue VL = N->getOperand(4);
 
   bool IsAdd = N->getOpcode() == RISCVISD::FADD_VL;
 
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case RISCVISD::VFMADD_VL:
   case RISCVISD::VFNMADD_VL:
   case RISCVISD::VFMSUB_VL:
   case RISCVISD::VFNMSUB_VL:
   case RISCVISD::STRICT_VFMADD_VL:
   case RISCVISD::STRICT_VFNMADD_VL:
   case RISCVISD::STRICT_VFMSUB_VL:
   case RISCVISD::STRICT_VFNMSUB_VL:
-    return performVFMADD_VLCombine(N, DAG);
+    return performVFMADD_VLCombine(N, DAG, Subtarget);
   case RISCVISD::FMUL_VL:
-    return performVFMUL_VLCombine(N, DAG);
+    return performVFMUL_VLCombine(N, DAG, Subtarget);
   case RISCVISD::FADD_VL:
   case RISCVISD::FSUB_VL:
-    return performFADDSUB_VLCombine(N, DAG);
+    return performFADDSUB_VLCombine(N, DAG, Subtarget);
   case ISD::LOAD:
   case ISD::STORE: {
     if (DCI.isAfterLegalizeDAG())
       if (SDValue V = performMemPairCombine(N, DCI))
         return V;
 
     if (N->getOpcode() != ISD::STORE)
       break;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

defm : VPatConversionTA<intrinsic, instruction, "V",
                             vti.LMul, fwti.RegClass, vti.RegClass>;
   }
 }
 
 multiclass VPatConversionWF_VF<string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableFloatVectors in {
     defvar fvti = fvtiToFWti.Vti;
     defvar fwti = fvtiToFWti.Wti;
-    let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
-                                 GetVTypePredicates<fwti>.Predicates) in
+    // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
+    let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
+                         !listconcat(GetVTypePredicates<fvti>.Predicates,
+                                     GetVTypePredicates<fwti>.Predicates)) in
       defm : VPatConversionTA<intrinsic, instruction, "V",
                               fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
                               fvti.LMul, fwti.RegClass, fvti.RegClass>;
   }
 }
 
 multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction> {
   foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in
   {
     defvar fvti = fvtiToFWti.Vti;
     defvar fwti = fvtiToFWti.Wti;
foreach fvtiToFWti = AllWidenableFloatVectors in {
     let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
                                  GetVTypePredicates<fwti>.Predicates) in
     defm : VPatConversionTA<intrinsic, instruction, "W",
                             fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
                             fvti.LMul, fvti.RegClass, fwti.RegClass>;
   }
 }
 
-multiclass VPatConversionVF_WF_RM <string intrinsic, string instruction> {
-  foreach fvtiToFWti = AllWidenableFloatVectors in {
+multiclass VPatConversionVF_WF_RM <string intrinsic, string instruction,
+                                   list<VTypeInfoToWide> wlist = AllWidenableFloatVectors> {
+  foreach fvtiToFWti = wlist in {
     defvar fvti = fvtiToFWti.Vti;
     defvar fwti = fvtiToFWti.Wti;
     let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
                                  GetVTypePredicates<fwti>.Predicates) in
     defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
                                         fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
                                         fvti.LMul, fvti.RegClass, fwti.RegClass>;
   }

 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 //===----------------------------------------------------------------------===//
 defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;
 defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;
 defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;
 defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
 defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
 defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
-defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
-defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
+defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
+                                                !ne(fvtiToFWti.Vti.Scalar, f16));
+defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
+                           WidenableFloatVectorsExceptF16>;
+// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
+defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
+                                          !eq(fvtiToFWti.Vti.Scalar, f16));
+let Predicates = [HasVInstructionsF16Minimal] in
+defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
+                           F16WidenableFloatVectors>;
+defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w", 
                                  "PseudoVFNCVTBF16_F_F">;
 defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
 
 //===----------------------------------------------------------------------===//
 // 14. Vector Reduction Operations
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 defm : VPatNConvertFP2ISDNode_W<any_fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
 defm : VPatNConvertFP2ISDNode_W<any_fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
 defm : VPatNConvertI2FPSDNode_W_RM<any_sint_to_fp, "PseudoVFNCVT_F_X_W">;
 defm : VPatNConvertI2FPSDNode_W_RM<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
 foreach fvtiToFWti = AllWidenableFloatVectors in {
   defvar fvti = fvtiToFWti.Vti;
   defvar fwti = fvtiToFWti.Wti;
-  let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
-                               GetVTypePredicates<fwti>.Predicates) in
+  let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
+                       !listconcat(GetVTypePredicates<fvti>.Predicates,
+                                   GetVTypePredicates<fwti>.Predicates)) in
   def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
             (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
                 (fvti.Vector (IMPLICIT_DEF)),
                 fwti.RegClass:$rs1,
                 // Value to indicate no rounding mode change in
                 // RISCVInsertReadWriteCSR
                 FRM_DYN,
                 fvti.AVL, fvti.Log2SEW, TA_MA)>;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

 defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
 
 defm : VPatWConvertI2FPVL_V<any_riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;
 defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
 
 foreach fvtiToFWti = AllWidenableFloatVectors in {
   defvar fvti = fvtiToFWti.Vti;
   defvar fwti = fvtiToFWti.Wti;
-  let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
-                               GetVTypePredicates<fwti>.Predicates) in
+  let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
+                       !listconcat(GetVTypePredicates<fvti>.Predicates,
+                                   GetVTypePredicates<fwti>.Predicates)) in
   def : Pat<(fwti.Vector (any_riscv_fpextend_vl
                              (fvti.Vector fvti.RegClass:$rs1),
                              (fvti.Mask V0),
                              VLOpFrag)),
             (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK")
                 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
                 (fvti.Mask V0),
                 GPR:$vl, fvti.Log2SEW, TA_MA)>;

 defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
 
 defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_RM_F_XU_W">;
 defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">;
 
 foreach fvtiToFWti = AllWidenableFloatVectors in {
   defvar fvti = fvtiToFWti.Vti;
   defvar fwti = fvtiToFWti.Wti;
-  let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
-                               GetVTypePredicates<fwti>.Predicates) in {
+  // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
+  let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
+                       !listconcat(GetVTypePredicates<fvti>.Predicates,
+                                   GetVTypePredicates<fwti>.Predicates)) in {
     def : Pat<(fvti.Vector (any_riscv_fpround_vl
                                (fwti.Vector fwti.RegClass:$rs1),
                                (fwti.Mask V0), VLOpFrag)),
               (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
                   (fwti.Mask V0),
                   // Value to indicate no rounding mode change in
                   // RISCVInsertReadWriteCSR
                   FRM_DYN,
                   GPR:$vl, fvti.Log2SEW, TA_MA)>;
 
+  let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
+                               GetVTypePredicates<fwti>.Predicates) in
     def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl
                                (fwti.Vector fwti.RegClass:$rs1),
                                (fwti.Mask V0), VLOpFrag)),
               (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK")
                   (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
                   (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
   }
 }

llvm/lib/Target/RISCV/RISCVSubtarget.h

bool isRegisterReservedByUser(Register i) const {
     return UserReservedRegister[i];
   }
 
   bool hasMacroFusion() const { return hasLUIADDIFusion(); }
 
   // Vector codegen related methods.
   bool hasVInstructions() const { return HasStdExtZve32x; }
   bool hasVInstructionsI64() const { return HasStdExtZve64x; }
+  bool hasVInstructionsF16Minimal() const {
+    return HasStdExtZvfhmin || HasStdExtZvfh;
+  }
   bool hasVInstructionsF16() const { return HasStdExtZvfh; }
   bool hasVInstructionsBF16() const { return HasStdExtZvfbfmin; }
   bool hasVInstructionsF32() const { return HasStdExtZve32f; }
   bool hasVInstructionsF64() const { return HasStdExtZve64d; }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
   bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
   unsigned getMaxInterleaveFactor() const {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 
 declare <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half>, <2 x i1>, i32)
 
 define <2 x float> @vfpext_v2f16_v2f32(<2 x half> %a, <2 x i1> %m, i32 zeroext %vl) {
 ; CHECK-LABEL: vfpext_v2f16_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwcvt.f.f.v v9, v8, v0.t

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+
 
 declare <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float>, <2 x i1>, i32)
 
 define <2 x half> @vfptrunc_v2f16_v2f32(<2 x float> %a, <2 x i1> %m, i32 zeroext %vl) {
 ; CHECK-LABEL: vfptrunc_v2f16_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfncvt.f.f.w v9, v8, v0.t

llvm/test/CodeGen/RISCV/rvv/vfadd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfhmin,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -target-abi=ilp32d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -target-abi=lp64d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
+
+; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd
 
 declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
   <vscale x 1 x half>,
   <vscale x 1 x half>,
   <vscale x 1 x half>,
   iXLen, iXLen);
 
 define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
-
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
 declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
   <vscale x 1 x half>,
   <vscale x 1 x float>,
   iXLen, iXLen);
 
 define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
 ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
 ; CHECK:       # %bb.0: # %entry

llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
 ;
 ; CHECK-LABEL: vfpext_nxv1f16_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v8, v9

llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
 
 declare <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
 
 define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
 ; CHECK-LABEL: vfpext_nxv2f16_nxv2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
 ; CHECK-NEXT:    vfwcvt.f.f.v v9, v8, v0.t

llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
 ;
 ; CHECK-LABEL: vfptrunc_nxv1f32_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfncvt.f.f.w v9, v8
 ; CHECK-NEXT:    vmv1r.v v8, v9

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
 
 declare <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
 
 define <vscale x 2 x half> @vfptrunc_nxv2f16_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
 ; CHECK-LABEL: vfptrunc_nxv2f16_nxv2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
 ; CHECK-NEXT:    vfncvt.f.f.w v9, v8, v0.t

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
-
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
 declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
   <vscale x 1 x float>,
   <vscale x 1 x half>,
   iXLen);
 
 define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
 ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
 ; CHECK:       # %bb.0: # %entry