In D159368#4650810, @wangpc wrote:

Ping.
Do we agree to do this?

I wonder if it would be a good idea to add a function getSEW(MachineInstr) which gets the SEW from the Opcode or from the Operand, depending on how the pseudo tracks SEW. This indirection would remove the complication of having inconsistent pseudos. WDYT?

I've added a simple test. I plan on removing this test in the future with a set
of tests that shows behavior all instructions for all different LMUL and SEW
pairs.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

I removed test case as I plan on adding one that is more complete and shows the intended behavior more effectivley.

Add reduction instr between vsetvlis

The reduction formula has a bug in it, and I plan to fix it in a follow up patch.

I am super pumped to hear more about MDL on our call later today. The thought that you've given to being able to model complex behavior is exciting!

In D158568#4623906, @wangpc wrote:

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

I'm not very familiar with how isCommutable works, but this change looks like a good idea as long as isCommutable only refers to the $rs2 and $rs1 operands, and does not say anything about commutability of $carry, $vl, or $sew.

SystemZ Cycles -> ReleaseAtCycle

Rebase.

I am failing build and will look into it. I built all targets locally and had no problem, but perhaps I missed something.

It is spelled Acquire, not Aquire... (:embarrased:)

According to RecurKind, an AnyOf reduction has the form select(icmp(), x, y) where one of (x,y) are loop invariant. In RecurrenceDescriptor::isAnyOfPattern there is the additional condition that both (x, y) are loop invariant. (switching between two variables). The functions in your test case satisfy the first definition of AnyOf but not the second IIUC. Is there a reason why the two definitions of AnyOf are conflicting?

LGTM.

int rdx = a;
for (i = 0; i < n; ++i)
  if(rdx != 3)
    rdx = b;

is equivalent to

int rdx = a != 3 ? b : a;

LGTM. Please wait to merge this and the type promotion patch together.

Yes, I agree with merging these patches at the same time.

But for the case regalloc-last-chance-recoloring-failure.ll, it uses the intirinsic @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64, this intrinsic is not supported in zvfhmin, so cannot selected is the excepted action. By example we also cannot select @llvm.riscv.vmulh.nxv1i64.i64 for ZVE64D, and any vector intrinsic for no V enable. I don't think we should do promotion for intrinsic too.
Actually target specific intrinsics basiclly comes from clang rvv-builtin. In https://reviews.llvm.org/D150253, any use of unsuportted builtin would cause a clang error. So there is no actual case will generate unsupportted intrinsic.

Add sanity check

I had reverted because of typo Mull which was supposed to be Mul. I have since recommitted with the fix.

I think that this patch and https://reviews.llvm.org/D153848 need to be committed at the same time. This will ensure that if the zvfhmin option is enabled, then we can codegen all LLVM IR.

Make getMinDepDistBytes private to DepChecker.

In D156429#4567088, @tra wrote:

When functions/lambdas are available, they would provide a better way to implement D156432 examples, IMO. I suspect it would obviate the need for !format.

In D156429#4567002, @tra wrote:

Do we really need it at all?

Are there other use cases for it besides !dump() in D156420 ?

Can we just implement some sort or !repr(value) to give us textual representation of the value and then just do "some string" # !repr(some_value) # "some other string" ? That would be sufficient for debugging purposes.

ping

In D151414#4552577, @jacquesguan wrote:

In D151414#4552130, @michaelmaitland wrote:

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

Thanks to point it. I add a check to prevent the combination to widen op when we have only zvfhmin. But these test can not pass with RUN line zvfhmin because the vf form need promotion of splat, when implement in https://reviews.llvm.org/D153848.

If I add RUN line with zvfhmin instead of zvfh llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll, the compiler gives LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13, followed by trace. Probably need to check for zvfh in performVFMADD_VLCombine? Also maybe need to check in other functions like performFADDSUB_VLCombine?

Abandoning because https://reviews.llvm.org/D156158 clarification of semantics makes this a non-issue.

Clarify how MinDepDistBytes intereacts with MaxSafeVectorWidthInBits

After taking a closer look, I can make all the changes needed in D150706.

Last update had wrong diff.

This was committed in cdffaac6ad2e0f9fcbe0ee75a5d3d78fea91cfa5. The revision didn't get appended to the commit, so this wasn't closed automatically.

Remove cast.

• Fix unneeded removal
• Rename ReadVMergeOp to mergeOp
• Rebase