[RISCV] Add Zvfhmin extension for clang

[jacquesguan]

Summary

This patch adds the Zvfhmin extension for clang.

[craig.topper]

Don’t you need to make f16 vectors legal types in the backend?

And you need to disable intrinsics for instructions that aren’t supported by Zfhmin. Like f16 vector fadd

And you also need to make the backend only allow f16 vector operations that are supported with Zfhmin.

[jacquesguan]

To enable specific EEW for specific insturction in instruction selection, I will create some parent revisions. Here is the first one. https://reviews.llvm.org/D150550

[craig.topper]

In D150253#4341545, @jacquesguan wrote:

To enable specific EEW for specific insturction in instruction selection, I will create some parent revisions. Here is the first one. https://reviews.llvm.org/D150550

@michaelmaitland was also going to be working on supporting Zvfhmin for SiFive. Maybe we can split up and share some of the work?

[jacquesguan]

In D150253#4343699, @craig.topper wrote:

In D150253#4341545, @jacquesguan wrote:

To enable specific EEW for specific insturction in instruction selection, I will create some parent revisions. Here is the first one. https://reviews.llvm.org/D150550

@michaelmaitland was also going to be working on supporting Zvfhmin for SiFive. Maybe we can split up and share some of the work?

Yes, in order to avoid duplicate work.

[jacquesguan]

make f16 vector type legal for Zvfhmin, add predicates to enable 2 convert pattern.

[jacquesguan]

@michaelmaitland , I update this revision with my local branch. May you have a look and see what missed compared with you version?

[jacquesguan]

Fix indention.

[michaelmaitland]

clang/include/clang/Basic/riscv_vector.td

2273–2279

In general, I believe that vfwcvt_f_f_v and vfncvt_f_f_w do not require Zvfhmin or Zvfh. The only time that these intrinsics require Zvfhmin or Zvfh is when the operands to these intrinsics have EEW=16.

clang/lib/Sema/Sema.cpp

2049 ↗

(On Diff #523696)

Should this output zvfhmin instead of zvfh when experimental-zvfhmin feature is not included?

[michaelmaitland]

clang/lib/Sema/Sema.cpp

2049 ↗

(On Diff #523696)

Or maybe it makes more sense to change "zvfh" to "zvfh or zvfhmin"?

[craig.topper]

Please split clang and llvm codegen into separate patches.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1018 ↗

(On Diff #523696)

This needs to be below By default everything must be expanded.

2096 ↗

(On Diff #523696)

Is this correct? This function is called by RISCVTargetTransformInfo::isLegalToVectorizeReduction, isLegalMaskedLoadStore, isLegalMaskedGatherScatter.

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

Doesn't HasStdExtZvfh already imply HasStdExtZvfhmin?

[michaelmaitland]

clang/include/clang/Basic/riscv_vector.td

2273–2279

The semantics for RequiredFeatures is Features required to enable for this builtin. Since not all types in the range require the ZvfhminOrZvfh feature, it may make sense to do some refactoring:

I think two possible solutions are:

1. to split def of vfwcvt_f_f_v and vfncvt_f_f_w by type_range and the type range x uses the RequiredFeatures
2. Use different required features for different type ranges (i.e. RequiredFeatures is a list of lists where the outer list is for each type in the range, and the inner list is the RequiredFeature for that type.)

[michaelmaitland]

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c

16

Do we need a test that checks calls to __riscv_vfwcvt_f and __riscv_vfncvt_f using type vfloat16m1_t without zvfh nor zvfhmin lead to the expected error asking for zvfh or zvfhmin?

[michaelmaitland]

In D150253#4355730, @jacquesguan wrote:

@michaelmaitland , I update this revision with my local branch. May you have a look and see what missed compared with you version?

I have left some comments on the clang side of this patch, but I think you are pretty close and have that under control.

I will take a closer look on what is left to do on the CodeGen side of things this week, and I will let you know if I have any comments and if I think there is any opportunity to collaborate here.

[jacquesguan]

Split into 2 revisions and address comment.

[jacquesguan]

https://reviews.llvm.org/D151414 this is the backend part.

clang/include/clang/Basic/riscv_vector.td

2273–2279

I split it into 2 definations.

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c

16

fp16 vector type check is in Sema/riscv-vector-float16-check.c.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1018 ↗

(On Diff #523696)

Fixed in https://reviews.llvm.org/D151414.

2096 ↗

(On Diff #523696)

Fixed in https://reviews.llvm.org/D151414.

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

The v spec doesn't metion this.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

I think the spec conveys this when it says The Zvfhmin extension depends on the Zve32f extension.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

My mistake, that says Zve32f, not Zvfh. However, the spec does say:

When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions become defined when SEW=16 and also says When the Zvfh extension is implemented, all instructions in Sections Vector Floating-Point Instructions. Since vfwcvt.f.f.v and vfncvt.f.f.w are part of Vector Floating-Point Instructions section, this is how it is implied.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

It's implemented in LLVM by this patch https://reviews.llvm.org/D150016

[jacquesguan]

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

This patch make Zvfh imply Zfhmin not Zvfhmin. I think the relation between Zvfh and Zvfhmin is just like the relation between Zfh and Zfhmin. Now Zfh doesn't imply Zfhmin, so I keep Zvfh not imply Zvfhmin.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.h

162 ↗

(On Diff #523696)

Oops. Too many extensions with similar names. Thanks.

[michaelmaitland]

LGTM.

[craig.topper]

We need to support reinterpret intrinsics so that we can load/store bf16 values.

[craig.topper]

clang/lib/Sema/SemaRISCVVectorLookup.cpp

207

You can reuse HasZvfh here

[jacquesguan]

In D150253#4381435, @craig.topper wrote:

We need to support reinterpret intrinsics so that we can load/store bf16 values.

Sorry, I don't understand your comment well. I think that change you mentioned should not be included into this revision which only support zvfhmin for clang.

[craig.topper]

In D150253#4382857, @jacquesguan wrote:

In D150253#4381435, @craig.topper wrote:

We need to support reinterpret intrinsics so that we can load/store bf16 values.

Sorry, I don't understand your comment well. I think that change you mentioned should not be included into this revision which only support zvfhmin for clang.

I think I was thinking of bfloat16. Sorry to many 16-bit float related patches lately.

[craig.topper]

LGTM

[craig.topper]

Do we need to enable these intrinsics for Zvfhmin?

vfloat16mf4_t __riscv_vle16_v_f16mf4 (const float16_t *base, size_t vl);
vfloat16mf2_t __riscv_vle16_v_f16mf2 (const float16_t *base, size_t vl);
vfloat16m1_t __riscv_vle16_v_f16m1 (const float16_t *base, size_t vl);
vfloat16m2_t __riscv_vle16_v_f16m2 (const float16_t *base, size_t vl);
vfloat16m4_t __riscv_vle16_v_f16m4 (const float16_t *base, size_t vl);
vfloat16m8_t __riscv_vle16_v_f16m8 (const float16_t *base, size_t vl);

Similar for all the other load/store intrinsics?

Also all the vreinterpret intrinsics.

And __riscv_vmerge_vvm_f16* and __riscv_vmv_v_v_f16*

They can be a separate patch.

[jacquesguan]

In D150253#4382884, @craig.topper wrote:

Do we need to enable these intrinsics for Zvfhmin?

vfloat16mf4_t __riscv_vle16_v_f16mf4 (const float16_t *base, size_t vl);
vfloat16mf2_t __riscv_vle16_v_f16mf2 (const float16_t *base, size_t vl);
vfloat16m1_t __riscv_vle16_v_f16m1 (const float16_t *base, size_t vl);
vfloat16m2_t __riscv_vle16_v_f16m2 (const float16_t *base, size_t vl);
vfloat16m4_t __riscv_vle16_v_f16m4 (const float16_t *base, size_t vl);
vfloat16m8_t __riscv_vle16_v_f16m8 (const float16_t *base, size_t vl);

Similar for all the other load/store intrinsics?

Also all the vreinterpret intrinsics.

And __riscv_vmerge_vvm_f16* and __riscv_vmv_v_v_f16*

They can be a separate patch.

Yes, I will create a new patch to do that.

[jacquesguan]

Address a comment.

[craig.topper]

The backend patch must go before the clang patch.

[jacquesguan]

Update dependency.

[eopXD]

Thank you for the patch. Few comments here.

clang/include/clang/Basic/riscv_vector.td

2274

I think using ZvfhminOrZvfh is not accurate here. By the v-spec:

When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions become defined when SEW=16.
The Zvfh extension depends on the Zve32f and Zfhmin extensions.

I think making it let RequiredFeatures = ["Zvfhmin"] would be clearer.

clang/lib/Sema/SemaRISCVVectorLookup.cpp

206

I think HasZvfhmin is a more accurate naming.

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c

21

If zvfhmin is not specified, should the compiler emit semantic error when encountering vfloat16*_t types?

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

16

This test case is already covered.

https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c#L356

[eopXD]

clang/lib/Sema/Sema.cpp

2050 ↗

(On Diff #527312)

We can remove !TI.hasFeature("experimental-zvfh") since zvfh will imply zvfhmin.

2050 ↗

(On Diff #527312)

"zvfh or zvfhmin" -> "zvfhmin"

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c

21

Sorry I missed the test case below. Please ignore this comment.

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

2274

Note that the spec says Zfhmin(no v) not Zvfhmin.

[eopXD]

clang/include/clang/Basic/riscv_vector.td

2274

My mistake. I suspect this is an oversight of the v-spec, just created an issue for this.

https://github.com/riscv/riscv-v-spec/issues/885

[jacquesguan]

clang/include/clang/Basic/riscv_vector.td

2274

Thanks for comment. I think that v-spec is in accordance with the scalar spec to some degree. Since zfh doesn't imply zfhmin, I don't think they will let zvfh imply zvfhmin.

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

16

Yes, but this test is for zvfhmin. vfncvt.c contains other convert cases not enable for zvfhmin so we can't just add a zvfhmin check.

[jacquesguan]

rebase

clang/include/clang/Basic/riscv_vector.td

 def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
 
 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
 let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
   def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
   def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
   def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
-  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
+  let RequiredFeatures = ["ZvfhminOrZvfh"] in
+    def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
+      let Name = "vfwcvt_f_f_v";
+      let IRName = "vfwcvt_f_f_v";
+      let MaskedIRName = "vfwcvt_f_f_v_mask";
+    }
 }
 
 // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
 let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
   def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
   def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
 }
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
         defm :
           RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
       let OverloadedName = "vfncvt_f" in {
         defm :
           RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvwu"]]>;
         defm :
           RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUwu"]]>;
       }
-      let OverloadedName = "vfncvt_f" in
-        defm :
-          RVVConvBuiltinSet<"vfncvt_f_f_w", "xf", [["v", "vwu"]]>;
+      let OverloadedName = "vfncvt_f" in {
+        defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>;
+        let RequiredFeatures = ["ZvfhminOrZvfh"] in
+        defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>;
+      }
     }
   }
 
   // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
   let OverloadedName = "vfcvt_x" in
     defm :
       RVVConvBuiltinSet<"vfcvt_x_f_v", "xfd", [["Iv", "Ivv"]]>;
   let OverloadedName = "vfcvt_xu" in
let OverloadedName = "vfncvt_xu" in
       defm :
         RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>;
     let OverloadedName = "vfncvt_f" in {
       defm :
         RVVConvBuiltinSet<"vfncvt_f_x_w", "csi", [["Fv", "Fvw"]]>;
       defm :
         RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUw"]]>;
     }
-    let OverloadedName = "vfncvt_f" in
-      defm :
-        RVVConvBuiltinSet<"vfncvt_f_f_w", "xf", [["v", "vw"]]>;
+    let OverloadedName = "vfncvt_f" in {
+      defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>;
+      let RequiredFeatures = ["ZvfhminOrZvfh"] in
+      defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>;
+    }
   }
 }
 }
 
 // 15. Vector Reduction Operations
 // 15.1. Vector Single-Width Integer Reduction Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand,
     MaskedPolicyScheme = HasPassthruOperand,

clang/include/clang/Support/RISCVVIntrinsicUtils.h

static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy,
                                    Policy &PolicyAttrs, bool HasFRMRoundModeOp);
 };
 
 // RVVRequire should be sync'ed with target features, but only
 // required features used in riscv_vector.td.
 enum RVVRequire : uint8_t {
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
-  RVV_REQ_Xsfvcp = 1 << 1,
+  RVV_REQ_ZvfhminOrZvfh = 1 << 1,
+  RVV_REQ_Xsfvcp = 1 << 2,
 
   LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
 };
 
 // Raw RVV intrinsic info, used to expand later.
 // This struct is highly compact for minimized code size.
 struct RVVIntrinsicRecord {
   // Intrinsic name, e.g. vadd_vv

clang/lib/Sema/SemaChecking.cpp

void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
   const TargetInfo &TI = Context.getTargetInfo();
   // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
   // least zve64x
   if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) ||
        Ty->isRVVType(/* ElementCount */ 1)) &&
       !TI.hasFeature("zve64x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
   if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
-      !TI.hasFeature("zvfh"))
-    Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfh";
+      !TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
+    Diag(Loc, diag::err_riscv_type_requires_extension, D)
+        << Ty << "zvfh or zvfhmin";
   if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
       !TI.hasFeature("zve32f"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
   if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ true) &&
       !TI.hasFeature("zve64d"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
   // Given that caller already checked isRVVType() before calling this function,
   // if we don't have at least zve32x supported, then we need to emit error.

clang/lib/Sema/SemaRISCVVectorLookup.cpp

bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                               Preprocessor &PP) override;
 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
     ArrayRef<RVVIntrinsicRecord> Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
   static const std::pair<const char *, uint8_t> FeatureCheckList[] = {
       {"64bit", RVV_REQ_RV64},
       {"xsfvcp", RVV_REQ_Xsfvcp}};
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
     // Check requirements.
     if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
           return (Record.RequiredExtensions & Item.second) == Item.second &&
                  !TI.hasFeature(Item.first);
for (unsigned int TypeRangeMaskShift = 0;
          TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);
          ++TypeRangeMaskShift) {
       unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
       BaseType = static_cast<BasicType>(BaseTypeI);
 
       if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
         continue;
 
+      if (BaseType == BasicType::Float16) {
+        if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) ==
+            RVV_REQ_ZvfhminOrZvfh) {
+          if (!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
+            continue;
+        } else if (!TI.hasFeature("zvfh")) {
+          continue;
+        }
+      }
+
       // Expanded with different LMUL.
       for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
         if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
           continue;
 
         std::optional<RVVTypes> Types =
             TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq);
 

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVF %s
+
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +zvfhmin -emit-llvm-only %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-ZVFHMIN-ERR
+
+#include <riscv_vector.h>
+
+// CHECK-ZVF-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-ZVF-NEXT:  entry:
+// CHECK-ZVF-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVF-NEXT:    ret <vscale x 4 x half> [[TMP0]]
+//
+
+// CHECK-ZVFHMIN-ERR: no matching function for call to '__riscv_vfadd'
+
+vfloat16m1_t test_vfadd_vv_f16m1(vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+  return __riscv_vfadd(op1, op2, vl);
+}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include <riscv_vector.h>
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:    ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:    ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
+  return __riscv_vfwcvt_f(src, vl);
+}

clang/test/Sema/riscv-vector-float16-check.c

 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh \
 // RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
 // REQUIRES: riscv-registered-target
 #include <riscv_vector.h>
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
-  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 }
 
-vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
-  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 }

clang/utils/TableGen/RISCVVEmitter.cpp

for (int Log2LMUL : Log2LMULList)
       Log2LMULMask |= 1 << (Log2LMUL + 3);
 
     SR.Log2LMULMask = Log2LMULMask;
 
     SR.RequiredExtensions = 0;
     for (auto RequiredFeature : RequiredFeatures) {
       RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
                                   .Case("RV64", RVV_REQ_RV64)
+                                  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
                                   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
                                   .Default(RVV_REQ_None);
       assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
       SR.RequiredExtensions |= RequireExt;
     }
 
     SR.NF = NF;
     SR.HasMasked = HasMasked;