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[RISCV] Enable more builtin for zvfhmin without zvfh

Authored by jacquesguan on Jun 1 2023, 2:03 AM.



This patch enables some fp16 vector type builtins that don't use fp arithmetic instruction for zvfhmin without zvfh.
Include following builtins:

vector load/store,
vector reinterpret,

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jacquesguan created this revision.Jun 1 2023, 2:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2023, 2:03 AM
jacquesguan requested review of this revision.Jun 1 2023, 2:03 AM
eopXD added a comment.EditedJun 1 2023, 10:44 AM

I think the topic of this patch is not accurate. The compiler already support these intrinsics with zvfh specified. Implementing zvfhmin is relaxing the implementation and let some of the intrinsics available when only zvfhmin and not zvfm is specified. So I think we can adjust the patch description a bit.

I think you may relax the extension specified, which is currently zvfh, to using zvfhmin, under the existing test cases under clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated to verify your implementation.

jacquesguan retitled this revision from [RISCV] Support more builtin for zvfhmin. to [RISCV] Enable more builtin for zvfhmin without zvfh.Aug 24 2023, 2:46 AM
jacquesguan edited the summary of this revision. (Show Details)
This revision is now accepted and ready to land.Sep 7 2023, 1:13 PM
This revision was landed with ongoing or failed builds.Sep 7 2023, 7:55 PM
This revision was automatically updated to reflect the committed changes.