[RISCV] Custom lower vector llvm.is.fpclass to vfclass.v

[liaolucy]

Summary

After D149063.
This patch adds support for both scalable and fixed-length vector.

[liaolucy]

clang-format

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1047

Isn't VT an FP type here?

4389

Why not scalable vectors?

4405

Capitalize variables names

4407

Shouldn't we be emitting an AND and SETNE with 0 like the scalar code?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll

12

The result of vfclass can only have single bit set according to the scalar documentation "Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags." So it can never equal 768.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

2031

Indent this 2 more spaces so it lines up with (vti.Vector on the previous line.

[liaolucy]

Update try to address comments.
Use AND and SETNE.
Update test case.

If the changes are correct, then it seems that this patch is not needed:
testcase:

declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32)
define <2 x i1> @isnan_v2f32(<2 x float> %x) nounwind {
  %1 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3)  ; nan
  ret <2 x i1> %1
}

Without this patch:

vsetivli        zero, 2, e32, mf2, ta, ma
vmfne.vv        v8, v8, v8
vmor.mm v0, v8, v8

with the patch, we get:

vsetivli        zero, 2, e32, mf2, ta, ma
vfclass.v       v8, v8
li      a0, 768
vand.vx v8, v8, a0
vmsne.vi        v0, v8, 0
ret

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4389

I did not find the scalable llvm.is.fpclass.
https://llvm.org/docs/LangRef.html#llvm-is-fpclass-intrinsic
It seems that this scalableintrinsic should be supported first.

[craig.topper]

In D151176#4366686, @liaolucy wrote:

Update try to address comments.
Use AND and SETNE.
Update test case.

If the changes are correct, then it seems that this patch is not needed:
testcase:

declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32)
define <2 x i1> @isnan_v2f32(<2 x float> %x) nounwind {
  %1 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3)  ; nan
  ret <2 x i1> %1
}

Without this patch:

vsetivli        zero, 2, e32, mf2, ta, ma
vmfne.vv        v8, v8, v8
vmor.mm v0, v8, v8

with the patch, we get:

vsetivli        zero, 2, e32, mf2, ta, ma
vfclass.v       v8, v8
li      a0, 768
vand.vx v8, v8, a0
vmsne.vi        v0, v8, 0
ret

The default expansion does know to create single instructions for some cases, but will probably generate worse code for mixing classes together. You should add more testing of different combinations of bits. Maybe we want to use fclass for some cases and default expansion for others.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4389

I don't think the syntax in the LangRef is an exhaustive list. Have you tried it?

[liaolucy]

1. support scalable vector
2. add more testcases

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4396

Reuse RISCVISD::FPCLASS_VL here. You can pass DAG.getRegister(RISCV::X0, XLenVT) as the VL.

4424

This is a VMSNE

[liaolucy]

Reuse RISCVISD::FPCLASS_VL
change the value name to VMSNE

[craig.topper]

LGTM

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4412

This MVT::Other result looks unnecessary. Removed in 1fea6bd8777a800af8f67e5d67afe25a713a8926

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   FDIV_VL,
   FMINNUM_VL,
   FMAXNUM_VL,
 
   // Vector unary ops with a mask as a second operand and VL as a third operand.
   FNEG_VL,
   FABS_VL,
   FSQRT_VL,
+  FCLASS_VL,
   FCOPYSIGN_VL, // Has a merge operand
   VFCVT_RTZ_X_F_VL,
   VFCVT_RTZ_XU_F_VL,
   VFCVT_X_F_VL,
   VFCVT_XU_F_VL,
   VFROUND_NOEXCEPT_VL,
   VFCVT_RM_X_F_VL,  // Has a rounding mode operand.
   VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
private:
   SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
                                              unsigned MaskOpc,
                                              unsigned VecOpc) const;
   SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
                                             SelectionDAG &DAG) const;
   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
                             bool HasMergeOp = false, bool HasMask = true) const;
+  SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
                     bool HasMergeOp = false) const;
   SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
                          unsigned VecOpc) const;
   SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
                              unsigned RISCVISDOpc) const;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

const auto SetCommonVFPActions = [&](MVT VT) {
       setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT,
                          Custom);
       // Expand various condition codes (explained above).
       setCondCodeAction(VFPCCToExpand, VT, Expand);
 
       setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal);
 
       setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND,
-                          ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT},
+                          ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT,
+                          ISD::IS_FPCLASS},
                          VT, Custom);
 
       setOperationAction(FloatingPointVecReduceOps, VT, Custom);
 
       // Expand FP operations that need libcalls.
       setOperationAction(ISD::FREM, VT, Expand);
       setOperationAction(ISD::FPOW, VT, Expand);
       setOperationAction(ISD::FCOS, VT, Expand);
if (Subtarget.useRVVForFixedLengthVectors()) {
         setOperationAction({ISD::VP_LOAD, ISD::VP_STORE,
                             ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
                             ISD::EXPERIMENTAL_VP_STRIDED_STORE, ISD::VP_GATHER,
                             ISD::VP_SCATTER},
                            VT, Custom);
 
         setOperationAction({ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV,
                             ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT,
-                            ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM},
+                            ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM,
+                            ISD::IS_FPCLASS},
                            VT, Custom);
 
         setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
 
         setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND,
                             ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT},
                            VT, Custom);
 
         setCondCodeAction(VFPCCToExpand, VT, Expand);
 
         setOperationAction(ISD::SETCC, VT, Custom);
         setOperationAction({ISD::VSELECT, ISD::SELECT}, VT, Custom);
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
   // enforce memory ordering.
   if (FenceSSID == SyncScope::SingleThread)
     // MEMBARRIER is a compiler barrier; it codegens to a no-op.
     return DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
 
   return Op;
 }
 
-static SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG,
-                               const RISCVSubtarget &Subtarget) {
+SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
+                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
   MVT VT = Op.getSimpleValueType();
   MVT XLenVT = Subtarget.getXLenVT();
   auto CNode = cast<ConstantSDNode>(Op.getOperand(1));
   unsigned Check = CNode->getZExtValue();
   unsigned TDCMask = 0;
   if (Check & fcSNan)
     TDCMask |= RISCV::FPMASK_Signaling_NaN;
SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
   if (Check & fcNegSubnormal)
     TDCMask |= RISCV::FPMASK_Negative_Subnormal;
   if (Check & fcPosZero)
     TDCMask |= RISCV::FPMASK_Positive_Zero;
   if (Check & fcNegZero)
     TDCMask |= RISCV::FPMASK_Negative_Zero;
 
   SDValue TDCMaskV = DAG.getConstant(TDCMask, DL, XLenVT);
+
+  if (VT.isVector()) {
+    SDValue Op0 = Op.getOperand(0);
+    MVT VT0 = Op.getOperand(0).getSimpleValueType();
+    MVT DstVT = VT0.changeVectorElementTypeToInteger();
+
+    if (VT.isScalableVector()) {
+      SDValue FPCLASS =
+          DAG.getNode(RISCVISD::FPCLASS, DL, DstVT, Op0, Op->getFlags());
+      SDValue AND = DAG.getNode(ISD::AND, DL, DstVT, FPCLASS,
+                                DAG.getConstant(TDCMask, DL, DstVT));
+      return DAG.getSetCC(DL, VT, AND, DAG.getConstant(0, DL, DstVT),
+                          ISD::SETNE);
+    }
+
+    MVT ContainerVT0 = getContainerForFixedLengthVector(VT0);
+    MVT ContainerVT = getContainerForFixedLengthVector(VT);
+    MVT ContainerDstVT = getContainerForFixedLengthVector(DstVT);
+    auto [Mask, VL] =
+        getDefaultVLOps(DstVT, ContainerDstVT, DL, DAG, Subtarget);
+
+    SDValue FPCLASS = DAG.getNode(
+        RISCVISD::FCLASS_VL, DL, DAG.getVTList(ContainerDstVT, MVT::Other),
+        {convertToScalableVector(ContainerVT0, Op0, DAG, Subtarget) /*Op0*/,
+         Mask, VL},
+        Op->getFlags());
+
+    TDCMaskV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerDstVT,
+                           DAG.getUNDEF(ContainerDstVT), TDCMaskV, VL);
+    SDValue AND = DAG.getNode(RISCVISD::AND_VL, DL, ContainerDstVT, FPCLASS,
+                              TDCMaskV, DAG.getUNDEF(ContainerDstVT), Mask, VL);
+
+    SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
+    SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerDstVT,
+                            DAG.getUNDEF(ContainerDstVT), SplatZero, VL);
+
+    SDValue VMSEQ = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+                                {AND, SplatZero, DAG.getCondCode(ISD::SETNE),
+                                 DAG.getUNDEF(ContainerVT), Mask, VL});
+    return convertFromScalableVector(VT, VMSEQ, DAG, Subtarget);
+  }
+
   SDValue FPCLASS = DAG.getNode(RISCVISD::FPCLASS, DL, VT, Op.getOperand(0));
   SDValue AND = DAG.getNode(ISD::AND, DL, VT, FPCLASS, TDCMaskV);
   return DAG.getSetCC(DL, VT, AND, DAG.getConstant(0, DL, XLenVT),
                       ISD::CondCode::SETNE);
 }
 
 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
                                             SelectionDAG &DAG) const {
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::INTRINSIC_WO_CHAIN:
     return LowerINTRINSIC_WO_CHAIN(Op, DAG);
   case ISD::INTRINSIC_W_CHAIN:
     return LowerINTRINSIC_W_CHAIN(Op, DAG);
   case ISD::INTRINSIC_VOID:
     return LowerINTRINSIC_VOID(Op, DAG);
   case ISD::IS_FPCLASS:
-    return LowerIS_FPCLASS(Op, DAG, Subtarget);
+    return LowerIS_FPCLASS(Op, DAG);
   case ISD::BITREVERSE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     assert(Subtarget.hasStdExtZbkb() && "Unexpected custom legalization");
     assert(Op.getOpcode() == ISD::BITREVERSE && "Unexpected opcode");
     // Expand bitreverse to a bswap(rev8) followed by brev8.
     SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Op.getOperand(0));
     return DAG.getNode(RISCVISD::BREV8, DL, VT, BSwap);
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(USUBSAT_VL)
   NODE_NAME_CASE(FADD_VL)
   NODE_NAME_CASE(FSUB_VL)
   NODE_NAME_CASE(FMUL_VL)
   NODE_NAME_CASE(FDIV_VL)
   NODE_NAME_CASE(FNEG_VL)
   NODE_NAME_CASE(FABS_VL)
   NODE_NAME_CASE(FSQRT_VL)
+  NODE_NAME_CASE(FCLASS_VL)
   NODE_NAME_CASE(VFMADD_VL)
   NODE_NAME_CASE(VFNMADD_VL)
   NODE_NAME_CASE(VFMSUB_VL)
   NODE_NAME_CASE(VFNMSUB_VL)
   NODE_NAME_CASE(VFWMADD_VL)
   NODE_NAME_CASE(VFWNMADD_VL)
   NODE_NAME_CASE(VFWMSUB_VL)
   NODE_NAME_CASE(VFWNMSUB_VL)

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 
 //===----------------------------------------------------------------------===//
 // Helpers to define the SDNode patterns.
 //===----------------------------------------------------------------------===//
 
 def rvv_vnot : PatFrag<(ops node:$in),
                        (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
 
+def riscv_vfclass : SDNode<"RISCVISD::FPCLASS",
+                             SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<0>,
+                                                  SDTCisFP<1>, SDTCisVec<1>,
+                                                  SDTCisSameSizeAs<0, 1>]>>;
+
 multiclass VPatUSLoadStoreSDNode<ValueType type,
                                  int log2sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,
                                  VReg reg_class,
                                  int sew = !shl(1, log2sew)>
 {
   defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
let Predicates = GetVTypePredicates<vti>.Predicates in {
     def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
                                      (vti.Vector (fneg vti.RegClass:$rs2)))),
               (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
                    vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
     def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
                                      (vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),
               (!cast<Instruction>("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
                    vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>;
+
+    // 14.14. Vector Floating-Point Classify Instruction
+    defvar ivti = GetIntVTypeInfo<vti>.Vti;
+    def : Pat<(ivti.Vector (riscv_vfclass (vti.Vector vti.RegClass:$rs))),
+               (!cast<Instruction>("PseudoVFCLASS_V_"#vti.LMul.MX)
+                 vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>;
    }
 }
 
 // 13.11. Vector Floating-Point MIN/MAX Instructions
 defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN">;
 defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX">;
 
 // 13.13. Vector Floating-Point Compare Instructions
 defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ,  "PseudoVMFEQ", "PseudoVMFEQ">;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def any_riscv_fmul_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl),
                          (riscv_strict_fmul_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>;
 def any_riscv_fdiv_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl),
                         [(riscv_fdiv_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl),
                          (riscv_strict_fdiv_vl node:$lhs, node:$rhs, node:$merge, node:$mask, node:$vl)]>;
 def any_riscv_fsqrt_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),
                         [(riscv_fsqrt_vl node:$src, node:$mask, node:$vl),
                          (riscv_strict_fsqrt_vl node:$src, node:$mask, node:$vl)]>;
 
+def riscv_fclass_vl : SDNode<"RISCVISD::FCLASS_VL",
+                             SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
+                                                  SDTCisFP<1>, SDTCisVec<1>,
+                                                  SDTCisSameSizeAs<0, 1>,
+                                                  SDTCVecEltisVT<2, i1>,
+                                                  SDTCisSameNumEltsAs<0, 2>,
+                                                  SDTCisVT<3, XLenVT>]>>;
+
 def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
                                               SDTCisSameAs<0, 2>,
                                               SDTCisSameAs<0, 3>,
                                               SDTCisVec<0>, SDTCisFP<0>,
                                               SDTCVecEltisVT<4, i1>,
                                               SDTCisSameNumEltsAs<0, 4>,
                                               SDTCisVT<5, XLenVT>]>;
 def riscv_vfmadd_vl  : SDNode<"RISCVISD::VFMADD_VL",  SDT_RISCVVecFMA_VL, [SDNPCommutative]>;
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
                    TAIL_AGNOSTIC)>;
 
     // Rounding without exception to implement nearbyint.
     def : Pat<(any_riscv_vfround_noexcept_vl (vti.Vector vti.RegClass:$rs1),
                                              (vti.Mask V0), VLOpFrag),
               (!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK")
                     (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
                     (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
+  
+    // 14.14. Vector Floating-Point Classify Instruction
+    def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2), 
+                               (vti.Mask true_mask), VLOpFrag),
+              (!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX)
+                 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
   }
 }
 
 foreach fvti = AllFloatVectors in {
   // Floating-point vselects:
   // 11.15. Vector Integer Merge Instructions
   // 13.15. Vector Floating-Point Merge Instruction
   let Predicates = GetVTypePredicates<fvti>.Predicates in {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
+; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
+; RUN:     -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+
+define <2 x i1> @isnan_v2f16(<2 x half> %x) {
+; CHECK-LABEL: isnan_v2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3)  ; nan
+  ret <2 x i1> %1
+}
+
+define <2 x i1> @isnan_v2f32(<2 x float> %x) {
+; CHECK-LABEL: isnan_v2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 927
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 639)
+  ret <2 x i1> %1
+}
+
+
+define <4 x i1> @isnan_v4f32(<4 x float> %x) {
+; CHECK-LABEL: isnan_v4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3)  ; nan
+  ret <4 x i1> %1
+}
+
+define <8 x i1> @isnan_v8f32(<8 x float> %x) {
+; CHECK-LABEL: isnan_v8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> %x, i32 2)
+  ret <8 x i1> %1
+}
+
+define <16 x i1> @isnan_v16f32(<16 x float> %x) {
+; CHECK-LABEL: isnan_v16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 256
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> %x, i32 1)
+  ret <16 x i1> %1
+}
+
+define <2 x i1> @isnormal_v2f64(<2 x double> %x) {
+; CHECK-LABEL: isnormal_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 129
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 516) ; 0x204 = "inf"
+  ret <2 x i1> %1
+}
+
+define <4 x i1> @isposinf_v4f64(<4 x double> %x) {
+; CHECK-LABEL: isposinf_v4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 128
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> %x, i32 512) ; 0x200 = "+inf"
+  ret <4 x i1> %1
+}
+
+define <8 x i1> @isneginf_v8f64(<8 x double> %x) {
+; CHECK-LABEL: isneginf_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> %x, i32 4) ; "-inf"
+  ret <8 x i1> %1
+}
+
+define <16 x i1> @isfinite_v16f64(<16 x double> %x) {
+; CHECK-LABEL: isfinite_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 126
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 504) ; 0x1f8 = "finite"
+  ret <16 x i1> %1
+}
+
+define <16 x i1> @isposfinite_v16f64(<16 x double> %x) {
+; CHECK-LABEL: isposfinite_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 112
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 448) ; 0x1c0 = "+finite"
+  ret <16 x i1> %1
+}
+
+define <16 x i1> @isnegfinite_v16f64(<16 x double> %x) {
+; CHECK-LABEL: isnegfinite_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 14
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 56) ; 0x38 = "-finite"
+  ret <16 x i1> %1
+}
+
+define <16 x i1> @isnotfinite_v16f64(<16 x double> %x) {
+; CHECK-LABEL: isnotfinite_v16f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 897
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 519) ; 0x207 = "inf|nan"
+  ret <16 x i1> %1
+}
+
+declare <2 x i1> @llvm.is.fpclass.v2f16(<2 x half>, i32)
+declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32)
+declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32)
+declare <8 x i1> @llvm.is.fpclass.v8f32(<8 x float>, i32)
+declare <16 x i1> @llvm.is.fpclass.v16f32(<16 x float>, i32)
+declare <2 x i1> @llvm.is.fpclass.v2f64(<2 x double>, i32)
+declare <4 x i1> @llvm.is.fpclass.v4f64(<4 x double>, i32)
+declare <8 x i1> @llvm.is.fpclass.v8f64(<8 x double>, i32)
+declare <16 x i1> @llvm.is.fpclass.v16f64(<16 x double>, i32)

llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 2 x i1> @isnan_nxv2f16(<vscale x 2 x half> %x) {
+; CHECK-LABEL: isnan_nxv2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3)  ; nan
+  ret <vscale x 2 x i1> %1
+}
+
+define <vscale x 2 x i1> @isnan_nxv2f32(<vscale x 2 x float> %x) {
+; CHECK-LABEL: isnan_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 927
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639)
+  ret <vscale x 2 x i1> %1
+}
+
+
+define <vscale x 4 x i1> @isnan_nxv4f32(<vscale x 4 x float> %x) {
+; CHECK-LABEL: isnan_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 768
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3)  ; nan
+  ret <vscale x 4 x i1> %1
+}
+
+define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {
+; CHECK-LABEL: isnan_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)
+  ret <vscale x 8 x i1> %1
+}
+
+define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {
+; CHECK-LABEL: isnan_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 256
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)
+  ret <vscale x 16 x i1> %1
+}
+
+define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x) {
+; CHECK-LABEL: isnormal_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 129
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516) ; 0x204 = "inf"
+  ret <vscale x 2 x i1> %1
+}
+
+define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {
+; CHECK-LABEL: isposinf_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 128
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"
+  ret <vscale x 4 x i1> %1
+}
+
+define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {
+; CHECK-LABEL: isneginf_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"
+  ret <vscale x 8 x i1> %1
+}
+
+define <vscale x 16 x i1> @isfinite_nxv16f32(<vscale x 16 x float> %x) {
+; CHECK-LABEL: isfinite_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 126
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 504) ; 0x1f8 = "finite"
+  ret <vscale x 16 x i1> %1
+}
+
+define <vscale x 16 x i1> @isposfinite_nxv16f32(<vscale x 16 x float> %x) {
+; CHECK-LABEL: isposfinite_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 112
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 448) ; 0x1c0 = "+finite"
+  ret <vscale x 16 x i1> %1
+}
+
+define <vscale x 16 x i1> @isnegfinite_nxv16f32(<vscale x 16 x float> %x) {
+; CHECK-LABEL: isnegfinite_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 14
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 56) ; 0x38 = "-finite"
+  ret <vscale x 16 x i1> %1
+}
+
+define <vscale x 16 x i1> @isnotfinite_nxv16f32(<vscale x 16 x float> %x) {
+; CHECK-LABEL: isnotfinite_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 897
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 519) ; 0x207 = "inf|nan"
+  ret <vscale x 16 x i1> %1
+}
+
+declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half>, i32)
+declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float>, i32)
+declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float>, i32)
+declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float>, i32)
+declare <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float>, i32)
+declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double>, i32)
+declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double>, i32)
+declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double>, i32)