llvm-tblgen: Let each emitter self-contained

[chapuni]

Summary

llvm-tblgen: Introduce llvm::TableGen::Emitter to register backends

Opt(flag, func, desc, default) registers an option into Action.

OptClass<EmitterC> is also available if EmitterC(RK).run(OS) is capable.

Action is defined as ManagedStatic<cl::opt> to guarantee to be created
when each registration of emitter is invoked.

FIXME: This may be move to llvm/include/llvm/TableGen/Main.h

llvm-tblgen: Cleanup for each EmitterClass to be invoked by uniform signature.

llvm-tblgen: Rewrite emitters to use TableGen::Emitter

Each emitter became self-contained since it has the registration of option.

[craig.topper]

llvm/utils/TableGen/AsmMatcherEmitter.cpp

4006–4007

I believe LLVM coding standards say to prefer static over anonymous namespaces. https://llvm.org/docs/CodingStandards.html#anonymous-namespaces. "make anonymous namespaces as small as possible, and only use them for class declarations."

[chapuni]

llvm/utils/TableGen/AsmMatcherEmitter.cpp

4006–4007

I have misunderstood usage of anonymous namespace. I will rework later.

I committed also c45e90cf152decb1a3dcd208273ca025e14f1b4f as a trivial change but I have noticed I did wrong thing. I will rework as well.

[chapuni]

• Avoid easy use of anonymous namespace
• Move decl of EmitDecoder()to TableGenBackends.h
• llvm::TableGen::Emitter::Opt(): Add 4th arg, isDefault
• LLVMTableGenMain() assumes TableGen::Emitter::Action is not null.

[myhsu]

In D144351#4138905, @chapuni wrote:

• Move decl of EmitDecoder()to TableGenBackends.h

maybe a dumb question: why?

llvm/utils/TableGen/TableGenBackends.h

80

nit: I believe function argument names should be camel case starting with upper case letter.

[chapuni]

• Fixup namings

[chapuni]

In D144351#4139448, @myhsu wrote:

In D144351#4138905, @chapuni wrote:

• Move decl of EmitDecoder()to TableGenBackends.h

maybe a dumb question: why?

DisassemblerEmitter.cpp declares it as ad-hoc decl extern. Since I touched around it, I have moved it to other header.
I have taken TableGenBackends.h since I thought excessive to introduce a new header like DecoderEmitter.h.

llvm/utils/TableGen/TableGenBackends.h

80

I have followed CommandLine.h.

[myhsu]

I think this patch generally LGTM. But I would love to know if plugin support or third-party extension in general is part of your roadmap, if that's the case...

FIXME: This may be move to llvm/include/llvm/TableGen/Main.h

then yeah, moving it to public header might be a good idea.

[chapuni]

In D144351#4148987, @myhsu wrote:

then yeah, moving it to public header might be a good idea.

I'm afraid if it would affect other *-tblgen. It was in public in my prototype.
I'd be happy to move it to public step-by-step.

When we could implement tblgen plugin, I wonder;

• If we took -load foo-pluigin.so, how it could be activated. I guess we should enhance TableGen::Emitter::Opt to activate myself. In my current implementation, TableGen::Emitter::Opt just registers an option.
• Or, could we enforce users to name their plugin as libtblgen-foo-option.so?

[chapuni]

• Move llvm::TableGen::Emitter to llvm/TableGen/TableGenBackend.h
• TableGen/BackGuide.rst: Modify using llvm::TableGen::Emitter`

[chapuni]

@myhsu I have exposed llvm::TableGen::Emitter into llvm/TableGen/TableGenBackend.h.

[myhsu]

LGTM Cheers

In D144351#4152342, @chapuni wrote:

In D144351#4148987, @myhsu wrote:

then yeah, moving it to public header might be a good idea.

I'm afraid if it would affect other *-tblgen. It was in public in my prototype.
I'd be happy to move it to public step-by-step.

When we could implement tblgen plugin, I wonder;

• If we took -load foo-pluigin.so, how it could be activated. I guess we should enhance TableGen::Emitter::Opt to activate myself. In my current implementation, TableGen::Emitter::Opt just registers an option.

IMHO activation upon the plugin is loaded makes more sense, because unlike using opt with legacy PassManager, there won't be multiple TG actions in a single invocation.

llvm/utils/TableGen/AsmMatcherEmitter.cpp

 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
   return Name;
 }
 
 void AsmMatcherEmitter::run(raw_ostream &OS) {
   CodeGenTarget Target(Records);
   Record *AsmParser = Target.getAsmParser();
   StringRef ClassName = AsmParser->getValueAsString("AsmParserClassName");
 
+  emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
+
   // Compute the information on the instructions to match.
   AsmMatcherInfo Info(AsmParser, Target, Records);
   Info.buildInfo();
 
   // Sort the instruction table using the partial order on classes. We use
   // stable_sort to ensure that ambiguous instructions are still
   // deterministically ordered.
   llvm::stable_sort(
#endif
   OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";
   OS << "#undef GET_MNEMONIC_CHECKER\n\n";
 
   emitMnemonicChecker(OS, Target, VariantCount,
                       HasMnemonicFirst, HasMnemonicAliases);
 
   OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
 }
 
-namespace llvm {
-
-void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
-  AsmMatcherEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<AsmMatcherEmitter>
+    X("gen-asm-matcher", "Generate assembly instruction matcher");

llvm/utils/TableGen/AsmWriterEmitter.cpp

 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
       Instructions.emplace_back(*I, i, Variant);
   }
 }
 
 void AsmWriterEmitter::run(raw_ostream &O) {
   std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
   unsigned BitsLeft = 0;
   unsigned AsmStrBits = 0;
+  emitSourceFileHeader("Assembly Writer Source Fragment", O);
   EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
   EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits);
   EmitGetRegisterName(O);
   EmitPrintAliasInstruction(O);
 }
 
-namespace llvm {
-
-void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Assembly Writer Source Fragment", OS);
-  AsmWriterEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<AsmWriterEmitter>
+    X("gen-asm-writer", "Generate assembly writer");

llvm/utils/TableGen/Attributes.cpp

 //===- Attributes.cpp - Generate attributes -------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "TableGenBackends.h"
 #include "llvm/TableGen/Record.h"
 #include <vector>
 using namespace llvm;
 
 #define DEBUG_TYPE "attr-enum"
 
 namespace {
 
 class Attributes {
 public:
   Attributes(RecordKeeper &R) : Records(R) {}
-  void emit(raw_ostream &OS);
+  void run(raw_ostream &OS);
 
 private:
   void emitTargetIndependentNames(raw_ostream &OS);
   void emitFnAttrCompatCheck(raw_ostream &OS, bool IsStringAttr);
   void emitAttributeProperties(raw_ostream &OF);
 
   RecordKeeper &Records;
 };
for (auto *A : Records.getAllDerivedDefinitions(KindName)) {
         OS << " | AttributeProperty::" << cast<DefInit>(P)->getDef()->getName();
       OS << ",\n";
     }
   }
   OS << "};\n";
   OS << "#endif\n";
 }
 
-void Attributes::emit(raw_ostream &OS) {
+void Attributes::run(raw_ostream &OS) {
   emitTargetIndependentNames(OS);
   emitFnAttrCompatCheck(OS, false);
   emitAttributeProperties(OS);
 }
 
-namespace llvm {
-
-void EmitAttributes(RecordKeeper &RK, raw_ostream &OS) {
-  Attributes(RK).emit(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<Attributes> X("gen-attrs",
+                                                 "Generate attributes");

llvm/utils/TableGen/CTagsEmitter.cpp

 //===- CTagsEmitter.cpp - Generate ctags-compatible index ------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void CTagsEmitter::run(raw_ostream &OS) {
   // Emit tags.
   llvm::sort(Tags);
   OS << "!_TAG_FILE_FORMAT\t1\t/original ctags format/\n";
   OS << "!_TAG_FILE_SORTED\t1\t/0=unsorted, 1=sorted, 2=foldcase/\n";
   for (const Tag &T : Tags)
     T.emit(OS);
 }
 
-namespace llvm {
-
-void EmitCTags(RecordKeeper &RK, raw_ostream &OS) { CTagsEmitter(RK).run(OS); }
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CTagsEmitter>
+    X("gen-ctags", "Generate ctags-compatible index");

llvm/utils/TableGen/CallingConvEmitter.cpp

 //===- CallingConvEmitter.cpp - Generate calling conventions --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 private:
   void EmitCallingConv(Record *CC, raw_ostream &O);
   void EmitAction(Record *Action, unsigned Indent, raw_ostream &O);
   void EmitArgRegisterLists(raw_ostream &O);
 };
 } // End anonymous namespace
 
 void CallingConvEmitter::run(raw_ostream &O) {
+  emitSourceFileHeader("Calling Convention Implementation Fragment", O);
+
   std::vector<Record *> CCs = Records.getAllDerivedDefinitions("CallingConv");
 
   // Emit prototypes for all of the non-custom CC's so that they can forward ref
   // each other.
   Records.startTimer("Emit prototypes");
   O << "#ifndef GET_CC_REGISTER_LISTS\n\n";
   for (Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom")) {
for (auto &Entry : AssignedSwiftRegsMap) {
     ListSeparator LS;
     for (const std::string &Reg : Registers)
       O << LS << Reg;
 
     O << " };\n";
   }
 }
 
-namespace llvm {
-
-void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Calling Convention Implementation Fragment", OS);
-  CallingConvEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CallingConvEmitter>
+    X("gen-callingconv", "Generate calling convention descriptions");

llvm/utils/TableGen/CodeEmitterGen.cpp

 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (const CodeGenInstruction *CGI : NumberedInstructions) {
     o << "    ";
     emitInstBits(o, Value);
     o << "," << '\t' << "// " << R->getName() << "\n";
   }
   o << "    UINT64_C(0)\n  };\n";
 }
 
 void CodeEmitterGen::run(raw_ostream &o) {
+  emitSourceFileHeader("Machine Code Emitter", o);
+
   CodeGenTarget Target(Records);
   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
 
   // For little-endian instruction bit encodings, reverse the bit order
   Target.reverseBitsForLittleEndianEncoding();
 
   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
     Target.getInstructionsByEnumValue();
if (any_of(NumberedInstructions, [](const CodeGenInstruction *CGI) {
     else
       o << "  return Value;\n";
     o << "}\n\n";
   }
 }
 
 } // end anonymous namespace
 
-namespace llvm {
-
-void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Machine Code Emitter", OS);
-  CodeEmitterGen(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<CodeEmitterGen>
+    X("gen-emitter", "Generate machine code emitter");

llvm/utils/TableGen/CompressInstEmitter.cpp

 //===-------- CompressInstEmitter.cpp - Generator for Compression ---------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 // CompressInstEmitter implements a tablegen-driven CompressPat based
 // Instruction Compression mechanism.
void CompressInstEmitter::run(raw_ostream &o) {
   // Generate compressInst() function.
   emitCompressInstEmitter(o, EmitterType::Compress);
   // Generate uncompressInst() function.
   emitCompressInstEmitter(o, EmitterType::Uncompress);
   // Generate isCompressibleInst() function.
   emitCompressInstEmitter(o, EmitterType::CheckCompress);
 }
 
-namespace llvm {
-
-void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS) {
-  CompressInstEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<CompressInstEmitter>
+    X("gen-compress-inst-emitter", "Generate RISCV compressed instructions.");

llvm/utils/TableGen/DAGISelEmitter.cpp

 //===- DAGISelEmitter.cpp - Generate an instruction selector --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool operator()(const PatternToMatch *LHS, const PatternToMatch *RHS) {
     // std::stable_sort with this predicate.
     return LHS->getID() < RHS->getID();
   }
 };
 } // End anonymous namespace
 
 
 void DAGISelEmitter::run(raw_ostream &OS) {
+  Records.startTimer("Parse patterns");
   emitSourceFileHeader("DAG Instruction Selector for the " +
                        CGP.getTargetInfo().getName().str() + " target", OS);
 
   OS << "// *** NOTE: This file is #included into the middle of the target\n"
      << "// *** instruction selector class.  These functions are really "
      << "methods.\n\n";
 
   OS << "// If GET_DAGISEL_DECL is #defined with any value, only function\n"
void DAGISelEmitter::run(raw_ostream &OS) {
   OptimizeMatcher(TheMatcher, CGP);
 
   //Matcher->dump();
 
   Records.startTimer("Emit matcher table");
   EmitMatcherTable(TheMatcher.get(), CGP, OS);
 }
 
-namespace llvm {
-
-void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS) {
-  RK.startTimer("Parse patterns");
-  DAGISelEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<DAGISelEmitter>
+    X("gen-dag-isel", "Generate a DAG instruction selector");

llvm/utils/TableGen/DFAEmitter.cpp

 //===- DFAEmitter.cpp - Finite state automaton emitter --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
else if (const auto *S = std::get_if<std::string>(&SingleAction))
       OS << '"' << *S << '"';
     else
       OS << std::get<unsigned>(SingleAction);
   }
   if (AT.size() > 1)
     OS << ")";
 }
 
-namespace llvm {
-
-void EmitAutomata(RecordKeeper &RK, raw_ostream &OS) {
-  AutomatonEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<AutomatonEmitter>
+    X("gen-automata", "Generate generic automata");

llvm/utils/TableGen/DFAPacketizerEmitter.cpp

 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
ScheduleClasses.push_back(
         {ItineraryIdx, Idx++, UniqueResources.insert(Resources), Resources});
   }
 }
 
 //
 // Run the worklist algorithm to generate the DFA.
 //
 void DFAPacketizerEmitter::run(raw_ostream &OS) {
+  emitSourceFileHeader("Target DFA Packetizer Tables", OS);
   OS << "\n"
      << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
   OS << "namespace llvm {\n";
 
   CodeGenTarget CGT(Records);
   CodeGenSchedModels CGS(Records, CGT);
 
   std::unordered_map<std::string, std::vector<const CodeGenProcModel *>>
OS << "DFAPacketizer *" << SubTargetClassName << "::"
      << "  unsigned ProcResIdxNum = " << TargetAndDFAName
      << "ProcResourceIndexStart[IID->SchedModel.ProcID + 1] - "
         "ProcResIdxStart;\n"
      << "  return new DFAPacketizer(IID, A, {&" << TargetAndDFAName
      << "ResourceIndices[ProcResIdxStart], ProcResIdxNum});\n"
      << "\n}\n\n";
 }
 
-namespace llvm {
-
-void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Target DFA Packetizer Tables", OS);
-  DFAPacketizerEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<DFAPacketizerEmitter>
+    X("gen-dfa-packetizer", "Generate DFA Packetizer for VLIW targets");

llvm/utils/TableGen/DXILEmitter.cpp

 //===- DXILEmitter.cpp - DXIL operation Emitter ---------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
Parameters.emit(
       },
       "ParameterKind::INVALID");
   OS << "  };\n\n";
   OS << "  unsigned Index = Prop.ParameterTableOffset;\n";
   OS << "  return DXILOpParameterKindTable + Index;\n";
   OS << "}\n ";
 }
 
-namespace llvm {
-
-void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
   std::vector<Record *> Ops = Records.getAllDerivedDefinitions("dxil_op");
   OS << "// Generated code, do not edit.\n";
   OS << "\n";
 
   std::vector<DXILOperationData> DXILOps;
   DXILOps.reserve(Ops.size());
   for (auto *Record : Ops) {
     DXILOps.emplace_back(DXILOperationData(Record));
static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
 
   OS << "#ifdef DXIL_OP_OPERATION_TABLE\n";
   emitDXILOperationTable(DXILOps, OS);
   OS << "#endif\n\n";
 
   OS << "\n";
 }
 
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
+                                "Generate DXIL operation information");

llvm/utils/TableGen/DecoderEmitter.cpp

 //===---------------- DecoderEmitter.cpp - Decoder Generator --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // It contains the tablegen backend that emits the decoder functions for
 // targets with fixed/variable length instruction set.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenHwModes.h"
 #include "CodeGenInstruction.h"
 #include "CodeGenTarget.h"
 #include "InfoByHwMode.h"
+#include "TableGenBackends.h"
 #include "VarLenCodeEmitterGen.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/CachedHashString.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/Statistic.h"

llvm/utils/TableGen/DirectiveEmitter.cpp

 //===- DirectiveEmitter.cpp - Directive Language Emitter ------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool DirectiveLanguage::HasValidityErrors() const {
   if (getDirectiveLanguages().size() != 1) {
     PrintFatalError("A single definition of DirectiveLanguage is needed.");
     return true;
   }
 
   return HasDuplicateClausesInDirectives(getDirectives());
 }
 
-namespace llvm {
-
 // Generate the declaration section for the enumeration in the directive
 // language
-void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
   const auto DirLang = DirectiveLanguage{Records};
   if (DirLang.HasValidityErrors())
     return;
 
   OS << "#ifndef LLVM_" << DirLang.getName() << "_INC\n";
   OS << "#define LLVM_" << DirLang.getName() << "_INC\n";
 
   if (DirLang.hasEnableBitmaskEnumInNamespace())
static void EmitDirectivesDecl(RecordKeeper &Records, raw_ostream &OS) {
   for (auto Ns : llvm::reverse(Namespaces))
     OS << "} // namespace " << Ns << "\n";
 
   OS << "} // namespace llvm\n";
 
   OS << "#endif // LLVM_" << DirLang.getName() << "_INC\n";
 }
 
-} // namespace llvm
-
 // Generate function implementation for get<Enum>Name(StringRef Str)
 static void GenerateGetName(const std::vector<Record *> &Records,
                             raw_ostream &OS, StringRef Enum,
                             const DirectiveLanguage &DirLang,
                             StringRef Prefix) {
   OS << "\n";
   OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get"
      << DirLang.getName() << Enum << "Name(" << Enum << " Kind) {\n";
void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang,
 
   // get<ClauseVal>Kind(StringRef Str)
   GenerateGetKindClauseVal(DirLang, OS);
 
   // isAllowedClauseForDirective(Directive D, Clause C, unsigned Version)
   GenerateIsAllowedClause(DirLang, OS);
 }
 
-namespace llvm {
-
 // Generate the implemenation section for the enumeration in the directive
 // language.
-void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
   const auto DirLang = DirectiveLanguage{Records};
   if (DirLang.HasValidityErrors())
     return;
 
   EmitDirectivesFlangImpl(DirLang, OS);
 
   GenerateClauseClassMacro(DirLang, OS);
 
   EmitDirectivesBasicImpl(DirLang, OS);
 }
 
-} // namespace llvm
+static TableGen::Emitter::Opt
+    X("gen-directive-decl", EmitDirectivesDecl,
+      "Generate directive related declaration code (header file)");
+
+static TableGen::Emitter::Opt
+    Y("gen-directive-impl", EmitDirectivesImpl,
+      "Generate directive related implementation code");

llvm/utils/TableGen/DisassemblerEmitter.cpp

 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 ///   ModR/M values are valid for a particular instruction.  These are used to
 ///   populate ModRMDecisions.
 /// X86RecognizableInstr.h contains the interface for a single instruction,
 ///   which knows how to translate itself from a CodeGenInstruction and provide
 ///   the information necessary for integration into the tables.
 /// X86RecognizableInstr.cpp contains the implementation for a single
 ///   instruction.
 
-namespace llvm {
-
-extern void EmitDecoder(RecordKeeper &RK, raw_ostream &OS,
-                        const std::string &PredicateNamespace);
-
-void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
   CodeGenTarget Target(Records);
   emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS);
 
   // X86 uses a custom disassembler.
   if (Target.getName() == "X86") {
     DisassemblerTables Tables;
 
     ArrayRef<const CodeGenInstruction*> numberedInstructions =
static void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
   }
 
   std::string PredicateNamespace = std::string(Target.getName());
   if (PredicateNamespace == "Thumb")
     PredicateNamespace = "ARM";
   EmitDecoder(Records, OS, PredicateNamespace);
 }
 
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler,
+                                "Generate disassembler");

llvm/utils/TableGen/ExegesisEmitter.cpp

 //===- ExegesisEmitter.cpp - Generate exegesis target data ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 void ExegesisEmitter::run(raw_ostream &OS) const {
   emitSourceFileHeader("Exegesis Tables", OS);
   emitPfmCounters(OS);
   emitPfmCountersLookupTable(OS);
 }
 
 } // end anonymous namespace
 
-namespace llvm {
-
-void EmitExegesis(RecordKeeper &RK, raw_ostream &OS) {
-  ExegesisEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<ExegesisEmitter>
+    X("gen-exegesis", "Generate llvm-exegesis tables");

llvm/utils/TableGen/FastISelEmitter.cpp

 ///===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (const auto &SimplePattern : SimplePatterns) {
     OS << "  }\n";
     OS << "}\n";
     OS << "\n";
   }
 
   // TODO: SignaturesWithConstantForms should be empty here.
 }
 
-namespace llvm {
-
-void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenDAGPatterns CGP(RK);
   const CodeGenTarget &Target = CGP.getTargetInfo();
   emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
                        Target.getName().str() + " target", OS);
 
   // Determine the target's namespace name.
   StringRef InstNS = Target.getInstNamespace();
   assert(!InstNS.empty() && "Can't determine target-specific namespace!");
 
   FastISelMap F(InstNS);
   F.collectPatterns(CGP);
   F.printImmediatePredicates(OS);
   F.printFunctionDefinitions(OS);
 }
 
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-fast-isel", EmitFastISel,
+                                "Generate a \"fast\" instruction selector");

llvm/utils/TableGen/GICombinerEmitter.cpp

 //===- GlobalCombinerEmitter.cpp - Generate a combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
OS << "\n  return false;\n"
      << "}\n"
      << "#endif // ifdef " << Name.upper() << "_GENCOMBINERHELPER_CPP\n";
 }
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 
-namespace llvm {
-void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenTarget Target(RK);
   emitSourceFileHeader("Global Combiner", OS);
 
   if (SelectedCombiners.empty())
     PrintFatalError("No combiners selected with -combiners");
   for (const auto &Combiner : SelectedCombiners) {
     Record *CombinerDef = RK.getDef(Combiner);
     if (!CombinerDef)
       PrintFatalError("Could not find " + Combiner);
     GICombinerEmitter(RK, Target, Combiner, CombinerDef).run(OS);
   }
   NumPatternTotalStatistic = NumPatternTotal;
 }
 
-} // namespace llvm
+static TableGen::Emitter::Opt X("gen-global-isel-combiner", EmitGICombiner,
+                                "Generate GlobalISel combiner");

llvm/utils/TableGen/GlobalISelEmitter.cpp

 //===- GlobalISelEmitter.cpp - Generate an instruction selector -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 }
 
 unsigned OperandMatcher::getInsnVarID() const { return Insn.getInsnVarID(); }
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 
-namespace llvm {
-void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS) {
-  GlobalISelEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<GlobalISelEmitter>
+    X("gen-global-isel", "Generate GlobalISel selector");

llvm/utils/TableGen/InstrDocsEmitter.cpp

 //===- InstrDocsEmitter.cpp - Opcode Documentation Generator --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (char C : Str) {
     // Underscore at the end of a line has a special meaning in rst.
     case '_': Result += "\\_"; break;
     default: Result += C;
     }
   }
   return Result;
 }
 
-namespace llvm {
-
-void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenDAGPatterns CDP(RK);
   CodeGenTarget &Target = CDP.getTargetInfo();
   unsigned VariantCount = Target.getAsmParserVariantCount();
 
   // Page title.
   std::string Title = std::string(Target.getName());
   Title += " Instructions";
   writeTitle(Title, OS);
if (!Predicates.empty()) {
       ListSeparator LS;
       for (Record *P : Predicates)
         OS << LS << "``" << P->getName() << "``";
       OS << "\n\n";
     }
   }
 }
 
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-instr-docs", EmitInstrDocs,
+                                "Generate instruction documentation");

llvm/utils/TableGen/InstrInfoEmitter.cpp

 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
   OS << "  };\n";
   OS << "} // end namespace Sched\n";
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
 
   OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
 }
 
-namespace llvm {
-
-void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
   RK.startTimer("Analyze DAG patterns");
   InstrInfoEmitter(RK).run(OS);
   RK.startTimer("Emit map table");
   EmitMapTable(RK, OS);
 }
 
-} // end namespace llvm
+static TableGen::Emitter::Opt X("gen-instr-info", EmitInstrInfo,
+                                "Generate instruction descriptions");

llvm/utils/TableGen/IntrinsicEmitter.cpp

 //===- IntrinsicEmitter.cpp - Generate intrinsic information --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (auto &I : BuiltinMap) {
     OS << "  }\n";
   }
   OS << "  return ";
   OS << "Intrinsic::not_intrinsic;\n";
   OS << "}\n";
   OS << "#endif\n\n";
 }
 
-void llvm::EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS) {
+static void EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS) {
   IntrinsicEmitter(RK).run(OS, /*Enums=*/true);
 }
 
-void llvm::EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS) {
+static TableGen::Emitter::Opt X("gen-intrinsic-enums", EmitIntrinsicEnums,
+                                "Generate intrinsic enums");
+
+static void EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS) {
   IntrinsicEmitter(RK).run(OS, /*Enums=*/false);
 }
+
+static TableGen::Emitter::Opt Y("gen-intrinsic-impl", EmitIntrinsicImpl,
+                                "Generate intrinsic information");

llvm/utils/TableGen/OptParserEmitter.cpp

 //===- OptParserEmitter.cpp - Table Driven Command Line Parsing -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
static MarshallingInfo createMarshallingInfo(const Record &R) {
   }
 
   return Ret;
 }
 
 /// OptParserEmitter - This tablegen backend takes an input .td file
 /// describing a list of options and emits a data structure for parsing and
 /// working with those options when given an input command line.
-namespace llvm {
-void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   // Get the option groups and options.
   const std::vector<Record*> &Groups =
     Records.getAllDerivedDefinitions("OptionGroup");
   std::vector<Record*> Opts = Records.getAllDerivedDefinitions("Option");
 
   emitSourceFileHeader("Option Parsing Definitions", OS);
 
   array_pod_sort(Opts.begin(), Opts.end(), CompareOptionRecords);
static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "static const unsigned SimpleEnumValueTablesSize = "
         "std::size(SimpleEnumValueTables);\n";
 
   OS << "#endif // SIMPLE_ENUM_VALUE_TABLE\n";
   OS << "\n";
 
   OS << "\n";
 }
-} // end namespace llvm
+
+static TableGen::Emitter::Opt X("gen-opt-parser-defs", EmitOptParser,
+                                "Generate option definitions");

llvm/utils/TableGen/OptRSTEmitter.cpp

 //===- OptParserEmitter.cpp - Table Driven Command Line Parsing -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "OptEmitter.h"
 #include "TableGenBackends.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/TableGen/Record.h"
 
 using namespace llvm;
 
 /// OptParserEmitter - This tablegen backend takes an input .td file
 /// describing a list of options and emits a RST man page.
-namespace llvm {
-void EmitOptRST(RecordKeeper &Records, raw_ostream &OS) {
+static void EmitOptRST(RecordKeeper &Records, raw_ostream &OS) {
   llvm::StringMap<std::vector<Record *>> OptionsByGroup;
   std::vector<Record *> OptionsWithoutGroup;
 
   // Get the options.
   std::vector<Record *> Opts = Records.getAllDerivedDefinitions("Option");
   array_pod_sort(Opts.begin(), Opts.end(), CompareOptionRecords);
 
   // Get the option groups.
for (Record *R : KV.getValue()) {
       if (!HelpText.empty()) {
         OS << ' ';
         OS.write_escaped(HelpText);
         OS << "\n\n";
       }
     }
   }
 }
-} // end namespace llvm
+
+static TableGen::Emitter::Opt X("gen-opt-rst", EmitOptRST,
+                                "Generate option RST");

llvm/utils/TableGen/PseudoLoweringEmitter.cpp

 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
     evaluateExpansion(Insts[i]);
 
   // Generate expansion code to lower the pseudo to an MCInst of the real
   // instruction.
   Records.startTimer("Emit expansion code");
   emitLoweringEmitter(o);
 }
 
-namespace llvm {
-
-void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
-  PseudoLoweringEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<PseudoLoweringEmitter>
+    X("gen-pseudo-lowering", "Generate pseudo instruction lowering");

llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISCV CPUs -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static std::string getMArch(const Record &Rec) {
   if (!ISAInfo)
     report_fatal_error("Invalid features");
 
   // RISCVISAInfo::toString will generate a march string with all the extensions
   // we have added to it.
   return (*ISAInfo)->toString();
 }
 
-void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
   OS << "#ifndef PROC\n"
      << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
      << "#endif\n\n";
 
   OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
   // Iterate on all definition records.
   for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
     std::string MArch = Rec->getValueAsString("DefaultMarch").str();
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
   for (const Record *Rec :
        RK.getAllDerivedDefinitions("RISCVTuneProcessorModel")) {
     OS << "TUNE_PROC(" << Rec->getName() << ", "
        << "\"" << Rec->getValueAsString("Name") << "\")\n";
   }
 
   OS << "\n#undef TUNE_PROC\n";
 }
+
+static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
+                                "Generate the list of CPU for RISCV");

llvm/utils/TableGen/RegisterBankEmitter.cpp

 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RegisterBankEmitter::run(raw_ostream &OS) {
   emitBaseClassDefinition(OS, TargetName, Banks);
   OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"
      << "#ifdef GET_TARGET_REGBANK_IMPL\n"
      << "#undef GET_TARGET_REGBANK_IMPL\n";
   emitBaseClassImplementation(OS, TargetName, Banks);
   OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
 }
 
-namespace llvm {
-
-void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS) {
-  RegisterBankEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<RegisterBankEmitter>
+    X("gen-register-bank", "Generate registers bank descriptions");

llvm/utils/TableGen/RegisterInfoEmitter.cpp

 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (const CodeGenRegister &R : RegBank.getRegisters()) {
     OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n';
     for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) {
       OS << "\tSubReg " << P.first->getName()
          << " = " << P.second->getName() << '\n';
     }
   }
 }
 
-namespace llvm {
-
-void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
-  RegisterInfoEmitter(RK).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<RegisterInfoEmitter>
+    X("gen-register-info", "Generate registers and register classes info");

llvm/utils/TableGen/SearchableTableEmitter.cpp

 //===- SearchableTableEmitter.cpp - Generate efficiently searchable tables -==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (const auto &Table : Tables)
     emitGenericTable(*Table, OS);
 
   // Put all #undefs last, to allow multiple sections guarded by the same
   // define.
   for (const auto &Guard : PreprocessorGuards)
     OS << "#undef " << Guard << "\n";
 }
 
-namespace llvm {
-
-void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS) {
-  SearchableTableEmitter(RK).run(OS);
-}
-
-} // namespace llvm
+static TableGen::Emitter::OptClass<SearchableTableEmitter>
+    X("gen-searchable-tables", "Generate generic binary-searchable table");

llvm/utils/TableGen/SubtargetEmitter.cpp

 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
class SubtargetEmitter {
 
   struct LessWriteProcResources {
     bool operator()(const MCWriteProcResEntry &LHS,
                     const MCWriteProcResEntry &RHS) {
       return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
     }
   };
 
-  const CodeGenTarget &TGT;
+  CodeGenTarget TGT;
   RecordKeeper &Records;
   CodeGenSchedModels &SchedModels;
   std::string Target;
 
   void Enumeration(raw_ostream &OS, DenseMap<Record *, unsigned> &FeatureMap);
   void EmitSubtargetInfoMacroCalls(raw_ostream &OS);
   unsigned FeatureKeyValues(raw_ostream &OS,
                             const DenseMap<Record *, unsigned> &FeatureMap);
class SubtargetEmitter {
   void emitGenMCSubtargetInfo(raw_ostream &OS);
   void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
 
   void EmitSchedModel(raw_ostream &OS);
   void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
   void ParseFeaturesFunction(raw_ostream &OS);
 
 public:
-  SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT)
-      : TGT(TGT), Records(R), SchedModels(TGT.getSchedModels()),
+  SubtargetEmitter(RecordKeeper &R)
+      : TGT(R), Records(R), SchedModels(TGT.getSchedModels()),
         Target(TGT.getName()) {}
 
   void run(raw_ostream &o);
 };
 
 } // end anonymous namespace
 
 //
#endif
 
   OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
 
   EmitMCInstrAnalysisPredicateFunctions(OS);
 }
 
-namespace llvm {
-
-void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
-  CodeGenTarget CGTarget(RK);
-  SubtargetEmitter(RK, CGTarget).run(OS);
-}
-
-} // end namespace llvm
+static TableGen::Emitter::OptClass<SubtargetEmitter>
+    X("gen-subtarget", "Generate subtarget enumerations");

llvm/utils/TableGen/TableGen.cpp

 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the main function for LLVM's TableGen.
 //
 //===----------------------------------------------------------------------===//
 
 #include "TableGenBackends.h" // Declares all backends.
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/InitLLVM.h"
+#include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Main.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/SetTheory.h"
 #include <cassert>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 
-enum ActionType {
-  PrintRecords,
-  PrintDetailedRecords,
-  NullBackend,
-  DumpJSON,
-  GenEmitter,
-  GenRegisterInfo,
-  GenInstrInfo,
-  GenInstrDocs,
-  GenAsmWriter,
-  GenAsmMatcher,
-  GenDisassembler,
-  GenPseudoLowering,
-  GenCompressInst,
-  GenCallingConv,
-  GenDAGISel,
-  GenDFAPacketizer,
-  GenFastISel,
-  GenSubtarget,
-  GenIntrinsicEnums,
-  GenIntrinsicImpl,
-  PrintEnums,
-  PrintSets,
-  GenOptParserDefs,
-  GenOptRST,
-  GenCTags,
-  GenAttributes,
-  GenSearchableTables,
-  GenGlobalISel,
-  GenGICombiner,
-  GenX86EVEX2VEXTables,
-  GenX86FoldTables,
-  GenX86MnemonicTables,
-  GenRegisterBank,
-  GenExegesis,
-  GenAutomata,
-  GenDirectivesEnumDecl,
-  GenDirectivesEnumImpl,
-  GenDXILOperation,
-  GenRISCVTargetDef,
-};
-
 namespace llvm {
 cl::opt<bool> EmitLongStrLiterals(
     "long-string-literals",
     cl::desc("when emitting large string tables, prefer string literals over "
              "comma-separated char literals. This can be a readability and "
              "compile-time performance win, but upsets some compilers"),
     cl::Hidden, cl::init(true));
 } // end namespace llvm
 
+namespace llvm {
+namespace TableGen {
+namespace Emitter {
+ManagedStatic<cl::opt<FnT>, OptCreatorT> Action;
+void *OptCreatorT::call() {
+  return new cl::opt<FnT>(cl::desc("Action to perform:"));
+}
+} // namespace Emitter
+} // namespace TableGen
+} // namespace llvm
+
 namespace {
-cl::opt<ActionType> Action(
-    cl::desc("Action to perform:"),
-    cl::values(
-        clEnumValN(PrintRecords, "print-records",
-                   "Print all records to stdout (default)"),
-        clEnumValN(PrintDetailedRecords, "print-detailed-records",
-                   "Print full details of all records to stdout"),
-        clEnumValN(NullBackend, "null-backend",
-                   "Do nothing after parsing (useful for timing)"),
-        clEnumValN(DumpJSON, "dump-json",
-                   "Dump all records as machine-readable JSON"),
-        clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
-        clEnumValN(GenRegisterInfo, "gen-register-info",
-                   "Generate registers and register classes info"),
-        clEnumValN(GenInstrInfo, "gen-instr-info",
-                   "Generate instruction descriptions"),
-        clEnumValN(GenInstrDocs, "gen-instr-docs",
-                   "Generate instruction documentation"),
-        clEnumValN(GenCallingConv, "gen-callingconv",
-                   "Generate calling convention descriptions"),
-        clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"),
-        clEnumValN(GenDisassembler, "gen-disassembler",
-                   "Generate disassembler"),
-        clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
-                   "Generate pseudo instruction lowering"),
-        clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
-                   "Generate RISCV compressed instructions."),
-        clEnumValN(GenAsmMatcher, "gen-asm-matcher",
-                   "Generate assembly instruction matcher"),
-        clEnumValN(GenDAGISel, "gen-dag-isel",
-                   "Generate a DAG instruction selector"),
-        clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
-                   "Generate DFA Packetizer for VLIW targets"),
-        clEnumValN(GenFastISel, "gen-fast-isel",
-                   "Generate a \"fast\" instruction selector"),
-        clEnumValN(GenSubtarget, "gen-subtarget",
-                   "Generate subtarget enumerations"),
-        clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
-                   "Generate intrinsic enums"),
-        clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
-                   "Generate intrinsic information"),
-        clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"),
-        clEnumValN(PrintSets, "print-sets",
-                   "Print expanded sets for testing DAG exprs"),
-        clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
-                   "Generate option definitions"),
-        clEnumValN(GenOptRST, "gen-opt-rst", "Generate option RST"),
-        clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"),
-        clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"),
-        clEnumValN(GenSearchableTables, "gen-searchable-tables",
-                   "Generate generic binary-searchable table"),
-        clEnumValN(GenGlobalISel, "gen-global-isel",
-                   "Generate GlobalISel selector"),
-        clEnumValN(GenGICombiner, "gen-global-isel-combiner",
-                   "Generate GlobalISel combiner"),
-        clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
-                   "Generate X86 EVEX to VEX compress tables"),
-        clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
-                   "Generate X86 fold tables"),
-        clEnumValN(GenX86MnemonicTables, "gen-x86-mnemonic-tables",
-                   "Generate X86 mnemonic tables"),
-        clEnumValN(GenRegisterBank, "gen-register-bank",
-                   "Generate registers bank descriptions"),
-        clEnumValN(GenExegesis, "gen-exegesis",
-                   "Generate llvm-exegesis tables"),
-        clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
-        clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
-                   "Generate directive related declaration code (header file)"),
-        clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
-                   "Generate directive related implementation code"),
-        clEnumValN(GenDXILOperation, "gen-dxil-operation",
-                   "Generate DXIL operation information"),
-        clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
-                   "Generate the list of CPU for RISCV")));
+
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
-bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
-  switch (Action) {
-  case PrintRecords:
-    OS << Records;              // No argument, dump all contents
-    break;
-  case PrintDetailedRecords:
-    EmitDetailedRecords(Records, OS);
-    break;
-  case NullBackend:             // No backend at all.
-    break;
-  case DumpJSON:
-    EmitJSON(Records, OS);
-    break;
-  case GenEmitter:
-    EmitCodeEmitter(Records, OS);
-    break;
-  case GenRegisterInfo:
-    EmitRegisterInfo(Records, OS);
-    break;
-  case GenInstrInfo:
-    EmitInstrInfo(Records, OS);
-    break;
-  case GenInstrDocs:
-    EmitInstrDocs(Records, OS);
-    break;
-  case GenCallingConv:
-    EmitCallingConv(Records, OS);
-    break;
-  case GenAsmWriter:
-    EmitAsmWriter(Records, OS);
-    break;
-  case GenAsmMatcher:
-    EmitAsmMatcher(Records, OS);
-    break;
-  case GenDisassembler:
-    EmitDisassembler(Records, OS);
-    break;
-  case GenPseudoLowering:
-    EmitPseudoLowering(Records, OS);
-    break;
-  case GenCompressInst:
-    EmitCompressInst(Records, OS);
-    break;
-  case GenDAGISel:
-    EmitDAGISel(Records, OS);
-    break;
-  case GenDFAPacketizer:
-    EmitDFAPacketizer(Records, OS);
-    break;
-  case GenFastISel:
-    EmitFastISel(Records, OS);
-    break;
-  case GenSubtarget:
-    EmitSubtarget(Records, OS);
-    break;
-  case GenIntrinsicEnums:
-    EmitIntrinsicEnums(Records, OS);
-    break;
-  case GenIntrinsicImpl:
-    EmitIntrinsicImpl(Records, OS);
-    break;
-  case GenOptParserDefs:
-    EmitOptParser(Records, OS);
-    break;
-  case GenOptRST:
-    EmitOptRST(Records, OS);
-    break;
-  case PrintEnums: {
-    for (Record *Rec : Records.getAllDerivedDefinitions(Class))
-      OS << Rec->getName() << ", ";
-    OS << "\n";
-    break;
-  }
-  case PrintSets:
-  {
-    SetTheory Sets;
-    Sets.addFieldExpander("Set", "Elements");
-    for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
-      OS << Rec->getName() << " = [";
-      const std::vector<Record*> *Elts = Sets.expand(Rec);
-      assert(Elts && "Couldn't expand Set instance");
-      for (Record *Elt : *Elts)
-        OS << ' ' << Elt->getName();
-      OS << " ]\n";
-    }
-    break;
-  }
-  case GenCTags:
-    EmitCTags(Records, OS);
-    break;
-  case GenAttributes:
-    EmitAttributes(Records, OS);
-    break;
-  case GenSearchableTables:
-    EmitSearchableTables(Records, OS);
-    break;
-  case GenGlobalISel:
-    EmitGlobalISel(Records, OS);
-    break;
-  case GenGICombiner:
-    EmitGICombiner(Records, OS);
-    break;
-  case GenRegisterBank:
-    EmitRegisterBank(Records, OS);
-    break;
-  case GenX86EVEX2VEXTables:
-    EmitX86EVEX2VEXTables(Records, OS);
-    break;
-  case GenX86MnemonicTables:
-    EmitX86MnemonicTables(Records, OS);
-    break;
-  case GenX86FoldTables:
-    EmitX86FoldTables(Records, OS);
-    break;
-  case GenExegesis:
-    EmitExegesis(Records, OS);
-    break;
-  case GenAutomata:
-    EmitAutomata(Records, OS);
-    break;
-  case GenDirectivesEnumDecl:
-    EmitDirectivesDecl(Records, OS);
-    break;
-  case GenDirectivesEnumImpl:
-    EmitDirectivesImpl(Records, OS);
-    break;
-  case GenDXILOperation:
-    EmitDXILOperation(Records, OS);
-    break;
-  case GenRISCVTargetDef:
-    EmitRISCVTargetDef(Records, OS);
-    break;
-  }
+void PrintRecords(RecordKeeper &Records, raw_ostream &OS) {
+  OS << Records; // No argument, dump all contents
+}
+
+void PrintEnums(RecordKeeper &Records, raw_ostream &OS) {
+
+void PrintSets(RecordKeeper &Records, raw_ostream &OS) {
+    const std::vector<Record *> *Elts = Sets.expand(Rec);
 
+bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
+  TableGen::Emitter::FnT ActionFn = TableGen::Emitter::Action->getValue();
+  assert(ActionFn != nullptr);
+  ActionFn(Records, OS);
   return false;
 }
-}
+
+TableGen::Emitter::Opt X[] = {
+    {"print-records", PrintRecords, "Print all records to stdout (default)",
+     true},
+    {"print-detailed-records", EmitDetailedRecords,
+     "Print full details of all records to stdout"},
+    {"null-backend", [](RecordKeeper &Records, raw_ostream &OS) {},
+     "Do nothing after parsing (useful for timing)"},
+    {"dump-json", EmitJSON, "Dump all records as machine-readable JSON"},
+    {"print-enums", PrintEnums, "Print enum values for a class"},
+    {"print-sets", PrintSets, "Print expanded sets for testing DAG exprs"},
+};
+
+} // namespace
 
 int main(int argc, char **argv) {
   InitLLVM X(argc, argv);
   cl::ParseCommandLineOptions(argc, argv);
 
   return TableGenMain(argv[0], &LLVMTableGenMain);
 }
 

llvm/utils/TableGen/TableGenBackends.h

 //===- TableGenBackends.h - Declarations for LLVM TableGen Backends -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations for all of the LLVM TableGen
 // backends. A "TableGen backend" is just a function. See below for a
 // precise description.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_UTILS_TABLEGEN_TABLEGENBACKENDS_H
 #define LLVM_UTILS_TABLEGEN_TABLEGENBACKENDS_H
 
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ManagedStatic.h"
+#include <string>
+
 // A TableGen backend is a function that looks like
 //
 //    EmitFoo(RecordKeeper &RK, raw_ostream &OS /*, anything else you need */ )
 //
 // What you do inside of that function is up to you, but it will usually
 // involve generating C++ code to the provided raw_ostream.
 //
 // The RecordKeeper is just a top-level container for an in-memory

 // LLVM.
 
 
 namespace llvm {
 
 class raw_ostream;
 class RecordKeeper;
 
-void EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS);
-void EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS);
-void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS);
-void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS);
-void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS);
-void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS);
-void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
-void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
-void EmitFastISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
-void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
-void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
-void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);
-void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);
-void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS);
+namespace TableGen {
+namespace Emitter {
+using FnT = void (*)(RecordKeeper &Records, raw_ostream &OS);
+
+struct OptCreatorT {
+  static void *call();
+};
+
+extern ManagedStatic<cl::opt<FnT>, OptCreatorT> Action;
+
+struct Opt {
+  Opt(StringRef Name, FnT CB, StringRef Desc, bool ByDefault = false) {
+    if (ByDefault)
+      Action->setInitialValue(CB);
+    Action->getParser().addLiteralOption(Name, CB, Desc);
+  }
+};
+
+template <class EmitterC> class OptClass : Opt {
+  static void run(RecordKeeper &RK, raw_ostream &OS) { EmitterC(RK).run(OS); }
+
+public:
+  OptClass(StringRef Name, StringRef Desc) : Opt(Name, run, Desc) {}
+};
+
+} // namespace Emitter
+} // namespace TableGen
+
 void EmitMapTable(RecordKeeper &RK, raw_ostream &OS);
-void EmitOptParser(RecordKeeper &RK, raw_ostream &OS);
-void EmitOptRST(RecordKeeper &RK, raw_ostream &OS);
-void EmitCTags(RecordKeeper &RK, raw_ostream &OS);
-void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);
-void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);
-void EmitGICombiner(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS);
-void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
-void EmitExegesis(RecordKeeper &RK, raw_ostream &OS);
-void EmitAutomata(RecordKeeper &RK, raw_ostream &OS);
-void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
-void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
-void EmitDXILOperation(RecordKeeper &RK, raw_ostream &OS);
-void EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS);
 
-} // End llvm namespace
+// Defined in DecoderEmitter.cpp
+void EmitDecoder(RecordKeeper &RK, raw_ostream &OS,
+                 const std::string &PredicateNamespace);
+
+} // namespace llvm
 
 #endif

llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp

 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
   // Print both tables
   printTable(EVEX2VEX128, OS);
   printTable(EVEX2VEX256, OS);
   // Print CheckVEXInstPredicate function.
   printCheckPredicate(EVEX2VEXPredicates, OS);
 }
 } // namespace
 
-namespace llvm {
-void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
-  X86EVEX2VEXTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86EVEX2VEXTablesEmitter>
+    X("gen-x86-EVEX2VEX-tables", "Generate X86 EVEX to VEX compress tables");

llvm/utils/TableGen/X86FoldTablesEmitter.cpp

 //===- utils/TableGen/X86FoldTablesEmitter.cpp - X86 backend-*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
class X86FoldTablesEmitter {
   FoldTable Table2;
   FoldTable Table3;
   FoldTable Table4;
 
 public:
   X86FoldTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
 
   // run - Generate the 6 X86 memory fold tables.
-  void run(formatted_raw_ostream &OS);
+  void run(raw_ostream &OS);
 
 private:
   // Decides to which table to add the entry with the given instructions.
   // S sets the strategy of adding the TB_NO_REVERSE flag.
   void updateTables(const CodeGenInstruction *RegInstr,
                     const CodeGenInstruction *MemInstr,
                     const UnfoldStrategy S = NO_STRATEGY);
 
if (MemInSize == RegInSize && MemOutSize == RegOutSize) {
     Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec;
     Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec;
     if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec) &&
         getRegOperandSize(RegOpRec) == getMemOperandSize(MemOpRec))
       addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);
   }
 }
 
-void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
+void X86FoldTablesEmitter::run(raw_ostream &o) {
+  formatted_raw_ostream OS(o);
   emitSourceFileHeader("X86 fold tables", OS);
 
   // Holds all memory instructions
   std::vector<const CodeGenInstruction *> MemInsts;
   // Holds all register instructions - divided according to opcode.
   std::map<uint8_t, std::vector<const CodeGenInstruction *>> RegInsts;
 
   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
void X86FoldTablesEmitter::run(raw_ostream &o) {
   printTable(Table2Addr, "Table2Addr", OS);
   printTable(Table0, "Table0", OS);
   printTable(Table1, "Table1", OS);
   printTable(Table2, "Table2", OS);
   printTable(Table3, "Table3", OS);
   printTable(Table4, "Table4", OS);
 }
 
-namespace llvm {
-
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &o) {
-  formatted_raw_ostream OS(o);
-  X86FoldTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86FoldTablesEmitter>
+    X("gen-x86-fold-tables", "Generate X86 fold tables");

llvm/utils/TableGen/X86MnemonicTables.cpp

 //==- X86MnemonicTables.cpp - Generate mnemonic extraction tables. -*- C++ -*-//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) {
     }
   }
   OS << "#endif // GET_X86_MNEMONIC_TABLES_CPP\n\n";
   OS << "} // end namespace X86\n} // end namespace llvm";
 }
 
 } // namespace
 
-namespace llvm {
-void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS) {
-  X86MnemonicTablesEmitter(RK).run(OS);
-}
-} // namespace llvm
+static TableGen::Emitter::OptClass<X86MnemonicTablesEmitter>
+    X("gen-x86-mnemonic-tables", "Generate X86 mnemonic tables");