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Differential D146506

Rewrite `llvm/test/TableGen` to use `%llvm-cg-tblgen`
AbandonedPublic

Authored by chapuni on Mar 21 2023, 2:00 AM.

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Reviewers
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Summary

llvm/test: Switch %llvm-cg-tblgen to llvm-cg-tblgen

This is a supplement to D146352

Diff Detail

Event Timeline

chapuni created this revision.Mar 21 2023, 2:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 21 2023, 2:00 AM
Herald added subscribers: luke, ormris, frasercrmck and 22 others. · View Herald Transcript
chapuni requested review of this revision.Mar 21 2023, 2:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 21 2023, 2:00 AM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald Transcript
chapuni edited the summary of this revision. (Show Details)Mar 21 2023, 2:01 AM
chapuni mentioned this in D146352: Introduce `llvm-min-tblgen` to build public header files.Mar 21 2023, 2:04 AM
Harbormaster completed remote builds in B220645: Diff 506876.Mar 21 2023, 2:06 AM
chapuni abandoned this revision.Apr 22 2023, 7:40 PM

D146352 doesn't require this anymore.

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Diff 506876

llvm/test/CMakeLists.txt

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesset(LLVM_TEST_DEPENDS
llvm-addr2line llvm-addr2line
llvm-ar llvm-ar
llvm-as llvm-as
llvm-bcanalyzer llvm-bcanalyzer
llvm-bitcode-strip llvm-bitcode-strip
llvm-c-test llvm-c-test
llvm-cat llvm-cat
llvm-cfi-verify llvm-cfi-verify
llvm-cg-tblgen
llvm-config llvm-config
llvm-cov llvm-cov
llvm-cvtres llvm-cvtres
llvm-cxxdump llvm-cxxdump
llvm-cxxfilt llvm-cxxfilt
llvm-cxxmap llvm-cxxmap
llvm-debuginfo-analyzer llvm-debuginfo-analyzer
llvm-debuginfod llvm-debuginfod
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llvm/test/TableGen/AliasAsmString.td

// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
let InstructionSet = ArchInstrInfo; let InstructionSet = ArchInstrInfo;
} }
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llvm/test/TableGen/AllowDuplicateRegisterNames.td

// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
// Check that MatchRegisterName and MatchRegisterAltName are generated // Check that MatchRegisterName and MatchRegisterAltName are generated
// correctly when multiple registers are defined with the same name and // correctly when multiple registers are defined with the same name and
// AllowDuplicateRegisterNames is set. // AllowDuplicateRegisterNames is set.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo; def ArchInstrInfo : InstrInfo;
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llvm/test/TableGen/AsmPredicateCombining.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \ // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | \
// RUN: FileCheck --check-prefix=DISASS %s // RUN: FileCheck --check-prefix=DISASS %s
// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \ // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | \
// RUN: FileCheck --check-prefix=MATCHER %s // RUN: FileCheck --check-prefix=MATCHER %s
// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \ // RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | \
// RUN: FileCheck --check-prefix=WRITER %s // RUN: FileCheck --check-prefix=WRITER %s
// Check that combining conditions in AssemblerPredicate generates the correct // Check that combining conditions in AssemblerPredicate generates the correct
// output when using both the (all_of) AND operator, and the (any_of) OR // output when using both the (all_of) AND operator, and the (any_of) OR
// operator. // operator.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
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llvm/test/TableGen/AsmPredicateCombiningRISCV.td

// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \ // RUN: %llvm-cg-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
// RUN: FileCheck --check-prefix=COMPRESS %s // RUN: FileCheck --check-prefix=COMPRESS %s
// Check that combining conditions in AssemblerPredicate generates the correct // Check that combining conditions in AssemblerPredicate generates the correct
// output when using both the (all_of) AND operator, and the (any_of) OR // output when using both the (all_of) AND operator, and the (any_of) OR
// operator in the RISC-V specific instruction compressor. // operator in the RISC-V specific instruction compressor.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
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llvm/test/TableGen/AsmPredicateCondsEmission.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
// Check that we don't generate invalid code of the form "( && Cond2)" when // Check that we don't generate invalid code of the form "( && Cond2)" when
// emitting AssemblerPredicate conditions. In the example below, the invalid // emitting AssemblerPredicate conditions. In the example below, the invalid
// code would be: "return ( && (Bits & arch::AssemblerCondition2));". // code would be: "return ( && (Bits & arch::AssemblerCondition2));".
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
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llvm/test/TableGen/AsmVariant.td

// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
// Check that specifying AsmVariant works correctly // Check that specifying AsmVariant works correctly
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def FooAsmParserVariant : AsmParserVariant { def FooAsmParserVariant : AsmParserVariant {
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llvm/test/TableGen/AsmWriterPCRelOp.td

// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
let InstructionSet = ArchInstrInfo; let InstructionSet = ArchInstrInfo;
} }
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llvm/test/TableGen/BigEncoder.td

// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/TableGen/BitOffsetDecoder.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/TableGen/CodeGenSchedule-duplicate-instrw.td

// RUN: not llvm-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s // RUN: not %llvm-cg-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def FakeTarget : Target { } def FakeTarget : Target { }
def FakeModel : SchedMachineModel { } def FakeModel : SchedMachineModel { }
def WriteA : SchedWrite; def WriteA : SchedWrite;
def WriteB : SchedWrite; def WriteB : SchedWrite;
let SchedModel = NoSchedModel in { let SchedModel = NoSchedModel in {
def : InstRW<[WriteA], (instrs COPY)>; def : InstRW<[WriteA], (instrs COPY)>;
def : InstRW<[WriteB], (instrs COPY)>; def : InstRW<[WriteB], (instrs COPY)>;
// CHECK: [[@LINE-1]]:3: error: Overlapping InstRW definition for "COPY" also matches previous "(instrs COPY)". // CHECK: [[@LINE-1]]:3: error: Overlapping InstRW definition for "COPY" also matches previous "(instrs COPY)".
// CHECK-NEXT: def : InstRW<[WriteB], (instrs COPY)>; // CHECK-NEXT: def : InstRW<[WriteB], (instrs COPY)>;
// CHECK: [[@LINE-6]]:3: note: Previous match was here. // CHECK: [[@LINE-6]]:3: note: Previous match was here.
// CHECK-NEXT: def : InstRW<[WriteA], (instrs COPY)>; // CHECK-NEXT: def : InstRW<[WriteA], (instrs COPY)>;
} }
No newline at end of file No newline at end of file

llvm/test/TableGen/CompressWriteLatencyEntry.td

// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
// Make sure that ReadAdvance entries are correctly processed. // Make sure that ReadAdvance entries are correctly processed.
// Not all ProcReadAdvance definitions implicitly inherit from SchedRead. // Not all ProcReadAdvance definitions implicitly inherit from SchedRead.
// Some ProcReadAdvances are subclasses of ReadAdvance. // Some ProcReadAdvances are subclasses of ReadAdvance.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def MyTarget : Target; def MyTarget : Target;
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llvm/test/TableGen/ConcatenatedSubregs.td

// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
// Checks that tablegen correctly and completely infers subregister relations. // Checks that tablegen correctly and completely infers subregister relations.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
class MyReg<string n, list<Register> subregs = []> class MyReg<string n, list<Register> subregs = []>
: Register<n> { : Register<n> {
let Namespace = "Test"; let Namespace = "Test";
let SubRegs = subregs; let SubRegs = subregs;
let CoveredBySubRegs = 1; let CoveredBySubRegs = 1;
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llvm/test/TableGen/ConstraintChecking1.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Unrecognized constraint '$dest1 ~ $src2' in 'Foo' // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Unrecognized constraint '$dest1 ~ $src2' in 'Foo'
def Foo : TestInstructionWithConstraints<"$dest1 ~ $src2">; def Foo : TestInstructionWithConstraints<"$dest1 ~ $src2">;

llvm/test/TableGen/ConstraintChecking2.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for @earlyclobber constraint in 'Foo' // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for @earlyclobber constraint in 'Foo'
def Foo : TestInstructionWithConstraints<"@earlyclobber ">; def Foo : TestInstructionWithConstraints<"@earlyclobber ">;

llvm/test/TableGen/ConstraintChecking3.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// (This is illegal because the '=' has to be surrounded by whitespace) // (This is illegal because the '=' has to be surrounded by whitespace)
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for tied-to constraint in 'Foo' // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for tied-to constraint in 'Foo'
def Foo : TestInstructionWithConstraints<"$dest1=$dest2">; def Foo : TestInstructionWithConstraints<"$dest1=$dest2">;

llvm/test/TableGen/ConstraintChecking4.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Output operands '$dest1' and '$dest2' of 'Foo' cannot be tied! // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Output operands '$dest1' and '$dest2' of 'Foo' cannot be tied!
def Foo : TestInstructionWithConstraints<"$dest1 = $dest2">; def Foo : TestInstructionWithConstraints<"$dest1 = $dest2">;

llvm/test/TableGen/ConstraintChecking5.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Input operands '$src1' and '$src2' of 'Foo' cannot be tied! // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Input operands '$src1' and '$src2' of 'Foo' cannot be tied!
def Foo : TestInstructionWithConstraints<"$src1 = $src2">; def Foo : TestInstructionWithConstraints<"$src1 = $src2">;

llvm/test/TableGen/ConstraintChecking6.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$dest1' of 'Foo' cannot have multiple operands tied to it! // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$dest1' of 'Foo' cannot have multiple operands tied to it!
def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest1 = $src2">; def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest1 = $src2">;

llvm/test/TableGen/ConstraintChecking7.td

// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "ConstraintChecking.inc" include "ConstraintChecking.inc"
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$src1' of 'Foo' cannot have multiple constraints! // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$src1' of 'Foo' cannot have multiple constraints!
def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest2 = $src1">; def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest2 = $src1">;

llvm/test/TableGen/ContextlessPredicates.td

// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val), def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val),
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llvm/test/TableGen/DAGDefaultOps.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s -o %t
// RUN: FileCheck --check-prefix=ADD %s < %t // RUN: FileCheck --check-prefix=ADD %s < %t
// RUN: FileCheck --check-prefix=ADDINT %s < %t // RUN: FileCheck --check-prefix=ADDINT %s < %t
// RUN: FileCheck --check-prefix=SUB %s < %t // RUN: FileCheck --check-prefix=SUB %s < %t
// RUN: FileCheck --check-prefix=MULINT %s < %t // RUN: FileCheck --check-prefix=MULINT %s < %t
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestInstrInfo : InstrInfo; def TestInstrInfo : InstrInfo;
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llvm/test/TableGen/DefaultOpsGlobalISel.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def SelectClamp : ComplexPattern<untyped, 2, "SelectClamp">; def SelectClamp : ComplexPattern<untyped, 2, "SelectClamp">;
def SelectOMod : ComplexPattern<untyped, 2, "SelectOMod">; def SelectOMod : ComplexPattern<untyped, 2, "SelectOMod">;
def SelectClampOMod : ComplexPattern<untyped, 3, "SelectClampOMod">; def SelectClampOMod : ComplexPattern<untyped, 3, "SelectClampOMod">;
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llvm/test/TableGen/DuplicateFieldValues.td

// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
// CHECK: ABCForm_A // CHECK: ABCForm_A
// CHECK-NOT: ABCForm_A // CHECK-NOT: ABCForm_A
// //
// include Target.td for InstrMapping class and define minimally required objects // include Target.td for InstrMapping class and define minimally required objects
// //
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llvm/test/TableGen/FastISelEmitter.td

// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
//===- Define the necessary boilerplate for our test target. --------------===// //===- Define the necessary boilerplate for our test target. --------------===//
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; } def MyTarget : Target { let InstructionSet = MyTargetISA; }
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llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td

// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 | FileCheck %s --implicit-check-not=error: // RUN: not %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
let InstructionSet = ArchInstrInfo; let InstructionSet = ArchInstrInfo;
} }
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llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
// RUN: FileCheck %s < %t // RUN: FileCheck %s < %t
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; } def MyTarget : Target { let InstructionSet = MyTargetISA; }
def R0 : Register<"r0"> { let Namespace = "MyTarget"; } def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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llvm/test/TableGen/GICombinerEmitter/defs-invalid.td

// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ // RUN: not %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombiner %s 2>&1 | \ // RUN: -combiners=MyCombiner %s 2>&1 | \
// RUN: FileCheck -implicit-check-not=error: %s // RUN: FileCheck -implicit-check-not=error: %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td" include "llvm/Target/GlobalISel/Combine.td"
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; } def MyTarget : Target { let InstructionSet = MyTargetISA; }
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llvm/test/TableGen/GICombinerEmitter/match-invalid.td

// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ // RUN: not %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombiner %s 2>&1 | \ // RUN: -combiners=MyCombiner %s 2>&1 | \
// RUN: FileCheck -implicit-check-not=error: %s // RUN: FileCheck -implicit-check-not=error: %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td" include "llvm/Target/GlobalISel/Combine.td"
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; } def MyTarget : Target { let InstructionSet = MyTargetISA; }
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llvm/test/TableGen/GICombinerEmitter/match-tree.td

// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ // RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombinerHelper -gicombiner-stop-after-build %s \ // RUN: -combiners=MyCombinerHelper -gicombiner-stop-after-build %s \
// RUN: -o %t.inc | FileCheck %s // RUN: -o %t.inc | FileCheck %s
// //
// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ // RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombinerHelper %s | \ // RUN: -combiners=MyCombinerHelper %s | \
// RUN: FileCheck --check-prefix=CODE %s // RUN: FileCheck --check-prefix=CODE %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td" include "llvm/Target/GlobalISel/Combine.td"
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; } def MyTarget : Target { let InstructionSet = MyTargetISA; }
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llvm/test/TableGen/GICombinerEmitter/parse-match-pattern.td

// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \ // RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombiner -gicombiner-stop-after-parse %s \ // RUN: -combiners=MyCombiner -gicombiner-stop-after-parse %s \
// RUN: -o /dev/null -debug 2>&1 | FileCheck %s // RUN: -o /dev/null -debug 2>&1 | FileCheck %s
// REQUIRES: asserts // REQUIRES: asserts
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td" include "llvm/Target/GlobalISel/Combine.td"
def MyTargetISA : InstrInfo; def MyTargetISA : InstrInfo;
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llvm/test/TableGen/GlobalISelEmitter-PR39045.td

// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %t // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %t
// RUN: FileCheck %s < %t // RUN: FileCheck %s < %t
// Both predicates should be tested // Both predicates should be tested
// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_b, // CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_b,
// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a, // CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
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llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def shiftl_1 : SDNodeXForm<timm, [{ def shiftl_1 : SDNodeXForm<timm, [{
return CurDAG->getTargetConstant(N->getZExtValue() << 1, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() << 1, SDLoc(N), MVT::i32);
}]>; }]>;
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llvm/test/TableGen/GlobalISelEmitter-atomic_store.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>; def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>;
// Check that the pattern for atomic_store inverts the operands to // Check that the pattern for atomic_store inverts the operands to
// match the order of G_STORE. // match the order of G_STORE.
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llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// GISEL-OPT: GIM_SwitchOpcode // GISEL-OPT: GIM_SwitchOpcode
// GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/ // GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/
// GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/ // GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/
// GISEL-OPT-NEXT: // Label // GISEL-OPT-NEXT: // Label
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llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
def G_TGT_CAT : MyTargetGenericInstruction { def G_TGT_CAT : MyTargetGenericInstruction {
let OutOperandList = (outs type0:$dst); let OutOperandList = (outs type0:$dst);
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llvm/test/TableGen/GlobalISelEmitter-input-discard.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def int_tgt_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; def int_tgt_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
// Test that using srcvalue works for discarded pattern inputs. // Test that using srcvalue works for discarded pattern inputs.
def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>; def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
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llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Verify that patterns will add temp registers if NumDstDef > NumSrcDef when NumSrcDef >= 1 // Verify that patterns will add temp registers if NumDstDef > NumSrcDef when NumSrcDef >= 1
// and that these temp registers are marked as dead // and that these temp registers are marked as dead
// Note: This is an extension of the test GlobalISelEmitter-output-discard.td // Note: This is an extension of the test GlobalISelEmitter-output-discard.td
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llvm/test/TableGen/GlobalISelEmitter-multiple-output.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Test the generation of patterns with multiple output operands and makes sure that // Test the generation of patterns with multiple output operands and makes sure that
// we are able to create a new instruction if necessary, or just simply change the // we are able to create a new instruction if necessary, or just simply change the
// opcode if the input and output operands of the generic instruction are the same // opcode if the input and output operands of the generic instruction are the same
// as the target-specific instruction // as the target-specific instruction
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llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
let Namespace = "MyTarget" in { let Namespace = "MyTarget" in {
def lo8 : SubRegIndex<8>; def lo8 : SubRegIndex<8>;
def hi8 : SubRegIndex<8, 8>; def hi8 : SubRegIndex<8, 8>;
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llvm/test/TableGen/GlobalISelEmitter-output-discard.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Test that extra explicit results are treated as dead defs. // Test that extra explicit results are treated as dead defs.
def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag), def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
(ins GPR32Op:$src0, GPR32Op:$src1), []>; (ins GPR32Op:$src0, GPR32Op:$src1), []>;
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llvm/test/TableGen/GlobalISelEmitter-setcc.td

// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t // RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// GISEL: GIM_Try // GISEL: GIM_Try
// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP, // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP,
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llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf // CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf
def : Pat<(zext (i16 (trunc i32:$src))), def : Pat<(zext (i16 (trunc i32:$src))),
(i32 $src)>; (i32 $src)>;

llvm/test/TableGen/GlobalISelEmitter-zero-reg.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def P0 : Register<"p0"> { let Namespace = "MyTarget"; } def P0 : Register<"p0"> { let Namespace = "MyTarget"; }
def PR32 : RegisterClass<"MyTarget", [i32], 32, (add P0)>; def PR32 : RegisterClass<"MyTarget", [i32], 32, (add P0)>;
def PR32Op : RegisterOperand<PR32>; def PR32Op : RegisterOperand<PR32>;
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llvm/test/TableGen/GlobalISelEmitter.td

// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21N -input-file=%T/non-optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21N -input-file=%T/non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21O -input-file=%T/optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21O -input-file=%T/optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20N -input-file=%T/non-optimized.cpp // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20N -input-file=%T/non-optimized.cpp
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llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
// Verify that all MI predicates are enumerated. // Verify that all MI predicates are enumerated.
// //
// CHECK: // PatFrag predicates. // CHECK: // PatFrag predicates.
// CHECK-NEXT: enum { // CHECK-NEXT: enum {
// CHECK-NEXT: GIPFP_MI_Predicate_and_or_pat = GIPFP_MI_Invalid + 1, // CHECK-NEXT: GIPFP_MI_Predicate_and_or_pat = GIPFP_MI_Invalid + 1,
// CHECK-NEXT: GIPFP_MI_Predicate_or_oneuse, // CHECK-NEXT: GIPFP_MI_Predicate_or_oneuse,
// CHECK-NEXT: GIPFP_MI_Predicate_patfrags_test_pat, // CHECK-NEXT: GIPFP_MI_Predicate_patfrags_test_pat,
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llvm/test/TableGen/GlobalISelEmitterFlags.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
class SrlPF<bit IC>: PatFrag< class SrlPF<bit IC>: PatFrag<
(ops node:$PATFRAG_Src0, node:$src1), (ops node:$PATFRAG_Src0, node:$src1),
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// CHECK: // (srl:{ *:[i32] } (shl:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0) // CHECK: // (srl:{ *:[i32] } (shl:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0)
// CHECK: GIR_Done // CHECK: GIR_Done
// CHECK: GIM_Try // CHECK: GIM_Try
// CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL // CHECK: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL
// CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1 // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1
// CHECK: // (sub:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src1) // CHECK: // (sub:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src1)
// CHECK: GIR_Done // CHECK: GIR_Done
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llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Two LOADs with same output size but different input size, hence their // Two LOADs with same output size but different input size, hence their
// GIM_CheckPointerToAny should *not* be merged // GIM_CheckPointerToAny should *not* be merged
def LOAD8 : I<(outs GPR8:$dst), (ins GPR8:$src), []>; def LOAD8 : I<(outs GPR8:$dst), (ins GPR8:$src), []>;
def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>;
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llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ 219, // CHECK: GIM_Try, /*On fail goto*//*Label 0*/ 219,
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llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
// Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group // Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group
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llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td

// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
// Boilerplate code. // Boilerplate code.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
let TargetPrefix = "mytarget" in { let TargetPrefix = "mytarget" in {
def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
} }
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llvm/test/TableGen/GlobalISelEmitterRegSequence.td

// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Boilerplate code for setting up some registers with subregs. // Boilerplate code for setting up some registers with subregs.
class MyReg<string n, list<Register> subregs = []> class MyReg<string n, list<Register> subregs = []>
: Register<n> { : Register<n> {
let SubRegs = subregs; let SubRegs = subregs;
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llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td

// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
//===- Boiler plate target code -===// //===- Boiler plate target code -===//
def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> { def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
let MIOperandInfo = (ops i32imm, i32imm); let MIOperandInfo = (ops i32imm, i32imm);
} }
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llvm/test/TableGen/GlobalISelEmitterSubreg.td

// RUN: llvm-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s // RUN: %llvm-cg-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
// RUN: cat %t.skipped | FileCheck %s --check-prefix=SKIPPED // RUN: cat %t.skipped | FileCheck %s --check-prefix=SKIPPED
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Boilerplate code for setting up some registers with subregs. // Boilerplate code for setting up some registers with subregs.
class MyReg<string n, list<Register> subregs = []> class MyReg<string n, list<Register> subregs = []>
: Register<n> { : Register<n> {
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llvm/test/TableGen/GlobalISelEmitterVariadic.td

// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>; def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>; def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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llvm/test/TableGen/HasNoUse.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Test the HasNoUse predicate // Test the HasNoUse predicate
def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>; def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
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llvm/test/TableGen/HwModeEncodeDecode.td

// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s --check-prefix=ENCODER // RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s --check-prefix=ENCODER
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=DECODER // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=DECODER
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/TableGen/HwModeSelect.td

// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s // RUN: not --crash %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
// The HwModeSelect class is intended to serve as a base class for other // The HwModeSelect class is intended to serve as a base class for other
// classes that are then used to select a value based on the HW mode. // classes that are then used to select a value based on the HW mode.
// It contains a list of HW modes, and a derived class should provide a // It contains a list of HW modes, and a derived class should provide a
// list of corresponding values. // list of corresponding values.
// These two lists must have the same size. Make sure that a violation of // These two lists must have the same size. Make sure that a violation of
// this requirement is diagnosed. // this requirement is diagnosed.
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llvm/test/TableGen/InvalidMCSchedClassDesc.td

// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
// Check if it is valid MCSchedClassDesc if didn't have the resources. // Check if it is valid MCSchedClassDesc if didn't have the resources.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def MyTarget : Target; def MyTarget : Target;
let OutOperandList = (outs), InOperandList = (ins) in { let OutOperandList = (outs), InOperandList = (ins) in {
def Inst_A : Instruction; def Inst_A : Instruction;
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llvm/test/TableGen/MissingOperandField.td

// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error: // RUN: not %llvm-cg-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
// Check that we emit reasonable diagnostics when fields do not have // Check that we emit reasonable diagnostics when fields do not have
// corresponding operands. // corresponding operands.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
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llvm/test/TableGen/MixedCasedMnemonic.td

// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=MATCHER // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=MATCHER
// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s --check-prefix=WRITER // RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s --check-prefix=WRITER
// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=ALIAS // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=ALIAS
// Check that an instruction that uses mixed upper/lower case in its mnemonic // Check that an instruction that uses mixed upper/lower case in its mnemonic
// is printed as-is, and is parsed in its "canonicalized" lowercase form. // is printed as-is, and is parsed in its "canonicalized" lowercase form.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
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llvm/test/TableGen/MnemonicAlias.td

// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
let InstructionSet = ArchInstrInfo; let InstructionSet = ArchInstrInfo;
} }
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llvm/test/TableGen/RegisterBankEmitter.td

// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def MyTarget : Target; def MyTarget : Target;
def R0 : Register<"r0">; def R0 : Register<"r0">;
let Size = 32 in { let Size = 32 in {
def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>; def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>; def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
} }
// CHECK: GPRRegBankCoverageData // CHECK: GPRRegBankCoverageData
// CHECK: MyTarget::ClassARegClassID // CHECK: MyTarget::ClassARegClassID
// CHECK: MyTarget::ClassBRegClassID // CHECK: MyTarget::ClassBRegClassID
def GPRRegBank : RegisterBank<"GPR", [ClassA]>; def GPRRegBank : RegisterBank<"GPR", [ClassA]>;

llvm/test/TableGen/RegisterClass.td

// RUN: not llvm-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s // RUN: not %llvm-cg-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def MyTarget : Target; def MyTarget : Target;
def R0 : Register<"r0">; def R0 : Register<"r0">;
def ClassA : RegisterClass<"MyTarget", [], 32, (add R0)>; // CHECK: [[@LINE]]:5: error: RegTypes list must not be empty! def ClassA : RegisterClass<"MyTarget", [], 32, (add R0)>; // CHECK: [[@LINE]]:5: error: RegTypes list must not be empty!

llvm/test/TableGen/RegisterEncoder.td

// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
// Check that EncoderMethod for RegisterOperand is working correctly // Check that EncoderMethod for RegisterOperand is working correctly
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
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llvm/test/TableGen/RegisterInfoEmitter-BaseClassOrder.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
let Namespace = "MyTarget" in { let Namespace = "MyTarget" in {
def R0 : Register<"r0">; // base class BaseA def R0 : Register<"r0">; // base class BaseA
def R1 : Register<"r1">; // base class BaseA def R1 : Register<"r1">; // base class BaseA
def R2 : Register<"r2">; // base class BaseC def R2 : Register<"r2">; // base class BaseC
def R3 : Register<"r3">; // base class BaseC def R3 : Register<"r3">; // base class BaseC
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llvm/test/TableGen/RegisterInfoEmitter-regcost-list.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// Checks two CostPerUse values for the registers. // Checks two CostPerUse values for the registers.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
let Namespace = "MyTarget" in { let Namespace = "MyTarget" in {
foreach Index = 0-3 in { foreach Index = 0-3 in {
// Adding two cost values per register. // Adding two cost values per register.
let CostPerUse = [1, Index] in { let CostPerUse = [1, Index] in {
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llvm/test/TableGen/RegisterInfoEmitter-regcost-tuple.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// Checks the cost values for the register tuple. // Checks the cost values for the register tuple.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
class MyClass<int size, list<ValueType> types, dag registers> class MyClass<int size, list<ValueType> types, dag registers>
: RegisterClass<"MyTarget", types, size, registers> { : RegisterClass<"MyTarget", types, size, registers> {
let Size = size; let Size = size;
} }
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llvm/test/TableGen/RegisterInfoEmitter-regcost.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// Checks the CostPerUse value for the registers. // Checks the CostPerUse value for the registers.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
let Namespace = "MyTarget" in { let Namespace = "MyTarget" in {
foreach Index = 0-3 in { foreach Index = 0-3 in {
// Adds register cost value 1. // Adds register cost value 1.
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llvm/test/TableGen/RegisterInfoEmitter-tsflags.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// Configure and test TSFlags for a target. // Configure and test TSFlags for a target.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
let Namespace = "MyTarget" in { let Namespace = "MyTarget" in {
def R : Register<"r">; def R : Register<"r">;
def D : Register<"d">; def D : Register<"d">;
def S : Register<"s">; def S : Register<"s">;
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llvm/test/TableGen/RelTest.td

// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s // RUN: not %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
// This test verifies that TableGen is displaying an error when mapped instruction // This test verifies that TableGen is displaying an error when mapped instruction
// does not contain a field listed under RowFields. // does not contain a field listed under RowFields.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
class SimpleReg<string n> : Register<n> { class SimpleReg<string n> : Register<n> {
let Namespace = "Simple"; let Namespace = "Simple";
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llvm/test/TableGen/SchedModelError.td

// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s // RUN: not %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTarget : Target; def TestTarget : Target;
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel' // CHECK: [[FILE]]:[[@LINE+1]]:5: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
def TestInst : Instruction { def TestInst : Instruction {
let OutOperandList = (outs); let OutOperandList = (outs);
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llvm/test/TableGen/VarLenDecoder.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
let InstructionSet = ArchInstrInfo; let InstructionSet = ArchInstrInfo;
} }
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llvm/test/TableGen/VarLenEncoder.td

// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
// Check if VarLenCodeEmitterGen works correctly. // Check if VarLenCodeEmitterGen works correctly.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def ArchInstrInfo : InstrInfo { } def ArchInstrInfo : InstrInfo { }
def Arch : Target { def Arch : Target {
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llvm/test/TableGen/address-space-patfrags.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
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llvm/test/TableGen/ambiguous-composition.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s
// //
// CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Test::subreg_hh32 or Test::subreg_h32 // CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Test::subreg_hh32 or Test::subreg_h32
// CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::subreg_ll32 or Test::subreg_l32 // CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::subreg_ll32 or Test::subreg_l32
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestInstrInfo : InstrInfo { def TestInstrInfo : InstrInfo {
} }
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llvm/test/TableGen/bare-minimum-psets.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// Test to check the bare minimum pressure sets. // Test to check the bare minimum pressure sets.
// At least one register pressure set is required for the target. // At least one register pressure set is required for the target.
// Allowed the pset only for D_32 regclass and ignored it for all // Allowed the pset only for D_32 regclass and ignored it for all
// other classes including the tuples. // other classes including the tuples.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
class MyClass<int size, list<ValueType> types, dag registers> class MyClass<int size, list<ValueType> types, dag registers>
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llvm/test/TableGen/dag-isel-complexpattern.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
} }
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llvm/test/TableGen/dag-isel-regclass-emit-enum.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
} }
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llvm/test/TableGen/dag-isel-res-order.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
} }
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llvm/test/TableGen/dag-isel-subregs.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
include "reg-with-subregs-common.td" include "reg-with-subregs-common.td"
// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR), // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
// CHECK: OPC_CheckChild1Integer, 0, // CHECK: OPC_CheckChild1Integer, 0,
// CHECK: OPC_EmitStringInteger, MVT::i32, sub0_sub1, // CHECK: OPC_EmitStringInteger, MVT::i32, sub0_sub1,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))), def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>; (EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
// CHECK: OPC_CheckChild1Integer, 30, // CHECK: OPC_CheckChild1Integer, 30,
// CHECK: OPC_EmitInteger, MVT::i32, 10|128,2/*266*/, // CHECK: OPC_EmitInteger, MVT::i32, 10|128,2/*266*/,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))), def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
(EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>; (EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;

llvm/test/TableGen/empty-psets.td

// RUN: not llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s 2>&1 | FileCheck %s // RUN: not %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s 2>&1 | FileCheck %s
// Negative test to check empty Psets for a target. // Negative test to check empty Psets for a target.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def R : Register<"r">; def R : Register<"r">;
def R_32 : RegisterClass<"MyTarget", [i32], 32, (add R)> { def R_32 : RegisterClass<"MyTarget", [i32], 32, (add R)> {
let GeneratePressureSet = 0; let GeneratePressureSet = 0;
} }
def MyTarget : Target; def MyTarget : Target;
// CHECK: error: RegUnitSets cannot be empty! // CHECK: error: RegUnitSets cannot be empty!

llvm/test/TableGen/generic-tables-instruction.td

// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
// XFAIL: vg_leak // XFAIL: vg_leak
include "llvm/TableGen/SearchableTable.td" include "llvm/TableGen/SearchableTable.td"
// CHECK-LABEL: GET_InstrTable_IMPL // CHECK-LABEL: GET_InstrTable_IMPL
// CHECK: constexpr MyInstr InstrTable[] = { // CHECK: constexpr MyInstr InstrTable[] = {
// CHECK: { B, 0xA }, // CHECK: { B, 0xA },
// CHECK: { C, 0x0 }, // CHECK: { C, 0x0 },
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llvm/test/TableGen/generic-tables.td

// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
// RUN: not llvm-tblgen -gen-searchable-tables -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s // RUN: not %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
// XFAIL: vg_leak // XFAIL: vg_leak
include "llvm/TableGen/SearchableTable.td" include "llvm/TableGen/SearchableTable.td"
// CHECK-LABEL: GET_BValues_DECL // CHECK-LABEL: GET_BValues_DECL
// CHECK: enum BValues { // CHECK: enum BValues {
// CHECK: BAlice = 172, // CHECK: BAlice = 172,
// CHECK: BBob = 20, // CHECK: BBob = 20,
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llvm/test/TableGen/get-operand-type-no-expand.td

Show All 23 Linesdef InstA : Instruction {
let Size = 1; let Size = 1;
let OutOperandList = (outs i512complex:$a); let OutOperandList = (outs i512complex:$a);
let InOperandList = (ins i8complex:$b, i32imm:$c); let InOperandList = (ins i8complex:$b, i32imm:$c);
field bits<8> Inst; field bits<8> Inst;
field bits<8> SoftFail = 0; field bits<8> SoftFail = 0;
let Namespace = "MyNamespace"; let Namespace = "MyNamespace";
} }
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \ // RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s \
// RUN: -instr-info-expand-mi-operand-info=1 \ // RUN: -instr-info-expand-mi-operand-info=1 \
// RUN: | FileCheck %s --check-prefix=CHECK-EXPAND // RUN: | FileCheck %s --check-prefix=CHECK-EXPAND
// CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE // CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-EXPAND: OpcodeOperandTypes[] = { // CHECK-EXPAND: OpcodeOperandTypes[] = {
// CHECK-EXPAND: /* InstA */ // CHECK-EXPAND: /* InstA */
// CHECK-EXPAND-NEXT: i8imm, i32imm, i8imm, i32imm, i32imm, // CHECK-EXPAND-NEXT: i8imm, i32imm, i8imm, i32imm, i32imm,
// CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE // CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \ // RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s \
// RUN: -instr-info-expand-mi-operand-info=0 \ // RUN: -instr-info-expand-mi-operand-info=0 \
// RUN: | FileCheck %s --check-prefix=CHECK-NOEXPAND // RUN: | FileCheck %s --check-prefix=CHECK-NOEXPAND
// CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE // CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-NOEXPAND: OpcodeOperandTypes[] = { // CHECK-NOEXPAND: OpcodeOperandTypes[] = {
// CHECK-NOEXPAND: /* InstA */ // CHECK-NOEXPAND: /* InstA */
// CHECK-NOEXPAND-NEXT: i512complex, i8complex, i32imm, // CHECK-NOEXPAND-NEXT: i512complex, i8complex, i32imm,
// CHECK-NOEXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE // CHECK-NOEXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE

llvm/test/TableGen/get-operand-type.td

// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
// Check that getOperandType has the expected info in it // Check that getOperandType has the expected info in it
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
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llvm/test/TableGen/gisel-physreg-input.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
} }
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llvm/test/TableGen/immarg-predicated.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
let TargetPrefix = "mytarget" in { let TargetPrefix = "mytarget" in {
def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
} }
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llvm/test/TableGen/immarg.td

// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
let TargetPrefix = "mytarget" in { let TargetPrefix = "mytarget" in {
def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
} }
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llvm/test/TableGen/inhibit-pset.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
include "reg-with-subregs-common.td" include "reg-with-subregs-common.td"
// CHECK-DAG: GPR32_AND_XR32RegClassID = // CHECK-DAG: GPR32_AND_XR32RegClassID =
// CHECK-DAG: XR32RegClassID = // CHECK-DAG: XR32RegClassID =
def X0 : Register <"x0">; def X0 : Register <"x0">;
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llvm/test/TableGen/predicate-patfags.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=SDAG %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=SDAG %s
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=GISEL %s // RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td" include "GlobalISelEmitterCommon.td"
// Test that a predicate works when there are multiple pattern trees // Test that a predicate works when there are multiple pattern trees
// in a PatFrags. // in a PatFrags.
def int_tgt_mul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty]>; def int_tgt_mul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty]>;
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llvm/test/TableGen/pset-enum.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s
include "reg-with-subregs-common.td" include "reg-with-subregs-common.td"
// CHECK-LABEL: // Register pressure sets enum. // CHECK-LABEL: // Register pressure sets enum.
// NAMESPACE-NEXT: namespace TestNamespace { // NAMESPACE-NEXT: namespace TestNamespace {
// CHECK-NEXT: enum RegisterPressureSets { // CHECK-NEXT: enum RegisterPressureSets {
// CHECK-NEXT: GPR32 = 0, // CHECK-NEXT: GPR32 = 0,
// CHECK-NEXT: }; // CHECK-NEXT: };
// NAMESPACE-NEXT: } // end namespace TestNamespace // NAMESPACE-NEXT: } // end namespace TestNamespace

llvm/test/TableGen/pseudo-inst-expansion.td

// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo; def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target { def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo; let InstructionSet = TestTargetInstrInfo;
} }
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llvm/test/TableGen/rc-weight-override.td

// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
include "reg-with-subregs-common.td" include "reg-with-subregs-common.td"
// CHECK-LABEL: static const RegClassWeight RCWeightTable[] = { // CHECK-LABEL: static const RegClassWeight RCWeightTable[] = {
// CHECK: {1, 256}, // GPR32 // CHECK: {1, 256}, // GPR32
// CHECK: {2, 256}, // GPR_64 // CHECK: {2, 256}, // GPR_64
// CHECK: {0, 256}, // GPR_64_W0 // CHECK: {0, 256}, // GPR_64_W0
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llvm/test/TableGen/searchabletables-intrinsic.td

// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
// XFAIL: vg_leak // XFAIL: vg_leak
include "llvm/TableGen/SearchableTable.td" include "llvm/TableGen/SearchableTable.td"
class IntrinsicProperty<bit is_default = 0> { class IntrinsicProperty<bit is_default = 0> {
bit IsDefault = is_default; bit IsDefault = is_default;
} }
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llvm/test/TableGen/simplify-patfrag.td

// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s // RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
// Minimal Target definition // Minimal Target definition
def DemoInstrInfo : InstrInfo; def DemoInstrInfo : InstrInfo;
def Demo : Target { def Demo : Target {
let InstructionSet = DemoInstrInfo; let InstructionSet = DemoInstrInfo;
} }
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llvm/test/TableGen/trydecode-emission.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
// Check that if decoding of an instruction fails and the instruction does not // Check that if decoding of an instruction fails and the instruction does not
// have a complete decoder method that can determine if the bitpattern is valid // have a complete decoder method that can determine if the bitpattern is valid
// or not then the decoder tries to find a more general instruction that // or not then the decoder tries to find a more general instruction that
// matches the bitpattern too. // matches the bitpattern too.
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
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llvm/test/TableGen/trydecode-emission2.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/TableGen/trydecode-emission3.td

// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s // RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { } def archInstrInfo : InstrInfo { }
def arch : Target { def arch : Target {
let InstructionSet = archInstrInfo; let InstructionSet = archInstrInfo;
} }
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llvm/test/lit.cfg.py

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linestools = [
ToolSubst('%llvm', FindTool('llvm'), unresolved='ignore'), ToolSubst('%llvm', FindTool('llvm'), unresolved='ignore'),
ToolSubst('%lli', FindTool('lli'), post='.', extra_args=lli_args), ToolSubst('%lli', FindTool('lli'), post='.', extra_args=lli_args),
ToolSubst('%llc_dwarf', FindTool('llc'), extra_args=llc_args), ToolSubst('%llc_dwarf', FindTool('llc'), extra_args=llc_args),
ToolSubst('%gold', config.gold_executable, unresolved='ignore'), ToolSubst('%gold', config.gold_executable, unresolved='ignore'),
ToolSubst('%ld64', ld64_cmd, unresolved='ignore'), ToolSubst('%ld64', ld64_cmd, unresolved='ignore'),
ToolSubst('%ocamlc', ocamlc_command, unresolved='ignore'), ToolSubst('%ocamlc', ocamlc_command, unresolved='ignore'),
ToolSubst('%ocamlopt', ocamlopt_command, unresolved='ignore'), ToolSubst('%ocamlopt', ocamlopt_command, unresolved='ignore'),
ToolSubst('%opt-viewer', opt_viewer_cmd), ToolSubst('%opt-viewer', opt_viewer_cmd),
ToolSubst('%llvm-cg-tblgen', FindTool('llvm-cg-tblgen')),
ToolSubst('%llvm-objcopy', FindTool('llvm-objcopy')), ToolSubst('%llvm-objcopy', FindTool('llvm-objcopy')),
ToolSubst('%llvm-strip', FindTool('llvm-strip')), ToolSubst('%llvm-strip', FindTool('llvm-strip')),
ToolSubst('%llvm-install-name-tool', FindTool('llvm-install-name-tool')), ToolSubst('%llvm-install-name-tool', FindTool('llvm-install-name-tool')),
ToolSubst('%llvm-bitcode-strip', FindTool('llvm-bitcode-strip')), ToolSubst('%llvm-bitcode-strip', FindTool('llvm-bitcode-strip')),
ToolSubst('%split-file', FindTool('split-file')), ToolSubst('%split-file', FindTool('split-file')),
] ]
# FIXME: Why do we have both `lli` and `%lli` that do slightly different things? # FIXME: Why do we have both `lli` and `%lli` that do slightly different things?
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