[Clang][RISCV] Guard vector int64, float32, float64 with semantic analysis

[eopXD]

Summary

Depends on D143657

[eopXD]

Bump CI.

[craig.topper]

clang/include/clang/AST/Type.h

7209

This function is RVV specific so it's name is misleading. It's also identical to the isRVVFloat32Type function

clang/include/clang/Basic/TargetInfo.h

668

Having a different virtual method for each type doesn't scale well. Could we have a single function that take the bitwidth and a bool for int or FP?

It's also very misleading based on the current names to return false for targets like X86 that do support float32 and float64.

Overall it might be cleaner to call S.Context.getTargetInfo().hasFeature( from RISCV-V specific code in Sema instead of trying to define a generic interface.

[eopXD]

clang/include/clang/Basic/TargetInfo.h

668

It's also very misleading based on the current names to return false for targets like X86 that do support float32 and float64.

This is the base class of TargetInfo, we may add code under x86 to override it.

[eopXD]

clang/lib/Sema/Sema.cpp

2049–2056

Overall it might be cleaner to call S.Context.getTargetInfo().hasFeature( from RISCV-V specific code in Sema instead of trying to define a generic interface.

If so, we will have something like:

if (Ty->isRVVInt64Type() && !Context.getTargetInfo().hasFeature("zve64x")) {
  Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
}

I don't have a preference here, if this matches your expectation, I will update the revision this way.

[craig.topper]

clang/lib/Sema/Sema.cpp

2049–2056

I'm ok with what you did the Zvfh patch.

[eopXD]

Update code.

[eopXD]

Update code.

[craig.topper]

LGTM

clang/include/clang/AST/Type.h

#include "clang/Basic/OpenCLExtensionTypes.def"
 
   /// Check if the type is the CUDA device builtin surface type.
   bool isCUDADeviceBuiltinSurfaceType() const;
   /// Check if the type is the CUDA device builtin texture type.
   bool isCUDADeviceBuiltinTextureType() const;
 
   bool isRVVType() const;
 
+  bool isVectorInt64Type() const;
   bool isVectorFloat16Type() const;
+  bool isVectorFloat32Type() const;
+  bool isVectorFloat64Type() const;
 
+  bool isRVVInt64Type() const;
   bool isRVVFloat16Type() const;
+  bool isRVVFloat32Type() const;
+  bool isRVVFloat64Type() const;
 
   /// Return the implicit lifetime for this type, which must not be dependent.
   Qualifiers::ObjCLifetime getObjCARCImplicitLifetime() const;
 
   enum ScalarTypeKind {
     STK_CPointer,
     STK_BlockPointer,
     STK_ObjCObjectPointer,

 inline bool Type::isRVVType() const {
 #define RVV_TYPE(Name, Id, SingletonId) \
   isSpecificBuiltinType(BuiltinType::Id) ||
   return
 #include "clang/Basic/RISCVVTypes.def"
     false; // end of boolean or operation.
 }
 
+inline bool Type::isVectorInt64Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_INT64(Name, Id, ...)                                   \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
+inline bool Type::isRVVInt64Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_INT64(Name, Id, ...)                                   \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
 inline bool Type::isVectorFloat16Type() const {
 #define RVV_TYPE(Name, Id, SingletonId) false ||
 #define RVV_VECTOR_TYPE_HALF_FLOAT(Name, Id, ...)                              \
   isSpecificBuiltinType(BuiltinType::Id) ||
   return
 #include "clang/Basic/RISCVVTypes.def"
       false; // end of boolean or operation.
 }
 
 inline bool Type::isRVVFloat16Type() const {
 #define RVV_TYPE(Name, Id, SingletonId) false ||
 #define RVV_VECTOR_TYPE_HALF_FLOAT(Name, Id, ...)                              \
   isSpecificBuiltinType(BuiltinType::Id) ||
   return
 #include "clang/Basic/RISCVVTypes.def"
       false; // end of boolean or operation.
 }
 
+inline bool Type::isVectorFloat32Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_FLOAT32(Name, Id, ...)                                 \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
+inline bool Type::isRVVFloat32Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_FLOAT32(Name, Id, ...)                                 \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
+inline bool Type::isVectorFloat64Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_FLOAT64(Name, Id, ...)                                 \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
+inline bool Type::isRVVFloat64Type() const {
+#define RVV_TYPE(Name, Id, SingletonId) false ||
+#define RVV_VECTOR_TYPE_FLOAT64(Name, Id, ...)                                 \
+  isSpecificBuiltinType(BuiltinType::Id) ||
+  return
+#include "clang/Basic/RISCVVTypes.def"
+      false; // end of boolean or operation.
+}
+
 inline bool Type::isTemplateTypeParmType() const {
   return isa<TemplateTypeParmType>(CanonicalType);
 }
 
 inline bool Type::isSpecificBuiltinType(unsigned K) const {
   if (const BuiltinType *BT = getAs<BuiltinType>()) {
     return BT->getKind() == static_cast<BuiltinType::Kind>(K);
   }

clang/include/clang/Basic/RISCVVTypes.def

#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned) \
   RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
 #endif
 
 #ifndef RVV_VECTOR_TYPE_FLOAT
 #define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
   RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
 #endif
 
+// The types below is simply an extra layer of labeling for type checking
+// utilities under clang/AST/Type.h.
+#ifndef RVV_VECTOR_TYPE_INT64
+#define RVV_VECTOR_TYPE_INT64 RVV_VECTOR_TYPE_INT
+#endif
+
 #ifndef RVV_VECTOR_TYPE_HALF_FLOAT
 #define RVV_VECTOR_TYPE_HALF_FLOAT RVV_VECTOR_TYPE_FLOAT
 #endif
 
+#ifndef RVV_VECTOR_TYPE_FLOAT32
+#define RVV_VECTOR_TYPE_FLOAT32 RVV_VECTOR_TYPE_FLOAT
+#endif
+
+#ifndef RVV_VECTOR_TYPE_FLOAT64
+#define RVV_VECTOR_TYPE_FLOAT64 RVV_VECTOR_TYPE_FLOAT
+#endif
+
 //===- Vector types -------------------------------------------------------===//
 
 RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t", RvvInt8mf8, RvvInt8mf8Ty, 1,   8, 1, true)
 RVV_VECTOR_TYPE_INT("__rvv_int8mf4_t", RvvInt8mf4, RvvInt8mf4Ty, 2,   8, 1, true)
 RVV_VECTOR_TYPE_INT("__rvv_int8mf2_t", RvvInt8mf2, RvvInt8mf2Ty, 4,   8, 1, true)
 RVV_VECTOR_TYPE_INT("__rvv_int8m1_t",  RvvInt8m1,  RvvInt8m1Ty,  8,   8, 1, true)
 RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, true)
 RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, true)

 RVV_VECTOR_TYPE_INT("__rvv_int32m8_t", RvvInt32m8, RvvInt32m8Ty, 16, 32, 1, true)
 
 RVV_VECTOR_TYPE_INT("__rvv_uint32mf2_t",RvvUint32mf2,RvvUint32mf2Ty,1,  32, 1, false)
 RVV_VECTOR_TYPE_INT("__rvv_uint32m1_t", RvvUint32m1, RvvUint32m1Ty, 2,  32, 1, false)
 RVV_VECTOR_TYPE_INT("__rvv_uint32m2_t", RvvUint32m2, RvvUint32m2Ty, 4,  32, 1, false)
 RVV_VECTOR_TYPE_INT("__rvv_uint32m4_t", RvvUint32m4, RvvUint32m4Ty, 8,  32, 1, false)
 RVV_VECTOR_TYPE_INT("__rvv_uint32m8_t", RvvUint32m8, RvvUint32m8Ty, 16, 32, 1, false)
 
-RVV_VECTOR_TYPE_INT("__rvv_int64m1_t", RvvInt64m1, RvvInt64m1Ty, 1,  64, 1, true)
-RVV_VECTOR_TYPE_INT("__rvv_int64m2_t", RvvInt64m2, RvvInt64m2Ty, 2,  64, 1, true)
-RVV_VECTOR_TYPE_INT("__rvv_int64m4_t", RvvInt64m4, RvvInt64m4Ty, 4,  64, 1, true)
-RVV_VECTOR_TYPE_INT("__rvv_int64m8_t", RvvInt64m8, RvvInt64m8Ty, 8,  64, 1, true)
-
-RVV_VECTOR_TYPE_INT("__rvv_uint64m1_t",RvvUint64m1,RvvUint64m1Ty,1,  64, 1, false)
-RVV_VECTOR_TYPE_INT("__rvv_uint64m2_t",RvvUint64m2,RvvUint64m2Ty,2,  64, 1, false)
-RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4,  64, 1, false)
-RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8,  64, 1, false)
+RVV_VECTOR_TYPE_INT64("__rvv_int64m1_t", RvvInt64m1, RvvInt64m1Ty, 1,  64, 1, true)
+RVV_VECTOR_TYPE_INT64("__rvv_int64m2_t", RvvInt64m2, RvvInt64m2Ty, 2,  64, 1, true)
+RVV_VECTOR_TYPE_INT64("__rvv_int64m4_t", RvvInt64m4, RvvInt64m4Ty, 4,  64, 1, true)
+RVV_VECTOR_TYPE_INT64("__rvv_int64m8_t", RvvInt64m8, RvvInt64m8Ty, 8,  64, 1, true)
+
+RVV_VECTOR_TYPE_INT64("__rvv_uint64m1_t",RvvUint64m1,RvvUint64m1Ty,1,  64, 1, false)
+RVV_VECTOR_TYPE_INT64("__rvv_uint64m2_t",RvvUint64m2,RvvUint64m2Ty,2,  64, 1, false)
+RVV_VECTOR_TYPE_INT64("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4,  64, 1, false)
+RVV_VECTOR_TYPE_INT64("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8,  64, 1, false)
 
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1,  16, 1)
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2,  16, 1)
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4,  16, 1)
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m2_t", RvvFloat16m2, RvvFloat16m2Ty, 8,  16, 1)
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1)
 RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32, 16, 1)
 
-RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2_t",RvvFloat32mf2,RvvFloat32mf2Ty,1,  32, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1_t", RvvFloat32m1, RvvFloat32m1Ty, 2,  32, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2_t", RvvFloat32m2, RvvFloat32m2Ty, 4,  32, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float32m4_t", RvvFloat32m4, RvvFloat32m4Ty, 8,  32, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float32m8_t", RvvFloat32m8, RvvFloat32m8Ty, 16, 32, 1)
-
-RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1_t", RvvFloat64m1, RvvFloat64m1Ty, 1,  64, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2_t", RvvFloat64m2, RvvFloat64m2Ty, 2,  64, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4_t", RvvFloat64m4, RvvFloat64m4Ty, 4,  64, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float64m8_t", RvvFloat64m8, RvvFloat64m8Ty, 8,  64, 1)
+RVV_VECTOR_TYPE_FLOAT32("__rvv_float32mf2_t",RvvFloat32mf2,RvvFloat32mf2Ty,1,  32, 1)
+RVV_VECTOR_TYPE_FLOAT32("__rvv_float32m1_t", RvvFloat32m1, RvvFloat32m1Ty, 2,  32, 1)
+RVV_VECTOR_TYPE_FLOAT32("__rvv_float32m2_t", RvvFloat32m2, RvvFloat32m2Ty, 4,  32, 1)
+RVV_VECTOR_TYPE_FLOAT32("__rvv_float32m4_t", RvvFloat32m4, RvvFloat32m4Ty, 8,  32, 1)
+RVV_VECTOR_TYPE_FLOAT32("__rvv_float32m8_t", RvvFloat32m8, RvvFloat32m8Ty, 16, 32, 1)
+
+RVV_VECTOR_TYPE_FLOAT64("__rvv_float64m1_t", RvvFloat64m1, RvvFloat64m1Ty, 1,  64, 1)
+RVV_VECTOR_TYPE_FLOAT64("__rvv_float64m2_t", RvvFloat64m2, RvvFloat64m2Ty, 2,  64, 1)
+RVV_VECTOR_TYPE_FLOAT64("__rvv_float64m4_t", RvvFloat64m4, RvvFloat64m4Ty, 4,  64, 1)
+RVV_VECTOR_TYPE_FLOAT64("__rvv_float64m8_t", RvvFloat64m8, RvvFloat64m8Ty, 8,  64, 1)
 
 RVV_PREDICATE_TYPE("__rvv_bool1_t",  RvvBool1,  RvvBool1Ty,  64)
 RVV_PREDICATE_TYPE("__rvv_bool2_t",  RvvBool2,  RvvBool2Ty,  32)
 RVV_PREDICATE_TYPE("__rvv_bool4_t",  RvvBool4,  RvvBool4Ty,  16)
 RVV_PREDICATE_TYPE("__rvv_bool8_t",  RvvBool8,  RvvBool8Ty,  8)
 RVV_PREDICATE_TYPE("__rvv_bool16_t", RvvBool16, RvvBool16Ty, 4)
 RVV_PREDICATE_TYPE("__rvv_bool32_t", RvvBool32, RvvBool32Ty, 2)
 RVV_PREDICATE_TYPE("__rvv_bool64_t", RvvBool64, RvvBool64Ty, 1)
 
 #undef RVV_VECTOR_TYPE_FLOAT
+#undef RVV_VECTOR_TYPE_FLOAT64
+#undef RVV_VECTOR_TYPE_FLOAT32
 #undef RVV_VECTOR_TYPE_HALF_FLOAT
 #undef RVV_VECTOR_TYPE_INT
+#undef RVV_VECTOR_TYPE_INT64
 #undef RVV_VECTOR_TYPE
 #undef RVV_PREDICATE_TYPE
 #undef RVV_TYPE

clang/include/clang/Basic/TargetInfo.h

public:
 
   /// Determine whether return of a floating point value is supported
   /// on this target.
   virtual bool hasFPReturn() const { return HasFPReturn; }
 
   /// Determine whether constrained floating point is supported on this target.
   virtual bool hasStrictFP() const { return HasStrictFP; }
 
+  /// Determine whether vector int64 type is supported on this target.
+  virtual bool hasVectorInt64Support() const { return false; }
+
   /// Determine whether vector half float (float16) type is supported on this
   /// target.
   virtual bool hasVectorFloat16Support() const { return false; }
 
+  /// Determine whether vector float32 type is supported on this target.
+  virtual bool hasVectorFloat32Support() const { return false; }
+
+  /// Determine whether vector float32 type is supported on this target.
+  virtual bool hasVectorFloat64Support() const { return false; }
+
   /// Return the alignment that is the largest alignment ever used for any
   /// scalar/SIMD data type on the target machine you are compiling for
   /// (including types with an extended alignment requirement).
   unsigned getSuitableAlign() const { return SuitableAlign; }
 
   /// Return the default alignment for __attribute__((aligned)) on
   /// this target, to be used if no alignment value is specified.
   unsigned getDefaultAlignForAttributeAligned() const {

clang/lib/Basic/Targets/RISCV.h

public:
 
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
 
+  bool hasVectorInt64Support() const override { return hasFeature("zve64x"); }
+
   bool hasVectorFloat16Support() const override { return hasFeature("zvfh"); }
 
+  bool hasVectorFloat32Support() const override { return hasFeature("zve32f"); }
+
+  bool hasVectorFloat64Support() const override { return hasFeature("zve64d"); }
+
   bool useFP16ConversionIntrinsics() const override {
     return false;
   }
 
   bool isValidCPUName(StringRef Name) const override;
   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
   bool isValidTuneCPUName(StringRef Name) const override;
   void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;

clang/lib/Sema/Sema.cpp

if (IsRetTy && !TI.hasFPReturn() && (IsDouble || IsFloat)) {
           << Context.getTargetInfo().getTriple().str()) {
         if (D)
           D->setInvalidDecl();
       }
       if (D)
         targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
     }
 
-    if (Ty->isVectorFloat16Type() &&
-        !Context.getTargetInfo().hasVectorFloat16Support()) {
+    if ((Ty->isVectorInt64Type() &&
+         !Context.getTargetInfo().hasVectorInt64Support()) ||
+        (Ty->isVectorFloat16Type() &&
+         !Context.getTargetInfo().hasVectorFloat16Support()) ||
+        (Ty->isVectorFloat32Type() &&
+         !Context.getTargetInfo().hasVectorFloat32Support()) ||
+        (Ty->isVectorFloat64Type() &&
+         !Context.getTargetInfo().hasVectorFloat64Support())) {
       Diag(Loc, diag::err_require_vector_support) << Ty;
+      if (Ty->isVectorInt64Type() && Ty->isRVVInt64Type()) {
+        Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+            << Ty << "zve64x";
+      }
       if (Ty->isVectorFloat16Type() && Ty->isRVVFloat16Type()) {
         Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
       }
+      if (Ty->isVectorFloat32Type() && Ty->isRVVFloat32Type()) {
+        Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+            << Ty << "zve32f";
+      }
+      if (Ty->isVectorFloat64Type() && Ty->isRVVFloat64Type()) {
+        Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+            << Ty << "zve64d";
+      }
     }
 
     // Don't allow SVE types in functions without a SVE target.
     if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
       llvm::StringMap<bool> CallerFeatureMap;
       Context.getFunctionFeatureMap(CallerFeatureMap, FD);
       if (!Builtin::evaluateRequiredTargetFeatures(
           "sve", CallerFeatureMap))

clang/lib/Sema/SemaRISCVVectorLookup.cpp

public:
   // return true, otherwise return false.
   bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                               Preprocessor &PP) override;
 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasVectorFloat32 = TI.hasFeature("zve32f");
-  bool HasVectorFloat64 = TI.hasFeature("zve64d");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : RVVIntrinsicRecords) {
     // Create Intrinsics for each type and LMUL.
     BasicType BaseType = BasicType::Unknown;
for (unsigned int TypeRangeMaskShift = 0;
          ++TypeRangeMaskShift) {
       unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
       BaseType = static_cast<BasicType>(BaseTypeI);
 
       if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
         continue;
 
       // Check requirement.
-      if (BaseType == BasicType::Float32 && !HasVectorFloat32)
-        continue;
-
-      if (BaseType == BasicType::Float64 && !HasVectorFloat64)
-        continue;
-
       if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
           !HasRV64)
         continue;
 
       if ((BaseType == BasicType::Int64) &&
           ((Record.RequiredExtensions & RVV_REQ_FullMultiply) ==
            RVV_REQ_FullMultiply) &&
           !HasFullMultiply)

clang/test/Sema/riscv-vector-float32-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve32x -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vfloat32m1_t foo() {  /* expected-error {{Vector type 'vfloat32m1_t' (aka '__rvv_float32m1_t') is not supported in the current target}} */ /* expected-error {{RISC-V type 'vfloat32m1_t' (aka '__rvv_float32m1_t') requires the 'zve32f' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/test/Sema/riscv-vector-float64-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve64f -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vfloat64m1_t foo() {  /* expected-error {{Vector type 'vfloat64m1_t' (aka '__rvv_float64m1_t') is not supported in the current target}} */ /* expected-error {{RISC-V type 'vfloat64m1_t' (aka '__rvv_float64m1_t') requires the 'zve64d' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/test/Sema/riscv-vector-int64-check.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +zve32x -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+vint64m1_t foo() {  /* expected-error {{Vector type 'vint64m1_t' (aka '__rvv_int64m1_t') is not supported in the current target}} */ /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/

clang/utils/TableGen/RISCVVEmitter.cpp

void RVVEmitter::createHeader(raw_ostream &OS) {
 
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
 
-  OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float32, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
-  OS << "#endif\n";
 
-  OS << "#if (__riscv_v_elen_fp >= 64)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = TypeCache.computeType(BasicType::Float64, Log2LMUL,
                                    PrototypeDescriptor::Vector);
     if (T)
       printType(*T);
   }
-  OS << "#endif\n\n";
 
   OS << "#define __riscv_v_intrinsic_overloading 1\n";
 
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
   OS << "#endif // __cplusplus\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }